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arm64: mpam: Initialise and context switch the MPAMSM_EL1 register

The MPAMSM_EL1 sets the MPAM labels, PMG and PARTID, for loads and stores
generated by a shared SMCU. Disable the traps so the kernel can use it and
set it to the same configuration as the per-EL cpu MPAM configuration.

If an SMCU is not shared with other cpus then it is implementation
defined whether the configuration from MPAMSM_EL1 is used or that from
the appropriate MPAMy_ELx. As we set the same, PMG_D and PARTID_D,
configuration for MPAM0_EL1, MPAM1_EL1 and MPAMSM_EL1 the resulting
configuration is the same regardless.

The range of valid configurations for the PARTID and PMG in MPAMSM_EL1 is
not currently specified in Arm Architectural Reference Manual but the
architect has confirmed that it is intended to be the same as that for the
cpu configuration in the MPAMy_ELx registers.

Tested-by: Gavin Shan <gshan@redhat.com>
Tested-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Tested-by: Peter Newman <peternewman@google.com>
Tested-by: Zeng Heng <zengheng4@huawei.com>
Tested-by: Punit Agrawal <punit.agrawal@oss.qualcomm.com>
Tested-by: Jesse Chick <jessechick@os.amperecomputing.com>
Reviewed-by: Zeng Heng <zengheng4@huawei.com>
Reviewed-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>

authored by

Ben Horgan and committed by
James Morse 37fe0f98 735dad99

+10 -1
+2 -1
arch/arm64/include/asm/el2_setup.h
··· 513 513 check_override id_aa64pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT, .Linit_mpam_\@, .Lskip_mpam_\@, x1, x2 514 514 515 515 .Linit_mpam_\@: 516 - msr_s SYS_MPAM2_EL2, xzr // use the default partition 516 + mov x0, #MPAM2_EL2_EnMPAMSM_MASK 517 + msr_s SYS_MPAM2_EL2, x0 // use the default partition, 517 518 // and disable lower traps 518 519 mrs_s x0, SYS_MPAMIDR_EL1 519 520 tbz x0, #MPAMIDR_EL1_HAS_HCR_SHIFT, .Lskip_mpam_\@ // skip if no MPAMHCR reg
+2
arch/arm64/include/asm/mpam.h
··· 53 53 return; 54 54 55 55 write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1); 56 + if (system_supports_sme()) 57 + write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1); 56 58 isb(); 57 59 58 60 /* Synchronising the EL0 write is left until the ERET to EL0 */
+2
arch/arm64/kernel/cpufeature.c
··· 2500 2500 regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); 2501 2501 2502 2502 write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1); 2503 + if (cpus_have_cap(ARM64_SME)) 2504 + write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1); 2503 2505 isb(); 2504 2506 2505 2507 /* Synchronising the EL0 write is left until the ERET to EL0 */
+4
arch/arm64/kernel/mpam.c
··· 28 28 */ 29 29 regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); 30 30 write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1); 31 + if (system_supports_sme()) { 32 + write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), 33 + SYS_MPAMSM_EL1); 34 + } 31 35 isb(); 32 36 33 37 write_sysreg_s(regval, SYS_MPAM0_EL1);