Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-dsa-lantiq_gswip-add-support-for-maxlinear-gsw1xx-switch-family'
Daniel Golle says:
====================
net: dsa: lantiq_gswip: Add support for MaxLinear GSW1xx switch family
This patch series extends the existing lantiq_gswip DSA driver to
support the MaxLinear GSW1xx family of dedicated Ethernet switch ICs.
These switches are based on the same IP as the Lantiq/Intel GSWIP found
in VR9 and xRX MIPS router SoCs which are currently supported by the
lantiq_gswip driver, but they are dedicated ICs connected via MDIO
rather than built-in components of a SoC accessible via memory-mapped
I/O.
The series includes several improvements and refactoring to implement
support for GSW1xx switch ICs by reusing the existing lantiq_gswip
driver.
The GSW1xx family includes several variants:
- GSW120: 4 ports, 2 PHYs, RGMII & SGMII/2500Base-X
- GSW125: 4 ports, 2 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
- GSW140: 6 ports, 4 PHYs, RGMII & SGMII/2500Base-X
- GSW141: 6 ports, 4 PHYs, RGMII & SGMII
- GSW145: 6 ports, 4 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
Key features implemented:
- MDIO-based register access using regmap
- Support for SGMII/1000Base-X/2500Base-X SerDes interfaces
- Configurable RGMII delays via device tree properties
- Configurable RMII clock direction
- Energy Efficient Ethernet (EEE) support
- enabling/disabling learning
====================
Link: https://patch.msgid.link/cover.1762170107.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+3088
-1588
+156
-8
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
+156
-8
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
···
4
4
$id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Lantiq GSWIP Ethernet switches
7
+
title: Lantiq GSWIP and MaxLinear GSW1xx Ethernet switches
8
8
9
-
allOf:
10
-
- $ref: dsa.yaml#/$defs/ethernet-ports
9
+
description:
10
+
Lantiq GSWIP and MaxLinear GSW1xx switches share the same hardware IP.
11
+
Lantiq switches are embedded in SoCs and accessed via memory-mapped I/O,
12
+
while MaxLinear switches are standalone ICs connected via MDIO.
13
+
14
+
$ref: dsa.yaml#
11
15
12
16
maintainers:
13
17
- Hauke Mehrtens <hauke@hauke-m.de>
···
22
18
- lantiq,xrx200-gswip
23
19
- lantiq,xrx300-gswip
24
20
- lantiq,xrx330-gswip
21
+
- maxlinear,gsw120
22
+
- maxlinear,gsw125
23
+
- maxlinear,gsw140
24
+
- maxlinear,gsw141
25
+
- maxlinear,gsw145
25
26
26
27
reg:
27
-
minItems: 3
28
+
minItems: 1
28
29
maxItems: 3
29
30
30
31
reg-names:
···
45
36
properties:
46
37
compatible:
47
38
const: lantiq,xrx200-mdio
48
-
49
-
required:
50
-
- compatible
51
39
52
40
gphy-fw:
53
41
type: object
···
97
91
98
92
additionalProperties: false
99
93
94
+
patternProperties:
95
+
"^(ethernet-)?ports$":
96
+
type: object
97
+
patternProperties:
98
+
"^(ethernet-)?port@[0-6]$":
99
+
$ref: dsa-port.yaml#
100
+
unevaluatedProperties: false
101
+
102
+
properties:
103
+
maxlinear,rmii-refclk-out:
104
+
type: boolean
105
+
description:
106
+
Configure the RMII reference clock to be a clock output
107
+
rather than an input. Only applicable for RMII mode.
108
+
tx-internal-delay-ps:
109
+
enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500]
110
+
description:
111
+
RGMII TX Clock Delay defined in pico seconds.
112
+
The delay lines adjust the MII clock vs. data timing.
113
+
If this property is not present the delay is determined by
114
+
the interface mode.
115
+
rx-internal-delay-ps:
116
+
enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500]
117
+
description:
118
+
RGMII RX Clock Delay defined in pico seconds.
119
+
The delay lines adjust the MII clock vs. data timing.
120
+
If this property is not present the delay is determined by
121
+
the interface mode.
122
+
100
123
required:
101
124
- compatible
102
125
- reg
126
+
127
+
allOf:
128
+
- if:
129
+
properties:
130
+
compatible:
131
+
contains:
132
+
enum:
133
+
- lantiq,xrx200-gswip
134
+
- lantiq,xrx300-gswip
135
+
- lantiq,xrx330-gswip
136
+
then:
137
+
properties:
138
+
reg:
139
+
minItems: 3
140
+
maxItems: 3
141
+
mdio:
142
+
required:
143
+
- compatible
144
+
else:
145
+
properties:
146
+
reg:
147
+
maxItems: 1
148
+
reg-names: false
149
+
gphy-fw: false
103
150
104
151
unevaluatedProperties: false
105
152
···
172
113
port@0 {
173
114
reg = <0>;
174
115
label = "lan3";
175
-
phy-mode = "rgmii";
116
+
phy-mode = "rgmii-id";
176
117
phy-handle = <&phy0>;
118
+
tx-internal-delay-ps = <2000>;
119
+
rx-internal-delay-ps = <2000>;
177
120
};
178
121
179
122
port@1 {
···
260
199
reset-names = "gphy";
261
200
};
262
201
};
202
+
};
203
+
204
+
- |
205
+
#include <dt-bindings/leds/common.h>
206
+
207
+
mdio {
208
+
#address-cells = <1>;
209
+
#size-cells = <0>;
210
+
211
+
switch@1f {
212
+
compatible = "maxlinear,gsw125";
213
+
reg = <0x1f>;
214
+
215
+
ports {
216
+
#address-cells = <1>;
217
+
#size-cells = <0>;
218
+
219
+
port@0 {
220
+
reg = <0>;
221
+
label = "lan0";
222
+
phy-handle = <&switchphy0>;
223
+
phy-mode = "internal";
224
+
};
225
+
226
+
port@1 {
227
+
reg = <1>;
228
+
label = "lan1";
229
+
phy-handle = <&switchphy1>;
230
+
phy-mode = "internal";
231
+
};
232
+
233
+
port@4 {
234
+
reg = <4>;
235
+
label = "wan";
236
+
phy-mode = "1000base-x";
237
+
managed = "in-band-status";
238
+
};
239
+
240
+
port@5 {
241
+
reg = <5>;
242
+
phy-mode = "rgmii-id";
243
+
tx-internal-delay-ps = <2000>;
244
+
rx-internal-delay-ps = <2000>;
245
+
ethernet = <ð0>;
246
+
247
+
fixed-link {
248
+
speed = <1000>;
249
+
full-duplex;
250
+
};
251
+
};
252
+
};
253
+
254
+
mdio {
255
+
#address-cells = <1>;
256
+
#size-cells = <0>;
257
+
258
+
switchphy0: switchphy@0 {
259
+
reg = <0>;
260
+
261
+
leds {
262
+
#address-cells = <1>;
263
+
#size-cells = <0>;
264
+
265
+
led@0 {
266
+
reg = <0>;
267
+
color = <LED_COLOR_ID_GREEN>;
268
+
function = LED_FUNCTION_LAN;
269
+
};
270
+
};
271
+
};
272
+
273
+
switchphy1: switchphy@1 {
274
+
reg = <1>;
275
+
276
+
leds {
277
+
#address-cells = <1>;
278
+
#size-cells = <0>;
279
+
280
+
led@0 {
281
+
reg = <0>;
282
+
color = <LED_COLOR_ID_GREEN>;
283
+
function = LED_FUNCTION_LAN;
284
+
};
285
+
};
286
+
};
287
+
};
288
+
};
263
289
};
+2
-1
MAINTAINERS
+2
-1
MAINTAINERS
···
14053
14053
K: landlock
14054
14054
K: LANDLOCK
14055
14055
14056
-
LANTIQ / INTEL Ethernet drivers
14056
+
LANTIQ / MAXLINEAR / INTEL Ethernet DSA drivers
14057
14057
M: Hauke Mehrtens <hauke@hauke-m.de>
14058
14058
L: netdev@vger.kernel.org
14059
14059
S: Maintained
···
14061
14061
F: drivers/net/dsa/lantiq/*
14062
14062
F: drivers/net/ethernet/lantiq_xrx200.c
14063
14063
F: net/dsa/tag_gswip.c
14064
+
F: net/dsa/tag_mxl-gsw1xx.c
14064
14065
14065
14066
LANTIQ MIPS ARCHITECTURE
14066
14067
M: John Crispin <john@phrozen.org>
+17
-1
drivers/net/dsa/lantiq/Kconfig
+17
-1
drivers/net/dsa/lantiq/Kconfig
···
1
+
config NET_DSA_LANTIQ_COMMON
2
+
tristate
3
+
select REGMAP
4
+
1
5
config NET_DSA_LANTIQ_GSWIP
2
6
tristate "Lantiq / Intel GSWIP"
3
7
depends on HAS_IOMEM
4
8
select NET_DSA_TAG_GSWIP
5
-
select REGMAP
9
+
select NET_DSA_LANTIQ_COMMON
6
10
help
7
11
This enables support for the Lantiq / Intel GSWIP 2.1 found in
8
12
the xrx200 / VR9 SoC.
13
+
14
+
config NET_DSA_MXL_GSW1XX
15
+
tristate "MaxLinear GSW1xx Ethernet switch support"
16
+
select NET_DSA_TAG_MXL_GSW1XX
17
+
select NET_DSA_LANTIQ_COMMON
18
+
help
19
+
This enables support for the MaxLinear GSW1xx family of 1GE switches
20
+
GSW120 4 port, 2 PHYs, RGMII & SGMII/2500Base-X
21
+
GSW125 4 port, 2 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
22
+
GSW140 6 port, 4 PHYs, RGMII & SGMII/2500Base-X
23
+
GSW141 6 port, 4 PHYs, RGMII & SGMII
24
+
GSW145 6 port, 4 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
+2
drivers/net/dsa/lantiq/Makefile
+2
drivers/net/dsa/lantiq/Makefile
+13
-1578
drivers/net/dsa/lantiq/lantiq_gswip.c
+13
-1578
drivers/net/dsa/lantiq/lantiq_gswip.c
···
2
2
/*
3
3
* Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs
4
4
*
5
-
* Copyright (C) 2010 Lantiq Deutschland
6
-
* Copyright (C) 2012 John Crispin <john@phrozen.org>
5
+
* Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
7
6
* Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
8
-
*
9
-
* The VLAN and bridge model the GSWIP hardware uses does not directly
10
-
* matches the model DSA uses.
11
-
*
12
-
* The hardware has 64 possible table entries for bridges with one VLAN
13
-
* ID, one flow id and a list of ports for each bridge. All entries which
14
-
* match the same flow ID are combined in the mac learning table, they
15
-
* act as one global bridge.
16
-
* The hardware does not support VLAN filter on the port, but on the
17
-
* bridge, this driver converts the DSA model to the hardware.
18
-
*
19
-
* The CPU gets all the exception frames which do not match any forwarding
20
-
* rule and the CPU port is also added to all bridges. This makes it possible
21
-
* to handle all the special cases easily in software.
22
-
* At the initialization the driver allocates one bridge table entry for
23
-
* each switch port which is used when the port is used without an
24
-
* explicit bridge. This prevents the frames from being forwarded
25
-
* between all LAN ports by default.
7
+
* Copyright (C) 2012 John Crispin <john@phrozen.org>
8
+
* Copyright (C) 2010 Lantiq Deutschland
26
9
*/
27
10
28
11
#include "lantiq_gswip.h"
29
12
#include "lantiq_pce.h"
30
13
14
+
#include <linux/clk.h>
31
15
#include <linux/delay.h>
32
-
#include <linux/etherdevice.h>
33
16
#include <linux/firmware.h>
34
-
#include <linux/if_bridge.h>
35
-
#include <linux/if_vlan.h>
36
-
#include <linux/iopoll.h>
37
17
#include <linux/mfd/syscon.h>
38
18
#include <linux/module.h>
39
-
#include <linux/of_mdio.h>
40
-
#include <linux/of_net.h>
41
19
#include <linux/of_platform.h>
42
-
#include <linux/phy.h>
43
-
#include <linux/phylink.h>
20
+
#include <linux/platform_device.h>
21
+
#include <linux/regmap.h>
22
+
#include <linux/reset.h>
44
23
#include <dt-bindings/mips/lantiq_rcu_gphy.h>
24
+
25
+
#include <net/dsa.h>
45
26
46
27
struct xway_gphy_match_data {
47
28
char *fe_firmware_name;
48
29
char *ge_firmware_name;
49
30
};
50
-
51
-
struct gswip_pce_table_entry {
52
-
u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
53
-
u16 table; // PCE_TBL_CTRL.ADDR = pData->table
54
-
u16 key[8];
55
-
u16 val[5];
56
-
u16 mask;
57
-
u8 gmap;
58
-
bool type;
59
-
bool valid;
60
-
bool key_mode;
61
-
};
62
-
63
-
struct gswip_rmon_cnt_desc {
64
-
unsigned int size;
65
-
unsigned int offset;
66
-
const char *name;
67
-
};
68
-
69
-
#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
70
-
71
-
static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
72
-
/** Receive Packet Count (only packets that are accepted and not discarded). */
73
-
MIB_DESC(1, 0x1F, "RxGoodPkts"),
74
-
MIB_DESC(1, 0x23, "RxUnicastPkts"),
75
-
MIB_DESC(1, 0x22, "RxMulticastPkts"),
76
-
MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
77
-
MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
78
-
MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
79
-
MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
80
-
MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
81
-
MIB_DESC(1, 0x20, "RxGoodPausePkts"),
82
-
MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
83
-
MIB_DESC(1, 0x12, "Rx64BytePkts"),
84
-
MIB_DESC(1, 0x13, "Rx127BytePkts"),
85
-
MIB_DESC(1, 0x14, "Rx255BytePkts"),
86
-
MIB_DESC(1, 0x15, "Rx511BytePkts"),
87
-
MIB_DESC(1, 0x16, "Rx1023BytePkts"),
88
-
/** Receive Size 1024-1522 (or more, if configured) Packet Count. */
89
-
MIB_DESC(1, 0x17, "RxMaxBytePkts"),
90
-
MIB_DESC(1, 0x18, "RxDroppedPkts"),
91
-
MIB_DESC(1, 0x19, "RxFilteredPkts"),
92
-
MIB_DESC(2, 0x24, "RxGoodBytes"),
93
-
MIB_DESC(2, 0x26, "RxBadBytes"),
94
-
MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
95
-
MIB_DESC(1, 0x0C, "TxGoodPkts"),
96
-
MIB_DESC(1, 0x06, "TxUnicastPkts"),
97
-
MIB_DESC(1, 0x07, "TxMulticastPkts"),
98
-
MIB_DESC(1, 0x00, "Tx64BytePkts"),
99
-
MIB_DESC(1, 0x01, "Tx127BytePkts"),
100
-
MIB_DESC(1, 0x02, "Tx255BytePkts"),
101
-
MIB_DESC(1, 0x03, "Tx511BytePkts"),
102
-
MIB_DESC(1, 0x04, "Tx1023BytePkts"),
103
-
/** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
104
-
MIB_DESC(1, 0x05, "TxMaxBytePkts"),
105
-
MIB_DESC(1, 0x08, "TxSingleCollCount"),
106
-
MIB_DESC(1, 0x09, "TxMultCollCount"),
107
-
MIB_DESC(1, 0x0A, "TxLateCollCount"),
108
-
MIB_DESC(1, 0x0B, "TxExcessCollCount"),
109
-
MIB_DESC(1, 0x0D, "TxPauseCount"),
110
-
MIB_DESC(1, 0x10, "TxDroppedPkts"),
111
-
MIB_DESC(2, 0x0E, "TxGoodBytes"),
112
-
};
113
-
114
-
static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
115
-
u32 cleared)
116
-
{
117
-
u32 val;
118
-
119
-
return regmap_read_poll_timeout(priv->gswip, offset, val,
120
-
!(val & cleared), 20, 50000);
121
-
}
122
-
123
-
static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 mask, u32 set,
124
-
int port)
125
-
{
126
-
int reg_port;
127
-
128
-
/* MII_CFG register only exists for MII ports */
129
-
if (!(priv->hw_info->mii_ports & BIT(port)))
130
-
return;
131
-
132
-
reg_port = port + priv->hw_info->mii_port_reg_offset;
133
-
134
-
regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), mask,
135
-
set);
136
-
}
137
-
138
-
static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 mask, u32 set,
139
-
int port)
140
-
{
141
-
int reg_port;
142
-
143
-
/* MII_PCDU register only exists for MII ports */
144
-
if (!(priv->hw_info->mii_ports & BIT(port)))
145
-
return;
146
-
147
-
reg_port = port + priv->hw_info->mii_port_reg_offset;
148
-
149
-
switch (reg_port) {
150
-
case 0:
151
-
regmap_write_bits(priv->mii, GSWIP_MII_PCDU0, mask, set);
152
-
break;
153
-
case 1:
154
-
regmap_write_bits(priv->mii, GSWIP_MII_PCDU1, mask, set);
155
-
break;
156
-
case 5:
157
-
regmap_write_bits(priv->mii, GSWIP_MII_PCDU5, mask, set);
158
-
break;
159
-
}
160
-
}
161
-
162
-
static int gswip_mdio_poll(struct gswip_priv *priv)
163
-
{
164
-
u32 ctrl;
165
-
166
-
return regmap_read_poll_timeout(priv->mdio, GSWIP_MDIO_CTRL, ctrl,
167
-
!(ctrl & GSWIP_MDIO_CTRL_BUSY), 40, 4000);
168
-
}
169
-
170
-
static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
171
-
{
172
-
struct gswip_priv *priv = bus->priv;
173
-
int err;
174
-
175
-
err = gswip_mdio_poll(priv);
176
-
if (err) {
177
-
dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
178
-
return err;
179
-
}
180
-
181
-
regmap_write(priv->mdio, GSWIP_MDIO_WRITE, val);
182
-
regmap_write(priv->mdio, GSWIP_MDIO_CTRL,
183
-
GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
184
-
((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
185
-
(reg & GSWIP_MDIO_CTRL_REGAD_MASK));
186
-
187
-
return 0;
188
-
}
189
-
190
-
static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
191
-
{
192
-
struct gswip_priv *priv = bus->priv;
193
-
u32 val;
194
-
int err;
195
-
196
-
err = gswip_mdio_poll(priv);
197
-
if (err) {
198
-
dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
199
-
return err;
200
-
}
201
-
202
-
regmap_write(priv->mdio, GSWIP_MDIO_CTRL,
203
-
GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
204
-
((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
205
-
(reg & GSWIP_MDIO_CTRL_REGAD_MASK));
206
-
207
-
err = gswip_mdio_poll(priv);
208
-
if (err) {
209
-
dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
210
-
return err;
211
-
}
212
-
213
-
err = regmap_read(priv->mdio, GSWIP_MDIO_READ, &val);
214
-
if (err)
215
-
return err;
216
-
217
-
return val;
218
-
}
219
-
220
-
static int gswip_mdio(struct gswip_priv *priv)
221
-
{
222
-
struct device_node *mdio_np, *switch_np = priv->dev->of_node;
223
-
struct device *dev = priv->dev;
224
-
struct mii_bus *bus;
225
-
int err = 0;
226
-
227
-
mdio_np = of_get_compatible_child(switch_np, "lantiq,xrx200-mdio");
228
-
if (!mdio_np)
229
-
mdio_np = of_get_child_by_name(switch_np, "mdio");
230
-
231
-
if (!of_device_is_available(mdio_np))
232
-
goto out_put_node;
233
-
234
-
bus = devm_mdiobus_alloc(dev);
235
-
if (!bus) {
236
-
err = -ENOMEM;
237
-
goto out_put_node;
238
-
}
239
-
240
-
bus->priv = priv;
241
-
bus->read = gswip_mdio_rd;
242
-
bus->write = gswip_mdio_wr;
243
-
bus->name = "lantiq,xrx200-mdio";
244
-
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev));
245
-
bus->parent = priv->dev;
246
-
247
-
err = devm_of_mdiobus_register(dev, bus, mdio_np);
248
-
249
-
out_put_node:
250
-
of_node_put(mdio_np);
251
-
252
-
return err;
253
-
}
254
-
255
-
static int gswip_pce_table_entry_read(struct gswip_priv *priv,
256
-
struct gswip_pce_table_entry *tbl)
257
-
{
258
-
int i;
259
-
int err;
260
-
u32 crtl;
261
-
u32 tmp;
262
-
u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
263
-
GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
264
-
265
-
mutex_lock(&priv->pce_table_lock);
266
-
267
-
err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
268
-
GSWIP_PCE_TBL_CTRL_BAS);
269
-
if (err)
270
-
goto out_unlock;
271
-
272
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index);
273
-
regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
274
-
GSWIP_PCE_TBL_CTRL_ADDR_MASK |
275
-
GSWIP_PCE_TBL_CTRL_OPMOD_MASK |
276
-
GSWIP_PCE_TBL_CTRL_BAS,
277
-
tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS);
278
-
279
-
err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
280
-
GSWIP_PCE_TBL_CTRL_BAS);
281
-
if (err)
282
-
goto out_unlock;
283
-
284
-
for (i = 0; i < ARRAY_SIZE(tbl->key); i++) {
285
-
err = regmap_read(priv->gswip, GSWIP_PCE_TBL_KEY(i), &tmp);
286
-
if (err)
287
-
goto out_unlock;
288
-
tbl->key[i] = tmp;
289
-
}
290
-
for (i = 0; i < ARRAY_SIZE(tbl->val); i++) {
291
-
err = regmap_read(priv->gswip, GSWIP_PCE_TBL_VAL(i), &tmp);
292
-
if (err)
293
-
goto out_unlock;
294
-
tbl->val[i] = tmp;
295
-
}
296
-
297
-
err = regmap_read(priv->gswip, GSWIP_PCE_TBL_MASK, &tmp);
298
-
if (err)
299
-
goto out_unlock;
300
-
301
-
tbl->mask = tmp;
302
-
err = regmap_read(priv->gswip, GSWIP_PCE_TBL_CTRL, &crtl);
303
-
if (err)
304
-
goto out_unlock;
305
-
306
-
tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
307
-
tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
308
-
tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
309
-
310
-
out_unlock:
311
-
mutex_unlock(&priv->pce_table_lock);
312
-
313
-
return err;
314
-
}
315
-
316
-
static int gswip_pce_table_entry_write(struct gswip_priv *priv,
317
-
struct gswip_pce_table_entry *tbl)
318
-
{
319
-
int i;
320
-
int err;
321
-
u32 crtl;
322
-
u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
323
-
GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
324
-
325
-
mutex_lock(&priv->pce_table_lock);
326
-
327
-
err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
328
-
GSWIP_PCE_TBL_CTRL_BAS);
329
-
if (err) {
330
-
mutex_unlock(&priv->pce_table_lock);
331
-
return err;
332
-
}
333
-
334
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index);
335
-
regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
336
-
GSWIP_PCE_TBL_CTRL_ADDR_MASK |
337
-
GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
338
-
tbl->table | addr_mode);
339
-
340
-
for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
341
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_KEY(i), tbl->key[i]);
342
-
343
-
for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
344
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(i), tbl->val[i]);
345
-
346
-
regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
347
-
GSWIP_PCE_TBL_CTRL_ADDR_MASK |
348
-
GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
349
-
tbl->table | addr_mode);
350
-
351
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, tbl->mask);
352
-
353
-
regmap_read(priv->gswip, GSWIP_PCE_TBL_CTRL, &crtl);
354
-
crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
355
-
GSWIP_PCE_TBL_CTRL_GMAP_MASK);
356
-
if (tbl->type)
357
-
crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
358
-
if (tbl->valid)
359
-
crtl |= GSWIP_PCE_TBL_CTRL_VLD;
360
-
crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
361
-
crtl |= GSWIP_PCE_TBL_CTRL_BAS;
362
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_CTRL, crtl);
363
-
364
-
err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
365
-
GSWIP_PCE_TBL_CTRL_BAS);
366
-
367
-
mutex_unlock(&priv->pce_table_lock);
368
-
369
-
return err;
370
-
}
371
-
372
-
/* Add the LAN port into a bridge with the CPU port by
373
-
* default. This prevents automatic forwarding of
374
-
* packages between the LAN ports when no explicit
375
-
* bridge is configured.
376
-
*/
377
-
static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
378
-
{
379
-
struct gswip_pce_table_entry vlan_active = {0,};
380
-
struct gswip_pce_table_entry vlan_mapping = {0,};
381
-
int err;
382
-
383
-
vlan_active.index = port + 1;
384
-
vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
385
-
vlan_active.key[0] = GSWIP_VLAN_UNAWARE_PVID;
386
-
vlan_active.val[0] = port + 1 /* fid */;
387
-
vlan_active.valid = add;
388
-
err = gswip_pce_table_entry_write(priv, &vlan_active);
389
-
if (err) {
390
-
dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
391
-
return err;
392
-
}
393
-
394
-
if (!add)
395
-
return 0;
396
-
397
-
vlan_mapping.index = port + 1;
398
-
vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
399
-
vlan_mapping.val[0] = GSWIP_VLAN_UNAWARE_PVID;
400
-
vlan_mapping.val[1] = BIT(port) | dsa_cpu_ports(priv->ds);
401
-
vlan_mapping.val[2] = 0;
402
-
err = gswip_pce_table_entry_write(priv, &vlan_mapping);
403
-
if (err) {
404
-
dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
405
-
return err;
406
-
}
407
-
408
-
return 0;
409
-
}
410
-
411
-
static int gswip_port_setup(struct dsa_switch *ds, int port)
412
-
{
413
-
struct gswip_priv *priv = ds->priv;
414
-
int err;
415
-
416
-
if (!dsa_is_cpu_port(ds, port)) {
417
-
err = gswip_add_single_port_br(priv, port, true);
418
-
if (err)
419
-
return err;
420
-
}
421
-
422
-
return 0;
423
-
}
424
-
425
-
static int gswip_port_enable(struct dsa_switch *ds, int port,
426
-
struct phy_device *phydev)
427
-
{
428
-
struct gswip_priv *priv = ds->priv;
429
-
430
-
if (!dsa_is_cpu_port(ds, port)) {
431
-
u32 mdio_phy = 0;
432
-
433
-
if (phydev)
434
-
mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
435
-
436
-
regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
437
-
GSWIP_MDIO_PHY_ADDR_MASK,
438
-
mdio_phy);
439
-
}
440
-
441
-
/* RMON Counter Enable for port */
442
-
regmap_write(priv->gswip, GSWIP_BM_PCFGp(port), GSWIP_BM_PCFG_CNTEN);
443
-
444
-
/* enable port fetch/store dma & VLAN Modification */
445
-
regmap_set_bits(priv->gswip, GSWIP_FDMA_PCTRLp(port),
446
-
GSWIP_FDMA_PCTRL_EN | GSWIP_FDMA_PCTRL_VLANMOD_BOTH);
447
-
regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),
448
-
GSWIP_SDMA_PCTRL_EN);
449
-
450
-
return 0;
451
-
}
452
-
453
-
static void gswip_port_disable(struct dsa_switch *ds, int port)
454
-
{
455
-
struct gswip_priv *priv = ds->priv;
456
-
457
-
regmap_clear_bits(priv->gswip, GSWIP_FDMA_PCTRLp(port),
458
-
GSWIP_FDMA_PCTRL_EN);
459
-
regmap_clear_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),
460
-
GSWIP_SDMA_PCTRL_EN);
461
-
}
462
-
463
-
static int gswip_pce_load_microcode(struct gswip_priv *priv)
464
-
{
465
-
int i;
466
-
int err;
467
-
468
-
regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
469
-
GSWIP_PCE_TBL_CTRL_ADDR_MASK |
470
-
GSWIP_PCE_TBL_CTRL_OPMOD_MASK |
471
-
GSWIP_PCE_TBL_CTRL_OPMOD_ADWR,
472
-
GSWIP_PCE_TBL_CTRL_OPMOD_ADWR);
473
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, 0);
474
-
475
-
for (i = 0; i < priv->hw_info->pce_microcode_size; i++) {
476
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, i);
477
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(0),
478
-
(*priv->hw_info->pce_microcode)[i].val_0);
479
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(1),
480
-
(*priv->hw_info->pce_microcode)[i].val_1);
481
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(2),
482
-
(*priv->hw_info->pce_microcode)[i].val_2);
483
-
regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(3),
484
-
(*priv->hw_info->pce_microcode)[i].val_3);
485
-
486
-
/* start the table access: */
487
-
regmap_set_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
488
-
GSWIP_PCE_TBL_CTRL_BAS);
489
-
err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
490
-
GSWIP_PCE_TBL_CTRL_BAS);
491
-
if (err)
492
-
return err;
493
-
}
494
-
495
-
/* tell the switch that the microcode is loaded */
496
-
regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0,
497
-
GSWIP_PCE_GCTRL_0_MC_VALID);
498
-
499
-
return 0;
500
-
}
501
-
502
-
static void gswip_port_commit_pvid(struct gswip_priv *priv, int port)
503
-
{
504
-
struct dsa_port *dp = dsa_to_port(priv->ds, port);
505
-
struct net_device *br = dsa_port_bridge_dev_get(dp);
506
-
u32 vinr;
507
-
int idx;
508
-
509
-
if (!dsa_port_is_user(dp))
510
-
return;
511
-
512
-
if (br) {
513
-
u16 pvid = GSWIP_VLAN_UNAWARE_PVID;
514
-
515
-
if (br_vlan_enabled(br))
516
-
br_vlan_get_pvid(br, &pvid);
517
-
518
-
/* VLAN-aware bridge ports with no PVID will use Active VLAN
519
-
* index 0. The expectation is that this drops all untagged and
520
-
* VID-0 tagged ingress traffic.
521
-
*/
522
-
idx = 0;
523
-
for (int i = priv->hw_info->max_ports;
524
-
i < ARRAY_SIZE(priv->vlans); i++) {
525
-
if (priv->vlans[i].bridge == br &&
526
-
priv->vlans[i].vid == pvid) {
527
-
idx = i;
528
-
break;
529
-
}
530
-
}
531
-
} else {
532
-
/* The Active VLAN table index as configured by
533
-
* gswip_add_single_port_br()
534
-
*/
535
-
idx = port + 1;
536
-
}
537
-
538
-
vinr = idx ? GSWIP_PCE_VCTRL_VINR_ALL : GSWIP_PCE_VCTRL_VINR_TAGGED;
539
-
regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),
540
-
GSWIP_PCE_VCTRL_VINR,
541
-
FIELD_PREP(GSWIP_PCE_VCTRL_VINR, vinr));
542
-
543
-
/* Note that in GSWIP 2.2 VLAN mode the VID needs to be programmed
544
-
* directly instead of referencing the index in the Active VLAN Tablet.
545
-
* However, without the VLANMD bit (9) in PCE_GCTRL_1 (0x457) even
546
-
* GSWIP 2.2 and newer hardware maintain the GSWIP 2.1 behavior.
547
-
*/
548
-
regmap_write(priv->gswip, GSWIP_PCE_DEFPVID(port), idx);
549
-
}
550
-
551
-
static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
552
-
bool vlan_filtering,
553
-
struct netlink_ext_ack *extack)
554
-
{
555
-
struct gswip_priv *priv = ds->priv;
556
-
557
-
if (vlan_filtering) {
558
-
/* Use tag based VLAN */
559
-
regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),
560
-
GSWIP_PCE_VCTRL_VSR |
561
-
GSWIP_PCE_VCTRL_UVR |
562
-
GSWIP_PCE_VCTRL_VIMR |
563
-
GSWIP_PCE_VCTRL_VEMR |
564
-
GSWIP_PCE_VCTRL_VID0,
565
-
GSWIP_PCE_VCTRL_UVR |
566
-
GSWIP_PCE_VCTRL_VIMR |
567
-
GSWIP_PCE_VCTRL_VEMR |
568
-
GSWIP_PCE_VCTRL_VID0);
569
-
regmap_clear_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),
570
-
GSWIP_PCE_PCTRL_0_TVM);
571
-
} else {
572
-
/* Use port based VLAN */
573
-
regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),
574
-
GSWIP_PCE_VCTRL_UVR |
575
-
GSWIP_PCE_VCTRL_VIMR |
576
-
GSWIP_PCE_VCTRL_VEMR |
577
-
GSWIP_PCE_VCTRL_VID0 |
578
-
GSWIP_PCE_VCTRL_VSR,
579
-
GSWIP_PCE_VCTRL_VSR);
580
-
regmap_set_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),
581
-
GSWIP_PCE_PCTRL_0_TVM);
582
-
}
583
-
584
-
gswip_port_commit_pvid(priv, port);
585
-
586
-
return 0;
587
-
}
588
-
589
-
static int gswip_setup(struct dsa_switch *ds)
590
-
{
591
-
unsigned int cpu_ports = dsa_cpu_ports(ds);
592
-
struct gswip_priv *priv = ds->priv;
593
-
struct dsa_port *cpu_dp;
594
-
int err, i;
595
-
596
-
regmap_write(priv->gswip, GSWIP_SWRES, GSWIP_SWRES_R0);
597
-
usleep_range(5000, 10000);
598
-
regmap_write(priv->gswip, GSWIP_SWRES, 0);
599
-
600
-
/* disable port fetch/store dma on all ports */
601
-
for (i = 0; i < priv->hw_info->max_ports; i++) {
602
-
gswip_port_disable(ds, i);
603
-
gswip_port_vlan_filtering(ds, i, false, NULL);
604
-
}
605
-
606
-
/* enable Switch */
607
-
regmap_set_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE);
608
-
609
-
err = gswip_pce_load_microcode(priv);
610
-
if (err) {
611
-
dev_err(priv->dev, "writing PCE microcode failed, %i\n", err);
612
-
return err;
613
-
}
614
-
615
-
/* Default unknown Broadcast/Multicast/Unicast port maps */
616
-
regmap_write(priv->gswip, GSWIP_PCE_PMAP1, cpu_ports);
617
-
regmap_write(priv->gswip, GSWIP_PCE_PMAP2, cpu_ports);
618
-
regmap_write(priv->gswip, GSWIP_PCE_PMAP3, cpu_ports);
619
-
620
-
/* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
621
-
* interoperability problem with this auto polling mechanism because
622
-
* their status registers think that the link is in a different state
623
-
* than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set
624
-
* as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the
625
-
* auto polling state machine consider the link being negotiated with
626
-
* 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads
627
-
* to the switch port being completely dead (RX and TX are both not
628
-
* working).
629
-
* Also with various other PHY / port combinations (PHY11G GPHY, PHY22F
630
-
* GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes
631
-
* it would work fine for a few minutes to hours and then stop, on
632
-
* other device it would no traffic could be sent or received at all.
633
-
* Testing shows that when PHY auto polling is disabled these problems
634
-
* go away.
635
-
*/
636
-
regmap_write(priv->mdio, GSWIP_MDIO_MDC_CFG0, 0x0);
637
-
638
-
/* Configure the MDIO Clock 2.5 MHz */
639
-
regmap_write_bits(priv->mdio, GSWIP_MDIO_MDC_CFG1, 0xff, 0x09);
640
-
641
-
/* bring up the mdio bus */
642
-
err = gswip_mdio(priv);
643
-
if (err) {
644
-
dev_err(priv->dev, "mdio bus setup failed\n");
645
-
return err;
646
-
}
647
-
648
-
/* Disable the xMII interface and clear it's isolation bit */
649
-
for (i = 0; i < priv->hw_info->max_ports; i++)
650
-
gswip_mii_mask_cfg(priv,
651
-
GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE,
652
-
0, i);
653
-
654
-
dsa_switch_for_each_cpu_port(cpu_dp, ds) {
655
-
/* enable special tag insertion on cpu port */
656
-
regmap_set_bits(priv->gswip, GSWIP_FDMA_PCTRLp(cpu_dp->index),
657
-
GSWIP_FDMA_PCTRL_STEN);
658
-
659
-
/* accept special tag in ingress direction */
660
-
regmap_set_bits(priv->gswip,
661
-
GSWIP_PCE_PCTRL_0p(cpu_dp->index),
662
-
GSWIP_PCE_PCTRL_0_INGRESS);
663
-
}
664
-
665
-
regmap_set_bits(priv->gswip, GSWIP_BM_QUEUE_GCTRL,
666
-
GSWIP_BM_QUEUE_GCTRL_GL_MOD);
667
-
668
-
/* VLAN aware Switching */
669
-
regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0,
670
-
GSWIP_PCE_GCTRL_0_VLAN);
671
-
672
-
/* Flush MAC Table */
673
-
regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0,
674
-
GSWIP_PCE_GCTRL_0_MTFL);
675
-
676
-
err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
677
-
GSWIP_PCE_GCTRL_0_MTFL);
678
-
if (err) {
679
-
dev_err(priv->dev, "MAC flushing didn't finish\n");
680
-
return err;
681
-
}
682
-
683
-
ds->mtu_enforcement_ingress = true;
684
-
685
-
return 0;
686
-
}
687
-
688
-
static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
689
-
int port,
690
-
enum dsa_tag_protocol mp)
691
-
{
692
-
struct gswip_priv *priv = ds->priv;
693
-
694
-
return priv->hw_info->tag_protocol;
695
-
}
696
-
697
-
static int gswip_vlan_active_create(struct gswip_priv *priv,
698
-
struct net_device *bridge,
699
-
int fid, u16 vid)
700
-
{
701
-
struct gswip_pce_table_entry vlan_active = {0,};
702
-
unsigned int max_ports = priv->hw_info->max_ports;
703
-
int idx = -1;
704
-
int err;
705
-
int i;
706
-
707
-
/* Look for a free slot */
708
-
for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
709
-
if (!priv->vlans[i].bridge) {
710
-
idx = i;
711
-
break;
712
-
}
713
-
}
714
-
715
-
if (idx == -1)
716
-
return -ENOSPC;
717
-
718
-
if (fid == -1)
719
-
fid = idx;
720
-
721
-
vlan_active.index = idx;
722
-
vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
723
-
vlan_active.key[0] = vid;
724
-
vlan_active.val[0] = fid;
725
-
vlan_active.valid = true;
726
-
727
-
err = gswip_pce_table_entry_write(priv, &vlan_active);
728
-
if (err) {
729
-
dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
730
-
return err;
731
-
}
732
-
733
-
priv->vlans[idx].bridge = bridge;
734
-
priv->vlans[idx].vid = vid;
735
-
priv->vlans[idx].fid = fid;
736
-
737
-
return idx;
738
-
}
739
-
740
-
static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
741
-
{
742
-
struct gswip_pce_table_entry vlan_active = {0,};
743
-
int err;
744
-
745
-
vlan_active.index = idx;
746
-
vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
747
-
vlan_active.valid = false;
748
-
err = gswip_pce_table_entry_write(priv, &vlan_active);
749
-
if (err)
750
-
dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
751
-
priv->vlans[idx].bridge = NULL;
752
-
753
-
return err;
754
-
}
755
-
756
-
static int gswip_vlan_add(struct gswip_priv *priv, struct net_device *bridge,
757
-
int port, u16 vid, bool untagged, bool pvid,
758
-
bool vlan_aware)
759
-
{
760
-
struct gswip_pce_table_entry vlan_mapping = {0,};
761
-
unsigned int max_ports = priv->hw_info->max_ports;
762
-
unsigned int cpu_ports = dsa_cpu_ports(priv->ds);
763
-
bool active_vlan_created = false;
764
-
int fid = -1, idx = -1;
765
-
int i, err;
766
-
767
-
/* Check if there is already a page for this bridge */
768
-
for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
769
-
if (priv->vlans[i].bridge == bridge) {
770
-
if (vlan_aware) {
771
-
if (fid != -1 && fid != priv->vlans[i].fid)
772
-
dev_err(priv->dev, "one bridge with multiple flow ids\n");
773
-
fid = priv->vlans[i].fid;
774
-
}
775
-
if (priv->vlans[i].vid == vid) {
776
-
idx = i;
777
-
break;
778
-
}
779
-
}
780
-
}
781
-
782
-
/* If this bridge is not programmed yet, add a Active VLAN table
783
-
* entry in a free slot and prepare the VLAN mapping table entry.
784
-
*/
785
-
if (idx == -1) {
786
-
idx = gswip_vlan_active_create(priv, bridge, fid, vid);
787
-
if (idx < 0)
788
-
return idx;
789
-
active_vlan_created = true;
790
-
791
-
vlan_mapping.index = idx;
792
-
vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
793
-
} else {
794
-
/* Read the existing VLAN mapping entry from the switch */
795
-
vlan_mapping.index = idx;
796
-
vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
797
-
err = gswip_pce_table_entry_read(priv, &vlan_mapping);
798
-
if (err) {
799
-
dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
800
-
err);
801
-
return err;
802
-
}
803
-
}
804
-
805
-
/* VLAN ID byte, maps to the VLAN ID of vlan active table */
806
-
vlan_mapping.val[0] = vid;
807
-
/* Update the VLAN mapping entry and write it to the switch */
808
-
vlan_mapping.val[1] |= cpu_ports;
809
-
vlan_mapping.val[1] |= BIT(port);
810
-
if (vlan_aware)
811
-
vlan_mapping.val[2] |= cpu_ports;
812
-
if (untagged)
813
-
vlan_mapping.val[2] &= ~BIT(port);
814
-
else
815
-
vlan_mapping.val[2] |= BIT(port);
816
-
err = gswip_pce_table_entry_write(priv, &vlan_mapping);
817
-
if (err) {
818
-
dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
819
-
/* In case an Active VLAN was creaetd delete it again */
820
-
if (active_vlan_created)
821
-
gswip_vlan_active_remove(priv, idx);
822
-
return err;
823
-
}
824
-
825
-
gswip_port_commit_pvid(priv, port);
826
-
827
-
return 0;
828
-
}
829
-
830
-
static int gswip_vlan_remove(struct gswip_priv *priv,
831
-
struct net_device *bridge, int port,
832
-
u16 vid)
833
-
{
834
-
struct gswip_pce_table_entry vlan_mapping = {0,};
835
-
unsigned int max_ports = priv->hw_info->max_ports;
836
-
int idx = -1;
837
-
int i;
838
-
int err;
839
-
840
-
/* Check if there is already a page for this bridge */
841
-
for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
842
-
if (priv->vlans[i].bridge == bridge &&
843
-
priv->vlans[i].vid == vid) {
844
-
idx = i;
845
-
break;
846
-
}
847
-
}
848
-
849
-
if (idx == -1) {
850
-
dev_err(priv->dev, "Port %d cannot find VID %u of bridge %s\n",
851
-
port, vid, bridge ? bridge->name : "(null)");
852
-
return -ENOENT;
853
-
}
854
-
855
-
vlan_mapping.index = idx;
856
-
vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
857
-
err = gswip_pce_table_entry_read(priv, &vlan_mapping);
858
-
if (err) {
859
-
dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
860
-
return err;
861
-
}
862
-
863
-
vlan_mapping.val[1] &= ~BIT(port);
864
-
vlan_mapping.val[2] &= ~BIT(port);
865
-
err = gswip_pce_table_entry_write(priv, &vlan_mapping);
866
-
if (err) {
867
-
dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
868
-
return err;
869
-
}
870
-
871
-
/* In case all ports are removed from the bridge, remove the VLAN */
872
-
if (!(vlan_mapping.val[1] & ~dsa_cpu_ports(priv->ds))) {
873
-
err = gswip_vlan_active_remove(priv, idx);
874
-
if (err) {
875
-
dev_err(priv->dev, "failed to write active VLAN: %d\n",
876
-
err);
877
-
return err;
878
-
}
879
-
}
880
-
881
-
gswip_port_commit_pvid(priv, port);
882
-
883
-
return 0;
884
-
}
885
-
886
-
static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
887
-
struct dsa_bridge bridge,
888
-
bool *tx_fwd_offload,
889
-
struct netlink_ext_ack *extack)
890
-
{
891
-
struct net_device *br = bridge.dev;
892
-
struct gswip_priv *priv = ds->priv;
893
-
int err;
894
-
895
-
/* Set up the VLAN for VLAN-unaware bridging for this port, and remove
896
-
* it from the "single-port bridge" through which it was operating as
897
-
* standalone.
898
-
*/
899
-
err = gswip_vlan_add(priv, br, port, GSWIP_VLAN_UNAWARE_PVID,
900
-
true, true, false);
901
-
if (err)
902
-
return err;
903
-
904
-
return gswip_add_single_port_br(priv, port, false);
905
-
}
906
-
907
-
static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
908
-
struct dsa_bridge bridge)
909
-
{
910
-
struct net_device *br = bridge.dev;
911
-
struct gswip_priv *priv = ds->priv;
912
-
913
-
/* Add the port back to the "single-port bridge", and remove it from
914
-
* the VLAN-unaware PVID created for this bridge.
915
-
*/
916
-
gswip_add_single_port_br(priv, port, true);
917
-
gswip_vlan_remove(priv, br, port, GSWIP_VLAN_UNAWARE_PVID);
918
-
}
919
-
920
-
static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
921
-
const struct switchdev_obj_port_vlan *vlan,
922
-
struct netlink_ext_ack *extack)
923
-
{
924
-
struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
925
-
struct gswip_priv *priv = ds->priv;
926
-
unsigned int max_ports = priv->hw_info->max_ports;
927
-
int pos = max_ports;
928
-
int i, idx = -1;
929
-
930
-
/* We only support VLAN filtering on bridges */
931
-
if (!dsa_is_cpu_port(ds, port) && !bridge)
932
-
return -EOPNOTSUPP;
933
-
934
-
/* Check if there is already a page for this VLAN */
935
-
for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
936
-
if (priv->vlans[i].bridge == bridge &&
937
-
priv->vlans[i].vid == vlan->vid) {
938
-
idx = i;
939
-
break;
940
-
}
941
-
}
942
-
943
-
/* If this VLAN is not programmed yet, we have to reserve
944
-
* one entry in the VLAN table. Make sure we start at the
945
-
* next position round.
946
-
*/
947
-
if (idx == -1) {
948
-
/* Look for a free slot */
949
-
for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
950
-
if (!priv->vlans[pos].bridge) {
951
-
idx = pos;
952
-
pos++;
953
-
break;
954
-
}
955
-
}
956
-
957
-
if (idx == -1) {
958
-
NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table");
959
-
return -ENOSPC;
960
-
}
961
-
}
962
-
963
-
return 0;
964
-
}
965
-
966
-
static int gswip_port_vlan_add(struct dsa_switch *ds, int port,
967
-
const struct switchdev_obj_port_vlan *vlan,
968
-
struct netlink_ext_ack *extack)
969
-
{
970
-
struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
971
-
struct gswip_priv *priv = ds->priv;
972
-
bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
973
-
bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
974
-
int err;
975
-
976
-
if (vlan->vid == GSWIP_VLAN_UNAWARE_PVID)
977
-
return 0;
978
-
979
-
err = gswip_port_vlan_prepare(ds, port, vlan, extack);
980
-
if (err)
981
-
return err;
982
-
983
-
/* We have to receive all packets on the CPU port and should not
984
-
* do any VLAN filtering here. This is also called with bridge
985
-
* NULL and then we do not know for which bridge to configure
986
-
* this.
987
-
*/
988
-
if (dsa_is_cpu_port(ds, port))
989
-
return 0;
990
-
991
-
return gswip_vlan_add(priv, bridge, port, vlan->vid, untagged, pvid,
992
-
true);
993
-
}
994
-
995
-
static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
996
-
const struct switchdev_obj_port_vlan *vlan)
997
-
{
998
-
struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
999
-
struct gswip_priv *priv = ds->priv;
1000
-
1001
-
if (vlan->vid == GSWIP_VLAN_UNAWARE_PVID)
1002
-
return 0;
1003
-
1004
-
/* We have to receive all packets on the CPU port and should not
1005
-
* do any VLAN filtering here. This is also called with bridge
1006
-
* NULL and then we do not know for which bridge to configure
1007
-
* this.
1008
-
*/
1009
-
if (dsa_is_cpu_port(ds, port))
1010
-
return 0;
1011
-
1012
-
return gswip_vlan_remove(priv, bridge, port, vlan->vid);
1013
-
}
1014
-
1015
-
static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1016
-
{
1017
-
struct gswip_priv *priv = ds->priv;
1018
-
struct gswip_pce_table_entry mac_bridge = {0,};
1019
-
int i;
1020
-
int err;
1021
-
1022
-
for (i = 0; i < 2048; i++) {
1023
-
mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1024
-
mac_bridge.index = i;
1025
-
1026
-
err = gswip_pce_table_entry_read(priv, &mac_bridge);
1027
-
if (err) {
1028
-
dev_err(priv->dev, "failed to read mac bridge: %d\n",
1029
-
err);
1030
-
return;
1031
-
}
1032
-
1033
-
if (!mac_bridge.valid)
1034
-
continue;
1035
-
1036
-
if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC)
1037
-
continue;
1038
-
1039
-
if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT,
1040
-
mac_bridge.val[0]))
1041
-
continue;
1042
-
1043
-
mac_bridge.valid = false;
1044
-
err = gswip_pce_table_entry_write(priv, &mac_bridge);
1045
-
if (err) {
1046
-
dev_err(priv->dev, "failed to write mac bridge: %d\n",
1047
-
err);
1048
-
return;
1049
-
}
1050
-
}
1051
-
}
1052
-
1053
-
static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1054
-
{
1055
-
struct gswip_priv *priv = ds->priv;
1056
-
u32 stp_state;
1057
-
1058
-
switch (state) {
1059
-
case BR_STATE_DISABLED:
1060
-
regmap_clear_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),
1061
-
GSWIP_SDMA_PCTRL_EN);
1062
-
return;
1063
-
case BR_STATE_BLOCKING:
1064
-
case BR_STATE_LISTENING:
1065
-
stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1066
-
break;
1067
-
case BR_STATE_LEARNING:
1068
-
stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1069
-
break;
1070
-
case BR_STATE_FORWARDING:
1071
-
stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1072
-
break;
1073
-
default:
1074
-
dev_err(priv->dev, "invalid STP state: %d\n", state);
1075
-
return;
1076
-
}
1077
-
1078
-
regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),
1079
-
GSWIP_SDMA_PCTRL_EN);
1080
-
regmap_write_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),
1081
-
GSWIP_PCE_PCTRL_0_PSTATE_MASK,
1082
-
stp_state);
1083
-
}
1084
-
1085
-
static int gswip_port_fdb(struct dsa_switch *ds, int port,
1086
-
struct net_device *bridge, const unsigned char *addr,
1087
-
u16 vid, bool add)
1088
-
{
1089
-
struct gswip_priv *priv = ds->priv;
1090
-
struct gswip_pce_table_entry mac_bridge = {0,};
1091
-
unsigned int max_ports = priv->hw_info->max_ports;
1092
-
int fid = -1;
1093
-
int i;
1094
-
int err;
1095
-
1096
-
for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1097
-
if (priv->vlans[i].bridge == bridge) {
1098
-
fid = priv->vlans[i].fid;
1099
-
break;
1100
-
}
1101
-
}
1102
-
1103
-
if (fid == -1) {
1104
-
dev_err(priv->dev, "no FID found for bridge %s\n",
1105
-
bridge->name);
1106
-
return -EINVAL;
1107
-
}
1108
-
1109
-
mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1110
-
mac_bridge.key_mode = true;
1111
-
mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1112
-
mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1113
-
mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1114
-
mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_KEY3_FID, fid);
1115
-
mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1116
-
mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC;
1117
-
mac_bridge.valid = add;
1118
-
1119
-
err = gswip_pce_table_entry_write(priv, &mac_bridge);
1120
-
if (err)
1121
-
dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
1122
-
1123
-
return err;
1124
-
}
1125
-
1126
-
static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1127
-
const unsigned char *addr, u16 vid,
1128
-
struct dsa_db db)
1129
-
{
1130
-
if (db.type != DSA_DB_BRIDGE)
1131
-
return -EOPNOTSUPP;
1132
-
1133
-
return gswip_port_fdb(ds, port, db.bridge.dev, addr, vid, true);
1134
-
}
1135
-
1136
-
static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1137
-
const unsigned char *addr, u16 vid,
1138
-
struct dsa_db db)
1139
-
{
1140
-
if (db.type != DSA_DB_BRIDGE)
1141
-
return -EOPNOTSUPP;
1142
-
1143
-
return gswip_port_fdb(ds, port, db.bridge.dev, addr, vid, false);
1144
-
}
1145
-
1146
-
static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1147
-
dsa_fdb_dump_cb_t *cb, void *data)
1148
-
{
1149
-
struct gswip_priv *priv = ds->priv;
1150
-
struct gswip_pce_table_entry mac_bridge = {0,};
1151
-
unsigned char addr[ETH_ALEN];
1152
-
int i;
1153
-
int err;
1154
-
1155
-
for (i = 0; i < 2048; i++) {
1156
-
mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1157
-
mac_bridge.index = i;
1158
-
1159
-
err = gswip_pce_table_entry_read(priv, &mac_bridge);
1160
-
if (err) {
1161
-
dev_err(priv->dev,
1162
-
"failed to read mac bridge entry %d: %d\n",
1163
-
i, err);
1164
-
return err;
1165
-
}
1166
-
1167
-
if (!mac_bridge.valid)
1168
-
continue;
1169
-
1170
-
addr[5] = mac_bridge.key[0] & 0xff;
1171
-
addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1172
-
addr[3] = mac_bridge.key[1] & 0xff;
1173
-
addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1174
-
addr[1] = mac_bridge.key[2] & 0xff;
1175
-
addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1176
-
if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC) {
1177
-
if (mac_bridge.val[0] & BIT(port)) {
1178
-
err = cb(addr, 0, true, data);
1179
-
if (err)
1180
-
return err;
1181
-
}
1182
-
} else {
1183
-
if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT,
1184
-
mac_bridge.val[0])) {
1185
-
err = cb(addr, 0, false, data);
1186
-
if (err)
1187
-
return err;
1188
-
}
1189
-
}
1190
-
}
1191
-
return 0;
1192
-
}
1193
-
1194
-
static int gswip_port_max_mtu(struct dsa_switch *ds, int port)
1195
-
{
1196
-
/* Includes 8 bytes for special header. */
1197
-
return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN;
1198
-
}
1199
-
1200
-
static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1201
-
{
1202
-
struct gswip_priv *priv = ds->priv;
1203
-
1204
-
/* CPU port always has maximum mtu of user ports, so use it to set
1205
-
* switch frame size, including 8 byte special header.
1206
-
*/
1207
-
if (dsa_is_cpu_port(ds, port)) {
1208
-
new_mtu += 8;
1209
-
regmap_write(priv->gswip, GSWIP_MAC_FLEN,
1210
-
VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN);
1211
-
}
1212
-
1213
-
/* Enable MLEN for ports with non-standard MTUs, including the special
1214
-
* header on the CPU port added above.
1215
-
*/
1216
-
if (new_mtu != ETH_DATA_LEN)
1217
-
regmap_set_bits(priv->gswip, GSWIP_MAC_CTRL_2p(port),
1218
-
GSWIP_MAC_CTRL_2_MLEN);
1219
-
else
1220
-
regmap_clear_bits(priv->gswip, GSWIP_MAC_CTRL_2p(port),
1221
-
GSWIP_MAC_CTRL_2_MLEN);
1222
-
1223
-
return 0;
1224
-
}
1225
31
1226
32
static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port,
1227
33
struct phylink_config *config)
···
96
1290
config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
97
1291
MAC_10 | MAC_100 | MAC_1000;
98
1292
}
99
-
100
-
static void gswip_phylink_get_caps(struct dsa_switch *ds, int port,
101
-
struct phylink_config *config)
102
-
{
103
-
struct gswip_priv *priv = ds->priv;
104
-
105
-
priv->hw_info->phylink_get_caps(ds, port, config);
106
-
}
107
-
108
-
static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
109
-
{
110
-
u32 mdio_phy;
111
-
112
-
if (link)
113
-
mdio_phy = GSWIP_MDIO_PHY_LINK_UP;
114
-
else
115
-
mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;
116
-
117
-
regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
118
-
GSWIP_MDIO_PHY_LINK_MASK, mdio_phy);
119
-
}
120
-
121
-
static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
122
-
phy_interface_t interface)
123
-
{
124
-
u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0;
125
-
126
-
switch (speed) {
127
-
case SPEED_10:
128
-
mdio_phy = GSWIP_MDIO_PHY_SPEED_M10;
129
-
130
-
if (interface == PHY_INTERFACE_MODE_RMII)
131
-
mii_cfg = GSWIP_MII_CFG_RATE_M50;
132
-
else
133
-
mii_cfg = GSWIP_MII_CFG_RATE_M2P5;
134
-
135
-
mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
136
-
break;
137
-
138
-
case SPEED_100:
139
-
mdio_phy = GSWIP_MDIO_PHY_SPEED_M100;
140
-
141
-
if (interface == PHY_INTERFACE_MODE_RMII)
142
-
mii_cfg = GSWIP_MII_CFG_RATE_M50;
143
-
else
144
-
mii_cfg = GSWIP_MII_CFG_RATE_M25;
145
-
146
-
mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
147
-
break;
148
-
149
-
case SPEED_1000:
150
-
mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
151
-
152
-
mii_cfg = GSWIP_MII_CFG_RATE_M125;
153
-
154
-
mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII;
155
-
break;
156
-
}
157
-
158
-
regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
159
-
GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy);
160
-
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);
161
-
regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),
162
-
GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0);
163
-
}
164
-
165
-
static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
166
-
{
167
-
u32 mac_ctrl_0, mdio_phy;
168
-
169
-
if (duplex == DUPLEX_FULL) {
170
-
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN;
171
-
mdio_phy = GSWIP_MDIO_PHY_FDUP_EN;
172
-
} else {
173
-
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS;
174
-
mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;
175
-
}
176
-
177
-
regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),
178
-
GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0);
179
-
regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
180
-
GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy);
181
-
}
182
-
183
-
static void gswip_port_set_pause(struct gswip_priv *priv, int port,
184
-
bool tx_pause, bool rx_pause)
185
-
{
186
-
u32 mac_ctrl_0, mdio_phy;
187
-
188
-
if (tx_pause && rx_pause) {
189
-
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX;
190
-
mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
191
-
GSWIP_MDIO_PHY_FCONRX_EN;
192
-
} else if (tx_pause) {
193
-
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX;
194
-
mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
195
-
GSWIP_MDIO_PHY_FCONRX_DIS;
196
-
} else if (rx_pause) {
197
-
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX;
198
-
mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
199
-
GSWIP_MDIO_PHY_FCONRX_EN;
200
-
} else {
201
-
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE;
202
-
mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
203
-
GSWIP_MDIO_PHY_FCONRX_DIS;
204
-
}
205
-
206
-
regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),
207
-
GSWIP_MAC_CTRL_0_FCON_MASK, mac_ctrl_0);
208
-
regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
209
-
GSWIP_MDIO_PHY_FCONTX_MASK | GSWIP_MDIO_PHY_FCONRX_MASK,
210
-
mdio_phy);
211
-
}
212
-
213
-
static void gswip_phylink_mac_config(struct phylink_config *config,
214
-
unsigned int mode,
215
-
const struct phylink_link_state *state)
216
-
{
217
-
struct dsa_port *dp = dsa_phylink_to_port(config);
218
-
struct gswip_priv *priv = dp->ds->priv;
219
-
int port = dp->index;
220
-
u32 miicfg = 0;
221
-
222
-
miicfg |= GSWIP_MII_CFG_LDCLKDIS;
223
-
224
-
switch (state->interface) {
225
-
case PHY_INTERFACE_MODE_SGMII:
226
-
case PHY_INTERFACE_MODE_1000BASEX:
227
-
case PHY_INTERFACE_MODE_2500BASEX:
228
-
return;
229
-
case PHY_INTERFACE_MODE_MII:
230
-
case PHY_INTERFACE_MODE_INTERNAL:
231
-
miicfg |= GSWIP_MII_CFG_MODE_MIIM;
232
-
break;
233
-
case PHY_INTERFACE_MODE_REVMII:
234
-
miicfg |= GSWIP_MII_CFG_MODE_MIIP;
235
-
break;
236
-
case PHY_INTERFACE_MODE_RMII:
237
-
miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
238
-
break;
239
-
case PHY_INTERFACE_MODE_RGMII:
240
-
case PHY_INTERFACE_MODE_RGMII_ID:
241
-
case PHY_INTERFACE_MODE_RGMII_RXID:
242
-
case PHY_INTERFACE_MODE_RGMII_TXID:
243
-
miicfg |= GSWIP_MII_CFG_MODE_RGMII;
244
-
break;
245
-
case PHY_INTERFACE_MODE_GMII:
246
-
miicfg |= GSWIP_MII_CFG_MODE_GMII;
247
-
break;
248
-
default:
249
-
dev_err(dp->ds->dev,
250
-
"Unsupported interface: %d\n", state->interface);
251
-
return;
252
-
}
253
-
254
-
gswip_mii_mask_cfg(priv,
255
-
GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK |
256
-
GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS,
257
-
miicfg, port);
258
-
259
-
switch (state->interface) {
260
-
case PHY_INTERFACE_MODE_RGMII_ID:
261
-
gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK |
262
-
GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
263
-
break;
264
-
case PHY_INTERFACE_MODE_RGMII_RXID:
265
-
gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
266
-
break;
267
-
case PHY_INTERFACE_MODE_RGMII_TXID:
268
-
gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port);
269
-
break;
270
-
default:
271
-
break;
272
-
}
273
-
}
274
-
275
-
static void gswip_phylink_mac_link_down(struct phylink_config *config,
276
-
unsigned int mode,
277
-
phy_interface_t interface)
278
-
{
279
-
struct dsa_port *dp = dsa_phylink_to_port(config);
280
-
struct gswip_priv *priv = dp->ds->priv;
281
-
int port = dp->index;
282
-
283
-
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
284
-
285
-
if (!dsa_port_is_cpu(dp))
286
-
gswip_port_set_link(priv, port, false);
287
-
}
288
-
289
-
static void gswip_phylink_mac_link_up(struct phylink_config *config,
290
-
struct phy_device *phydev,
291
-
unsigned int mode,
292
-
phy_interface_t interface,
293
-
int speed, int duplex,
294
-
bool tx_pause, bool rx_pause)
295
-
{
296
-
struct dsa_port *dp = dsa_phylink_to_port(config);
297
-
struct gswip_priv *priv = dp->ds->priv;
298
-
int port = dp->index;
299
-
300
-
if (!dsa_port_is_cpu(dp)) {
301
-
gswip_port_set_link(priv, port, true);
302
-
gswip_port_set_speed(priv, port, speed, interface);
303
-
gswip_port_set_duplex(priv, port, duplex);
304
-
gswip_port_set_pause(priv, port, tx_pause, rx_pause);
305
-
}
306
-
307
-
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, GSWIP_MII_CFG_EN, port);
308
-
}
309
-
310
-
static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
311
-
uint8_t *data)
312
-
{
313
-
int i;
314
-
315
-
if (stringset != ETH_SS_STATS)
316
-
return;
317
-
318
-
for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
319
-
ethtool_puts(&data, gswip_rmon_cnt[i].name);
320
-
}
321
-
322
-
static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
323
-
u32 index)
324
-
{
325
-
u32 result, val;
326
-
int err;
327
-
328
-
regmap_write(priv->gswip, GSWIP_BM_RAM_ADDR, index);
329
-
regmap_write_bits(priv->gswip, GSWIP_BM_RAM_CTRL,
330
-
GSWIP_BM_RAM_CTRL_ADDR_MASK | GSWIP_BM_RAM_CTRL_OPMOD |
331
-
GSWIP_BM_RAM_CTRL_BAS,
332
-
table | GSWIP_BM_RAM_CTRL_BAS);
333
-
334
-
err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
335
-
GSWIP_BM_RAM_CTRL_BAS);
336
-
if (err) {
337
-
dev_err(priv->dev, "timeout while reading table: %u, index: %u\n",
338
-
table, index);
339
-
return 0;
340
-
}
341
-
342
-
regmap_read(priv->gswip, GSWIP_BM_RAM_VAL(0), &result);
343
-
regmap_read(priv->gswip, GSWIP_BM_RAM_VAL(1), &val);
344
-
result |= val << 16;
345
-
346
-
return result;
347
-
}
348
-
349
-
static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
350
-
uint64_t *data)
351
-
{
352
-
struct gswip_priv *priv = ds->priv;
353
-
const struct gswip_rmon_cnt_desc *rmon_cnt;
354
-
int i;
355
-
u64 high;
356
-
357
-
for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
358
-
rmon_cnt = &gswip_rmon_cnt[i];
359
-
360
-
data[i] = gswip_bcm_ram_entry_read(priv, port,
361
-
rmon_cnt->offset);
362
-
if (rmon_cnt->size == 2) {
363
-
high = gswip_bcm_ram_entry_read(priv, port,
364
-
rmon_cnt->offset + 1);
365
-
data[i] |= high << 32;
366
-
}
367
-
}
368
-
}
369
-
370
-
static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
371
-
{
372
-
if (sset != ETH_SS_STATS)
373
-
return 0;
374
-
375
-
return ARRAY_SIZE(gswip_rmon_cnt);
376
-
}
377
-
378
-
static struct phylink_pcs *gswip_phylink_mac_select_pcs(struct phylink_config *config,
379
-
phy_interface_t interface)
380
-
{
381
-
struct dsa_port *dp = dsa_phylink_to_port(config);
382
-
struct gswip_priv *priv = dp->ds->priv;
383
-
384
-
if (priv->hw_info->mac_select_pcs)
385
-
return priv->hw_info->mac_select_pcs(config, interface);
386
-
387
-
return NULL;
388
-
}
389
-
390
-
static const struct phylink_mac_ops gswip_phylink_mac_ops = {
391
-
.mac_config = gswip_phylink_mac_config,
392
-
.mac_link_down = gswip_phylink_mac_link_down,
393
-
.mac_link_up = gswip_phylink_mac_link_up,
394
-
.mac_select_pcs = gswip_phylink_mac_select_pcs,
395
-
};
396
-
397
-
static const struct dsa_switch_ops gswip_switch_ops = {
398
-
.get_tag_protocol = gswip_get_tag_protocol,
399
-
.setup = gswip_setup,
400
-
.port_setup = gswip_port_setup,
401
-
.port_enable = gswip_port_enable,
402
-
.port_disable = gswip_port_disable,
403
-
.port_bridge_join = gswip_port_bridge_join,
404
-
.port_bridge_leave = gswip_port_bridge_leave,
405
-
.port_fast_age = gswip_port_fast_age,
406
-
.port_vlan_filtering = gswip_port_vlan_filtering,
407
-
.port_vlan_add = gswip_port_vlan_add,
408
-
.port_vlan_del = gswip_port_vlan_del,
409
-
.port_stp_state_set = gswip_port_stp_state_set,
410
-
.port_fdb_add = gswip_port_fdb_add,
411
-
.port_fdb_del = gswip_port_fdb_del,
412
-
.port_fdb_dump = gswip_port_fdb_dump,
413
-
.port_change_mtu = gswip_port_change_mtu,
414
-
.port_max_mtu = gswip_port_max_mtu,
415
-
.phylink_get_caps = gswip_phylink_get_caps,
416
-
.get_strings = gswip_get_strings,
417
-
.get_ethtool_stats = gswip_get_ethtool_stats,
418
-
.get_sset_count = gswip_get_sset_count,
419
-
};
420
1293
421
1294
static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
422
1295
.fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
···
317
1832
return err;
318
1833
}
319
1834
320
-
static int gswip_validate_cpu_port(struct dsa_switch *ds)
321
-
{
322
-
struct gswip_priv *priv = ds->priv;
323
-
struct dsa_port *cpu_dp;
324
-
int cpu_port = -1;
325
-
326
-
dsa_switch_for_each_cpu_port(cpu_dp, ds) {
327
-
if (cpu_port != -1)
328
-
return dev_err_probe(ds->dev, -EINVAL,
329
-
"only a single CPU port is supported\n");
330
-
331
-
cpu_port = cpu_dp->index;
332
-
}
333
-
334
-
if (cpu_port == -1)
335
-
return dev_err_probe(ds->dev, -EINVAL, "no CPU port defined\n");
336
-
337
-
if (BIT(cpu_port) & ~priv->hw_info->allowed_cpu_ports)
338
-
return dev_err_probe(ds->dev, -EINVAL,
339
-
"unsupported CPU port defined\n");
340
-
341
-
return 0;
342
-
}
343
-
344
1835
static const struct regmap_config sw_regmap_config = {
345
1836
.name = "switch",
346
1837
.reg_bits = 32,
···
390
1929
if (!priv->ds)
391
1930
return -ENOMEM;
392
1931
393
-
priv->ds->dev = dev;
394
-
priv->ds->num_ports = priv->hw_info->max_ports;
395
-
priv->ds->priv = priv;
396
-
priv->ds->ops = &gswip_switch_ops;
397
-
priv->ds->phylink_mac_ops = &gswip_phylink_mac_ops;
398
1932
priv->dev = dev;
399
-
mutex_init(&priv->pce_table_lock);
400
-
regmap_read(priv->gswip, GSWIP_VERSION, &version);
401
1933
402
-
/* The hardware has the 'major/minor' version bytes in the wrong order
403
-
* preventing numerical comparisons. Construct a 16-bit unsigned integer
404
-
* having the REV field as most significant byte and the MOD field as
405
-
* least significant byte. This is effectively swapping the two bytes of
406
-
* the version variable, but other than using swab16 it doesn't affect
407
-
* the source variable.
408
-
*/
409
-
priv->version = GSWIP_VERSION_REV(version) << 8 |
410
-
GSWIP_VERSION_MOD(version);
1934
+
regmap_read(priv->gswip, GSWIP_VERSION, &version);
411
1935
412
1936
np = dev->of_node;
413
1937
switch (version) {
···
422
1976
"gphy fw probe failed\n");
423
1977
}
424
1978
425
-
err = dsa_register_switch(priv->ds);
426
-
if (err) {
427
-
dev_err_probe(dev, err, "dsa switch registration failed\n");
428
-
goto gphy_fw_remove;
429
-
}
430
-
431
-
err = gswip_validate_cpu_port(priv->ds);
1979
+
err = gswip_probe_common(priv, version);
432
1980
if (err)
433
-
goto disable_switch;
1981
+
goto gphy_fw_remove;
434
1982
435
1983
platform_set_drvdata(pdev, priv);
436
1984
437
-
dev_info(dev, "probed GSWIP version %lx mod %lx\n",
438
-
GSWIP_VERSION_REV(version), GSWIP_VERSION_MOD(version));
439
1985
return 0;
440
1986
441
-
disable_switch:
442
-
regmap_clear_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE);
443
-
dsa_unregister_switch(priv->ds);
444
1987
gphy_fw_remove:
445
1988
for (i = 0; i < priv->num_gphy_fw; i++)
446
1989
gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
···
445
2010
return;
446
2011
447
2012
/* disable the switch */
448
-
regmap_clear_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE);
2013
+
gswip_disable_switch(priv);
449
2014
450
2015
dsa_unregister_switch(priv->ds);
451
2016
+20
drivers/net/dsa/lantiq/lantiq_gswip.h
+20
drivers/net/dsa/lantiq/lantiq_gswip.h
···
2
2
#ifndef __LANTIQ_GSWIP_H
3
3
#define __LANTIQ_GSWIP_H
4
4
5
+
#include <linux/bitfield.h>
5
6
#include <linux/clk.h>
6
7
#include <linux/mutex.h>
7
8
#include <linux/phylink.h>
···
82
81
#define GSWIP_MII_PCDU5 0x05
83
82
#define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
84
83
#define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
84
+
#define GSWIP_MII_PCDU_TXDLY(x) u16_encode_bits(((x) / 500), GSWIP_MII_PCDU_TXDLY_MASK)
85
+
#define GSWIP_MII_PCDU_RXDLY(x) u16_encode_bits(((x) / 500), GSWIP_MII_PCDU_RXDLY_MASK)
86
+
#define GSWIP_MII_PCDU_RXDLY_DEFAULT 2000 /* picoseconds */
87
+
#define GSWIP_MII_PCDU_TXDLY_DEFAULT 2000 /* picoseconds */
85
88
86
89
/* GSWIP Core Registers */
87
90
#define GSWIP_SWRES 0x000
···
162
157
#define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
163
158
#define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
164
159
#define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
160
+
/* Ethernet Switch PCE Port Control Register 3 */
161
+
#define GSWIP_PCE_PCTRL_3p(p) (0x483 + ((p) * 0xA))
162
+
#define GSWIP_PCE_PCTRL_3_LNDIS BIT(15) /* Learning Disable */
165
163
#define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
166
164
#define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
167
165
#define GSWIP_PCE_VCTRL_VINR GENMASK(2, 1) /* VLAN Ingress Tag Rule */
···
198
190
#define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
199
191
#define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */
200
192
#define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
193
+
#define GSWIP_MAC_CTRL_4p(p) (0x907 + ((p) * 0xC))
194
+
#define GSWIP_MAC_CTRL_4_LPIEN BIT(7) /* LPI Mode Enable */
195
+
#define GSWIP_MAC_CTRL_4_GWAIT_MASK GENMASK(14, 8) /* LPI Wait Time 1G */
196
+
#define GSWIP_MAC_CTRL_4_GWAIT(t) u16_encode_bits((t), GSWIP_MAC_CTRL_4_GWAIT_MASK)
197
+
#define GSWIP_MAC_CTRL_4_WAIT_MASK GENMASK(6, 0) /* LPI Wait Time 100M */
198
+
#define GSWIP_MAC_CTRL_4_WAIT(t) u16_encode_bits((t), GSWIP_MAC_CTRL_4_WAIT_MASK)
201
199
202
200
/* Ethernet Switch Fetch DMA Port Control Register */
203
201
#define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
···
228
214
#define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0) /* Filtering identifier */
229
215
#define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned entries */
230
216
#define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0) /* Static, non-aging entry */
217
+
#define GSWIP_TABLE_MAC_BRIDGE_VAL1_VALID BIT(1) /* Valid bit */
231
218
232
219
#define XRX200_GPHY_FW_ALIGN (16 * 1024)
233
220
···
255
240
unsigned int allowed_cpu_ports;
256
241
unsigned int mii_ports;
257
242
int mii_port_reg_offset;
243
+
bool supports_2500m;
258
244
const struct gswip_pce_microcode (*pce_microcode)[];
259
245
size_t pce_microcode_size;
260
246
enum dsa_tag_protocol tag_protocol;
···
293
277
struct mutex pce_table_lock;
294
278
u16 version;
295
279
};
280
+
281
+
void gswip_disable_switch(struct gswip_priv *priv);
282
+
283
+
int gswip_probe_common(struct gswip_priv *priv, u32 version);
296
284
297
285
#endif /* __LANTIQ_GSWIP_H */
+1737
drivers/net/dsa/lantiq/lantiq_gswip_common.c
+1737
drivers/net/dsa/lantiq/lantiq_gswip_common.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Lantiq / Intel / MaxLinear GSWIP common function library
4
+
*
5
+
* Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
6
+
* Copyright (C) 2023 - 2024 MaxLinear Inc.
7
+
* Copyright (C) 2022 Snap One, LLC. All rights reserved.
8
+
* Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
9
+
* Copyright (C) 2012 John Crispin <john@phrozen.org>
10
+
* Copyright (C) 2010 Lantiq Deutschland
11
+
*
12
+
* The VLAN and bridge model the GSWIP hardware uses does not directly
13
+
* matches the model DSA uses.
14
+
*
15
+
* The hardware has 64 possible table entries for bridges with one VLAN
16
+
* ID, one flow id and a list of ports for each bridge. All entries which
17
+
* match the same flow ID are combined in the mac learning table, they
18
+
* act as one global bridge.
19
+
* The hardware does not support VLAN filter on the port, but on the
20
+
* bridge, this driver converts the DSA model to the hardware.
21
+
*
22
+
* The CPU gets all the exception frames which do not match any forwarding
23
+
* rule and the CPU port is also added to all bridges. This makes it possible
24
+
* to handle all the special cases easily in software.
25
+
* At the initialization the driver allocates one bridge table entry for
26
+
* each switch port which is used when the port is used without an
27
+
* explicit bridge. This prevents the frames from being forwarded
28
+
* between all LAN ports by default.
29
+
*/
30
+
31
+
#include "lantiq_gswip.h"
32
+
33
+
#include <linux/delay.h>
34
+
#include <linux/etherdevice.h>
35
+
#include <linux/if_bridge.h>
36
+
#include <linux/if_vlan.h>
37
+
#include <linux/iopoll.h>
38
+
#include <linux/module.h>
39
+
#include <linux/of_mdio.h>
40
+
#include <linux/of_net.h>
41
+
#include <linux/phy.h>
42
+
#include <linux/phylink.h>
43
+
#include <linux/regmap.h>
44
+
#include <net/dsa.h>
45
+
46
+
struct gswip_pce_table_entry {
47
+
u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
48
+
u16 table; // PCE_TBL_CTRL.ADDR = pData->table
49
+
u16 key[8];
50
+
u16 val[5];
51
+
u16 mask;
52
+
u8 gmap;
53
+
bool type;
54
+
bool valid;
55
+
bool key_mode;
56
+
};
57
+
58
+
struct gswip_rmon_cnt_desc {
59
+
unsigned int size;
60
+
unsigned int offset;
61
+
const char *name;
62
+
};
63
+
64
+
#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
65
+
66
+
static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
67
+
/** Receive Packet Count (only packets that are accepted and not discarded). */
68
+
MIB_DESC(1, 0x1F, "RxGoodPkts"),
69
+
MIB_DESC(1, 0x23, "RxUnicastPkts"),
70
+
MIB_DESC(1, 0x22, "RxMulticastPkts"),
71
+
MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
72
+
MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
73
+
MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
74
+
MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
75
+
MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
76
+
MIB_DESC(1, 0x20, "RxGoodPausePkts"),
77
+
MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
78
+
MIB_DESC(1, 0x12, "Rx64BytePkts"),
79
+
MIB_DESC(1, 0x13, "Rx127BytePkts"),
80
+
MIB_DESC(1, 0x14, "Rx255BytePkts"),
81
+
MIB_DESC(1, 0x15, "Rx511BytePkts"),
82
+
MIB_DESC(1, 0x16, "Rx1023BytePkts"),
83
+
/** Receive Size 1024-1522 (or more, if configured) Packet Count. */
84
+
MIB_DESC(1, 0x17, "RxMaxBytePkts"),
85
+
MIB_DESC(1, 0x18, "RxDroppedPkts"),
86
+
MIB_DESC(1, 0x19, "RxFilteredPkts"),
87
+
MIB_DESC(2, 0x24, "RxGoodBytes"),
88
+
MIB_DESC(2, 0x26, "RxBadBytes"),
89
+
MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
90
+
MIB_DESC(1, 0x0C, "TxGoodPkts"),
91
+
MIB_DESC(1, 0x06, "TxUnicastPkts"),
92
+
MIB_DESC(1, 0x07, "TxMulticastPkts"),
93
+
MIB_DESC(1, 0x00, "Tx64BytePkts"),
94
+
MIB_DESC(1, 0x01, "Tx127BytePkts"),
95
+
MIB_DESC(1, 0x02, "Tx255BytePkts"),
96
+
MIB_DESC(1, 0x03, "Tx511BytePkts"),
97
+
MIB_DESC(1, 0x04, "Tx1023BytePkts"),
98
+
/** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
99
+
MIB_DESC(1, 0x05, "TxMaxBytePkts"),
100
+
MIB_DESC(1, 0x08, "TxSingleCollCount"),
101
+
MIB_DESC(1, 0x09, "TxMultCollCount"),
102
+
MIB_DESC(1, 0x0A, "TxLateCollCount"),
103
+
MIB_DESC(1, 0x0B, "TxExcessCollCount"),
104
+
MIB_DESC(1, 0x0D, "TxPauseCount"),
105
+
MIB_DESC(1, 0x10, "TxDroppedPkts"),
106
+
MIB_DESC(2, 0x0E, "TxGoodBytes"),
107
+
};
108
+
109
+
static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
110
+
u32 cleared)
111
+
{
112
+
u32 val;
113
+
114
+
return regmap_read_poll_timeout(priv->gswip, offset, val,
115
+
!(val & cleared), 20, 50000);
116
+
}
117
+
118
+
static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 mask, u32 set,
119
+
int port)
120
+
{
121
+
int reg_port;
122
+
123
+
/* MII_CFG register only exists for MII ports */
124
+
if (!(priv->hw_info->mii_ports & BIT(port)))
125
+
return;
126
+
127
+
reg_port = port + priv->hw_info->mii_port_reg_offset;
128
+
129
+
regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), mask,
130
+
set);
131
+
}
132
+
133
+
static int gswip_mdio_poll(struct gswip_priv *priv)
134
+
{
135
+
u32 ctrl;
136
+
137
+
return regmap_read_poll_timeout(priv->mdio, GSWIP_MDIO_CTRL, ctrl,
138
+
!(ctrl & GSWIP_MDIO_CTRL_BUSY), 40, 4000);
139
+
}
140
+
141
+
static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
142
+
{
143
+
struct gswip_priv *priv = bus->priv;
144
+
int err;
145
+
146
+
err = gswip_mdio_poll(priv);
147
+
if (err) {
148
+
dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
149
+
return err;
150
+
}
151
+
152
+
regmap_write(priv->mdio, GSWIP_MDIO_WRITE, val);
153
+
regmap_write(priv->mdio, GSWIP_MDIO_CTRL,
154
+
GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
155
+
((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
156
+
(reg & GSWIP_MDIO_CTRL_REGAD_MASK));
157
+
158
+
return 0;
159
+
}
160
+
161
+
static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
162
+
{
163
+
struct gswip_priv *priv = bus->priv;
164
+
u32 val;
165
+
int err;
166
+
167
+
err = gswip_mdio_poll(priv);
168
+
if (err) {
169
+
dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
170
+
return err;
171
+
}
172
+
173
+
regmap_write(priv->mdio, GSWIP_MDIO_CTRL,
174
+
GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
175
+
((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
176
+
(reg & GSWIP_MDIO_CTRL_REGAD_MASK));
177
+
178
+
err = gswip_mdio_poll(priv);
179
+
if (err) {
180
+
dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
181
+
return err;
182
+
}
183
+
184
+
err = regmap_read(priv->mdio, GSWIP_MDIO_READ, &val);
185
+
if (err)
186
+
return err;
187
+
188
+
return val;
189
+
}
190
+
191
+
static int gswip_mdio(struct gswip_priv *priv)
192
+
{
193
+
struct device_node *mdio_np, *switch_np = priv->dev->of_node;
194
+
struct device *dev = priv->dev;
195
+
struct mii_bus *bus;
196
+
int err = 0;
197
+
198
+
mdio_np = of_get_compatible_child(switch_np, "lantiq,xrx200-mdio");
199
+
if (!mdio_np)
200
+
mdio_np = of_get_child_by_name(switch_np, "mdio");
201
+
202
+
if (!of_device_is_available(mdio_np))
203
+
goto out_put_node;
204
+
205
+
bus = devm_mdiobus_alloc(dev);
206
+
if (!bus) {
207
+
err = -ENOMEM;
208
+
goto out_put_node;
209
+
}
210
+
211
+
bus->priv = priv;
212
+
bus->read = gswip_mdio_rd;
213
+
bus->write = gswip_mdio_wr;
214
+
bus->name = "lantiq,xrx200-mdio";
215
+
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev));
216
+
bus->parent = priv->dev;
217
+
218
+
err = devm_of_mdiobus_register(dev, bus, mdio_np);
219
+
220
+
out_put_node:
221
+
of_node_put(mdio_np);
222
+
223
+
return err;
224
+
}
225
+
226
+
static int gswip_pce_table_entry_read(struct gswip_priv *priv,
227
+
struct gswip_pce_table_entry *tbl)
228
+
{
229
+
int i;
230
+
int err;
231
+
u32 crtl;
232
+
u32 tmp;
233
+
u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
234
+
GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
235
+
236
+
mutex_lock(&priv->pce_table_lock);
237
+
238
+
err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
239
+
GSWIP_PCE_TBL_CTRL_BAS);
240
+
if (err)
241
+
goto out_unlock;
242
+
243
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index);
244
+
regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
245
+
GSWIP_PCE_TBL_CTRL_ADDR_MASK |
246
+
GSWIP_PCE_TBL_CTRL_OPMOD_MASK |
247
+
GSWIP_PCE_TBL_CTRL_BAS,
248
+
tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS);
249
+
250
+
err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
251
+
GSWIP_PCE_TBL_CTRL_BAS);
252
+
if (err)
253
+
goto out_unlock;
254
+
255
+
for (i = 0; i < ARRAY_SIZE(tbl->key); i++) {
256
+
err = regmap_read(priv->gswip, GSWIP_PCE_TBL_KEY(i), &tmp);
257
+
if (err)
258
+
goto out_unlock;
259
+
tbl->key[i] = tmp;
260
+
}
261
+
for (i = 0; i < ARRAY_SIZE(tbl->val); i++) {
262
+
err = regmap_read(priv->gswip, GSWIP_PCE_TBL_VAL(i), &tmp);
263
+
if (err)
264
+
goto out_unlock;
265
+
tbl->val[i] = tmp;
266
+
}
267
+
268
+
err = regmap_read(priv->gswip, GSWIP_PCE_TBL_MASK, &tmp);
269
+
if (err)
270
+
goto out_unlock;
271
+
272
+
tbl->mask = tmp;
273
+
err = regmap_read(priv->gswip, GSWIP_PCE_TBL_CTRL, &crtl);
274
+
if (err)
275
+
goto out_unlock;
276
+
277
+
tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
278
+
tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
279
+
tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
280
+
281
+
out_unlock:
282
+
mutex_unlock(&priv->pce_table_lock);
283
+
284
+
return err;
285
+
}
286
+
287
+
static int gswip_pce_table_entry_write(struct gswip_priv *priv,
288
+
struct gswip_pce_table_entry *tbl)
289
+
{
290
+
int i;
291
+
int err;
292
+
u32 crtl;
293
+
u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
294
+
GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
295
+
296
+
mutex_lock(&priv->pce_table_lock);
297
+
298
+
err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
299
+
GSWIP_PCE_TBL_CTRL_BAS);
300
+
if (err) {
301
+
mutex_unlock(&priv->pce_table_lock);
302
+
return err;
303
+
}
304
+
305
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index);
306
+
regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
307
+
GSWIP_PCE_TBL_CTRL_ADDR_MASK |
308
+
GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
309
+
tbl->table | addr_mode);
310
+
311
+
for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
312
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_KEY(i), tbl->key[i]);
313
+
314
+
for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
315
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(i), tbl->val[i]);
316
+
317
+
regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
318
+
GSWIP_PCE_TBL_CTRL_ADDR_MASK |
319
+
GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
320
+
tbl->table | addr_mode);
321
+
322
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, tbl->mask);
323
+
324
+
regmap_read(priv->gswip, GSWIP_PCE_TBL_CTRL, &crtl);
325
+
crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
326
+
GSWIP_PCE_TBL_CTRL_GMAP_MASK);
327
+
if (tbl->type)
328
+
crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
329
+
if (tbl->valid)
330
+
crtl |= GSWIP_PCE_TBL_CTRL_VLD;
331
+
crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
332
+
crtl |= GSWIP_PCE_TBL_CTRL_BAS;
333
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_CTRL, crtl);
334
+
335
+
err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
336
+
GSWIP_PCE_TBL_CTRL_BAS);
337
+
338
+
mutex_unlock(&priv->pce_table_lock);
339
+
340
+
return err;
341
+
}
342
+
343
+
/* Add the LAN port into a bridge with the CPU port by
344
+
* default. This prevents automatic forwarding of
345
+
* packages between the LAN ports when no explicit
346
+
* bridge is configured.
347
+
*/
348
+
static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
349
+
{
350
+
struct gswip_pce_table_entry vlan_active = {0,};
351
+
struct gswip_pce_table_entry vlan_mapping = {0,};
352
+
int err;
353
+
354
+
vlan_active.index = port + 1;
355
+
vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
356
+
vlan_active.key[0] = GSWIP_VLAN_UNAWARE_PVID;
357
+
vlan_active.val[0] = port + 1 /* fid */;
358
+
vlan_active.valid = add;
359
+
err = gswip_pce_table_entry_write(priv, &vlan_active);
360
+
if (err) {
361
+
dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
362
+
return err;
363
+
}
364
+
365
+
if (!add)
366
+
return 0;
367
+
368
+
vlan_mapping.index = port + 1;
369
+
vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
370
+
vlan_mapping.val[0] = GSWIP_VLAN_UNAWARE_PVID;
371
+
vlan_mapping.val[1] = BIT(port) | dsa_cpu_ports(priv->ds);
372
+
vlan_mapping.val[2] = 0;
373
+
err = gswip_pce_table_entry_write(priv, &vlan_mapping);
374
+
if (err) {
375
+
dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
376
+
return err;
377
+
}
378
+
379
+
return 0;
380
+
}
381
+
382
+
static int gswip_port_set_learning(struct gswip_priv *priv, int port,
383
+
bool enable)
384
+
{
385
+
if (!GSWIP_VERSION_GE(priv, GSWIP_VERSION_2_2))
386
+
return -EOPNOTSUPP;
387
+
388
+
/* learning disable bit */
389
+
return regmap_update_bits(priv->gswip, GSWIP_PCE_PCTRL_3p(port),
390
+
GSWIP_PCE_PCTRL_3_LNDIS,
391
+
enable ? 0 : GSWIP_PCE_PCTRL_3_LNDIS);
392
+
}
393
+
394
+
static int gswip_port_pre_bridge_flags(struct dsa_switch *ds, int port,
395
+
struct switchdev_brport_flags flags,
396
+
struct netlink_ext_ack *extack)
397
+
{
398
+
struct gswip_priv *priv = ds->priv;
399
+
unsigned long supported = 0;
400
+
401
+
if (GSWIP_VERSION_GE(priv, GSWIP_VERSION_2_2))
402
+
supported |= BR_LEARNING;
403
+
404
+
if (flags.mask & ~supported)
405
+
return -EINVAL;
406
+
407
+
return 0;
408
+
}
409
+
410
+
static int gswip_port_bridge_flags(struct dsa_switch *ds, int port,
411
+
struct switchdev_brport_flags flags,
412
+
struct netlink_ext_ack *extack)
413
+
{
414
+
struct gswip_priv *priv = ds->priv;
415
+
416
+
if (flags.mask & BR_LEARNING)
417
+
return gswip_port_set_learning(priv, port,
418
+
!!(flags.val & BR_LEARNING));
419
+
420
+
return 0;
421
+
}
422
+
423
+
static int gswip_port_setup(struct dsa_switch *ds, int port)
424
+
{
425
+
struct gswip_priv *priv = ds->priv;
426
+
int err;
427
+
428
+
if (!dsa_is_cpu_port(ds, port)) {
429
+
err = gswip_add_single_port_br(priv, port, true);
430
+
if (err)
431
+
return err;
432
+
}
433
+
434
+
return 0;
435
+
}
436
+
437
+
static int gswip_port_enable(struct dsa_switch *ds, int port,
438
+
struct phy_device *phydev)
439
+
{
440
+
struct gswip_priv *priv = ds->priv;
441
+
442
+
if (!dsa_is_cpu_port(ds, port)) {
443
+
u32 mdio_phy = 0;
444
+
445
+
if (phydev)
446
+
mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
447
+
448
+
regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
449
+
GSWIP_MDIO_PHY_ADDR_MASK,
450
+
mdio_phy);
451
+
}
452
+
453
+
/* RMON Counter Enable for port */
454
+
regmap_write(priv->gswip, GSWIP_BM_PCFGp(port), GSWIP_BM_PCFG_CNTEN);
455
+
456
+
/* enable port fetch/store dma & VLAN Modification */
457
+
regmap_set_bits(priv->gswip, GSWIP_FDMA_PCTRLp(port),
458
+
GSWIP_FDMA_PCTRL_EN | GSWIP_FDMA_PCTRL_VLANMOD_BOTH);
459
+
regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),
460
+
GSWIP_SDMA_PCTRL_EN);
461
+
462
+
return 0;
463
+
}
464
+
465
+
static void gswip_port_disable(struct dsa_switch *ds, int port)
466
+
{
467
+
struct gswip_priv *priv = ds->priv;
468
+
469
+
regmap_clear_bits(priv->gswip, GSWIP_FDMA_PCTRLp(port),
470
+
GSWIP_FDMA_PCTRL_EN);
471
+
regmap_clear_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),
472
+
GSWIP_SDMA_PCTRL_EN);
473
+
}
474
+
475
+
static int gswip_pce_load_microcode(struct gswip_priv *priv)
476
+
{
477
+
int i;
478
+
int err;
479
+
480
+
regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
481
+
GSWIP_PCE_TBL_CTRL_ADDR_MASK |
482
+
GSWIP_PCE_TBL_CTRL_OPMOD_MASK |
483
+
GSWIP_PCE_TBL_CTRL_OPMOD_ADWR,
484
+
GSWIP_PCE_TBL_CTRL_OPMOD_ADWR);
485
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, 0);
486
+
487
+
for (i = 0; i < priv->hw_info->pce_microcode_size; i++) {
488
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, i);
489
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(0),
490
+
(*priv->hw_info->pce_microcode)[i].val_0);
491
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(1),
492
+
(*priv->hw_info->pce_microcode)[i].val_1);
493
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(2),
494
+
(*priv->hw_info->pce_microcode)[i].val_2);
495
+
regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(3),
496
+
(*priv->hw_info->pce_microcode)[i].val_3);
497
+
498
+
/* start the table access: */
499
+
regmap_set_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
500
+
GSWIP_PCE_TBL_CTRL_BAS);
501
+
err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
502
+
GSWIP_PCE_TBL_CTRL_BAS);
503
+
if (err)
504
+
return err;
505
+
}
506
+
507
+
/* tell the switch that the microcode is loaded */
508
+
regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0,
509
+
GSWIP_PCE_GCTRL_0_MC_VALID);
510
+
511
+
return 0;
512
+
}
513
+
514
+
static void gswip_port_commit_pvid(struct gswip_priv *priv, int port)
515
+
{
516
+
struct dsa_port *dp = dsa_to_port(priv->ds, port);
517
+
struct net_device *br = dsa_port_bridge_dev_get(dp);
518
+
u32 vinr;
519
+
int idx;
520
+
521
+
if (!dsa_port_is_user(dp))
522
+
return;
523
+
524
+
if (br) {
525
+
u16 pvid = GSWIP_VLAN_UNAWARE_PVID;
526
+
527
+
if (br_vlan_enabled(br))
528
+
br_vlan_get_pvid(br, &pvid);
529
+
530
+
/* VLAN-aware bridge ports with no PVID will use Active VLAN
531
+
* index 0. The expectation is that this drops all untagged and
532
+
* VID-0 tagged ingress traffic.
533
+
*/
534
+
idx = 0;
535
+
for (int i = priv->hw_info->max_ports;
536
+
i < ARRAY_SIZE(priv->vlans); i++) {
537
+
if (priv->vlans[i].bridge == br &&
538
+
priv->vlans[i].vid == pvid) {
539
+
idx = i;
540
+
break;
541
+
}
542
+
}
543
+
} else {
544
+
/* The Active VLAN table index as configured by
545
+
* gswip_add_single_port_br()
546
+
*/
547
+
idx = port + 1;
548
+
}
549
+
550
+
vinr = idx ? GSWIP_PCE_VCTRL_VINR_ALL : GSWIP_PCE_VCTRL_VINR_TAGGED;
551
+
regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),
552
+
GSWIP_PCE_VCTRL_VINR,
553
+
FIELD_PREP(GSWIP_PCE_VCTRL_VINR, vinr));
554
+
555
+
/* Note that in GSWIP 2.2 VLAN mode the VID needs to be programmed
556
+
* directly instead of referencing the index in the Active VLAN Tablet.
557
+
* However, without the VLANMD bit (9) in PCE_GCTRL_1 (0x457) even
558
+
* GSWIP 2.2 and newer hardware maintain the GSWIP 2.1 behavior.
559
+
*/
560
+
regmap_write(priv->gswip, GSWIP_PCE_DEFPVID(port), idx);
561
+
}
562
+
563
+
static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
564
+
bool vlan_filtering,
565
+
struct netlink_ext_ack *extack)
566
+
{
567
+
struct gswip_priv *priv = ds->priv;
568
+
569
+
if (vlan_filtering) {
570
+
/* Use tag based VLAN */
571
+
regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),
572
+
GSWIP_PCE_VCTRL_VSR |
573
+
GSWIP_PCE_VCTRL_UVR |
574
+
GSWIP_PCE_VCTRL_VIMR |
575
+
GSWIP_PCE_VCTRL_VEMR |
576
+
GSWIP_PCE_VCTRL_VID0,
577
+
GSWIP_PCE_VCTRL_UVR |
578
+
GSWIP_PCE_VCTRL_VIMR |
579
+
GSWIP_PCE_VCTRL_VEMR |
580
+
GSWIP_PCE_VCTRL_VID0);
581
+
regmap_clear_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),
582
+
GSWIP_PCE_PCTRL_0_TVM);
583
+
} else {
584
+
/* Use port based VLAN */
585
+
regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),
586
+
GSWIP_PCE_VCTRL_UVR |
587
+
GSWIP_PCE_VCTRL_VIMR |
588
+
GSWIP_PCE_VCTRL_VEMR |
589
+
GSWIP_PCE_VCTRL_VID0 |
590
+
GSWIP_PCE_VCTRL_VSR,
591
+
GSWIP_PCE_VCTRL_VSR);
592
+
regmap_set_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),
593
+
GSWIP_PCE_PCTRL_0_TVM);
594
+
}
595
+
596
+
gswip_port_commit_pvid(priv, port);
597
+
598
+
return 0;
599
+
}
600
+
601
+
static void gswip_mii_delay_setup(struct gswip_priv *priv, struct dsa_port *dp,
602
+
phy_interface_t interface)
603
+
{
604
+
u32 tx_delay = GSWIP_MII_PCDU_TXDLY_DEFAULT;
605
+
u32 rx_delay = GSWIP_MII_PCDU_RXDLY_DEFAULT;
606
+
struct device_node *port_dn = dp->dn;
607
+
u16 mii_pcdu_reg;
608
+
609
+
/* As MII_PCDU registers only exist for MII ports, silently return
610
+
* unless the port is an MII port
611
+
*/
612
+
if (!(priv->hw_info->mii_ports & BIT(dp->index)))
613
+
return;
614
+
615
+
switch (dp->index + priv->hw_info->mii_port_reg_offset) {
616
+
case 0:
617
+
mii_pcdu_reg = GSWIP_MII_PCDU0;
618
+
break;
619
+
case 1:
620
+
mii_pcdu_reg = GSWIP_MII_PCDU1;
621
+
break;
622
+
case 5:
623
+
mii_pcdu_reg = GSWIP_MII_PCDU5;
624
+
break;
625
+
default:
626
+
return;
627
+
}
628
+
629
+
/* legacy code to set default delays according to the interface mode */
630
+
switch (interface) {
631
+
case PHY_INTERFACE_MODE_RGMII_ID:
632
+
tx_delay = 0;
633
+
rx_delay = 0;
634
+
break;
635
+
case PHY_INTERFACE_MODE_RGMII_RXID:
636
+
rx_delay = 0;
637
+
break;
638
+
case PHY_INTERFACE_MODE_RGMII_TXID:
639
+
tx_delay = 0;
640
+
break;
641
+
default:
642
+
break;
643
+
}
644
+
645
+
/* allow settings delays using device tree properties */
646
+
of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
647
+
of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
648
+
649
+
regmap_write_bits(priv->mii, mii_pcdu_reg,
650
+
GSWIP_MII_PCDU_TXDLY_MASK |
651
+
GSWIP_MII_PCDU_RXDLY_MASK,
652
+
GSWIP_MII_PCDU_TXDLY(tx_delay) |
653
+
GSWIP_MII_PCDU_RXDLY(rx_delay));
654
+
}
655
+
656
+
static int gswip_setup(struct dsa_switch *ds)
657
+
{
658
+
unsigned int cpu_ports = dsa_cpu_ports(ds);
659
+
struct gswip_priv *priv = ds->priv;
660
+
struct dsa_port *cpu_dp;
661
+
int err, i;
662
+
663
+
regmap_write(priv->gswip, GSWIP_SWRES, GSWIP_SWRES_R0);
664
+
usleep_range(5000, 10000);
665
+
regmap_write(priv->gswip, GSWIP_SWRES, 0);
666
+
667
+
/* disable port fetch/store dma on all ports */
668
+
for (i = 0; i < priv->hw_info->max_ports; i++) {
669
+
gswip_port_disable(ds, i);
670
+
gswip_port_vlan_filtering(ds, i, false, NULL);
671
+
}
672
+
673
+
/* enable Switch */
674
+
regmap_set_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE);
675
+
676
+
err = gswip_pce_load_microcode(priv);
677
+
if (err) {
678
+
dev_err(priv->dev, "writing PCE microcode failed, %i\n", err);
679
+
return err;
680
+
}
681
+
682
+
/* Default unknown Broadcast/Multicast/Unicast port maps */
683
+
regmap_write(priv->gswip, GSWIP_PCE_PMAP1, cpu_ports);
684
+
regmap_write(priv->gswip, GSWIP_PCE_PMAP2, cpu_ports);
685
+
regmap_write(priv->gswip, GSWIP_PCE_PMAP3, cpu_ports);
686
+
687
+
/* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
688
+
* interoperability problem with this auto polling mechanism because
689
+
* their status registers think that the link is in a different state
690
+
* than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set
691
+
* as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the
692
+
* auto polling state machine consider the link being negotiated with
693
+
* 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads
694
+
* to the switch port being completely dead (RX and TX are both not
695
+
* working).
696
+
* Also with various other PHY / port combinations (PHY11G GPHY, PHY22F
697
+
* GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes
698
+
* it would work fine for a few minutes to hours and then stop, on
699
+
* other device it would no traffic could be sent or received at all.
700
+
* Testing shows that when PHY auto polling is disabled these problems
701
+
* go away.
702
+
*/
703
+
regmap_write(priv->mdio, GSWIP_MDIO_MDC_CFG0, 0x0);
704
+
705
+
/* Configure the MDIO Clock 2.5 MHz */
706
+
regmap_write_bits(priv->mdio, GSWIP_MDIO_MDC_CFG1, 0xff, 0x09);
707
+
708
+
/* bring up the mdio bus */
709
+
err = gswip_mdio(priv);
710
+
if (err) {
711
+
dev_err(priv->dev, "mdio bus setup failed\n");
712
+
return err;
713
+
}
714
+
715
+
/* Disable the xMII interface and clear it's isolation bit */
716
+
for (i = 0; i < priv->hw_info->max_ports; i++)
717
+
gswip_mii_mask_cfg(priv,
718
+
GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE,
719
+
0, i);
720
+
721
+
dsa_switch_for_each_cpu_port(cpu_dp, ds) {
722
+
/* enable special tag insertion on cpu port */
723
+
regmap_set_bits(priv->gswip, GSWIP_FDMA_PCTRLp(cpu_dp->index),
724
+
GSWIP_FDMA_PCTRL_STEN);
725
+
726
+
/* accept special tag in ingress direction */
727
+
regmap_set_bits(priv->gswip,
728
+
GSWIP_PCE_PCTRL_0p(cpu_dp->index),
729
+
GSWIP_PCE_PCTRL_0_INGRESS);
730
+
}
731
+
732
+
regmap_set_bits(priv->gswip, GSWIP_BM_QUEUE_GCTRL,
733
+
GSWIP_BM_QUEUE_GCTRL_GL_MOD);
734
+
735
+
/* VLAN aware Switching */
736
+
regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0,
737
+
GSWIP_PCE_GCTRL_0_VLAN);
738
+
739
+
/* Flush MAC Table */
740
+
regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0,
741
+
GSWIP_PCE_GCTRL_0_MTFL);
742
+
743
+
err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
744
+
GSWIP_PCE_GCTRL_0_MTFL);
745
+
if (err) {
746
+
dev_err(priv->dev, "MAC flushing didn't finish\n");
747
+
return err;
748
+
}
749
+
750
+
ds->mtu_enforcement_ingress = true;
751
+
752
+
return 0;
753
+
}
754
+
755
+
static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
756
+
int port,
757
+
enum dsa_tag_protocol mp)
758
+
{
759
+
struct gswip_priv *priv = ds->priv;
760
+
761
+
return priv->hw_info->tag_protocol;
762
+
}
763
+
764
+
static int gswip_vlan_active_create(struct gswip_priv *priv,
765
+
struct net_device *bridge,
766
+
int fid, u16 vid)
767
+
{
768
+
struct gswip_pce_table_entry vlan_active = {0,};
769
+
unsigned int max_ports = priv->hw_info->max_ports;
770
+
int idx = -1;
771
+
int err;
772
+
int i;
773
+
774
+
/* Look for a free slot */
775
+
for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
776
+
if (!priv->vlans[i].bridge) {
777
+
idx = i;
778
+
break;
779
+
}
780
+
}
781
+
782
+
if (idx == -1)
783
+
return -ENOSPC;
784
+
785
+
if (fid == -1)
786
+
fid = idx;
787
+
788
+
vlan_active.index = idx;
789
+
vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
790
+
vlan_active.key[0] = vid;
791
+
vlan_active.val[0] = fid;
792
+
vlan_active.valid = true;
793
+
794
+
err = gswip_pce_table_entry_write(priv, &vlan_active);
795
+
if (err) {
796
+
dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
797
+
return err;
798
+
}
799
+
800
+
priv->vlans[idx].bridge = bridge;
801
+
priv->vlans[idx].vid = vid;
802
+
priv->vlans[idx].fid = fid;
803
+
804
+
return idx;
805
+
}
806
+
807
+
static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
808
+
{
809
+
struct gswip_pce_table_entry vlan_active = {0,};
810
+
int err;
811
+
812
+
vlan_active.index = idx;
813
+
vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
814
+
vlan_active.valid = false;
815
+
err = gswip_pce_table_entry_write(priv, &vlan_active);
816
+
if (err)
817
+
dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
818
+
priv->vlans[idx].bridge = NULL;
819
+
820
+
return err;
821
+
}
822
+
823
+
static int gswip_vlan_add(struct gswip_priv *priv, struct net_device *bridge,
824
+
int port, u16 vid, bool untagged, bool pvid,
825
+
bool vlan_aware)
826
+
{
827
+
struct gswip_pce_table_entry vlan_mapping = {0,};
828
+
unsigned int max_ports = priv->hw_info->max_ports;
829
+
unsigned int cpu_ports = dsa_cpu_ports(priv->ds);
830
+
bool active_vlan_created = false;
831
+
int fid = -1, idx = -1;
832
+
int i, err;
833
+
834
+
/* Check if there is already a page for this bridge */
835
+
for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
836
+
if (priv->vlans[i].bridge == bridge) {
837
+
if (vlan_aware) {
838
+
if (fid != -1 && fid != priv->vlans[i].fid)
839
+
dev_err(priv->dev, "one bridge with multiple flow ids\n");
840
+
fid = priv->vlans[i].fid;
841
+
}
842
+
if (priv->vlans[i].vid == vid) {
843
+
idx = i;
844
+
break;
845
+
}
846
+
}
847
+
}
848
+
849
+
/* If this bridge is not programmed yet, add a Active VLAN table
850
+
* entry in a free slot and prepare the VLAN mapping table entry.
851
+
*/
852
+
if (idx == -1) {
853
+
idx = gswip_vlan_active_create(priv, bridge, fid, vid);
854
+
if (idx < 0)
855
+
return idx;
856
+
active_vlan_created = true;
857
+
858
+
vlan_mapping.index = idx;
859
+
vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
860
+
} else {
861
+
/* Read the existing VLAN mapping entry from the switch */
862
+
vlan_mapping.index = idx;
863
+
vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
864
+
err = gswip_pce_table_entry_read(priv, &vlan_mapping);
865
+
if (err) {
866
+
dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
867
+
err);
868
+
return err;
869
+
}
870
+
}
871
+
872
+
/* VLAN ID byte, maps to the VLAN ID of vlan active table */
873
+
vlan_mapping.val[0] = vid;
874
+
/* Update the VLAN mapping entry and write it to the switch */
875
+
vlan_mapping.val[1] |= cpu_ports;
876
+
vlan_mapping.val[1] |= BIT(port);
877
+
if (vlan_aware)
878
+
vlan_mapping.val[2] |= cpu_ports;
879
+
if (untagged)
880
+
vlan_mapping.val[2] &= ~BIT(port);
881
+
else
882
+
vlan_mapping.val[2] |= BIT(port);
883
+
err = gswip_pce_table_entry_write(priv, &vlan_mapping);
884
+
if (err) {
885
+
dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
886
+
/* In case an Active VLAN was creaetd delete it again */
887
+
if (active_vlan_created)
888
+
gswip_vlan_active_remove(priv, idx);
889
+
return err;
890
+
}
891
+
892
+
gswip_port_commit_pvid(priv, port);
893
+
894
+
return 0;
895
+
}
896
+
897
+
static int gswip_vlan_remove(struct gswip_priv *priv,
898
+
struct net_device *bridge, int port,
899
+
u16 vid)
900
+
{
901
+
struct gswip_pce_table_entry vlan_mapping = {0,};
902
+
unsigned int max_ports = priv->hw_info->max_ports;
903
+
int idx = -1;
904
+
int i;
905
+
int err;
906
+
907
+
/* Check if there is already a page for this bridge */
908
+
for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
909
+
if (priv->vlans[i].bridge == bridge &&
910
+
priv->vlans[i].vid == vid) {
911
+
idx = i;
912
+
break;
913
+
}
914
+
}
915
+
916
+
if (idx == -1) {
917
+
dev_err(priv->dev, "Port %d cannot find VID %u of bridge %s\n",
918
+
port, vid, bridge ? bridge->name : "(null)");
919
+
return -ENOENT;
920
+
}
921
+
922
+
vlan_mapping.index = idx;
923
+
vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
924
+
err = gswip_pce_table_entry_read(priv, &vlan_mapping);
925
+
if (err) {
926
+
dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
927
+
return err;
928
+
}
929
+
930
+
vlan_mapping.val[1] &= ~BIT(port);
931
+
vlan_mapping.val[2] &= ~BIT(port);
932
+
err = gswip_pce_table_entry_write(priv, &vlan_mapping);
933
+
if (err) {
934
+
dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
935
+
return err;
936
+
}
937
+
938
+
/* In case all ports are removed from the bridge, remove the VLAN */
939
+
if (!(vlan_mapping.val[1] & ~dsa_cpu_ports(priv->ds))) {
940
+
err = gswip_vlan_active_remove(priv, idx);
941
+
if (err) {
942
+
dev_err(priv->dev, "failed to write active VLAN: %d\n",
943
+
err);
944
+
return err;
945
+
}
946
+
}
947
+
948
+
gswip_port_commit_pvid(priv, port);
949
+
950
+
return 0;
951
+
}
952
+
953
+
static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
954
+
struct dsa_bridge bridge,
955
+
bool *tx_fwd_offload,
956
+
struct netlink_ext_ack *extack)
957
+
{
958
+
struct net_device *br = bridge.dev;
959
+
struct gswip_priv *priv = ds->priv;
960
+
int err;
961
+
962
+
/* Set up the VLAN for VLAN-unaware bridging for this port, and remove
963
+
* it from the "single-port bridge" through which it was operating as
964
+
* standalone.
965
+
*/
966
+
err = gswip_vlan_add(priv, br, port, GSWIP_VLAN_UNAWARE_PVID,
967
+
true, true, false);
968
+
if (err)
969
+
return err;
970
+
971
+
return gswip_add_single_port_br(priv, port, false);
972
+
}
973
+
974
+
static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
975
+
struct dsa_bridge bridge)
976
+
{
977
+
struct net_device *br = bridge.dev;
978
+
struct gswip_priv *priv = ds->priv;
979
+
980
+
/* Add the port back to the "single-port bridge", and remove it from
981
+
* the VLAN-unaware PVID created for this bridge.
982
+
*/
983
+
gswip_add_single_port_br(priv, port, true);
984
+
gswip_vlan_remove(priv, br, port, GSWIP_VLAN_UNAWARE_PVID);
985
+
}
986
+
987
+
static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
988
+
const struct switchdev_obj_port_vlan *vlan,
989
+
struct netlink_ext_ack *extack)
990
+
{
991
+
struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
992
+
struct gswip_priv *priv = ds->priv;
993
+
unsigned int max_ports = priv->hw_info->max_ports;
994
+
int pos = max_ports;
995
+
int i, idx = -1;
996
+
997
+
/* We only support VLAN filtering on bridges */
998
+
if (!dsa_is_cpu_port(ds, port) && !bridge)
999
+
return -EOPNOTSUPP;
1000
+
1001
+
/* Check if there is already a page for this VLAN */
1002
+
for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1003
+
if (priv->vlans[i].bridge == bridge &&
1004
+
priv->vlans[i].vid == vlan->vid) {
1005
+
idx = i;
1006
+
break;
1007
+
}
1008
+
}
1009
+
1010
+
/* If this VLAN is not programmed yet, we have to reserve
1011
+
* one entry in the VLAN table. Make sure we start at the
1012
+
* next position round.
1013
+
*/
1014
+
if (idx == -1) {
1015
+
/* Look for a free slot */
1016
+
for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
1017
+
if (!priv->vlans[pos].bridge) {
1018
+
idx = pos;
1019
+
pos++;
1020
+
break;
1021
+
}
1022
+
}
1023
+
1024
+
if (idx == -1) {
1025
+
NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table");
1026
+
return -ENOSPC;
1027
+
}
1028
+
}
1029
+
1030
+
return 0;
1031
+
}
1032
+
1033
+
static int gswip_port_vlan_add(struct dsa_switch *ds, int port,
1034
+
const struct switchdev_obj_port_vlan *vlan,
1035
+
struct netlink_ext_ack *extack)
1036
+
{
1037
+
struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1038
+
struct gswip_priv *priv = ds->priv;
1039
+
bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1040
+
bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1041
+
int err;
1042
+
1043
+
if (vlan->vid == GSWIP_VLAN_UNAWARE_PVID)
1044
+
return 0;
1045
+
1046
+
err = gswip_port_vlan_prepare(ds, port, vlan, extack);
1047
+
if (err)
1048
+
return err;
1049
+
1050
+
/* We have to receive all packets on the CPU port and should not
1051
+
* do any VLAN filtering here. This is also called with bridge
1052
+
* NULL and then we do not know for which bridge to configure
1053
+
* this.
1054
+
*/
1055
+
if (dsa_is_cpu_port(ds, port))
1056
+
return 0;
1057
+
1058
+
return gswip_vlan_add(priv, bridge, port, vlan->vid, untagged, pvid,
1059
+
true);
1060
+
}
1061
+
1062
+
static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
1063
+
const struct switchdev_obj_port_vlan *vlan)
1064
+
{
1065
+
struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1066
+
struct gswip_priv *priv = ds->priv;
1067
+
1068
+
if (vlan->vid == GSWIP_VLAN_UNAWARE_PVID)
1069
+
return 0;
1070
+
1071
+
/* We have to receive all packets on the CPU port and should not
1072
+
* do any VLAN filtering here. This is also called with bridge
1073
+
* NULL and then we do not know for which bridge to configure
1074
+
* this.
1075
+
*/
1076
+
if (dsa_is_cpu_port(ds, port))
1077
+
return 0;
1078
+
1079
+
return gswip_vlan_remove(priv, bridge, port, vlan->vid);
1080
+
}
1081
+
1082
+
static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1083
+
{
1084
+
struct gswip_priv *priv = ds->priv;
1085
+
struct gswip_pce_table_entry mac_bridge = {0,};
1086
+
int i;
1087
+
int err;
1088
+
1089
+
for (i = 0; i < 2048; i++) {
1090
+
mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1091
+
mac_bridge.index = i;
1092
+
1093
+
err = gswip_pce_table_entry_read(priv, &mac_bridge);
1094
+
if (err) {
1095
+
dev_err(priv->dev, "failed to read mac bridge: %d\n",
1096
+
err);
1097
+
return;
1098
+
}
1099
+
1100
+
if (!mac_bridge.valid)
1101
+
continue;
1102
+
1103
+
if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC)
1104
+
continue;
1105
+
1106
+
if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT,
1107
+
mac_bridge.val[0]))
1108
+
continue;
1109
+
1110
+
mac_bridge.valid = false;
1111
+
err = gswip_pce_table_entry_write(priv, &mac_bridge);
1112
+
if (err) {
1113
+
dev_err(priv->dev, "failed to write mac bridge: %d\n",
1114
+
err);
1115
+
return;
1116
+
}
1117
+
}
1118
+
}
1119
+
1120
+
static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1121
+
{
1122
+
struct gswip_priv *priv = ds->priv;
1123
+
u32 stp_state;
1124
+
1125
+
switch (state) {
1126
+
case BR_STATE_DISABLED:
1127
+
regmap_clear_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),
1128
+
GSWIP_SDMA_PCTRL_EN);
1129
+
return;
1130
+
case BR_STATE_BLOCKING:
1131
+
case BR_STATE_LISTENING:
1132
+
stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1133
+
break;
1134
+
case BR_STATE_LEARNING:
1135
+
stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1136
+
break;
1137
+
case BR_STATE_FORWARDING:
1138
+
stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1139
+
break;
1140
+
default:
1141
+
dev_err(priv->dev, "invalid STP state: %d\n", state);
1142
+
return;
1143
+
}
1144
+
1145
+
regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),
1146
+
GSWIP_SDMA_PCTRL_EN);
1147
+
regmap_write_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),
1148
+
GSWIP_PCE_PCTRL_0_PSTATE_MASK,
1149
+
stp_state);
1150
+
}
1151
+
1152
+
static int gswip_port_fdb(struct dsa_switch *ds, int port,
1153
+
struct net_device *bridge, const unsigned char *addr,
1154
+
u16 vid, bool add)
1155
+
{
1156
+
struct gswip_priv *priv = ds->priv;
1157
+
struct gswip_pce_table_entry mac_bridge = {0,};
1158
+
unsigned int max_ports = priv->hw_info->max_ports;
1159
+
int fid = -1;
1160
+
int i;
1161
+
int err;
1162
+
1163
+
for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1164
+
if (priv->vlans[i].bridge == bridge) {
1165
+
fid = priv->vlans[i].fid;
1166
+
break;
1167
+
}
1168
+
}
1169
+
1170
+
if (fid == -1) {
1171
+
dev_err(priv->dev, "no FID found for bridge %s\n",
1172
+
bridge->name);
1173
+
return -EINVAL;
1174
+
}
1175
+
1176
+
mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1177
+
mac_bridge.key_mode = true;
1178
+
mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1179
+
mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1180
+
mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1181
+
mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_KEY3_FID, fid);
1182
+
mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1183
+
if (GSWIP_VERSION_GE(priv, GSWIP_VERSION_2_2_ETC))
1184
+
mac_bridge.val[1] = add ? (GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC |
1185
+
GSWIP_TABLE_MAC_BRIDGE_VAL1_VALID) : 0;
1186
+
else
1187
+
mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC;
1188
+
1189
+
mac_bridge.valid = add;
1190
+
1191
+
err = gswip_pce_table_entry_write(priv, &mac_bridge);
1192
+
if (err)
1193
+
dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
1194
+
1195
+
return err;
1196
+
}
1197
+
1198
+
static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1199
+
const unsigned char *addr, u16 vid,
1200
+
struct dsa_db db)
1201
+
{
1202
+
if (db.type != DSA_DB_BRIDGE)
1203
+
return -EOPNOTSUPP;
1204
+
1205
+
return gswip_port_fdb(ds, port, db.bridge.dev, addr, vid, true);
1206
+
}
1207
+
1208
+
static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1209
+
const unsigned char *addr, u16 vid,
1210
+
struct dsa_db db)
1211
+
{
1212
+
if (db.type != DSA_DB_BRIDGE)
1213
+
return -EOPNOTSUPP;
1214
+
1215
+
return gswip_port_fdb(ds, port, db.bridge.dev, addr, vid, false);
1216
+
}
1217
+
1218
+
static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1219
+
dsa_fdb_dump_cb_t *cb, void *data)
1220
+
{
1221
+
struct gswip_priv *priv = ds->priv;
1222
+
struct gswip_pce_table_entry mac_bridge = {0,};
1223
+
unsigned char addr[ETH_ALEN];
1224
+
int i;
1225
+
int err;
1226
+
1227
+
for (i = 0; i < 2048; i++) {
1228
+
mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1229
+
mac_bridge.index = i;
1230
+
1231
+
err = gswip_pce_table_entry_read(priv, &mac_bridge);
1232
+
if (err) {
1233
+
dev_err(priv->dev,
1234
+
"failed to read mac bridge entry %d: %d\n",
1235
+
i, err);
1236
+
return err;
1237
+
}
1238
+
1239
+
if (!mac_bridge.valid)
1240
+
continue;
1241
+
1242
+
addr[5] = mac_bridge.key[0] & 0xff;
1243
+
addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1244
+
addr[3] = mac_bridge.key[1] & 0xff;
1245
+
addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1246
+
addr[1] = mac_bridge.key[2] & 0xff;
1247
+
addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1248
+
if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC) {
1249
+
if (mac_bridge.val[0] & BIT(port)) {
1250
+
err = cb(addr, 0, true, data);
1251
+
if (err)
1252
+
return err;
1253
+
}
1254
+
} else {
1255
+
if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT,
1256
+
mac_bridge.val[0])) {
1257
+
err = cb(addr, 0, false, data);
1258
+
if (err)
1259
+
return err;
1260
+
}
1261
+
}
1262
+
}
1263
+
return 0;
1264
+
}
1265
+
1266
+
static int gswip_port_max_mtu(struct dsa_switch *ds, int port)
1267
+
{
1268
+
/* Includes 8 bytes for special header. */
1269
+
return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN;
1270
+
}
1271
+
1272
+
static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1273
+
{
1274
+
struct gswip_priv *priv = ds->priv;
1275
+
1276
+
/* CPU port always has maximum mtu of user ports, so use it to set
1277
+
* switch frame size, including 8 byte special header.
1278
+
*/
1279
+
if (dsa_is_cpu_port(ds, port)) {
1280
+
new_mtu += 8;
1281
+
regmap_write(priv->gswip, GSWIP_MAC_FLEN,
1282
+
VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN);
1283
+
}
1284
+
1285
+
/* Enable MLEN for ports with non-standard MTUs, including the special
1286
+
* header on the CPU port added above.
1287
+
*/
1288
+
if (new_mtu != ETH_DATA_LEN)
1289
+
regmap_set_bits(priv->gswip, GSWIP_MAC_CTRL_2p(port),
1290
+
GSWIP_MAC_CTRL_2_MLEN);
1291
+
else
1292
+
regmap_clear_bits(priv->gswip, GSWIP_MAC_CTRL_2p(port),
1293
+
GSWIP_MAC_CTRL_2_MLEN);
1294
+
1295
+
return 0;
1296
+
}
1297
+
1298
+
static void gswip_phylink_get_caps(struct dsa_switch *ds, int port,
1299
+
struct phylink_config *config)
1300
+
{
1301
+
struct gswip_priv *priv = ds->priv;
1302
+
1303
+
priv->hw_info->phylink_get_caps(ds, port, config);
1304
+
}
1305
+
1306
+
static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
1307
+
{
1308
+
u32 mdio_phy;
1309
+
1310
+
if (link)
1311
+
mdio_phy = GSWIP_MDIO_PHY_LINK_UP;
1312
+
else
1313
+
mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;
1314
+
1315
+
regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
1316
+
GSWIP_MDIO_PHY_LINK_MASK, mdio_phy);
1317
+
}
1318
+
1319
+
static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
1320
+
phy_interface_t interface)
1321
+
{
1322
+
u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0;
1323
+
1324
+
switch (speed) {
1325
+
case SPEED_10:
1326
+
mdio_phy = GSWIP_MDIO_PHY_SPEED_M10;
1327
+
1328
+
if (interface == PHY_INTERFACE_MODE_RMII)
1329
+
mii_cfg = GSWIP_MII_CFG_RATE_M50;
1330
+
else
1331
+
mii_cfg = GSWIP_MII_CFG_RATE_M2P5;
1332
+
1333
+
mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1334
+
break;
1335
+
1336
+
case SPEED_100:
1337
+
mdio_phy = GSWIP_MDIO_PHY_SPEED_M100;
1338
+
1339
+
if (interface == PHY_INTERFACE_MODE_RMII)
1340
+
mii_cfg = GSWIP_MII_CFG_RATE_M50;
1341
+
else
1342
+
mii_cfg = GSWIP_MII_CFG_RATE_M25;
1343
+
1344
+
mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1345
+
break;
1346
+
1347
+
case SPEED_1000:
1348
+
mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
1349
+
1350
+
mii_cfg = GSWIP_MII_CFG_RATE_M125;
1351
+
1352
+
mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII;
1353
+
break;
1354
+
}
1355
+
1356
+
regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
1357
+
GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy);
1358
+
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);
1359
+
regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),
1360
+
GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0);
1361
+
}
1362
+
1363
+
static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
1364
+
{
1365
+
u32 mac_ctrl_0, mdio_phy;
1366
+
1367
+
if (duplex == DUPLEX_FULL) {
1368
+
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN;
1369
+
mdio_phy = GSWIP_MDIO_PHY_FDUP_EN;
1370
+
} else {
1371
+
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS;
1372
+
mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;
1373
+
}
1374
+
1375
+
regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),
1376
+
GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0);
1377
+
regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
1378
+
GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy);
1379
+
}
1380
+
1381
+
static void gswip_port_set_pause(struct gswip_priv *priv, int port,
1382
+
bool tx_pause, bool rx_pause)
1383
+
{
1384
+
u32 mac_ctrl_0, mdio_phy;
1385
+
1386
+
if (tx_pause && rx_pause) {
1387
+
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX;
1388
+
mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1389
+
GSWIP_MDIO_PHY_FCONRX_EN;
1390
+
} else if (tx_pause) {
1391
+
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX;
1392
+
mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1393
+
GSWIP_MDIO_PHY_FCONRX_DIS;
1394
+
} else if (rx_pause) {
1395
+
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX;
1396
+
mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1397
+
GSWIP_MDIO_PHY_FCONRX_EN;
1398
+
} else {
1399
+
mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE;
1400
+
mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1401
+
GSWIP_MDIO_PHY_FCONRX_DIS;
1402
+
}
1403
+
1404
+
regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),
1405
+
GSWIP_MAC_CTRL_0_FCON_MASK, mac_ctrl_0);
1406
+
regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
1407
+
GSWIP_MDIO_PHY_FCONTX_MASK | GSWIP_MDIO_PHY_FCONRX_MASK,
1408
+
mdio_phy);
1409
+
}
1410
+
1411
+
static void gswip_phylink_mac_config(struct phylink_config *config,
1412
+
unsigned int mode,
1413
+
const struct phylink_link_state *state)
1414
+
{
1415
+
struct dsa_port *dp = dsa_phylink_to_port(config);
1416
+
struct gswip_priv *priv = dp->ds->priv;
1417
+
int port = dp->index;
1418
+
u32 miicfg = 0;
1419
+
1420
+
miicfg |= GSWIP_MII_CFG_LDCLKDIS;
1421
+
1422
+
switch (state->interface) {
1423
+
case PHY_INTERFACE_MODE_SGMII:
1424
+
case PHY_INTERFACE_MODE_1000BASEX:
1425
+
case PHY_INTERFACE_MODE_2500BASEX:
1426
+
return;
1427
+
case PHY_INTERFACE_MODE_MII:
1428
+
case PHY_INTERFACE_MODE_INTERNAL:
1429
+
miicfg |= GSWIP_MII_CFG_MODE_MIIM;
1430
+
break;
1431
+
case PHY_INTERFACE_MODE_REVMII:
1432
+
miicfg |= GSWIP_MII_CFG_MODE_MIIP;
1433
+
break;
1434
+
case PHY_INTERFACE_MODE_RMII:
1435
+
miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
1436
+
if (of_property_read_bool(dp->dn, "maxlinear,rmii-refclk-out"))
1437
+
miicfg |= GSWIP_MII_CFG_RMII_CLK;
1438
+
break;
1439
+
case PHY_INTERFACE_MODE_RGMII:
1440
+
case PHY_INTERFACE_MODE_RGMII_ID:
1441
+
case PHY_INTERFACE_MODE_RGMII_RXID:
1442
+
case PHY_INTERFACE_MODE_RGMII_TXID:
1443
+
miicfg |= GSWIP_MII_CFG_MODE_RGMII;
1444
+
break;
1445
+
case PHY_INTERFACE_MODE_GMII:
1446
+
miicfg |= GSWIP_MII_CFG_MODE_GMII;
1447
+
break;
1448
+
default:
1449
+
dev_err(dp->ds->dev,
1450
+
"Unsupported interface: %d\n", state->interface);
1451
+
return;
1452
+
}
1453
+
1454
+
gswip_mii_mask_cfg(priv,
1455
+
GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK |
1456
+
GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS,
1457
+
miicfg, port);
1458
+
1459
+
gswip_mii_delay_setup(priv, dp, state->interface);
1460
+
}
1461
+
1462
+
static void gswip_phylink_mac_link_down(struct phylink_config *config,
1463
+
unsigned int mode,
1464
+
phy_interface_t interface)
1465
+
{
1466
+
struct dsa_port *dp = dsa_phylink_to_port(config);
1467
+
struct gswip_priv *priv = dp->ds->priv;
1468
+
int port = dp->index;
1469
+
1470
+
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
1471
+
1472
+
if (!dsa_port_is_cpu(dp))
1473
+
gswip_port_set_link(priv, port, false);
1474
+
}
1475
+
1476
+
static void gswip_phylink_mac_link_up(struct phylink_config *config,
1477
+
struct phy_device *phydev,
1478
+
unsigned int mode,
1479
+
phy_interface_t interface,
1480
+
int speed, int duplex,
1481
+
bool tx_pause, bool rx_pause)
1482
+
{
1483
+
struct dsa_port *dp = dsa_phylink_to_port(config);
1484
+
struct gswip_priv *priv = dp->ds->priv;
1485
+
int port = dp->index;
1486
+
1487
+
if (!dsa_port_is_cpu(dp) || interface != PHY_INTERFACE_MODE_INTERNAL) {
1488
+
gswip_port_set_link(priv, port, true);
1489
+
gswip_port_set_speed(priv, port, speed, interface);
1490
+
gswip_port_set_duplex(priv, port, duplex);
1491
+
gswip_port_set_pause(priv, port, tx_pause, rx_pause);
1492
+
}
1493
+
1494
+
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, GSWIP_MII_CFG_EN, port);
1495
+
}
1496
+
1497
+
static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1498
+
uint8_t *data)
1499
+
{
1500
+
int i;
1501
+
1502
+
if (stringset != ETH_SS_STATS)
1503
+
return;
1504
+
1505
+
for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
1506
+
ethtool_puts(&data, gswip_rmon_cnt[i].name);
1507
+
}
1508
+
1509
+
static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
1510
+
u32 index)
1511
+
{
1512
+
u32 result, val;
1513
+
int err;
1514
+
1515
+
regmap_write(priv->gswip, GSWIP_BM_RAM_ADDR, index);
1516
+
regmap_write_bits(priv->gswip, GSWIP_BM_RAM_CTRL,
1517
+
GSWIP_BM_RAM_CTRL_ADDR_MASK | GSWIP_BM_RAM_CTRL_OPMOD |
1518
+
GSWIP_BM_RAM_CTRL_BAS,
1519
+
table | GSWIP_BM_RAM_CTRL_BAS);
1520
+
1521
+
err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
1522
+
GSWIP_BM_RAM_CTRL_BAS);
1523
+
if (err) {
1524
+
dev_err(priv->dev, "timeout while reading table: %u, index: %u\n",
1525
+
table, index);
1526
+
return 0;
1527
+
}
1528
+
1529
+
regmap_read(priv->gswip, GSWIP_BM_RAM_VAL(0), &result);
1530
+
regmap_read(priv->gswip, GSWIP_BM_RAM_VAL(1), &val);
1531
+
result |= val << 16;
1532
+
1533
+
return result;
1534
+
}
1535
+
1536
+
static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
1537
+
uint64_t *data)
1538
+
{
1539
+
struct gswip_priv *priv = ds->priv;
1540
+
const struct gswip_rmon_cnt_desc *rmon_cnt;
1541
+
int i;
1542
+
u64 high;
1543
+
1544
+
for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
1545
+
rmon_cnt = &gswip_rmon_cnt[i];
1546
+
1547
+
data[i] = gswip_bcm_ram_entry_read(priv, port,
1548
+
rmon_cnt->offset);
1549
+
if (rmon_cnt->size == 2) {
1550
+
high = gswip_bcm_ram_entry_read(priv, port,
1551
+
rmon_cnt->offset + 1);
1552
+
data[i] |= high << 32;
1553
+
}
1554
+
}
1555
+
}
1556
+
1557
+
static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
1558
+
{
1559
+
if (sset != ETH_SS_STATS)
1560
+
return 0;
1561
+
1562
+
return ARRAY_SIZE(gswip_rmon_cnt);
1563
+
}
1564
+
1565
+
static int gswip_set_mac_eee(struct dsa_switch *ds, int port,
1566
+
struct ethtool_keee *e)
1567
+
{
1568
+
if (e->tx_lpi_timer > 0x7f)
1569
+
return -EINVAL;
1570
+
1571
+
return 0;
1572
+
}
1573
+
1574
+
static void gswip_phylink_mac_disable_tx_lpi(struct phylink_config *config)
1575
+
{
1576
+
struct dsa_port *dp = dsa_phylink_to_port(config);
1577
+
struct gswip_priv *priv = dp->ds->priv;
1578
+
1579
+
regmap_clear_bits(priv->gswip, GSWIP_MAC_CTRL_4p(dp->index),
1580
+
GSWIP_MAC_CTRL_4_LPIEN);
1581
+
}
1582
+
1583
+
static int gswip_phylink_mac_enable_tx_lpi(struct phylink_config *config,
1584
+
u32 timer, bool tx_clock_stop)
1585
+
{
1586
+
struct dsa_port *dp = dsa_phylink_to_port(config);
1587
+
struct gswip_priv *priv = dp->ds->priv;
1588
+
1589
+
return regmap_update_bits(priv->gswip, GSWIP_MAC_CTRL_4p(dp->index),
1590
+
GSWIP_MAC_CTRL_4_LPIEN |
1591
+
GSWIP_MAC_CTRL_4_GWAIT_MASK |
1592
+
GSWIP_MAC_CTRL_4_WAIT_MASK,
1593
+
GSWIP_MAC_CTRL_4_LPIEN |
1594
+
GSWIP_MAC_CTRL_4_GWAIT(timer) |
1595
+
GSWIP_MAC_CTRL_4_WAIT(timer));
1596
+
}
1597
+
1598
+
static bool gswip_support_eee(struct dsa_switch *ds, int port)
1599
+
{
1600
+
struct gswip_priv *priv = ds->priv;
1601
+
1602
+
if (GSWIP_VERSION_GE(priv, GSWIP_VERSION_2_2))
1603
+
return true;
1604
+
1605
+
return false;
1606
+
}
1607
+
1608
+
static struct phylink_pcs *gswip_phylink_mac_select_pcs(struct phylink_config *config,
1609
+
phy_interface_t interface)
1610
+
{
1611
+
struct dsa_port *dp = dsa_phylink_to_port(config);
1612
+
struct gswip_priv *priv = dp->ds->priv;
1613
+
1614
+
if (priv->hw_info->mac_select_pcs)
1615
+
return priv->hw_info->mac_select_pcs(config, interface);
1616
+
1617
+
return NULL;
1618
+
}
1619
+
1620
+
static const struct phylink_mac_ops gswip_phylink_mac_ops = {
1621
+
.mac_config = gswip_phylink_mac_config,
1622
+
.mac_link_down = gswip_phylink_mac_link_down,
1623
+
.mac_link_up = gswip_phylink_mac_link_up,
1624
+
.mac_disable_tx_lpi = gswip_phylink_mac_disable_tx_lpi,
1625
+
.mac_enable_tx_lpi = gswip_phylink_mac_enable_tx_lpi,
1626
+
.mac_select_pcs = gswip_phylink_mac_select_pcs,
1627
+
};
1628
+
1629
+
static const struct dsa_switch_ops gswip_switch_ops = {
1630
+
.get_tag_protocol = gswip_get_tag_protocol,
1631
+
.setup = gswip_setup,
1632
+
.port_setup = gswip_port_setup,
1633
+
.port_enable = gswip_port_enable,
1634
+
.port_disable = gswip_port_disable,
1635
+
.port_pre_bridge_flags = gswip_port_pre_bridge_flags,
1636
+
.port_bridge_flags = gswip_port_bridge_flags,
1637
+
.port_bridge_join = gswip_port_bridge_join,
1638
+
.port_bridge_leave = gswip_port_bridge_leave,
1639
+
.port_fast_age = gswip_port_fast_age,
1640
+
.port_vlan_filtering = gswip_port_vlan_filtering,
1641
+
.port_vlan_add = gswip_port_vlan_add,
1642
+
.port_vlan_del = gswip_port_vlan_del,
1643
+
.port_stp_state_set = gswip_port_stp_state_set,
1644
+
.port_fdb_add = gswip_port_fdb_add,
1645
+
.port_fdb_del = gswip_port_fdb_del,
1646
+
.port_fdb_dump = gswip_port_fdb_dump,
1647
+
.port_change_mtu = gswip_port_change_mtu,
1648
+
.port_max_mtu = gswip_port_max_mtu,
1649
+
.phylink_get_caps = gswip_phylink_get_caps,
1650
+
.get_strings = gswip_get_strings,
1651
+
.get_ethtool_stats = gswip_get_ethtool_stats,
1652
+
.get_sset_count = gswip_get_sset_count,
1653
+
.set_mac_eee = gswip_set_mac_eee,
1654
+
.support_eee = gswip_support_eee,
1655
+
};
1656
+
1657
+
void gswip_disable_switch(struct gswip_priv *priv)
1658
+
{
1659
+
regmap_clear_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE);
1660
+
}
1661
+
EXPORT_SYMBOL_GPL(gswip_disable_switch);
1662
+
1663
+
static int gswip_validate_cpu_port(struct dsa_switch *ds)
1664
+
{
1665
+
struct gswip_priv *priv = ds->priv;
1666
+
struct dsa_port *cpu_dp;
1667
+
int cpu_port = -1;
1668
+
1669
+
dsa_switch_for_each_cpu_port(cpu_dp, ds) {
1670
+
if (cpu_port != -1)
1671
+
return dev_err_probe(ds->dev, -EINVAL,
1672
+
"only a single CPU port is supported\n");
1673
+
1674
+
cpu_port = cpu_dp->index;
1675
+
}
1676
+
1677
+
if (cpu_port == -1)
1678
+
return dev_err_probe(ds->dev, -EINVAL, "no CPU port defined\n");
1679
+
1680
+
if (BIT(cpu_port) & ~priv->hw_info->allowed_cpu_ports)
1681
+
return dev_err_probe(ds->dev, -EINVAL,
1682
+
"unsupported CPU port defined\n");
1683
+
1684
+
return 0;
1685
+
}
1686
+
1687
+
int gswip_probe_common(struct gswip_priv *priv, u32 version)
1688
+
{
1689
+
int err;
1690
+
1691
+
mutex_init(&priv->pce_table_lock);
1692
+
1693
+
priv->ds = devm_kzalloc(priv->dev, sizeof(*priv->ds), GFP_KERNEL);
1694
+
if (!priv->ds)
1695
+
return -ENOMEM;
1696
+
1697
+
priv->ds->dev = priv->dev;
1698
+
priv->ds->num_ports = priv->hw_info->max_ports;
1699
+
priv->ds->ops = &gswip_switch_ops;
1700
+
priv->ds->phylink_mac_ops = &gswip_phylink_mac_ops;
1701
+
priv->ds->priv = priv;
1702
+
1703
+
/* The hardware has the 'major/minor' version bytes in the wrong order
1704
+
* preventing numerical comparisons. Construct a 16-bit unsigned integer
1705
+
* having the REV field as most significant byte and the MOD field as
1706
+
* least significant byte. This is effectively swapping the two bytes of
1707
+
* the version variable, but other than using swab16 it doesn't affect
1708
+
* the source variable.
1709
+
*/
1710
+
priv->version = GSWIP_VERSION_REV(version) << 8 |
1711
+
GSWIP_VERSION_MOD(version);
1712
+
1713
+
err = dsa_register_switch(priv->ds);
1714
+
if (err)
1715
+
return dev_err_probe(priv->dev, err, "dsa switch registration failed\n");
1716
+
1717
+
err = gswip_validate_cpu_port(priv->ds);
1718
+
if (err)
1719
+
goto disable_switch;
1720
+
1721
+
dev_info(priv->dev, "probed GSWIP version %lx mod %lx\n",
1722
+
GSWIP_VERSION_REV(version), GSWIP_VERSION_MOD(version));
1723
+
1724
+
return 0;
1725
+
1726
+
disable_switch:
1727
+
gswip_disable_switch(priv);
1728
+
dsa_unregister_switch(priv->ds);
1729
+
1730
+
return err;
1731
+
}
1732
+
EXPORT_SYMBOL_GPL(gswip_probe_common);
1733
+
1734
+
MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
1735
+
MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
1736
+
MODULE_DESCRIPTION("Lantiq / Intel / MaxLinear GSWIP common functions");
1737
+
MODULE_LICENSE("GPL");
+733
drivers/net/dsa/lantiq/mxl-gsw1xx.c
+733
drivers/net/dsa/lantiq/mxl-gsw1xx.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/* DSA Driver for MaxLinear GSW1xx switch devices
3
+
*
4
+
* Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
5
+
* Copyright (C) 2023 - 2024 MaxLinear Inc.
6
+
* Copyright (C) 2022 Snap One, LLC. All rights reserved.
7
+
* Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
8
+
* Copyright (C) 2012 John Crispin <john@phrozen.org>
9
+
* Copyright (C) 2010 Lantiq Deutschland
10
+
*/
11
+
12
+
#include <linux/bits.h>
13
+
#include <linux/delay.h>
14
+
#include <linux/module.h>
15
+
#include <linux/of_device.h>
16
+
#include <linux/of_mdio.h>
17
+
#include <linux/regmap.h>
18
+
#include <net/dsa.h>
19
+
20
+
#include "lantiq_gswip.h"
21
+
#include "mxl-gsw1xx.h"
22
+
#include "mxl-gsw1xx_pce.h"
23
+
24
+
struct gsw1xx_priv {
25
+
struct mdio_device *mdio_dev;
26
+
int smdio_badr;
27
+
struct regmap *sgmii;
28
+
struct regmap *gpio;
29
+
struct regmap *clk;
30
+
struct regmap *shell;
31
+
struct phylink_pcs pcs;
32
+
phy_interface_t tbi_interface;
33
+
struct gswip_priv gswip;
34
+
};
35
+
36
+
static int gsw1xx_config_smdio_badr(struct gsw1xx_priv *priv,
37
+
unsigned int reg)
38
+
{
39
+
struct mii_bus *bus = priv->mdio_dev->bus;
40
+
int sw_addr = priv->mdio_dev->addr;
41
+
int smdio_badr = priv->smdio_badr;
42
+
int res;
43
+
44
+
if (smdio_badr == GSW1XX_SMDIO_BADR_UNKNOWN ||
45
+
reg - smdio_badr >= GSW1XX_SMDIO_BADR ||
46
+
smdio_badr > reg) {
47
+
/* Configure the Switch Base Address */
48
+
smdio_badr = reg & ~GENMASK(3, 0);
49
+
res = __mdiobus_write(bus, sw_addr, GSW1XX_SMDIO_BADR, smdio_badr);
50
+
if (res < 0) {
51
+
dev_err(&priv->mdio_dev->dev,
52
+
"%s: Error %d, configuring switch base\n",
53
+
__func__, res);
54
+
return res;
55
+
}
56
+
priv->smdio_badr = smdio_badr;
57
+
}
58
+
59
+
return smdio_badr;
60
+
}
61
+
62
+
static int gsw1xx_regmap_read(void *context, unsigned int reg,
63
+
unsigned int *val)
64
+
{
65
+
struct gsw1xx_priv *priv = context;
66
+
struct mii_bus *bus = priv->mdio_dev->bus;
67
+
int sw_addr = priv->mdio_dev->addr;
68
+
int smdio_badr;
69
+
int res;
70
+
71
+
smdio_badr = gsw1xx_config_smdio_badr(priv, reg);
72
+
if (smdio_badr < 0)
73
+
return smdio_badr;
74
+
75
+
res = __mdiobus_read(bus, sw_addr, reg - smdio_badr);
76
+
if (res < 0) {
77
+
dev_err(&priv->mdio_dev->dev, "%s: Error %d reading 0x%x\n",
78
+
__func__, res, reg);
79
+
return res;
80
+
}
81
+
82
+
*val = res;
83
+
84
+
return 0;
85
+
}
86
+
87
+
static int gsw1xx_regmap_write(void *context, unsigned int reg,
88
+
unsigned int val)
89
+
{
90
+
struct gsw1xx_priv *priv = context;
91
+
struct mii_bus *bus = priv->mdio_dev->bus;
92
+
int sw_addr = priv->mdio_dev->addr;
93
+
int smdio_badr;
94
+
int res;
95
+
96
+
smdio_badr = gsw1xx_config_smdio_badr(priv, reg);
97
+
if (smdio_badr < 0)
98
+
return smdio_badr;
99
+
100
+
res = __mdiobus_write(bus, sw_addr, reg - smdio_badr, val);
101
+
if (res < 0)
102
+
dev_err(&priv->mdio_dev->dev,
103
+
"%s: Error %d, writing 0x%x:0x%x\n", __func__, res, reg,
104
+
val);
105
+
106
+
return res;
107
+
}
108
+
109
+
static const struct regmap_bus gsw1xx_regmap_bus = {
110
+
.reg_write = gsw1xx_regmap_write,
111
+
.reg_read = gsw1xx_regmap_read,
112
+
};
113
+
114
+
static void gsw1xx_mdio_regmap_lock(void *mdio_lock)
115
+
{
116
+
mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
117
+
}
118
+
119
+
static void gsw1xx_mdio_regmap_unlock(void *mdio_lock)
120
+
{
121
+
mutex_unlock(mdio_lock);
122
+
}
123
+
124
+
static unsigned int gsw1xx_pcs_inband_caps(struct phylink_pcs *pcs,
125
+
phy_interface_t interface)
126
+
{
127
+
return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
128
+
}
129
+
130
+
static struct gsw1xx_priv *pcs_to_gsw1xx(struct phylink_pcs *pcs)
131
+
{
132
+
return container_of(pcs, struct gsw1xx_priv, pcs);
133
+
}
134
+
135
+
static int gsw1xx_pcs_enable(struct phylink_pcs *pcs)
136
+
{
137
+
struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
138
+
139
+
/* Deassert SGMII shell reset */
140
+
return regmap_clear_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
141
+
GSW1XX_RST_REQ_SGMII_SHELL);
142
+
}
143
+
144
+
static void gsw1xx_pcs_disable(struct phylink_pcs *pcs)
145
+
{
146
+
struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
147
+
148
+
/* Assert SGMII shell reset */
149
+
regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
150
+
GSW1XX_RST_REQ_SGMII_SHELL);
151
+
152
+
priv->tbi_interface = PHY_INTERFACE_MODE_NA;
153
+
}
154
+
155
+
static void gsw1xx_pcs_get_state(struct phylink_pcs *pcs,
156
+
unsigned int neg_mode,
157
+
struct phylink_link_state *state)
158
+
{
159
+
struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
160
+
int ret;
161
+
u32 val;
162
+
163
+
ret = regmap_read(priv->sgmii, GSW1XX_SGMII_TBI_TBISTAT, &val);
164
+
if (ret < 0)
165
+
return;
166
+
167
+
state->link = !!(val & GSW1XX_SGMII_TBI_TBISTAT_LINK);
168
+
state->an_complete = !!(val & GSW1XX_SGMII_TBI_TBISTAT_AN_COMPLETE);
169
+
170
+
ret = regmap_read(priv->sgmii, GSW1XX_SGMII_TBI_LPSTAT, &val);
171
+
if (ret < 0)
172
+
return;
173
+
174
+
state->duplex = (val & GSW1XX_SGMII_TBI_LPSTAT_DUPLEX) ?
175
+
DUPLEX_FULL : DUPLEX_HALF;
176
+
if (val & GSW1XX_SGMII_TBI_LPSTAT_PAUSE_RX)
177
+
state->pause |= MLO_PAUSE_RX;
178
+
179
+
if (val & GSW1XX_SGMII_TBI_LPSTAT_PAUSE_TX)
180
+
state->pause |= MLO_PAUSE_TX;
181
+
182
+
switch (FIELD_GET(GSW1XX_SGMII_TBI_LPSTAT_SPEED, val)) {
183
+
case GSW1XX_SGMII_TBI_LPSTAT_SPEED_10:
184
+
state->speed = SPEED_10;
185
+
break;
186
+
case GSW1XX_SGMII_TBI_LPSTAT_SPEED_100:
187
+
state->speed = SPEED_100;
188
+
break;
189
+
case GSW1XX_SGMII_TBI_LPSTAT_SPEED_1000:
190
+
state->speed = SPEED_1000;
191
+
break;
192
+
case GSW1XX_SGMII_TBI_LPSTAT_SPEED_NOSGMII:
193
+
if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
194
+
state->speed = SPEED_1000;
195
+
else if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
196
+
state->speed = SPEED_2500;
197
+
else
198
+
state->speed = SPEED_UNKNOWN;
199
+
break;
200
+
}
201
+
}
202
+
203
+
static int gsw1xx_pcs_phy_xaui_write(struct gsw1xx_priv *priv, u16 addr,
204
+
u16 data)
205
+
{
206
+
int ret, val;
207
+
208
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_D, data);
209
+
if (ret < 0)
210
+
return ret;
211
+
212
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_A, addr);
213
+
if (ret < 0)
214
+
return ret;
215
+
216
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_C,
217
+
GSW1XX_SGMII_PHY_WRITE |
218
+
GSW1XX_SGMII_PHY_RESET_N);
219
+
if (ret < 0)
220
+
return ret;
221
+
222
+
return regmap_read_poll_timeout(priv->sgmii, GSW1XX_SGMII_PHY_C,
223
+
val, val & GSW1XX_SGMII_PHY_STATUS,
224
+
1000, 100000);
225
+
}
226
+
227
+
static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv)
228
+
{
229
+
int ret;
230
+
u16 val;
231
+
232
+
/* Assert and deassert SGMII shell reset */
233
+
ret = regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
234
+
GSW1XX_RST_REQ_SGMII_SHELL);
235
+
if (ret < 0)
236
+
return ret;
237
+
238
+
ret = regmap_clear_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
239
+
GSW1XX_RST_REQ_SGMII_SHELL);
240
+
if (ret < 0)
241
+
return ret;
242
+
243
+
/* Hardware Bringup FSM Enable */
244
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_HWBU_CTRL,
245
+
GSW1XX_SGMII_PHY_HWBU_CTRL_EN_HWBU_FSM |
246
+
GSW1XX_SGMII_PHY_HWBU_CTRL_HW_FSM_EN);
247
+
if (ret < 0)
248
+
return ret;
249
+
250
+
/* Configure SGMII PHY Receiver */
251
+
val = FIELD_PREP(GSW1XX_SGMII_PHY_RX0_CFG2_EQ,
252
+
GSW1XX_SGMII_PHY_RX0_CFG2_EQ_DEF) |
253
+
GSW1XX_SGMII_PHY_RX0_CFG2_LOS_EN |
254
+
GSW1XX_SGMII_PHY_RX0_CFG2_TERM_EN |
255
+
FIELD_PREP(GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT,
256
+
GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF);
257
+
258
+
/* TODO: Take care of inverted RX pair once generic property is
259
+
* available
260
+
*/
261
+
262
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_RX0_CFG2, val);
263
+
if (ret < 0)
264
+
return ret;
265
+
266
+
val = FIELD_PREP(GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL,
267
+
GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF);
268
+
269
+
/* TODO: Take care of inverted TX pair once generic property is
270
+
* available
271
+
*/
272
+
273
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_TX0_CFG3, val);
274
+
if (ret < 0)
275
+
return ret;
276
+
277
+
/* Reset and Release TBI */
278
+
val = GSW1XX_SGMII_TBI_TBICTL_INITTBI | GSW1XX_SGMII_TBI_TBICTL_ENTBI |
279
+
GSW1XX_SGMII_TBI_TBICTL_CRSTRR | GSW1XX_SGMII_TBI_TBICTL_CRSOFF;
280
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_TBICTL, val);
281
+
if (ret < 0)
282
+
return ret;
283
+
val &= ~GSW1XX_SGMII_TBI_TBICTL_INITTBI;
284
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_TBICTL, val);
285
+
if (ret < 0)
286
+
return ret;
287
+
288
+
/* Release Tx Data Buffers */
289
+
ret = regmap_set_bits(priv->sgmii, GSW1XX_SGMII_PCS_TXB_CTL,
290
+
GSW1XX_SGMII_PCS_TXB_CTL_INIT_TX_TXB);
291
+
if (ret < 0)
292
+
return ret;
293
+
ret = regmap_clear_bits(priv->sgmii, GSW1XX_SGMII_PCS_TXB_CTL,
294
+
GSW1XX_SGMII_PCS_TXB_CTL_INIT_TX_TXB);
295
+
if (ret < 0)
296
+
return ret;
297
+
298
+
/* Release Rx Data Buffers */
299
+
ret = regmap_set_bits(priv->sgmii, GSW1XX_SGMII_PCS_RXB_CTL,
300
+
GSW1XX_SGMII_PCS_RXB_CTL_INIT_RX_RXB);
301
+
if (ret < 0)
302
+
return ret;
303
+
return regmap_clear_bits(priv->sgmii, GSW1XX_SGMII_PCS_RXB_CTL,
304
+
GSW1XX_SGMII_PCS_RXB_CTL_INIT_RX_RXB);
305
+
}
306
+
307
+
static int gsw1xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
308
+
phy_interface_t interface,
309
+
const unsigned long *advertising,
310
+
bool permit_pause_to_mac)
311
+
{
312
+
struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
313
+
u16 txaneg, anegctl, nco_ctrl;
314
+
bool reconf = false;
315
+
int ret = 0;
316
+
317
+
/* do not unnecessarily disrupt link and skip resetting the hardware in
318
+
* case the PCS has previously been successfully configured for this
319
+
* interface mode
320
+
*/
321
+
if (priv->tbi_interface == interface)
322
+
reconf = true;
323
+
324
+
/* mark PCS configuration as incomplete */
325
+
priv->tbi_interface = PHY_INTERFACE_MODE_NA;
326
+
327
+
if (!reconf)
328
+
ret = gsw1xx_pcs_reset(priv);
329
+
330
+
if (ret)
331
+
return ret;
332
+
333
+
/* override bootstrap pin settings
334
+
* OVRANEG sets ANEG Mode, Enable ANEG and restart ANEG to be
335
+
* taken from bits ANMODE, ANEGEN, RANEG of the ANEGCTL register.
336
+
* OVERABL sets ability bits in tx_config_reg to be taken from
337
+
* the TXANEGH and TXANEGL registers.
338
+
*/
339
+
anegctl = GSW1XX_SGMII_TBI_ANEGCTL_OVRANEG |
340
+
GSW1XX_SGMII_TBI_ANEGCTL_OVRABL;
341
+
342
+
switch (phylink_get_link_timer_ns(interface)) {
343
+
case 10000:
344
+
anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_LT,
345
+
GSW1XX_SGMII_TBI_ANEGCTL_LT_10US);
346
+
break;
347
+
case 1600000:
348
+
anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_LT,
349
+
GSW1XX_SGMII_TBI_ANEGCTL_LT_1_6MS);
350
+
break;
351
+
case 5000000:
352
+
anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_LT,
353
+
GSW1XX_SGMII_TBI_ANEGCTL_LT_5MS);
354
+
break;
355
+
case 10000000:
356
+
anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_LT,
357
+
GSW1XX_SGMII_TBI_ANEGCTL_LT_10MS);
358
+
break;
359
+
default:
360
+
return -EINVAL;
361
+
}
362
+
363
+
if (neg_mode & PHYLINK_PCS_NEG_INBAND)
364
+
anegctl |= GSW1XX_SGMII_TBI_ANEGCTL_ANEGEN;
365
+
366
+
txaneg = phylink_mii_c22_pcs_encode_advertisement(interface, advertising);
367
+
368
+
if (interface == PHY_INTERFACE_MODE_SGMII) {
369
+
/* lacking a defined reverse-SGMII interface mode this
370
+
* driver only supports SGMII (MAC side) for now
371
+
*/
372
+
anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_ANMODE,
373
+
GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_SGMII_MAC);
374
+
txaneg |= ADVERTISE_LPACK;
375
+
} else if (interface == PHY_INTERFACE_MODE_1000BASEX ||
376
+
interface == PHY_INTERFACE_MODE_2500BASEX) {
377
+
anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_ANMODE,
378
+
GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_1000BASEX);
379
+
} else {
380
+
dev_err(priv->gswip.dev, "%s: wrong interface mode %s\n",
381
+
__func__, phy_modes(interface));
382
+
return -EINVAL;
383
+
}
384
+
385
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_TXANEGH,
386
+
FIELD_GET(GENMASK(15, 8), txaneg));
387
+
if (ret < 0)
388
+
return ret;
389
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_TXANEGL,
390
+
FIELD_GET(GENMASK(7, 0), txaneg));
391
+
if (ret < 0)
392
+
return ret;
393
+
ret = regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL, anegctl);
394
+
if (ret < 0)
395
+
return ret;
396
+
397
+
if (!reconf) {
398
+
/* setup SerDes clock speed */
399
+
if (interface == PHY_INTERFACE_MODE_2500BASEX)
400
+
nco_ctrl = GSW1XX_SGMII_2G5 | GSW1XX_SGMII_2G5_NCO2;
401
+
else
402
+
nco_ctrl = GSW1XX_SGMII_1G | GSW1XX_SGMII_1G_NCO1;
403
+
404
+
ret = regmap_update_bits(priv->clk, GSW1XX_CLK_NCO_CTRL,
405
+
GSW1XX_SGMII_HSP_MASK |
406
+
GSW1XX_SGMII_SEL,
407
+
nco_ctrl);
408
+
if (ret)
409
+
return ret;
410
+
411
+
ret = gsw1xx_pcs_phy_xaui_write(priv, 0x30, 0x80);
412
+
if (ret)
413
+
return ret;
414
+
}
415
+
416
+
/* PCS configuration has now been completed, store mode to prevent
417
+
* disrupting the link in case of future calls of this function for the
418
+
* same interface mode.
419
+
*/
420
+
priv->tbi_interface = interface;
421
+
422
+
return 0;
423
+
}
424
+
425
+
static void gsw1xx_pcs_an_restart(struct phylink_pcs *pcs)
426
+
{
427
+
struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
428
+
429
+
regmap_set_bits(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL,
430
+
GSW1XX_SGMII_TBI_ANEGCTL_RANEG);
431
+
}
432
+
433
+
static void gsw1xx_pcs_link_up(struct phylink_pcs *pcs,
434
+
unsigned int neg_mode,
435
+
phy_interface_t interface, int speed,
436
+
int duplex)
437
+
{
438
+
struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
439
+
u16 lpstat;
440
+
441
+
/* When in-band AN is enabled hardware will set lpstat */
442
+
if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
443
+
return;
444
+
445
+
/* Force speed and duplex settings */
446
+
if (interface == PHY_INTERFACE_MODE_SGMII) {
447
+
if (speed == SPEED_10)
448
+
lpstat = FIELD_PREP(GSW1XX_SGMII_TBI_LPSTAT_SPEED,
449
+
GSW1XX_SGMII_TBI_LPSTAT_SPEED_10);
450
+
else if (speed == SPEED_100)
451
+
lpstat = FIELD_PREP(GSW1XX_SGMII_TBI_LPSTAT_SPEED,
452
+
GSW1XX_SGMII_TBI_LPSTAT_SPEED_100);
453
+
else
454
+
lpstat = FIELD_PREP(GSW1XX_SGMII_TBI_LPSTAT_SPEED,
455
+
GSW1XX_SGMII_TBI_LPSTAT_SPEED_1000);
456
+
} else {
457
+
lpstat = FIELD_PREP(GSW1XX_SGMII_TBI_LPSTAT_SPEED,
458
+
GSW1XX_SGMII_TBI_LPSTAT_SPEED_NOSGMII);
459
+
}
460
+
461
+
if (duplex == DUPLEX_FULL)
462
+
lpstat |= GSW1XX_SGMII_TBI_LPSTAT_DUPLEX;
463
+
464
+
regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_LPSTAT, lpstat);
465
+
}
466
+
467
+
static const struct phylink_pcs_ops gsw1xx_pcs_ops = {
468
+
.pcs_inband_caps = gsw1xx_pcs_inband_caps,
469
+
.pcs_enable = gsw1xx_pcs_enable,
470
+
.pcs_disable = gsw1xx_pcs_disable,
471
+
.pcs_get_state = gsw1xx_pcs_get_state,
472
+
.pcs_config = gsw1xx_pcs_config,
473
+
.pcs_an_restart = gsw1xx_pcs_an_restart,
474
+
.pcs_link_up = gsw1xx_pcs_link_up,
475
+
};
476
+
477
+
static void gsw1xx_phylink_get_caps(struct dsa_switch *ds, int port,
478
+
struct phylink_config *config)
479
+
{
480
+
struct gswip_priv *priv = ds->priv;
481
+
482
+
config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
483
+
MAC_10 | MAC_100 | MAC_1000;
484
+
485
+
switch (port) {
486
+
case 0:
487
+
case 1:
488
+
case 2:
489
+
case 3:
490
+
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
491
+
config->supported_interfaces);
492
+
break;
493
+
case 4: /* port 4: SGMII */
494
+
__set_bit(PHY_INTERFACE_MODE_SGMII,
495
+
config->supported_interfaces);
496
+
__set_bit(PHY_INTERFACE_MODE_1000BASEX,
497
+
config->supported_interfaces);
498
+
if (priv->hw_info->supports_2500m) {
499
+
__set_bit(PHY_INTERFACE_MODE_2500BASEX,
500
+
config->supported_interfaces);
501
+
config->mac_capabilities |= MAC_2500FD;
502
+
}
503
+
return; /* no support for EEE on SGMII port */
504
+
case 5: /* port 5: RGMII or RMII */
505
+
__set_bit(PHY_INTERFACE_MODE_RMII,
506
+
config->supported_interfaces);
507
+
phy_interface_set_rgmii(config->supported_interfaces);
508
+
break;
509
+
}
510
+
511
+
config->lpi_capabilities = MAC_100FD | MAC_1000FD;
512
+
config->lpi_timer_default = 20;
513
+
memcpy(config->lpi_interfaces, config->supported_interfaces,
514
+
sizeof(config->lpi_interfaces));
515
+
}
516
+
517
+
static struct phylink_pcs *gsw1xx_phylink_mac_select_pcs(struct phylink_config *config,
518
+
phy_interface_t interface)
519
+
{
520
+
struct dsa_port *dp = dsa_phylink_to_port(config);
521
+
struct gswip_priv *gswip_priv = dp->ds->priv;
522
+
struct gsw1xx_priv *gsw1xx_priv = container_of(gswip_priv,
523
+
struct gsw1xx_priv,
524
+
gswip);
525
+
526
+
switch (dp->index) {
527
+
case GSW1XX_SGMII_PORT:
528
+
return &gsw1xx_priv->pcs;
529
+
default:
530
+
return NULL;
531
+
}
532
+
}
533
+
534
+
static struct regmap *gsw1xx_regmap_init(struct gsw1xx_priv *priv,
535
+
const char *name,
536
+
unsigned int reg_base,
537
+
unsigned int max_register)
538
+
{
539
+
const struct regmap_config config = {
540
+
.name = name,
541
+
.reg_bits = 16,
542
+
.val_bits = 16,
543
+
.reg_base = reg_base,
544
+
.max_register = max_register,
545
+
.lock = gsw1xx_mdio_regmap_lock,
546
+
.unlock = gsw1xx_mdio_regmap_unlock,
547
+
.lock_arg = &priv->mdio_dev->bus->mdio_lock,
548
+
};
549
+
550
+
return devm_regmap_init(&priv->mdio_dev->dev, &gsw1xx_regmap_bus,
551
+
priv, &config);
552
+
}
553
+
554
+
static int gsw1xx_probe(struct mdio_device *mdiodev)
555
+
{
556
+
struct device *dev = &mdiodev->dev;
557
+
struct gsw1xx_priv *priv;
558
+
u32 version;
559
+
int ret;
560
+
561
+
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
562
+
if (!priv)
563
+
return -ENOMEM;
564
+
565
+
priv->mdio_dev = mdiodev;
566
+
priv->smdio_badr = GSW1XX_SMDIO_BADR_UNKNOWN;
567
+
568
+
priv->gswip.dev = dev;
569
+
priv->gswip.hw_info = of_device_get_match_data(dev);
570
+
if (!priv->gswip.hw_info)
571
+
return -EINVAL;
572
+
573
+
priv->gswip.gswip = gsw1xx_regmap_init(priv, "switch",
574
+
GSW1XX_SWITCH_BASE, 0xfff);
575
+
if (IS_ERR(priv->gswip.gswip))
576
+
return PTR_ERR(priv->gswip.gswip);
577
+
578
+
priv->gswip.mdio = gsw1xx_regmap_init(priv, "mdio", GSW1XX_MMDIO_BASE,
579
+
0xff);
580
+
if (IS_ERR(priv->gswip.mdio))
581
+
return PTR_ERR(priv->gswip.mdio);
582
+
583
+
priv->gswip.mii = gsw1xx_regmap_init(priv, "mii", GSW1XX_RGMII_BASE,
584
+
0xff);
585
+
if (IS_ERR(priv->gswip.mii))
586
+
return PTR_ERR(priv->gswip.mii);
587
+
588
+
priv->sgmii = gsw1xx_regmap_init(priv, "sgmii", GSW1XX_SGMII_BASE,
589
+
0xfff);
590
+
if (IS_ERR(priv->sgmii))
591
+
return PTR_ERR(priv->sgmii);
592
+
593
+
priv->gpio = gsw1xx_regmap_init(priv, "gpio", GSW1XX_GPIO_BASE, 0xff);
594
+
if (IS_ERR(priv->gpio))
595
+
return PTR_ERR(priv->gpio);
596
+
597
+
priv->clk = gsw1xx_regmap_init(priv, "clk", GSW1XX_CLK_BASE, 0xff);
598
+
if (IS_ERR(priv->clk))
599
+
return PTR_ERR(priv->clk);
600
+
601
+
priv->shell = gsw1xx_regmap_init(priv, "shell", GSW1XX_SHELL_BASE,
602
+
0xff);
603
+
if (IS_ERR(priv->shell))
604
+
return PTR_ERR(priv->shell);
605
+
606
+
priv->pcs.ops = &gsw1xx_pcs_ops;
607
+
priv->pcs.poll = true;
608
+
__set_bit(PHY_INTERFACE_MODE_SGMII,
609
+
priv->pcs.supported_interfaces);
610
+
__set_bit(PHY_INTERFACE_MODE_1000BASEX,
611
+
priv->pcs.supported_interfaces);
612
+
if (priv->gswip.hw_info->supports_2500m)
613
+
__set_bit(PHY_INTERFACE_MODE_2500BASEX,
614
+
priv->pcs.supported_interfaces);
615
+
priv->tbi_interface = PHY_INTERFACE_MODE_NA;
616
+
617
+
/* assert SGMII reset to power down SGMII unit */
618
+
ret = regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
619
+
GSW1XX_RST_REQ_SGMII_SHELL);
620
+
if (ret < 0)
621
+
return ret;
622
+
623
+
/* configure GPIO pin-mux for MMDIO in case of external PHY connected to
624
+
* SGMII or RGMII as slave interface
625
+
*/
626
+
regmap_set_bits(priv->gpio, GPIO_ALTSEL0, 3);
627
+
regmap_set_bits(priv->gpio, GPIO_ALTSEL1, 3);
628
+
629
+
ret = regmap_read(priv->gswip.gswip, GSWIP_VERSION, &version);
630
+
if (ret)
631
+
return ret;
632
+
633
+
ret = gswip_probe_common(&priv->gswip, version);
634
+
if (ret)
635
+
return ret;
636
+
637
+
dev_set_drvdata(dev, &priv->gswip);
638
+
639
+
return 0;
640
+
}
641
+
642
+
static void gsw1xx_remove(struct mdio_device *mdiodev)
643
+
{
644
+
struct gswip_priv *priv = dev_get_drvdata(&mdiodev->dev);
645
+
646
+
if (!priv)
647
+
return;
648
+
649
+
gswip_disable_switch(priv);
650
+
651
+
dsa_unregister_switch(priv->ds);
652
+
}
653
+
654
+
static void gsw1xx_shutdown(struct mdio_device *mdiodev)
655
+
{
656
+
struct gswip_priv *priv = dev_get_drvdata(&mdiodev->dev);
657
+
658
+
if (!priv)
659
+
return;
660
+
661
+
dev_set_drvdata(&mdiodev->dev, NULL);
662
+
663
+
gswip_disable_switch(priv);
664
+
}
665
+
666
+
static const struct gswip_hw_info gsw12x_data = {
667
+
.max_ports = GSW1XX_PORTS,
668
+
.allowed_cpu_ports = BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT),
669
+
.mii_ports = BIT(GSW1XX_MII_PORT),
670
+
.mii_port_reg_offset = -GSW1XX_MII_PORT,
671
+
.mac_select_pcs = gsw1xx_phylink_mac_select_pcs,
672
+
.phylink_get_caps = &gsw1xx_phylink_get_caps,
673
+
.supports_2500m = true,
674
+
.pce_microcode = &gsw1xx_pce_microcode,
675
+
.pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode),
676
+
.tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX,
677
+
};
678
+
679
+
static const struct gswip_hw_info gsw140_data = {
680
+
.max_ports = GSW1XX_PORTS,
681
+
.allowed_cpu_ports = BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT),
682
+
.mii_ports = BIT(GSW1XX_MII_PORT),
683
+
.mii_port_reg_offset = -GSW1XX_MII_PORT,
684
+
.mac_select_pcs = gsw1xx_phylink_mac_select_pcs,
685
+
.phylink_get_caps = &gsw1xx_phylink_get_caps,
686
+
.supports_2500m = true,
687
+
.pce_microcode = &gsw1xx_pce_microcode,
688
+
.pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode),
689
+
.tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX,
690
+
};
691
+
692
+
static const struct gswip_hw_info gsw141_data = {
693
+
.max_ports = GSW1XX_PORTS,
694
+
.allowed_cpu_ports = BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT),
695
+
.mii_ports = BIT(GSW1XX_MII_PORT),
696
+
.mii_port_reg_offset = -GSW1XX_MII_PORT,
697
+
.mac_select_pcs = gsw1xx_phylink_mac_select_pcs,
698
+
.phylink_get_caps = gsw1xx_phylink_get_caps,
699
+
.pce_microcode = &gsw1xx_pce_microcode,
700
+
.pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode),
701
+
.tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX,
702
+
};
703
+
704
+
/*
705
+
* GSW125 is the industrial temperature version of GSW120.
706
+
* GSW145 is the industrial temperature version of GSW140.
707
+
*/
708
+
static const struct of_device_id gsw1xx_of_match[] = {
709
+
{ .compatible = "maxlinear,gsw120", .data = &gsw12x_data },
710
+
{ .compatible = "maxlinear,gsw125", .data = &gsw12x_data },
711
+
{ .compatible = "maxlinear,gsw140", .data = &gsw140_data },
712
+
{ .compatible = "maxlinear,gsw141", .data = &gsw141_data },
713
+
{ .compatible = "maxlinear,gsw145", .data = &gsw140_data },
714
+
{ /* sentinel */ },
715
+
};
716
+
717
+
MODULE_DEVICE_TABLE(of, gsw1xx_of_match);
718
+
719
+
static struct mdio_driver gsw1xx_driver = {
720
+
.probe = gsw1xx_probe,
721
+
.remove = gsw1xx_remove,
722
+
.shutdown = gsw1xx_shutdown,
723
+
.mdiodrv.driver = {
724
+
.name = "mxl-gsw1xx",
725
+
.of_match_table = gsw1xx_of_match,
726
+
},
727
+
};
728
+
729
+
mdio_module_driver(gsw1xx_driver);
730
+
731
+
MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
732
+
MODULE_DESCRIPTION("Driver for MaxLinear GSW1xx ethernet switch");
733
+
MODULE_LICENSE("GPL");
+126
drivers/net/dsa/lantiq/mxl-gsw1xx.h
+126
drivers/net/dsa/lantiq/mxl-gsw1xx.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/* Register definitions for MaxLinear GSW1xx series switches
3
+
*
4
+
* Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
5
+
* Copyright (C) 2023 - 2024 MaxLinear Inc.
6
+
*/
7
+
#ifndef __MXL_GSW1XX_H
8
+
#define __MXL_GSW1XX_H
9
+
10
+
#include <linux/bitfield.h>
11
+
12
+
#define GSW1XX_PORTS 6
13
+
/* Port used for RGMII or optional RMII */
14
+
#define GSW1XX_MII_PORT 5
15
+
/* Port used for SGMII */
16
+
#define GSW1XX_SGMII_PORT 4
17
+
18
+
#define GSW1XX_SYS_CLK_FREQ 340000000
19
+
20
+
/* SMDIO switch register base address */
21
+
#define GSW1XX_SMDIO_BADR 0x1f
22
+
#define GSW1XX_SMDIO_BADR_UNKNOWN -1
23
+
24
+
/* GSW1XX SGMII PCS */
25
+
#define GSW1XX_SGMII_BASE 0xd000
26
+
#define GSW1XX_SGMII_PHY_HWBU_CTRL 0x009
27
+
#define GSW1XX_SGMII_PHY_HWBU_CTRL_EN_HWBU_FSM BIT(0)
28
+
#define GSW1XX_SGMII_PHY_HWBU_CTRL_HW_FSM_EN BIT(3)
29
+
#define GSW1XX_SGMII_TBI_TXANEGH 0x300
30
+
#define GSW1XX_SGMII_TBI_TXANEGL 0x301
31
+
#define GSW1XX_SGMII_TBI_ANEGCTL 0x304
32
+
#define GSW1XX_SGMII_TBI_ANEGCTL_LT GENMASK(1, 0)
33
+
#define GSW1XX_SGMII_TBI_ANEGCTL_LT_10US 0
34
+
#define GSW1XX_SGMII_TBI_ANEGCTL_LT_1_6MS 1
35
+
#define GSW1XX_SGMII_TBI_ANEGCTL_LT_5MS 2
36
+
#define GSW1XX_SGMII_TBI_ANEGCTL_LT_10MS 3
37
+
#define GSW1XX_SGMII_TBI_ANEGCTL_ANEGEN BIT(2)
38
+
#define GSW1XX_SGMII_TBI_ANEGCTL_RANEG BIT(3)
39
+
#define GSW1XX_SGMII_TBI_ANEGCTL_OVRABL BIT(4)
40
+
#define GSW1XX_SGMII_TBI_ANEGCTL_OVRANEG BIT(5)
41
+
#define GSW1XX_SGMII_TBI_ANEGCTL_ANMODE GENMASK(7, 6)
42
+
#define GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_1000BASEX 1
43
+
#define GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_SGMII_PHY 2
44
+
#define GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_SGMII_MAC 3
45
+
#define GSW1XX_SGMII_TBI_ANEGCTL_BCOMP BIT(15)
46
+
47
+
#define GSW1XX_SGMII_TBI_TBICTL 0x305
48
+
#define GSW1XX_SGMII_TBI_TBICTL_INITTBI BIT(0)
49
+
#define GSW1XX_SGMII_TBI_TBICTL_ENTBI BIT(1)
50
+
#define GSW1XX_SGMII_TBI_TBICTL_CRSTRR BIT(4)
51
+
#define GSW1XX_SGMII_TBI_TBICTL_CRSOFF BIT(5)
52
+
#define GSW1XX_SGMII_TBI_TBISTAT 0x309
53
+
#define GSW1XX_SGMII_TBI_TBISTAT_LINK BIT(0)
54
+
#define GSW1XX_SGMII_TBI_TBISTAT_AN_COMPLETE BIT(1)
55
+
#define GSW1XX_SGMII_TBI_LPSTAT 0x30a
56
+
#define GSW1XX_SGMII_TBI_LPSTAT_DUPLEX BIT(0)
57
+
#define GSW1XX_SGMII_TBI_LPSTAT_PAUSE_RX BIT(1)
58
+
#define GSW1XX_SGMII_TBI_LPSTAT_PAUSE_TX BIT(2)
59
+
#define GSW1XX_SGMII_TBI_LPSTAT_SPEED GENMASK(6, 5)
60
+
#define GSW1XX_SGMII_TBI_LPSTAT_SPEED_10 0
61
+
#define GSW1XX_SGMII_TBI_LPSTAT_SPEED_100 1
62
+
#define GSW1XX_SGMII_TBI_LPSTAT_SPEED_1000 2
63
+
#define GSW1XX_SGMII_TBI_LPSTAT_SPEED_NOSGMII 3
64
+
#define GSW1XX_SGMII_PHY_D 0x100
65
+
#define GSW1XX_SGMII_PHY_A 0x101
66
+
#define GSW1XX_SGMII_PHY_C 0x102
67
+
#define GSW1XX_SGMII_PHY_STATUS BIT(0)
68
+
#define GSW1XX_SGMII_PHY_READ BIT(4)
69
+
#define GSW1XX_SGMII_PHY_WRITE BIT(8)
70
+
#define GSW1XX_SGMII_PHY_RESET_N BIT(12)
71
+
#define GSW1XX_SGMII_PCS_RXB_CTL 0x401
72
+
#define GSW1XX_SGMII_PCS_RXB_CTL_INIT_RX_RXB BIT(1)
73
+
#define GSW1XX_SGMII_PCS_TXB_CTL 0x404
74
+
#define GSW1XX_SGMII_PCS_TXB_CTL_INIT_TX_TXB BIT(1)
75
+
76
+
#define GSW1XX_SGMII_PHY_RX0_CFG2 0x004
77
+
#define GSW1XX_SGMII_PHY_RX0_CFG2_EQ GENMASK(2, 0)
78
+
#define GSW1XX_SGMII_PHY_RX0_CFG2_EQ_DEF 2
79
+
#define GSW1XX_SGMII_PHY_RX0_CFG2_INVERT BIT(3)
80
+
#define GSW1XX_SGMII_PHY_RX0_CFG2_LOS_EN BIT(4)
81
+
#define GSW1XX_SGMII_PHY_RX0_CFG2_TERM_EN BIT(5)
82
+
#define GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT GENMASK(12, 6)
83
+
#define GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF 20
84
+
85
+
#define GSW1XX_SGMII_PHY_TX0_CFG3 0x007
86
+
#define GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_EN BIT(12)
87
+
#define GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL GENMASK(11, 9)
88
+
#define GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF 4
89
+
#define GSW1XX_SGMII_PHY_TX0_CFG3_INVERT BIT(8)
90
+
91
+
/* GSW1XX PDI Registers */
92
+
#define GSW1XX_SWITCH_BASE 0xe000
93
+
94
+
/* GSW1XX MII Registers */
95
+
#define GSW1XX_RGMII_BASE 0xf100
96
+
97
+
/* GSW1XX GPIO Registers */
98
+
#define GSW1XX_GPIO_BASE 0xf300
99
+
#define GPIO_ALTSEL0 0x83
100
+
#define GPIO_ALTSEL0_EXTPHY_MUX_VAL 0x03c3
101
+
#define GPIO_ALTSEL1 0x84
102
+
#define GPIO_ALTSEL1_EXTPHY_MUX_VAL 0x003f
103
+
104
+
/* MDIO bus controller */
105
+
#define GSW1XX_MMDIO_BASE 0xf400
106
+
107
+
/* generic IC registers */
108
+
#define GSW1XX_SHELL_BASE 0xfa00
109
+
#define GSW1XX_SHELL_RST_REQ 0x01
110
+
#define GSW1XX_RST_REQ_SGMII_SHELL BIT(5)
111
+
/* RGMII PAD Slew Control Register */
112
+
#define GSW1XX_SHELL_RGMII_SLEW_CFG 0x78
113
+
#define RGMII_SLEW_CFG_RX_2_5_V BIT(4)
114
+
#define RGMII_SLEW_CFG_TX_2_5_V BIT(5)
115
+
116
+
/* SGMII clock related settings */
117
+
#define GSW1XX_CLK_BASE 0xf900
118
+
#define GSW1XX_CLK_NCO_CTRL 0x68
119
+
#define GSW1XX_SGMII_HSP_MASK GENMASK(3, 2)
120
+
#define GSW1XX_SGMII_SEL BIT(1)
121
+
#define GSW1XX_SGMII_1G 0x0
122
+
#define GSW1XX_SGMII_2G5 0xc
123
+
#define GSW1XX_SGMII_1G_NCO1 0x0
124
+
#define GSW1XX_SGMII_2G5_NCO2 0x2
125
+
126
+
#endif /* __MXL_GSW1XX_H */
+154
drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h
+154
drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* PCE microcode code update for driver for MaxLinear GSW1xx switch chips
4
+
*
5
+
* Copyright (C) 2023 - 2024 MaxLinear Inc.
6
+
* Copyright (C) 2022 Snap One, LLC. All rights reserved.
7
+
* Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
8
+
* Copyright (C) 2012 John Crispin <john@phrozen.org>
9
+
* Copyright (C) 2010 Lantiq Deutschland
10
+
*/
11
+
12
+
#include "lantiq_gswip.h"
13
+
14
+
#define INSTR 0
15
+
#define IPV6 1
16
+
#define LENACCU 2
17
+
18
+
/* GSWIP_2.X */
19
+
enum {
20
+
OUT_MAC0 = 0,
21
+
OUT_MAC1,
22
+
OUT_MAC2,
23
+
OUT_MAC3,
24
+
OUT_MAC4,
25
+
OUT_MAC5,
26
+
OUT_ETHTYP,
27
+
OUT_VTAG0,
28
+
OUT_VTAG1,
29
+
OUT_ITAG0,
30
+
OUT_ITAG1, /* 10 */
31
+
OUT_ITAG2,
32
+
OUT_ITAG3,
33
+
OUT_IP0,
34
+
OUT_IP1,
35
+
OUT_IP2,
36
+
OUT_IP3,
37
+
OUT_SIP0,
38
+
OUT_SIP1,
39
+
OUT_SIP2,
40
+
OUT_SIP3, /* 20 */
41
+
OUT_SIP4,
42
+
OUT_SIP5,
43
+
OUT_SIP6,
44
+
OUT_SIP7,
45
+
OUT_DIP0,
46
+
OUT_DIP1,
47
+
OUT_DIP2,
48
+
OUT_DIP3,
49
+
OUT_DIP4,
50
+
OUT_DIP5, /* 30 */
51
+
OUT_DIP6,
52
+
OUT_DIP7,
53
+
OUT_SESID,
54
+
OUT_PROT,
55
+
OUT_APP0,
56
+
OUT_APP1,
57
+
OUT_IGMP0,
58
+
OUT_IGMP1,
59
+
OUT_STAG0 = 61,
60
+
OUT_STAG1 = 62,
61
+
OUT_NONE = 63,
62
+
};
63
+
64
+
/* parser's microcode flag type */
65
+
enum {
66
+
FLAG_ITAG = 0,
67
+
FLAG_VLAN,
68
+
FLAG_SNAP,
69
+
FLAG_PPPOE,
70
+
FLAG_IPV6,
71
+
FLAG_IPV6FL,
72
+
FLAG_IPV4,
73
+
FLAG_IGMP,
74
+
FLAG_TU,
75
+
FLAG_HOP,
76
+
FLAG_NN1, /* 10 */
77
+
FLAG_NN2,
78
+
FLAG_END,
79
+
FLAG_NO, /* 13 */
80
+
FLAG_SVLAN, /* 14 */
81
+
};
82
+
83
+
#define PCE_MC_M(val, msk, ns, out, len, type, flags, ipv4_len) \
84
+
{ (val), (msk), ((ns) << 10 | (out) << 4 | (len) >> 1),\
85
+
((len) & 1) << 15 | (type) << 13 | (flags) << 9 | (ipv4_len) << 8 }
86
+
87
+
/* V22_2X (IPv6 issue fixed) */
88
+
static const struct gswip_pce_microcode gsw1xx_pce_microcode[] = {
89
+
/* value mask ns fields L type flags ipv4_len */
90
+
PCE_MC_M(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
91
+
PCE_MC_M(0x8100, 0xFFFF, 4, OUT_STAG0, 2, INSTR, FLAG_SVLAN, 0),
92
+
PCE_MC_M(0x88A8, 0xFFFF, 4, OUT_STAG0, 2, INSTR, FLAG_SVLAN, 0),
93
+
PCE_MC_M(0x9100, 0xFFFF, 4, OUT_STAG0, 2, INSTR, FLAG_SVLAN, 0),
94
+
PCE_MC_M(0x8100, 0xFFFF, 5, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
95
+
PCE_MC_M(0x88A8, 0xFFFF, 6, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
96
+
PCE_MC_M(0x9100, 0xFFFF, 4, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
97
+
PCE_MC_M(0x8864, 0xFFFF, 20, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
98
+
PCE_MC_M(0x0800, 0xFFFF, 24, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
99
+
PCE_MC_M(0x86DD, 0xFFFF, 25, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
100
+
PCE_MC_M(0x8863, 0xFFFF, 19, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
101
+
PCE_MC_M(0x0000, 0xF800, 13, OUT_NONE, 0, INSTR, FLAG_NO, 0),
102
+
PCE_MC_M(0x0000, 0x0000, 44, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
103
+
PCE_MC_M(0x0600, 0x0600, 44, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
104
+
PCE_MC_M(0x0000, 0x0000, 15, OUT_NONE, 1, INSTR, FLAG_NO, 0),
105
+
PCE_MC_M(0xAAAA, 0xFFFF, 17, OUT_NONE, 1, INSTR, FLAG_NO, 0),
106
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_NO, 0),
107
+
PCE_MC_M(0x0300, 0xFF00, 45, OUT_NONE, 0, INSTR, FLAG_SNAP, 0),
108
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_NO, 0),
109
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_DIP7, 3, INSTR, FLAG_NO, 0),
110
+
PCE_MC_M(0x0000, 0x0000, 21, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0),
111
+
PCE_MC_M(0x0021, 0xFFFF, 24, OUT_NONE, 1, INSTR, FLAG_NO, 0),
112
+
PCE_MC_M(0x0057, 0xFFFF, 25, OUT_NONE, 1, INSTR, FLAG_NO, 0),
113
+
PCE_MC_M(0x0000, 0x0000, 44, OUT_NONE, 0, INSTR, FLAG_NO, 0),
114
+
PCE_MC_M(0x4000, 0xF000, 27, OUT_IP0, 4, INSTR, FLAG_IPV4, 1),
115
+
PCE_MC_M(0x6000, 0xF000, 30, OUT_IP0, 3, INSTR, FLAG_IPV6, 0),
116
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_NO, 0),
117
+
PCE_MC_M(0x0000, 0x0000, 28, OUT_IP3, 2, INSTR, FLAG_NO, 0),
118
+
PCE_MC_M(0x0000, 0x0000, 29, OUT_SIP0, 4, INSTR, FLAG_NO, 0),
119
+
PCE_MC_M(0x0000, 0x0000, 44, OUT_NONE, 0, LENACCU, FLAG_NO, 0),
120
+
PCE_MC_M(0x1100, 0xFF00, 43, OUT_PROT, 1, INSTR, FLAG_NO, 0),
121
+
PCE_MC_M(0x0600, 0xFF00, 43, OUT_PROT, 1, INSTR, FLAG_NO, 0),
122
+
PCE_MC_M(0x0000, 0xFF00, 36, OUT_IP3, 17, INSTR, FLAG_HOP, 0),
123
+
PCE_MC_M(0x2B00, 0xFF00, 36, OUT_IP3, 17, INSTR, FLAG_NN1, 0),
124
+
PCE_MC_M(0x3C00, 0xFF00, 36, OUT_IP3, 17, INSTR, FLAG_NN2, 0),
125
+
PCE_MC_M(0x0000, 0x0000, 43, OUT_PROT, 1, INSTR, FLAG_NO, 0),
126
+
PCE_MC_M(0x0000, 0x00F0, 38, OUT_NONE, 0, INSTR, FLAG_NO, 0),
127
+
PCE_MC_M(0x0000, 0x0000, 44, OUT_NONE, 0, INSTR, FLAG_NO, 0),
128
+
PCE_MC_M(0x0000, 0xFF00, 36, OUT_NONE, 0, IPV6, FLAG_HOP, 0),
129
+
PCE_MC_M(0x2B00, 0xFF00, 36, OUT_NONE, 0, IPV6, FLAG_NN1, 0),
130
+
PCE_MC_M(0x3C00, 0xFF00, 36, OUT_NONE, 0, IPV6, FLAG_NN2, 0),
131
+
PCE_MC_M(0x0000, 0x00FC, 44, OUT_PROT, 0, IPV6, FLAG_NO, 0),
132
+
PCE_MC_M(0x0000, 0x0000, 44, OUT_NONE, 0, IPV6, FLAG_NO, 0),
133
+
PCE_MC_M(0x0000, 0x0000, 44, OUT_SIP0, 16, INSTR, FLAG_NO, 0),
134
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_APP0, 4, INSTR, FLAG_IGMP, 0),
135
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
136
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
137
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
138
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
139
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
140
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
141
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
142
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
143
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
144
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
145
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
146
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
147
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
148
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
149
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
150
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
151
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
152
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
153
+
PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0),
154
+
};
+2
include/net/dsa.h
+2
include/net/dsa.h
···
56
56
#define DSA_TAG_PROTO_VSC73XX_8021Q_VALUE 28
57
57
#define DSA_TAG_PROTO_BRCM_LEGACY_FCS_VALUE 29
58
58
#define DSA_TAG_PROTO_YT921X_VALUE 30
59
+
#define DSA_TAG_PROTO_MXL_GSW1XX_VALUE 31
59
60
60
61
enum dsa_tag_protocol {
61
62
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
···
90
89
DSA_TAG_PROTO_LAN937X = DSA_TAG_PROTO_LAN937X_VALUE,
91
90
DSA_TAG_PROTO_VSC73XX_8021Q = DSA_TAG_PROTO_VSC73XX_8021Q_VALUE,
92
91
DSA_TAG_PROTO_YT921X = DSA_TAG_PROTO_YT921X_VALUE,
92
+
DSA_TAG_PROTO_MXL_GSW1XX = DSA_TAG_PROTO_MXL_GSW1XX_VALUE,
93
93
};
94
94
95
95
struct dsa_switch;
+1
include/uapi/linux/if_ether.h
+1
include/uapi/linux/if_ether.h
···
92
92
#define ETH_P_ETHERCAT 0x88A4 /* EtherCAT */
93
93
#define ETH_P_8021AD 0x88A8 /* 802.1ad Service VLAN */
94
94
#define ETH_P_802_EX1 0x88B5 /* 802.1 Local Experimental 1. */
95
+
#define ETH_P_MXLGSW 0x88C3 /* MaxLinear GSW DSA [ NOT AN OFFICIALLY REGISTERED ID ] */
95
96
#define ETH_P_PREAUTH 0x88C7 /* 802.11 Preauthentication */
96
97
#define ETH_P_TIPC 0x88CA /* TIPC */
97
98
#define ETH_P_LLDP 0x88CC /* Link Layer Discovery Protocol */
+8
net/dsa/Kconfig
+8
net/dsa/Kconfig
···
104
104
Say Y or M if you want to enable support for tagging frames for
105
105
Mediatek switches.
106
106
107
+
config NET_DSA_TAG_MXL_GSW1XX
108
+
tristate "Tag driver for MaxLinear GSW1xx switches"
109
+
help
110
+
The GSW1xx family of switches supports an 8-byte special tag which
111
+
can be used on the CPU port of the switch.
112
+
Say Y or M if you want to enable support for tagging frames for
113
+
MaxLinear GSW1xx switches.
114
+
107
115
config NET_DSA_TAG_KSZ
108
116
tristate "Tag driver for Microchip 8795/937x/9477/9893 families of switches"
109
117
help
+1
net/dsa/Makefile
+1
net/dsa/Makefile
···
28
28
obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
29
29
obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o
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30
obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
31
+
obj-$(CONFIG_NET_DSA_TAG_MXL_GSW1XX) += tag_mxl-gsw1xx.o
31
32
obj-$(CONFIG_NET_DSA_TAG_NONE) += tag_none.o
32
33
obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o
33
34
obj-$(CONFIG_NET_DSA_TAG_OCELOT_8021Q) += tag_ocelot_8021q.o
+116
net/dsa/tag_mxl-gsw1xx.c
+116
net/dsa/tag_mxl-gsw1xx.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* DSA driver Special Tag support for MaxLinear GSW1xx switch chips
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+
*
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+
* Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
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+
* Copyright (C) 2023 - 2024 MaxLinear Inc.
7
+
*/
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+
9
+
#include <linux/bitops.h>
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+
#include <linux/etherdevice.h>
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+
#include <linux/skbuff.h>
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+
#include <net/dsa.h>
13
+
14
+
#include "tag.h"
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+
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+
/* To define the outgoing port and to discover the incoming port a special
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+
* tag is used by the GSW1xx.
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+
*
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* Dest MAC Src MAC special TAG EtherType
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+
* ...| 1 2 3 4 5 6 | 1 2 3 4 5 6 | 1 2 3 4 5 6 7 8 | 1 2 |...
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+
* |<--------------->|
22
+
*/
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+
24
+
#define GSW1XX_TAG_NAME "gsw1xx"
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+
26
+
/* special tag header length (RX and TX) */
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+
#define GSW1XX_HEADER_LEN 8
28
+
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+
/* Word 0 = Ethertype -> 0x88C3 */
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+
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+
/* Word 1 */
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+
#define GSW1XX_TX_PORT_MAP GENMASK(7, 0)
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+
#define GSW1XX_TX_PORT_MAP_EN BIT(15)
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+
#define GSW1XX_TX_CLASS_EN BIT(14)
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+
#define GSW1XX_TX_TIME_STAMP_EN BIT(13)
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+
#define GSW1XX_TX_LRN_DIS BIT(12)
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+
#define GSW1XX_TX_CLASS GENMASK(11, 8)
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+
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+
/* special tag in RX path header */
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+
/* Word 2 */
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+
#define GSW1XX_RX_PORT_MAP GENMASK(15, 8)
42
+
43
+
static struct sk_buff *gsw1xx_tag_xmit(struct sk_buff *skb,
44
+
struct net_device *dev)
45
+
{
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+
struct dsa_port *dp = dsa_user_to_port(dev);
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+
__be16 *gsw1xx_tag;
48
+
49
+
/* provide additional space 'GSW1XX_HEADER_LEN' bytes */
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+
skb_push(skb, GSW1XX_HEADER_LEN);
51
+
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+
/* add space between MAC address and Ethertype */
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+
dsa_alloc_etype_header(skb, GSW1XX_HEADER_LEN);
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+
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+
/* special tag ingress */
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+
gsw1xx_tag = dsa_etype_header_pos_tx(skb);
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+
gsw1xx_tag[0] = htons(ETH_P_MXLGSW);
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+
gsw1xx_tag[1] = htons(GSW1XX_TX_PORT_MAP_EN | GSW1XX_TX_LRN_DIS |
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+
FIELD_PREP(GSW1XX_TX_PORT_MAP, BIT(dp->index)));
60
+
61
+
gsw1xx_tag[2] = 0;
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+
gsw1xx_tag[3] = 0;
63
+
64
+
return skb;
65
+
}
66
+
67
+
static struct sk_buff *gsw1xx_tag_rcv(struct sk_buff *skb,
68
+
struct net_device *dev)
69
+
{
70
+
int port;
71
+
__be16 *gsw1xx_tag;
72
+
73
+
if (unlikely(!pskb_may_pull(skb, GSW1XX_HEADER_LEN))) {
74
+
dev_warn_ratelimited(&dev->dev, "Dropping packet, cannot pull SKB\n");
75
+
return NULL;
76
+
}
77
+
78
+
gsw1xx_tag = dsa_etype_header_pos_rx(skb);
79
+
80
+
if (unlikely(ntohs(gsw1xx_tag[0]) != ETH_P_MXLGSW)) {
81
+
dev_warn_ratelimited(&dev->dev, "Dropping packet due to invalid special tag\n");
82
+
dev_warn_ratelimited(&dev->dev, "Tag: %8ph\n", gsw1xx_tag);
83
+
return NULL;
84
+
}
85
+
86
+
/* Get source port information */
87
+
port = FIELD_GET(GSW1XX_RX_PORT_MAP, ntohs(gsw1xx_tag[1]));
88
+
skb->dev = dsa_conduit_find_user(dev, 0, port);
89
+
if (!skb->dev) {
90
+
dev_warn_ratelimited(&dev->dev, "Dropping packet due to invalid source port\n");
91
+
dev_warn_ratelimited(&dev->dev, "Tag: %8ph\n", gsw1xx_tag);
92
+
return NULL;
93
+
}
94
+
95
+
/* remove the GSW1xx special tag between MAC addresses and the current
96
+
* ethertype field.
97
+
*/
98
+
skb_pull_rcsum(skb, GSW1XX_HEADER_LEN);
99
+
dsa_strip_etype_header(skb, GSW1XX_HEADER_LEN);
100
+
101
+
return skb;
102
+
}
103
+
104
+
static const struct dsa_device_ops gsw1xx_netdev_ops = {
105
+
.name = GSW1XX_TAG_NAME,
106
+
.proto = DSA_TAG_PROTO_MXL_GSW1XX,
107
+
.xmit = gsw1xx_tag_xmit,
108
+
.rcv = gsw1xx_tag_rcv,
109
+
.needed_headroom = GSW1XX_HEADER_LEN,
110
+
};
111
+
112
+
MODULE_DESCRIPTION("DSA tag driver for MaxLinear GSW1xx 8 byte protocol");
113
+
MODULE_LICENSE("GPL");
114
+
MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MXL_GSW1XX, GSW1XX_TAG_NAME);
115
+
116
+
module_dsa_tag_driver(gsw1xx_netdev_ops);