Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'rdma-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband
Pull infiniband/rdma updates from Roland Dreier:
- mostly cxgb4 fixes unblocked by the merge of some prerequisites via
the net tree
- drop deprecated MSI-X API use.
- a couple other miscellaneous things.
* tag 'rdma-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband:
RDMA/cxgb4: Fix over-dereference when terminating
RDMA/cxgb4: Use uninitialized_var()
RDMA/cxgb4: Add missing debug stats
RDMA/cxgb4: Initialize reserved fields in a FW work request
RDMA/cxgb4: Use pr_warn_ratelimited
RDMA/cxgb4: Max fastreg depth depends on DSGL support
RDMA/cxgb4: SQ flush fix
RDMA/cxgb4: rmb() after reading valid gen bit
RDMA/cxgb4: Endpoint timeout fixes
RDMA/cxgb4: Use the BAR2/WC path for kernel QPs and T5 devices
IB/mlx5: Add block multicast loopback support
IB/mthca: Use pci_enable_msix_exact() instead of pci_enable_msix()
IB/qib: Use pci_enable_msix_range() instead of pci_enable_msix()
+269
-124
+55
-32
drivers/infiniband/hw/cxgb4/cm.c
+55
-32
drivers/infiniband/hw/cxgb4/cm.c
···
173
173
add_timer(&ep->timer);
174
174
}
175
175
176
-
static void stop_ep_timer(struct c4iw_ep *ep)
176
+
static int stop_ep_timer(struct c4iw_ep *ep)
177
177
{
178
178
PDBG("%s ep %p stopping\n", __func__, ep);
179
179
del_timer_sync(&ep->timer);
180
-
if (!test_and_set_bit(TIMEOUT, &ep->com.flags))
180
+
if (!test_and_set_bit(TIMEOUT, &ep->com.flags)) {
181
181
c4iw_put_ep(&ep->com);
182
+
return 0;
183
+
}
184
+
return 1;
182
185
}
183
186
184
187
static int c4iw_l2t_send(struct c4iw_rdev *rdev, struct sk_buff *skb,
···
1168
1165
PDBG("%s ep %p tid %u\n", __func__, ep, ep->hwtid);
1169
1166
1170
1167
/*
1171
-
* Stop mpa timer. If it expired, then the state has
1172
-
* changed and we bail since ep_timeout already aborted
1173
-
* the connection.
1168
+
* Stop mpa timer. If it expired, then
1169
+
* we ignore the MPA reply. process_timeout()
1170
+
* will abort the connection.
1174
1171
*/
1175
-
stop_ep_timer(ep);
1176
-
if (ep->com.state != MPA_REQ_SENT)
1172
+
if (stop_ep_timer(ep))
1177
1173
return;
1178
1174
1179
1175
/*
···
1377
1375
1378
1376
PDBG("%s ep %p tid %u\n", __func__, ep, ep->hwtid);
1379
1377
1380
-
if (ep->com.state != MPA_REQ_WAIT)
1381
-
return;
1382
-
1383
1378
/*
1384
1379
* If we get more than the supported amount of private data
1385
1380
* then we must fail this connection.
1386
1381
*/
1387
1382
if (ep->mpa_pkt_len + skb->len > sizeof(ep->mpa_pkt)) {
1388
-
stop_ep_timer(ep);
1383
+
(void)stop_ep_timer(ep);
1389
1384
abort_connection(ep, skb, GFP_KERNEL);
1390
1385
return;
1391
1386
}
···
1412
1413
if (mpa->revision > mpa_rev) {
1413
1414
printk(KERN_ERR MOD "%s MPA version mismatch. Local = %d,"
1414
1415
" Received = %d\n", __func__, mpa_rev, mpa->revision);
1415
-
stop_ep_timer(ep);
1416
+
(void)stop_ep_timer(ep);
1416
1417
abort_connection(ep, skb, GFP_KERNEL);
1417
1418
return;
1418
1419
}
1419
1420
1420
1421
if (memcmp(mpa->key, MPA_KEY_REQ, sizeof(mpa->key))) {
1421
-
stop_ep_timer(ep);
1422
+
(void)stop_ep_timer(ep);
1422
1423
abort_connection(ep, skb, GFP_KERNEL);
1423
1424
return;
1424
1425
}
···
1429
1430
* Fail if there's too much private data.
1430
1431
*/
1431
1432
if (plen > MPA_MAX_PRIVATE_DATA) {
1432
-
stop_ep_timer(ep);
1433
+
(void)stop_ep_timer(ep);
1433
1434
abort_connection(ep, skb, GFP_KERNEL);
1434
1435
return;
1435
1436
}
···
1438
1439
* If plen does not account for pkt size
1439
1440
*/
1440
1441
if (ep->mpa_pkt_len > (sizeof(*mpa) + plen)) {
1441
-
stop_ep_timer(ep);
1442
+
(void)stop_ep_timer(ep);
1442
1443
abort_connection(ep, skb, GFP_KERNEL);
1443
1444
return;
1444
1445
}
···
1495
1496
ep->mpa_attr.xmit_marker_enabled, ep->mpa_attr.version,
1496
1497
ep->mpa_attr.p2p_type);
1497
1498
1498
-
__state_set(&ep->com, MPA_REQ_RCVD);
1499
-
stop_ep_timer(ep);
1499
+
/*
1500
+
* If the endpoint timer already expired, then we ignore
1501
+
* the start request. process_timeout() will abort
1502
+
* the connection.
1503
+
*/
1504
+
if (!stop_ep_timer(ep)) {
1505
+
__state_set(&ep->com, MPA_REQ_RCVD);
1500
1506
1501
-
/* drive upcall */
1502
-
mutex_lock(&ep->parent_ep->com.mutex);
1503
-
if (ep->parent_ep->com.state != DEAD) {
1504
-
if (connect_request_upcall(ep))
1507
+
/* drive upcall */
1508
+
mutex_lock(&ep->parent_ep->com.mutex);
1509
+
if (ep->parent_ep->com.state != DEAD) {
1510
+
if (connect_request_upcall(ep))
1511
+
abort_connection(ep, skb, GFP_KERNEL);
1512
+
} else {
1505
1513
abort_connection(ep, skb, GFP_KERNEL);
1506
-
} else {
1507
-
abort_connection(ep, skb, GFP_KERNEL);
1514
+
}
1515
+
mutex_unlock(&ep->parent_ep->com.mutex);
1508
1516
}
1509
-
mutex_unlock(&ep->parent_ep->com.mutex);
1510
1517
return;
1511
1518
}
1512
1519
···
2270
2265
disconnect = 0;
2271
2266
break;
2272
2267
case MORIBUND:
2273
-
stop_ep_timer(ep);
2268
+
(void)stop_ep_timer(ep);
2274
2269
if (ep->com.cm_id && ep->com.qp) {
2275
2270
attrs.next_state = C4IW_QP_STATE_IDLE;
2276
2271
c4iw_modify_qp(ep->com.qp->rhp, ep->com.qp,
···
2330
2325
case CONNECTING:
2331
2326
break;
2332
2327
case MPA_REQ_WAIT:
2333
-
stop_ep_timer(ep);
2328
+
(void)stop_ep_timer(ep);
2334
2329
break;
2335
2330
case MPA_REQ_SENT:
2336
-
stop_ep_timer(ep);
2331
+
(void)stop_ep_timer(ep);
2337
2332
if (mpa_rev == 1 || (mpa_rev == 2 && ep->tried_with_mpa_v1))
2338
2333
connect_reply_upcall(ep, -ECONNRESET);
2339
2334
else {
···
2438
2433
__state_set(&ep->com, MORIBUND);
2439
2434
break;
2440
2435
case MORIBUND:
2441
-
stop_ep_timer(ep);
2436
+
(void)stop_ep_timer(ep);
2442
2437
if ((ep->com.cm_id) && (ep->com.qp)) {
2443
2438
attrs.next_state = C4IW_QP_STATE_IDLE;
2444
2439
c4iw_modify_qp(ep->com.qp->rhp,
···
3033
3028
if (!test_and_set_bit(CLOSE_SENT, &ep->com.flags)) {
3034
3029
close = 1;
3035
3030
if (abrupt) {
3036
-
stop_ep_timer(ep);
3031
+
(void)stop_ep_timer(ep);
3037
3032
ep->com.state = ABORTING;
3038
3033
} else
3039
3034
ep->com.state = MORIBUND;
···
3467
3462
__state_set(&ep->com, ABORTING);
3468
3463
close_complete_upcall(ep, -ETIMEDOUT);
3469
3464
break;
3465
+
case ABORTING:
3466
+
case DEAD:
3467
+
3468
+
/*
3469
+
* These states are expected if the ep timed out at the same
3470
+
* time as another thread was calling stop_ep_timer().
3471
+
* So we silently do nothing for these states.
3472
+
*/
3473
+
abort = 0;
3474
+
break;
3470
3475
default:
3471
3476
WARN(1, "%s unexpected state ep %p tid %u state %u\n",
3472
3477
__func__, ep, ep->hwtid, ep->com.state);
···
3498
3483
3499
3484
tmp = timeout_list.next;
3500
3485
list_del(tmp);
3486
+
tmp->next = NULL;
3487
+
tmp->prev = NULL;
3501
3488
spin_unlock_irq(&timeout_lock);
3502
3489
ep = list_entry(tmp, struct c4iw_ep, entry);
3503
3490
process_timeout(ep);
···
3516
3499
unsigned int opcode;
3517
3500
int ret;
3518
3501
3502
+
process_timedout_eps();
3519
3503
while ((skb = skb_dequeue(&rxq))) {
3520
3504
rpl = cplhdr(skb);
3521
3505
dev = *((struct c4iw_dev **) (skb->cb + sizeof(void *)));
···
3526
3508
ret = work_handlers[opcode](dev, skb);
3527
3509
if (!ret)
3528
3510
kfree_skb(skb);
3511
+
process_timedout_eps();
3529
3512
}
3530
-
process_timedout_eps();
3531
3513
}
3532
3514
3533
3515
static DECLARE_WORK(skb_work, process_work);
···
3539
3521
3540
3522
spin_lock(&timeout_lock);
3541
3523
if (!test_and_set_bit(TIMEOUT, &ep->com.flags)) {
3542
-
list_add_tail(&ep->entry, &timeout_list);
3543
-
kickit = 1;
3524
+
/*
3525
+
* Only insert if it is not already on the list.
3526
+
*/
3527
+
if (!ep->entry.next) {
3528
+
list_add_tail(&ep->entry, &timeout_list);
3529
+
kickit = 1;
3530
+
}
3544
3531
}
3545
3532
spin_unlock(&timeout_lock);
3546
3533
if (kickit)
+9
-15
drivers/infiniband/hw/cxgb4/cq.c
+9
-15
drivers/infiniband/hw/cxgb4/cq.c
···
235
235
struct t4_cq *cq = &chp->cq;
236
236
int idx;
237
237
struct t4_swsqe *swsqe;
238
-
int error = (qhp->attr.state != C4IW_QP_STATE_CLOSING &&
239
-
qhp->attr.state != C4IW_QP_STATE_IDLE);
240
238
241
239
if (wq->sq.flush_cidx == -1)
242
240
wq->sq.flush_cidx = wq->sq.cidx;
243
241
idx = wq->sq.flush_cidx;
244
242
BUG_ON(idx >= wq->sq.size);
245
243
while (idx != wq->sq.pidx) {
246
-
if (error) {
247
-
swsqe = &wq->sq.sw_sq[idx];
248
-
BUG_ON(swsqe->flushed);
249
-
swsqe->flushed = 1;
250
-
insert_sq_cqe(wq, cq, swsqe);
251
-
if (wq->sq.oldest_read == swsqe) {
252
-
BUG_ON(swsqe->opcode != FW_RI_READ_REQ);
253
-
advance_oldest_read(wq);
254
-
}
255
-
flushed++;
256
-
} else {
257
-
t4_sq_consume(wq);
244
+
swsqe = &wq->sq.sw_sq[idx];
245
+
BUG_ON(swsqe->flushed);
246
+
swsqe->flushed = 1;
247
+
insert_sq_cqe(wq, cq, swsqe);
248
+
if (wq->sq.oldest_read == swsqe) {
249
+
BUG_ON(swsqe->opcode != FW_RI_READ_REQ);
250
+
advance_oldest_read(wq);
258
251
}
252
+
flushed++;
259
253
if (++idx == wq->sq.size)
260
254
idx = 0;
261
255
}
···
672
678
static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc)
673
679
{
674
680
struct c4iw_qp *qhp = NULL;
675
-
struct t4_cqe cqe = {0, 0}, *rd_cqe;
681
+
struct t4_cqe uninitialized_var(cqe), *rd_cqe;
676
682
struct t4_wq *wq;
677
683
u32 credit = 0;
678
684
u8 cqe_flushed;
+33
-8
drivers/infiniband/hw/cxgb4/device.c
+33
-8
drivers/infiniband/hw/cxgb4/device.c
···
682
682
idr_destroy(&ctx->dev->hwtid_idr);
683
683
idr_destroy(&ctx->dev->stid_idr);
684
684
idr_destroy(&ctx->dev->atid_idr);
685
-
iounmap(ctx->dev->rdev.oc_mw_kva);
685
+
if (ctx->dev->rdev.bar2_kva)
686
+
iounmap(ctx->dev->rdev.bar2_kva);
687
+
if (ctx->dev->rdev.oc_mw_kva)
688
+
iounmap(ctx->dev->rdev.oc_mw_kva);
686
689
ib_dealloc_device(&ctx->dev->ibdev);
687
690
ctx->dev = NULL;
688
691
}
···
725
722
}
726
723
devp->rdev.lldi = *infop;
727
724
728
-
devp->rdev.oc_mw_pa = pci_resource_start(devp->rdev.lldi.pdev, 2) +
729
-
(pci_resource_len(devp->rdev.lldi.pdev, 2) -
730
-
roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size));
731
-
devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
732
-
devp->rdev.lldi.vr->ocq.size);
725
+
/*
726
+
* For T5 devices, we map all of BAR2 with WC.
727
+
* For T4 devices with onchip qp mem, we map only that part
728
+
* of BAR2 with WC.
729
+
*/
730
+
devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
731
+
if (is_t5(devp->rdev.lldi.adapter_type)) {
732
+
devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
733
+
pci_resource_len(devp->rdev.lldi.pdev, 2));
734
+
if (!devp->rdev.bar2_kva) {
735
+
pr_err(MOD "Unable to ioremap BAR2\n");
736
+
return ERR_PTR(-EINVAL);
737
+
}
738
+
} else if (ocqp_supported(infop)) {
739
+
devp->rdev.oc_mw_pa =
740
+
pci_resource_start(devp->rdev.lldi.pdev, 2) +
741
+
pci_resource_len(devp->rdev.lldi.pdev, 2) -
742
+
roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
743
+
devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
744
+
devp->rdev.lldi.vr->ocq.size);
745
+
if (!devp->rdev.oc_mw_kva) {
746
+
pr_err(MOD "Unable to ioremap onchip mem\n");
747
+
return ERR_PTR(-EINVAL);
748
+
}
749
+
}
733
750
734
751
PDBG(KERN_INFO MOD "ocq memory: "
735
752
"hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
···
1026
1003
static void resume_rc_qp(struct c4iw_qp *qp)
1027
1004
{
1028
1005
spin_lock(&qp->lock);
1029
-
t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc);
1006
+
t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc,
1007
+
is_t5(qp->rhp->rdev.lldi.adapter_type), NULL);
1030
1008
qp->wq.sq.wq_pidx_inc = 0;
1031
-
t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc);
1009
+
t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc,
1010
+
is_t5(qp->rhp->rdev.lldi.adapter_type), NULL);
1032
1011
qp->wq.rq.wq_pidx_inc = 0;
1033
1012
spin_unlock(&qp->lock);
1034
1013
}
+2
drivers/infiniband/hw/cxgb4/iw_cxgb4.h
+2
drivers/infiniband/hw/cxgb4/iw_cxgb4.h
+5
-1
drivers/infiniband/hw/cxgb4/mem.c
+5
-1
drivers/infiniband/hw/cxgb4/mem.c
···
259
259
260
260
if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
261
261
stag_idx = c4iw_get_resource(&rdev->resource.tpt_table);
262
-
if (!stag_idx)
262
+
if (!stag_idx) {
263
+
mutex_lock(&rdev->stats.lock);
264
+
rdev->stats.stag.fail++;
265
+
mutex_unlock(&rdev->stats.lock);
263
266
return -ENOMEM;
267
+
}
264
268
mutex_lock(&rdev->stats.lock);
265
269
rdev->stats.stag.cur += 32;
266
270
if (rdev->stats.stag.cur > rdev->stats.stag.max)
+1
-1
drivers/infiniband/hw/cxgb4/provider.c
+1
-1
drivers/infiniband/hw/cxgb4/provider.c
+44
-26
drivers/infiniband/hw/cxgb4/qp.c
+44
-26
drivers/infiniband/hw/cxgb4/qp.c
···
212
212
213
213
wq->db = rdev->lldi.db_reg;
214
214
wq->gts = rdev->lldi.gts_reg;
215
-
if (user) {
216
-
wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
217
-
(wq->sq.qid << rdev->qpshift);
218
-
wq->sq.udb &= PAGE_MASK;
219
-
wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
220
-
(wq->rq.qid << rdev->qpshift);
221
-
wq->rq.udb &= PAGE_MASK;
215
+
if (user || is_t5(rdev->lldi.adapter_type)) {
216
+
u32 off;
217
+
218
+
off = (wq->sq.qid << rdev->qpshift) & PAGE_MASK;
219
+
if (user) {
220
+
wq->sq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
221
+
} else {
222
+
off += 128 * (wq->sq.qid & rdev->qpmask) + 8;
223
+
wq->sq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
224
+
}
225
+
off = (wq->rq.qid << rdev->qpshift) & PAGE_MASK;
226
+
if (user) {
227
+
wq->rq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
228
+
} else {
229
+
off += 128 * (wq->rq.qid & rdev->qpmask) + 8;
230
+
wq->rq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
231
+
}
222
232
}
223
233
wq->rdev = rdev;
224
234
wq->rq.msn = 1;
···
309
299
if (ret)
310
300
goto free_dma;
311
301
312
-
PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
302
+
PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%lx rqudb 0x%lx\n",
313
303
__func__, wq->sq.qid, wq->rq.qid, wq->db,
314
-
(unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
304
+
(__force unsigned long) wq->sq.udb,
305
+
(__force unsigned long) wq->rq.udb);
315
306
316
307
return 0;
317
308
free_dma:
···
436
425
default:
437
426
return -EINVAL;
438
427
}
428
+
wqe->send.r3 = 0;
429
+
wqe->send.r4 = 0;
439
430
440
431
plen = 0;
441
432
if (wr->num_sge) {
···
568
555
int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
569
556
int rem;
570
557
571
-
if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
558
+
if (wr->wr.fast_reg.page_list_len >
559
+
t4_max_fr_depth(use_dsgl))
572
560
return -EINVAL;
573
561
574
562
wqe->fr.qpbinde_to_dcacpu = 0;
···
664
650
665
651
spin_lock_irqsave(&qhp->rhp->lock, flags);
666
652
spin_lock(&qhp->lock);
667
-
if (qhp->rhp->db_state == NORMAL) {
668
-
t4_ring_sq_db(&qhp->wq, inc);
669
-
} else {
653
+
if (qhp->rhp->db_state == NORMAL)
654
+
t4_ring_sq_db(&qhp->wq, inc,
655
+
is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
656
+
else {
670
657
add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
671
658
qhp->wq.sq.wq_pidx_inc += inc;
672
659
}
···
682
667
683
668
spin_lock_irqsave(&qhp->rhp->lock, flags);
684
669
spin_lock(&qhp->lock);
685
-
if (qhp->rhp->db_state == NORMAL) {
686
-
t4_ring_rq_db(&qhp->wq, inc);
687
-
} else {
670
+
if (qhp->rhp->db_state == NORMAL)
671
+
t4_ring_rq_db(&qhp->wq, inc,
672
+
is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
673
+
else {
688
674
add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
689
675
qhp->wq.rq.wq_pidx_inc += inc;
690
676
}
···
702
686
enum fw_wr_opcodes fw_opcode = 0;
703
687
enum fw_ri_wr_flags fw_flags;
704
688
struct c4iw_qp *qhp;
705
-
union t4_wr *wqe;
689
+
union t4_wr *wqe = NULL;
706
690
u32 num_wrs;
707
691
struct t4_swsqe *swsqe;
708
692
unsigned long flag;
···
808
792
idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
809
793
}
810
794
if (!qhp->rhp->rdev.status_page->db_off) {
811
-
t4_ring_sq_db(&qhp->wq, idx);
795
+
t4_ring_sq_db(&qhp->wq, idx,
796
+
is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
812
797
spin_unlock_irqrestore(&qhp->lock, flag);
813
798
} else {
814
799
spin_unlock_irqrestore(&qhp->lock, flag);
···
823
806
{
824
807
int err = 0;
825
808
struct c4iw_qp *qhp;
826
-
union t4_recv_wr *wqe;
809
+
union t4_recv_wr *wqe = NULL;
827
810
u32 num_wrs;
828
811
u8 len16 = 0;
829
812
unsigned long flag;
···
875
858
num_wrs--;
876
859
}
877
860
if (!qhp->rhp->rdev.status_page->db_off) {
878
-
t4_ring_rq_db(&qhp->wq, idx);
861
+
t4_ring_rq_db(&qhp->wq, idx,
862
+
is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
879
863
spin_unlock_irqrestore(&qhp->lock, flag);
880
864
} else {
881
865
spin_unlock_irqrestore(&qhp->lock, flag);
···
1370
1352
switch (attrs->next_state) {
1371
1353
case C4IW_QP_STATE_CLOSING:
1372
1354
BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1355
+
t4_set_wq_in_error(&qhp->wq);
1373
1356
set_state(qhp, C4IW_QP_STATE_CLOSING);
1374
1357
ep = qhp->ep;
1375
1358
if (!internal) {
···
1378
1359
disconnect = 1;
1379
1360
c4iw_get_ep(&qhp->ep->com);
1380
1361
}
1381
-
t4_set_wq_in_error(&qhp->wq);
1382
1362
ret = rdma_fini(rhp, qhp, ep);
1383
1363
if (ret)
1384
1364
goto err;
1385
1365
break;
1386
1366
case C4IW_QP_STATE_TERMINATE:
1367
+
t4_set_wq_in_error(&qhp->wq);
1387
1368
set_state(qhp, C4IW_QP_STATE_TERMINATE);
1388
1369
qhp->attr.layer_etype = attrs->layer_etype;
1389
1370
qhp->attr.ecode = attrs->ecode;
1390
-
t4_set_wq_in_error(&qhp->wq);
1391
1371
ep = qhp->ep;
1392
1372
disconnect = 1;
1373
+
c4iw_get_ep(&qhp->ep->com);
1393
1374
if (!internal)
1394
1375
terminate = 1;
1395
1376
else {
···
1397
1378
if (ret)
1398
1379
goto err;
1399
1380
}
1400
-
c4iw_get_ep(&qhp->ep->com);
1401
1381
break;
1402
1382
case C4IW_QP_STATE_ERROR:
1403
-
set_state(qhp, C4IW_QP_STATE_ERROR);
1404
1383
t4_set_wq_in_error(&qhp->wq);
1384
+
set_state(qhp, C4IW_QP_STATE_ERROR);
1405
1385
if (!internal) {
1406
1386
abort = 1;
1407
1387
disconnect = 1;
···
1695
1677
mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1696
1678
insert_mmap(ucontext, mm2);
1697
1679
mm3->key = uresp.sq_db_gts_key;
1698
-
mm3->addr = qhp->wq.sq.udb;
1680
+
mm3->addr = (__force unsigned long) qhp->wq.sq.udb;
1699
1681
mm3->len = PAGE_SIZE;
1700
1682
insert_mmap(ucontext, mm3);
1701
1683
mm4->key = uresp.rq_db_gts_key;
1702
-
mm4->addr = qhp->wq.rq.udb;
1684
+
mm4->addr = (__force unsigned long) qhp->wq.rq.udb;
1703
1685
mm4->len = PAGE_SIZE;
1704
1686
insert_mmap(ucontext, mm4);
1705
1687
if (mm5) {
+7
-3
drivers/infiniband/hw/cxgb4/resource.c
+7
-3
drivers/infiniband/hw/cxgb4/resource.c
···
179
179
kfree(entry);
180
180
} else {
181
181
qid = c4iw_get_resource(&rdev->resource.qid_table);
182
-
if (!qid)
182
+
if (!qid) {
183
+
mutex_lock(&rdev->stats.lock);
184
+
rdev->stats.qid.fail++;
185
+
mutex_unlock(&rdev->stats.lock);
183
186
goto out;
187
+
}
184
188
mutex_lock(&rdev->stats.lock);
185
189
rdev->stats.qid.cur += rdev->qpmask + 1;
186
190
mutex_unlock(&rdev->stats.lock);
···
326
322
unsigned long addr = gen_pool_alloc(rdev->rqt_pool, size << 6);
327
323
PDBG("%s addr 0x%x size %d\n", __func__, (u32)addr, size << 6);
328
324
if (!addr)
329
-
printk_ratelimited(KERN_WARNING MOD "%s: Out of RQT memory\n",
330
-
pci_name(rdev->lldi.pdev));
325
+
pr_warn_ratelimited(MOD "%s: Out of RQT memory\n",
326
+
pci_name(rdev->lldi.pdev));
331
327
mutex_lock(&rdev->stats.lock);
332
328
if (addr) {
333
329
rdev->stats.rqt.cur += roundup(size << 6, 1 << MIN_RQT_SHIFT);
+67
-5
drivers/infiniband/hw/cxgb4/t4.h
+67
-5
drivers/infiniband/hw/cxgb4/t4.h
···
84
84
sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
85
85
#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
86
86
sizeof(struct fw_ri_immd)) & ~31UL)
87
-
#define T4_MAX_FR_DEPTH (1024 / sizeof(u64))
87
+
#define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
88
+
#define T4_MAX_FR_DSGL 1024
89
+
#define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
90
+
91
+
static inline int t4_max_fr_depth(int use_dsgl)
92
+
{
93
+
return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
94
+
}
88
95
89
96
#define T4_RQ_NUM_SLOTS 2
90
97
#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
···
299
292
unsigned long phys_addr;
300
293
struct t4_swsqe *sw_sq;
301
294
struct t4_swsqe *oldest_read;
302
-
u64 udb;
295
+
u64 __iomem *udb;
303
296
size_t memsize;
304
297
u32 qid;
305
298
u16 in_use;
···
321
314
dma_addr_t dma_addr;
322
315
DEFINE_DMA_UNMAP_ADDR(mapping);
323
316
struct t4_swrqe *sw_rq;
324
-
u64 udb;
317
+
u64 __iomem *udb;
325
318
size_t memsize;
326
319
u32 qid;
327
320
u32 msn;
···
442
435
return wq->sq.size * T4_SQ_NUM_SLOTS;
443
436
}
444
437
445
-
static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc)
438
+
/* This function copies 64 byte coalesced work request to memory
439
+
* mapped BAR2 space. For coalesced WRs, the SGE fetches data
440
+
* from the FIFO instead of from Host.
441
+
*/
442
+
static inline void pio_copy(u64 __iomem *dst, u64 *src)
446
443
{
444
+
int count = 8;
445
+
446
+
while (count) {
447
+
writeq(*src, dst);
448
+
src++;
449
+
dst++;
450
+
count--;
451
+
}
452
+
}
453
+
454
+
static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
455
+
union t4_wr *wqe)
456
+
{
457
+
458
+
/* Flush host queue memory writes. */
447
459
wmb();
460
+
if (t5) {
461
+
if (inc == 1 && wqe) {
462
+
PDBG("%s: WC wq->sq.pidx = %d\n",
463
+
__func__, wq->sq.pidx);
464
+
pio_copy(wq->sq.udb + 7, (void *)wqe);
465
+
} else {
466
+
PDBG("%s: DB wq->sq.pidx = %d\n",
467
+
__func__, wq->sq.pidx);
468
+
writel(PIDX_T5(inc), wq->sq.udb);
469
+
}
470
+
471
+
/* Flush user doorbell area writes. */
472
+
wmb();
473
+
return;
474
+
}
448
475
writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
449
476
}
450
477
451
-
static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc)
478
+
static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
479
+
union t4_recv_wr *wqe)
452
480
{
481
+
482
+
/* Flush host queue memory writes. */
453
483
wmb();
484
+
if (t5) {
485
+
if (inc == 1 && wqe) {
486
+
PDBG("%s: WC wq->rq.pidx = %d\n",
487
+
__func__, wq->rq.pidx);
488
+
pio_copy(wq->rq.udb + 7, (void *)wqe);
489
+
} else {
490
+
PDBG("%s: DB wq->rq.pidx = %d\n",
491
+
__func__, wq->rq.pidx);
492
+
writel(PIDX_T5(inc), wq->rq.udb);
493
+
}
494
+
495
+
/* Flush user doorbell area writes. */
496
+
wmb();
497
+
return;
498
+
}
454
499
writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
455
500
}
456
501
···
627
568
printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
628
569
BUG_ON(1);
629
570
} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
571
+
572
+
/* Ensure CQE is flushed to memory */
573
+
rmb();
630
574
*cqe = &cq->queue[cq->cidx];
631
575
ret = 0;
632
576
} else
+2
drivers/infiniband/hw/mlx5/main.c
+2
drivers/infiniband/hw/mlx5/main.c
···
282
282
props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
283
283
IB_GUARD_T10DIF_CSUM;
284
284
}
285
+
if (flags & MLX5_DEV_CAP_FLAG_BLOCK_MCAST)
286
+
props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
285
287
286
288
props->vendor_id = be32_to_cpup((__be32 *)(out_mad->data + 36)) &
287
289
0xffffff;
+12
drivers/infiniband/hw/mlx5/qp.c
+12
drivers/infiniband/hw/mlx5/qp.c
···
807
807
spin_lock_init(&qp->sq.lock);
808
808
spin_lock_init(&qp->rq.lock);
809
809
810
+
if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
811
+
if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_BLOCK_MCAST)) {
812
+
mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
813
+
return -EINVAL;
814
+
} else {
815
+
qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
816
+
}
817
+
}
818
+
810
819
if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
811
820
qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
812
821
···
886
877
887
878
if (qp->wq_sig)
888
879
in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
880
+
881
+
if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
882
+
in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
889
883
890
884
if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
891
885
int rcqe_sz;
+2
-6
drivers/infiniband/hw/mthca/mthca_main.c
+2
-6
drivers/infiniband/hw/mthca/mthca_main.c
···
858
858
entries[1].entry = 1;
859
859
entries[2].entry = 2;
860
860
861
-
err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
862
-
if (err) {
863
-
if (err > 0)
864
-
mthca_info(mdev, "Only %d MSI-X vectors available, "
865
-
"not using MSI-X\n", err);
861
+
err = pci_enable_msix_exact(mdev->pdev, entries, ARRAY_SIZE(entries));
862
+
if (err)
866
863
return err;
867
-
}
868
864
869
865
mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
870
866
mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
+28
-27
drivers/infiniband/hw/qib/qib_pcie.c
+28
-27
drivers/infiniband/hw/qib/qib_pcie.c
···
197
197
struct qib_msix_entry *qib_msix_entry)
198
198
{
199
199
int ret;
200
-
u32 tabsize = 0;
201
-
u16 msix_flags;
200
+
int nvec = *msixcnt;
202
201
struct msix_entry *msix_entry;
203
202
int i;
203
+
204
+
ret = pci_msix_vec_count(dd->pcidev);
205
+
if (ret < 0)
206
+
goto do_intx;
207
+
208
+
nvec = min(nvec, ret);
204
209
205
210
/* We can't pass qib_msix_entry array to qib_msix_setup
206
211
* so use a dummy msix_entry array and copy the allocated
207
212
* irq back to the qib_msix_entry array. */
208
-
msix_entry = kmalloc(*msixcnt * sizeof(*msix_entry), GFP_KERNEL);
209
-
if (!msix_entry) {
210
-
ret = -ENOMEM;
213
+
msix_entry = kmalloc(nvec * sizeof(*msix_entry), GFP_KERNEL);
214
+
if (!msix_entry)
211
215
goto do_intx;
212
-
}
213
-
for (i = 0; i < *msixcnt; i++)
216
+
217
+
for (i = 0; i < nvec; i++)
214
218
msix_entry[i] = qib_msix_entry[i].msix;
215
219
216
-
pci_read_config_word(dd->pcidev, pos + PCI_MSIX_FLAGS, &msix_flags);
217
-
tabsize = 1 + (msix_flags & PCI_MSIX_FLAGS_QSIZE);
218
-
if (tabsize > *msixcnt)
219
-
tabsize = *msixcnt;
220
-
ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize);
221
-
if (ret > 0) {
222
-
tabsize = ret;
223
-
ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize);
224
-
}
225
-
do_intx:
226
-
if (ret) {
227
-
qib_dev_err(dd,
228
-
"pci_enable_msix %d vectors failed: %d, falling back to INTx\n",
229
-
tabsize, ret);
230
-
tabsize = 0;
231
-
}
232
-
for (i = 0; i < tabsize; i++)
220
+
ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec);
221
+
if (ret < 0)
222
+
goto free_msix_entry;
223
+
else
224
+
nvec = ret;
225
+
226
+
for (i = 0; i < nvec; i++)
233
227
qib_msix_entry[i].msix = msix_entry[i];
228
+
234
229
kfree(msix_entry);
235
-
*msixcnt = tabsize;
230
+
*msixcnt = nvec;
231
+
return;
236
232
237
-
if (ret)
238
-
qib_enable_intx(dd->pcidev);
233
+
free_msix_entry:
234
+
kfree(msix_entry);
239
235
236
+
do_intx:
237
+
qib_dev_err(dd, "pci_enable_msix_range %d vectors failed: %d, "
238
+
"falling back to INTx\n", nvec, ret);
239
+
*msixcnt = 0;
240
+
qib_enable_intx(dd->pcidev);
240
241
}
241
242
242
243
/**
+1
include/linux/mlx5/device.h
+1
include/linux/mlx5/device.h
···
179
179
MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
180
180
MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
181
181
MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
182
+
MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
182
183
MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
183
184
MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
184
185
MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,