+2 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 3791 3791 adev->gfx.mcbp = true; 3792 3792 else if (amdgpu_mcbp == 0) 3793 3793 adev->gfx.mcbp = false; 3794 3794 - else if ((amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 0, 0)) && 3795 3795 - (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 0, 0)) && 3796 3796 - adev->gfx.num_gfx_rings) 3797 3797 - adev->gfx.mcbp = true; 3798 3794 3799 3795 if (amdgpu_sriov_vf(adev)) 3800 3796 adev->gfx.mcbp = true; ··· 4526 4530 r = amdgpu_device_evict_resources(adev); 4527 4531 if (r) 4528 4532 return r; 4533 4533 + 4534 4534 + amdgpu_ttm_set_buffer_funcs_status(adev, false); 4529 4535 4530 4536 amdgpu_fence_driver_hw_fini(adev); 4531 4537

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h

reviewed

··· 46 46 #define MCA_REG__STATUS__ERRORCODEEXT(x) MCA_REG_FIELD(x, 21, 16) 47 47 #define MCA_REG__STATUS__ERRORCODE(x) MCA_REG_FIELD(x, 15, 0) 48 48 49 49 + #define MCA_REG__SYND__ERRORINFORMATION(x) MCA_REG_FIELD(x, 17, 0) 50 50 + 49 51 enum amdgpu_mca_ip { 50 52 AMDGPU_MCA_IP_UNKNOW = -1, 51 53 AMDGPU_MCA_IP_PSP = 0,

+17

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

reviewed

··· 28 28 #include <linux/reboot.h> 29 29 #include <linux/syscalls.h> 30 30 #include <linux/pm_runtime.h> 31 31 + #include <linux/list_sort.h> 31 32 32 33 #include "amdgpu.h" 33 34 #include "amdgpu_ras.h" ··· 3666 3665 return err_node; 3667 3666 } 3668 3667 3668 3668 + static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b) 3669 3669 + { 3670 3670 + struct ras_err_node *nodea = container_of(a, struct ras_err_node, node); 3671 3671 + struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node); 3672 3672 + struct amdgpu_smuio_mcm_config_info *infoa = &nodea->err_info.mcm_info; 3673 3673 + struct amdgpu_smuio_mcm_config_info *infob = &nodeb->err_info.mcm_info; 3674 3674 + 3675 3675 + if (unlikely(infoa->socket_id != infob->socket_id)) 3676 3676 + return infoa->socket_id - infob->socket_id; 3677 3677 + else 3678 3678 + return infoa->die_id - infob->die_id; 3679 3679 + 3680 3680 + return 0; 3681 3681 + } 3682 3682 + 3669 3683 static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data, 3670 3684 struct amdgpu_smuio_mcm_config_info *mcm_info) 3671 3685 { ··· 3698 3682 3699 3683 err_data->err_list_count++; 3700 3684 list_add_tail(&err_node->node, &err_data->err_node_list); 3685 3685 + list_sort(NULL, &err_data->err_node_list, ras_err_info_cmp); 3701 3686 3702 3687 return &err_node->err_info; 3703 3688 }

+5

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

reviewed

··· 129 129 { 130 130 int data; 131 131 132 132 + if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2)) { 133 133 + /* Default enabled */ 134 134 + *flags |= AMD_CG_SUPPORT_HDP_MGCG; 135 135 + return; 136 136 + } 132 137 /* AMD_CG_SUPPORT_HDP_LS */ 133 138 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 134 139 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)

+8 -4

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

reviewed

··· 60 60 #define GFX_CMD_USB_PD_USE_LFB 0x480 61 61 62 62 /* Retry times for vmbx ready wait */ 63 63 - #define PSP_VMBX_POLLING_LIMIT 20000 63 63 + #define PSP_VMBX_POLLING_LIMIT 3000 64 64 65 65 /* VBIOS gfl defines */ 66 66 #define MBOX_READY_MASK 0x80000000 ··· 161 161 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 162 162 { 163 163 struct amdgpu_device *adev = psp->adev; 164 164 - int retry_loop, ret; 164 164 + int retry_loop, retry_cnt, ret; 165 165 166 166 + retry_cnt = 167 167 + (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) ? 168 168 + PSP_VMBX_POLLING_LIMIT : 169 169 + 10; 166 170 /* Wait for bootloader to signify that it is ready having bit 31 of 167 171 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 168 172 * If there is an error in processing command, bits[7:0] will be set. 169 173 * This is applicable for PSP v13.0.6 and newer. 170 174 */ 171 171 - for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) { 175 175 + for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) { 172 176 ret = psp_wait_for( 173 177 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 174 178 0x80000000, 0xffffffff, false); ··· 825 821 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) 826 822 return 0; 827 823 828 828 - if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10007) 824 824 + if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10109) 829 825 return 0; 830 826 831 827 for_each_inst(i, inst_mask) {

+10 -5

drivers/gpu/drm/amd/amdgpu/soc15.c

reviewed

··· 1423 1423 if (amdgpu_sriov_vf(adev)) 1424 1424 *flags = 0; 1425 1425 1426 1426 - adev->nbio.funcs->get_clockgating_state(adev, flags); 1426 1426 + if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) 1427 1427 + adev->nbio.funcs->get_clockgating_state(adev, flags); 1427 1428 1428 1428 - adev->hdp.funcs->get_clock_gating_state(adev, flags); 1429 1429 + if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) 1430 1430 + adev->hdp.funcs->get_clock_gating_state(adev, flags); 1429 1431 1430 1430 - if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) { 1432 1432 + if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && 1433 1433 + (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))) { 1431 1434 /* AMD_CG_SUPPORT_DRM_MGCG */ 1432 1435 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1433 1436 if (!(data & 0x01000000)) ··· 1443 1440 } 1444 1441 1445 1442 /* AMD_CG_SUPPORT_ROM_MGCG */ 1446 1446 - adev->smuio.funcs->get_clock_gating_state(adev, flags); 1443 1443 + if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) 1444 1444 + adev->smuio.funcs->get_clock_gating_state(adev, flags); 1447 1445 1448 1448 - adev->df.funcs->get_clockgating_state(adev, flags); 1446 1446 + if (adev->df.funcs && adev->df.funcs->get_clockgating_state) 1447 1447 + adev->df.funcs->get_clockgating_state(adev, flags); 1449 1448 } 1450 1449 1451 1450 static int soc15_common_set_powergating_state(void *handle,

+6

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

reviewed

··· 63 63 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id); 64 64 edid_caps->panel_patch.disable_fams = true; 65 65 break; 66 66 + /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */ 67 67 + case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB): 68 68 + case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B): 69 69 + DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id); 70 70 + edid_caps->panel_patch.remove_sink_ext_caps = true; 71 71 + break; 66 72 default: 67 73 return; 68 74 }

+7 -1

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

reviewed

··· 2386 2386 return BP_RESULT_BADBIOSTABLE; 2387 2387 2388 2388 info->num_chans = info_v30->channel_num; 2389 2389 - info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8; 2389 2389 + /* As suggested by VBIOS we should always use 2390 2390 + * dram_channel_width_bytes = 2 when using VRAM 2391 2391 + * table version 3.0. This is because the channel_width 2392 2392 + * param in the VRAM info table is changed in 7000 series and 2393 2393 + * no longer represents the memory channel width. 2394 2394 + */ 2395 2395 + info->dram_channel_width_bytes = 2; 2390 2396 2391 2397 return result; 2392 2398 }

+4

drivers/gpu/drm/amd/display/dc/dml/Makefile

reviewed

··· 61 61 endif 62 62 63 63 ifneq ($(CONFIG_FRAME_WARN),0) 64 64 + ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) 65 65 + frame_warn_flag := -Wframe-larger-than=3072 66 66 + else 64 67 frame_warn_flag := -Wframe-larger-than=2048 68 68 + endif 65 69 endif 66 70 67 71 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)

+3 -3

drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c

reviewed

··· 9447 9447 9448 9448 // Output 9449 9449 CalculateWatermarks_params->Watermark = &s->dummy_watermark; // Watermarks *Watermark 9450 9450 - CalculateWatermarks_params->DRAMClockChangeSupport = &mode_lib->ms.support.DRAMClockChangeSupport[j]; 9450 9450 + CalculateWatermarks_params->DRAMClockChangeSupport = &mode_lib->ms.support.DRAMClockChangeSupport[0]; 9451 9451 CalculateWatermarks_params->MaxActiveDRAMClockChangeLatencySupported = &s->dummy_single_array[0][0]; // dml_float_t *MaxActiveDRAMClockChangeLatencySupported[] 9452 9452 CalculateWatermarks_params->SubViewportLinesNeededInMALL = &mode_lib->ms.SubViewportLinesNeededInMALL[j]; // dml_uint_t SubViewportLinesNeededInMALL[] 9453 9453 - CalculateWatermarks_params->FCLKChangeSupport = &mode_lib->ms.support.FCLKChangeSupport[j]; 9453 9453 + CalculateWatermarks_params->FCLKChangeSupport = &mode_lib->ms.support.FCLKChangeSupport[0]; 9454 9454 CalculateWatermarks_params->MaxActiveFCLKChangeLatencySupported = &s->dummy_single[0]; // dml_float_t *MaxActiveFCLKChangeLatencySupported 9455 9455 - CalculateWatermarks_params->USRRetrainingSupport = &mode_lib->ms.support.USRRetrainingSupport[j]; 9455 9455 + CalculateWatermarks_params->USRRetrainingSupport = &mode_lib->ms.support.USRRetrainingSupport[0]; 9456 9456 9457 9457 CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( 9458 9458 &mode_lib->scratch,

+17

drivers/gpu/drm/amd/include/kgd_pp_interface.h

reviewed

··· 1085 1085 uint16_t average_dram_reads; 1086 1086 /* time filtered DRAM write bandwidth [MB/sec] */ 1087 1087 uint16_t average_dram_writes; 1088 1088 + /* time filtered IPU read bandwidth [MB/sec] */ 1089 1089 + uint16_t average_ipu_reads; 1090 1090 + /* time filtered IPU write bandwidth [MB/sec] */ 1091 1091 + uint16_t average_ipu_writes; 1088 1092 1089 1093 /* Driver attached timestamp (in ns) */ 1090 1094 uint64_t system_clock_counter; ··· 1108 1104 uint32_t average_all_core_power; 1109 1105 /* calculated core power [mW] */ 1110 1106 uint16_t average_core_power[16]; 1107 1107 + /* time filtered total system power [mW] */ 1108 1108 + uint16_t average_sys_power; 1111 1109 /* maximum IRM defined STAPM power limit [mW] */ 1112 1110 uint16_t stapm_power_limit; 1113 1111 /* time filtered STAPM power limit [mW] */ ··· 1122 1116 uint16_t average_ipuclk_frequency; 1123 1117 uint16_t average_fclk_frequency; 1124 1118 uint16_t average_vclk_frequency; 1119 1119 + uint16_t average_uclk_frequency; 1120 1120 + uint16_t average_mpipu_frequency; 1125 1121 1126 1122 /* Current clocks */ 1127 1123 /* target core frequency [MHz] */ ··· 1132 1124 uint16_t current_core_maxfreq; 1133 1125 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1134 1126 uint16_t current_gfx_maxfreq; 1127 1127 + 1128 1128 + /* Throttle Residency (ASIC dependent) */ 1129 1129 + uint32_t throttle_residency_prochot; 1130 1130 + uint32_t throttle_residency_spl; 1131 1131 + uint32_t throttle_residency_fppt; 1132 1132 + uint32_t throttle_residency_sppt; 1133 1133 + uint32_t throttle_residency_thm_core; 1134 1134 + uint32_t throttle_residency_thm_gfx; 1135 1135 + uint32_t throttle_residency_thm_soc; 1135 1136 1136 1137 /* Metrics table alpha filter time constant [us] */ 1137 1138 uint32_t time_filter_alphavalue;

+10

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

reviewed

··· 1408 1408 METRICS_PCIE_WIDTH, 1409 1409 METRICS_CURR_FANPWM, 1410 1410 METRICS_CURR_SOCKETPOWER, 1411 1411 + METRICS_AVERAGE_VPECLK, 1412 1412 + METRICS_AVERAGE_IPUCLK, 1413 1413 + METRICS_AVERAGE_MPIPUCLK, 1414 1414 + METRICS_THROTTLER_RESIDENCY_PROCHOT, 1415 1415 + METRICS_THROTTLER_RESIDENCY_SPL, 1416 1416 + METRICS_THROTTLER_RESIDENCY_FPPT, 1417 1417 + METRICS_THROTTLER_RESIDENCY_SPPT, 1418 1418 + METRICS_THROTTLER_RESIDENCY_THM_CORE, 1419 1419 + METRICS_THROTTLER_RESIDENCY_THM_GFX, 1420 1420 + METRICS_THROTTLER_RESIDENCY_THM_SOC, 1411 1421 } MetricsMember_t; 1412 1422 1413 1423 enum smu_cmn2asic_mapping_type {

+45 -32

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

reviewed

··· 27 27 // *** IMPORTANT *** 28 28 // SMU TEAM: Always increment the interface version if 29 29 // any structure is changed in this file 30 30 - #define PMFW_DRIVER_IF_VERSION 6 30 30 + #define PMFW_DRIVER_IF_VERSION 7 31 31 32 32 typedef struct { 33 33 int32_t value; ··· 150 150 } DpmClocks_t; 151 151 152 152 typedef struct { 153 153 - uint16_t CoreFrequency[16]; //Target core frequency [MHz] 154 154 - uint16_t CorePower[16]; //CAC calculated core power [mW] 155 155 - uint16_t CoreTemperature[16]; //TSEN measured core temperature [centi-C] 156 156 - uint16_t GfxTemperature; //TSEN measured GFX temperature [centi-C] 157 157 - uint16_t SocTemperature; //TSEN measured SOC temperature [centi-C] 158 158 - uint16_t StapmOpnLimit; //Maximum IRM defined STAPM power limit [mW] 159 159 - uint16_t StapmCurrentLimit; //Time filtered STAPM power limit [mW] 160 160 - uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz] 161 161 - uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz] 162 162 - uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis sensors [centi-C] 163 163 - uint16_t GfxclkFrequency; //Time filtered target GFXCLK frequency [MHz] 164 164 - uint16_t FclkFrequency; //Time filtered target FCLK frequency [MHz] 165 165 - uint16_t GfxActivity; //Time filtered GFX busy % [0-100] 166 166 - uint16_t SocclkFrequency; //Time filtered target SOCCLK frequency [MHz] 167 167 - uint16_t VclkFrequency; //Time filtered target VCLK frequency [MHz] 168 168 - uint16_t VcnActivity; //Time filtered VCN busy % [0-100] 169 169 - uint16_t VpeclkFrequency; //Time filtered target VPECLK frequency [MHz] 170 170 - uint16_t IpuclkFrequency; //Time filtered target IPUCLK frequency [MHz] 171 171 - uint16_t IpuBusy[8]; //Time filtered IPU per-column busy % [0-100] 172 172 - uint16_t DRAMReads; //Time filtered DRAM read bandwidth [MB/sec] 173 173 - uint16_t DRAMWrites; //Time filtered DRAM write bandwidth [MB/sec] 174 174 - uint16_t CoreC0Residency[16]; //Time filtered per-core C0 residency % [0-100] 175 175 - uint16_t IpuPower; //Time filtered IPU power [mW] 176 176 - uint32_t ApuPower; //Time filtered APU power [mW] 177 177 - uint32_t GfxPower; //Time filtered GFX power [mW] 178 178 - uint32_t dGpuPower; //Time filtered dGPU power [mW] 179 179 - uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW] 180 180 - uint32_t AllCorePower; //Time filtered sum of core power across all cores in the socket [mW] 181 181 - uint32_t FilterAlphaValue; //Metrics table alpha filter time constant [us] 182 182 - uint32_t MetricsCounter; //Counter that is incremented on every metrics table update [PM_TIMER cycles] 183 183 - uint32_t spare[16]; 153 153 + uint16_t CoreFrequency[16]; //Target core frequency [MHz] 154 154 + uint16_t CorePower[16]; //CAC calculated core power [mW] 155 155 + uint16_t CoreTemperature[16]; //TSEN measured core temperature [centi-C] 156 156 + uint16_t GfxTemperature; //TSEN measured GFX temperature [centi-C] 157 157 + uint16_t SocTemperature; //TSEN measured SOC temperature [centi-C] 158 158 + uint16_t StapmOpnLimit; //Maximum IRM defined STAPM power limit [mW] 159 159 + uint16_t StapmCurrentLimit; //Time filtered STAPM power limit [mW] 160 160 + uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz] 161 161 + uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz] 162 162 + uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis sensors [centi-C] 163 163 + uint16_t GfxclkFrequency; //Time filtered target GFXCLK frequency [MHz] 164 164 + uint16_t FclkFrequency; //Time filtered target FCLK frequency [MHz] 165 165 + uint16_t GfxActivity; //Time filtered GFX busy % [0-100] 166 166 + uint16_t SocclkFrequency; //Time filtered target SOCCLK frequency [MHz] 167 167 + uint16_t VclkFrequency; //Time filtered target VCLK frequency [MHz] 168 168 + uint16_t VcnActivity; //Time filtered VCN busy % [0-100] 169 169 + uint16_t VpeclkFrequency; //Time filtered target VPECLK frequency [MHz] 170 170 + uint16_t IpuclkFrequency; //Time filtered target IPUCLK frequency [MHz] 171 171 + uint16_t IpuBusy[8]; //Time filtered IPU per-column busy % [0-100] 172 172 + uint16_t DRAMReads; //Time filtered DRAM read bandwidth [MB/sec] 173 173 + uint16_t DRAMWrites; //Time filtered DRAM write bandwidth [MB/sec] 174 174 + uint16_t CoreC0Residency[16]; //Time filtered per-core C0 residency % [0-100] 175 175 + uint16_t IpuPower; //Time filtered IPU power [mW] 176 176 + uint32_t ApuPower; //Time filtered APU power [mW] 177 177 + uint32_t GfxPower; //Time filtered GFX power [mW] 178 178 + uint32_t dGpuPower; //Time filtered dGPU power [mW] 179 179 + uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW] 180 180 + uint32_t AllCorePower; //Time filtered sum of core power across all cores in the socket [mW] 181 181 + uint32_t FilterAlphaValue; //Metrics table alpha filter time constant [us] 182 182 + uint32_t MetricsCounter; //Counter that is incremented on every metrics table update [PM_TIMER cycles] 183 183 + uint16_t MemclkFrequency; //Time filtered target MEMCLK frequency [MHz] 184 184 + uint16_t MpipuclkFrequency; //Time filtered target MPIPUCLK frequency [MHz] 185 185 + uint16_t IpuReads; //Time filtered IPU read bandwidth [MB/sec] 186 186 + uint16_t IpuWrites; //Time filtered IPU write bandwidth [MB/sec] 187 187 + uint32_t ThrottleResidency_PROCHOT; //Counter that is incremented on every metrics table update when PROCHOT was engaged [PM_TIMER cycles] 188 188 + uint32_t ThrottleResidency_SPL; //Counter that is incremented on every metrics table update when SPL was engaged [PM_TIMER cycles] 189 189 + uint32_t ThrottleResidency_FPPT; //Counter that is incremented on every metrics table update when fast PPT was engaged [PM_TIMER cycles] 190 190 + uint32_t ThrottleResidency_SPPT; //Counter that is incremented on every metrics table update when slow PPT was engaged [PM_TIMER cycles] 191 191 + uint32_t ThrottleResidency_THM_CORE; //Counter that is incremented on every metrics table update when CORE thermal throttling was engaged [PM_TIMER cycles] 192 192 + uint32_t ThrottleResidency_THM_GFX; //Counter that is incremented on every metrics table update when GFX thermal throttling was engaged [PM_TIMER cycles] 193 193 + uint32_t ThrottleResidency_THM_SOC; //Counter that is incremented on every metrics table update when SOC thermal throttling was engaged [PM_TIMER cycles] 194 194 + uint16_t Psys; //Time filtered Psys power [mW] 195 195 + uint16_t spare1; 196 196 + uint32_t spare[6]; 184 197 } SmuMetrics_t; 185 198 186 199 //ISP tile definitions

+8 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

reviewed

··· 2593 2593 static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 2594 2594 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry) 2595 2595 { 2596 2596 + struct smu_context *smu = adev->powerplay.pp_handle; 2596 2597 uint32_t errcode, instlo; 2597 2598 2598 2599 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo); 2599 2600 if (instlo != 0x03b30400) 2600 2601 return false; 2601 2602 2602 2602 - errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode); 2603 2603 + if (!(adev->flags & AMD_IS_APU) && smu->smc_fw_version >= 0x00555600) { 2604 2604 + errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]); 2605 2605 + errcode &= 0xff; 2606 2606 + } else { 2607 2607 + errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode); 2608 2608 + } 2609 2609 + 2603 2610 return mca_smu_check_error_code(adev, mca_ras, errcode); 2604 2611 } 2605 2612

+43 -3

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

reviewed

··· 246 246 *value = 0; 247 247 break; 248 248 case METRICS_AVERAGE_UCLK: 249 249 - *value = 0; 249 249 + *value = metrics->MemclkFrequency; 250 250 break; 251 251 case METRICS_AVERAGE_FCLK: 252 252 *value = metrics->FclkFrequency; 253 253 + break; 254 254 + case METRICS_AVERAGE_VPECLK: 255 255 + *value = metrics->VpeclkFrequency; 256 256 + break; 257 257 + case METRICS_AVERAGE_IPUCLK: 258 258 + *value = metrics->IpuclkFrequency; 259 259 + break; 260 260 + case METRICS_AVERAGE_MPIPUCLK: 261 261 + *value = metrics->MpipuclkFrequency; 253 262 break; 254 263 case METRICS_AVERAGE_GFXACTIVITY: 255 264 *value = metrics->GfxActivity / 100; ··· 279 270 *value = metrics->SocTemperature / 100 * 280 271 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 281 272 break; 282 282 - case METRICS_THROTTLER_STATUS: 283 283 - *value = 0; 273 273 + case METRICS_THROTTLER_RESIDENCY_PROCHOT: 274 274 + *value = metrics->ThrottleResidency_PROCHOT; 275 275 + break; 276 276 + case METRICS_THROTTLER_RESIDENCY_SPL: 277 277 + *value = metrics->ThrottleResidency_SPL; 278 278 + break; 279 279 + case METRICS_THROTTLER_RESIDENCY_FPPT: 280 280 + *value = metrics->ThrottleResidency_FPPT; 281 281 + break; 282 282 + case METRICS_THROTTLER_RESIDENCY_SPPT: 283 283 + *value = metrics->ThrottleResidency_SPPT; 284 284 + break; 285 285 + case METRICS_THROTTLER_RESIDENCY_THM_CORE: 286 286 + *value = metrics->ThrottleResidency_THM_CORE; 287 287 + break; 288 288 + case METRICS_THROTTLER_RESIDENCY_THM_GFX: 289 289 + *value = metrics->ThrottleResidency_THM_GFX; 290 290 + break; 291 291 + case METRICS_THROTTLER_RESIDENCY_THM_SOC: 292 292 + *value = metrics->ThrottleResidency_THM_SOC; 284 293 break; 285 294 case METRICS_VOLTAGE_VDDGFX: 286 295 *value = 0; ··· 525 498 sizeof(uint16_t) * 16); 526 499 gpu_metrics->average_dram_reads = metrics.DRAMReads; 527 500 gpu_metrics->average_dram_writes = metrics.DRAMWrites; 501 501 + gpu_metrics->average_ipu_reads = metrics.IpuReads; 502 502 + gpu_metrics->average_ipu_writes = metrics.IpuWrites; 528 503 529 504 gpu_metrics->average_socket_power = metrics.SocketPower; 530 505 gpu_metrics->average_ipu_power = metrics.IpuPower; ··· 534 505 gpu_metrics->average_gfx_power = metrics.GfxPower; 535 506 gpu_metrics->average_dgpu_power = metrics.dGpuPower; 536 507 gpu_metrics->average_all_core_power = metrics.AllCorePower; 508 508 + gpu_metrics->average_sys_power = metrics.Psys; 537 509 memcpy(&gpu_metrics->average_core_power[0], 538 510 &metrics.CorePower[0], 539 511 sizeof(uint16_t) * 16); ··· 545 515 gpu_metrics->average_fclk_frequency = metrics.FclkFrequency; 546 516 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 547 517 gpu_metrics->average_ipuclk_frequency = metrics.IpuclkFrequency; 518 518 + gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 519 519 + gpu_metrics->average_mpipu_frequency = metrics.MpipuclkFrequency; 548 520 549 521 memcpy(&gpu_metrics->current_coreclk[0], 550 522 &metrics.CoreFrequency[0], 551 523 sizeof(uint16_t) * 16); 552 524 gpu_metrics->current_core_maxfreq = metrics.InfrastructureCpuMaxFreq; 553 525 gpu_metrics->current_gfx_maxfreq = metrics.InfrastructureGfxMaxFreq; 526 526 + 527 527 + gpu_metrics->throttle_residency_prochot = metrics.ThrottleResidency_PROCHOT; 528 528 + gpu_metrics->throttle_residency_spl = metrics.ThrottleResidency_SPL; 529 529 + gpu_metrics->throttle_residency_fppt = metrics.ThrottleResidency_FPPT; 530 530 + gpu_metrics->throttle_residency_sppt = metrics.ThrottleResidency_SPPT; 531 531 + gpu_metrics->throttle_residency_thm_core = metrics.ThrottleResidency_THM_CORE; 532 532 + gpu_metrics->throttle_residency_thm_gfx = metrics.ThrottleResidency_THM_GFX; 533 533 + gpu_metrics->throttle_residency_thm_soc = metrics.ThrottleResidency_THM_SOC; 554 534 555 535 gpu_metrics->time_filter_alphavalue = metrics.FilterAlphaValue; 556 536 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();

+1

drivers/gpu/drm/bridge/Kconfig

reviewed

··· 313 313 select REGMAP_I2C 314 314 select DRM_PANEL 315 315 select DRM_MIPI_DSI 316 316 + select VIDEOMODE_HELPERS 316 317 help 317 318 Toshiba TC358768AXBG/TC358778XBG DSI bridge chip driver. 318 319

+52 -26

drivers/gpu/drm/drm_atomic_helper.c

reviewed

··· 2012 2012 return ret; 2013 2013 2014 2014 drm_atomic_helper_async_commit(dev, state); 2015 2015 - drm_atomic_helper_cleanup_planes(dev, state); 2015 2015 + drm_atomic_helper_unprepare_planes(dev, state); 2016 2016 2017 2017 return 0; 2018 2018 } ··· 2072 2072 return 0; 2073 2073 2074 2074 err: 2075 2075 - drm_atomic_helper_cleanup_planes(dev, state); 2075 2075 + drm_atomic_helper_unprepare_planes(dev, state); 2076 2076 return ret; 2077 2077 } 2078 2078 EXPORT_SYMBOL(drm_atomic_helper_commit); ··· 2650 2650 } 2651 2651 EXPORT_SYMBOL(drm_atomic_helper_prepare_planes); 2652 2652 2653 2653 + /** 2654 2654 + * drm_atomic_helper_unprepare_planes - release plane resources on aborts 2655 2655 + * @dev: DRM device 2656 2656 + * @state: atomic state object with old state structures 2657 2657 + * 2658 2658 + * This function cleans up plane state, specifically framebuffers, from the 2659 2659 + * atomic state. It undoes the effects of drm_atomic_helper_prepare_planes() 2660 2660 + * when aborting an atomic commit. For cleaning up after a successful commit 2661 2661 + * use drm_atomic_helper_cleanup_planes(). 2662 2662 + */ 2663 2663 + void drm_atomic_helper_unprepare_planes(struct drm_device *dev, 2664 2664 + struct drm_atomic_state *state) 2665 2665 + { 2666 2666 + struct drm_plane *plane; 2667 2667 + struct drm_plane_state *new_plane_state; 2668 2668 + int i; 2669 2669 + 2670 2670 + for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2671 2671 + const struct drm_plane_helper_funcs *funcs = plane->helper_private; 2672 2672 + 2673 2673 + if (funcs->end_fb_access) 2674 2674 + funcs->end_fb_access(plane, new_plane_state); 2675 2675 + } 2676 2676 + 2677 2677 + for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2678 2678 + const struct drm_plane_helper_funcs *funcs = plane->helper_private; 2679 2679 + 2680 2680 + if (funcs->cleanup_fb) 2681 2681 + funcs->cleanup_fb(plane, new_plane_state); 2682 2682 + } 2683 2683 + } 2684 2684 + EXPORT_SYMBOL(drm_atomic_helper_unprepare_planes); 2685 2685 + 2653 2686 static bool plane_crtc_active(const struct drm_plane_state *state) 2654 2687 { 2655 2688 return state->crtc && state->crtc->state->active; ··· 2817 2784 2818 2785 funcs->atomic_flush(crtc, old_state); 2819 2786 } 2787 2787 + 2788 2788 + /* 2789 2789 + * Signal end of framebuffer access here before hw_done. After hw_done, 2790 2790 + * a later commit might have already released the plane state. 2791 2791 + */ 2792 2792 + for_each_old_plane_in_state(old_state, plane, old_plane_state, i) { 2793 2793 + const struct drm_plane_helper_funcs *funcs = plane->helper_private; 2794 2794 + 2795 2795 + if (funcs->end_fb_access) 2796 2796 + funcs->end_fb_access(plane, old_plane_state); 2797 2797 + } 2820 2798 } 2821 2799 EXPORT_SYMBOL(drm_atomic_helper_commit_planes); 2822 2800 ··· 2955 2911 * configuration. Hence the old configuration must be perserved in @old_state to 2956 2912 * be able to call this function. 2957 2913 * 2958 2958 - * This function must also be called on the new state when the atomic update 2959 2959 - * fails at any point after calling drm_atomic_helper_prepare_planes(). 2914 2914 + * This function may not be called on the new state when the atomic update 2915 2915 + * fails at any point after calling drm_atomic_helper_prepare_planes(). Use 2916 2916 + * drm_atomic_helper_unprepare_planes() in this case. 2960 2917 */ 2961 2918 void drm_atomic_helper_cleanup_planes(struct drm_device *dev, 2962 2919 struct drm_atomic_state *old_state) 2963 2920 { 2964 2921 struct drm_plane *plane; 2965 2965 - struct drm_plane_state *old_plane_state, *new_plane_state; 2922 2922 + struct drm_plane_state *old_plane_state; 2966 2923 int i; 2967 2924 2968 2968 - for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, new_plane_state, i) { 2925 2925 + for_each_old_plane_in_state(old_state, plane, old_plane_state, i) { 2969 2926 const struct drm_plane_helper_funcs *funcs = plane->helper_private; 2970 2927 2971 2971 - if (funcs->end_fb_access) 2972 2972 - funcs->end_fb_access(plane, new_plane_state); 2973 2973 - } 2974 2974 - 2975 2975 - for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, new_plane_state, i) { 2976 2976 - const struct drm_plane_helper_funcs *funcs; 2977 2977 - struct drm_plane_state *plane_state; 2978 2978 - 2979 2979 - /* 2980 2980 - * This might be called before swapping when commit is aborted, 2981 2981 - * in which case we have to cleanup the new state. 2982 2982 - */ 2983 2983 - if (old_plane_state == plane->state) 2984 2984 - plane_state = new_plane_state; 2985 2985 - else 2986 2986 - plane_state = old_plane_state; 2987 2987 - 2988 2988 - funcs = plane->helper_private; 2989 2989 - 2990 2928 if (funcs->cleanup_fb) 2991 2991 - funcs->cleanup_fb(plane, plane_state); 2929 2929 + funcs->cleanup_fb(plane, old_plane_state); 2992 2930 } 2993 2931 } 2994 2932 EXPORT_SYMBOL(drm_atomic_helper_cleanup_planes);

+3 -5

drivers/gpu/drm/exynos/exynos_drm_dma.c

reviewed

··· 107 107 return 0; 108 108 109 109 if (!priv->mapping) { 110 110 - void *mapping; 110 110 + void *mapping = NULL; 111 111 112 112 if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)) 113 113 mapping = arm_iommu_create_mapping(&platform_bus_type, 114 114 EXYNOS_DEV_ADDR_START, EXYNOS_DEV_ADDR_SIZE); 115 115 else if (IS_ENABLED(CONFIG_IOMMU_DMA)) 116 116 mapping = iommu_get_domain_for_dev(priv->dma_dev); 117 117 - else 118 118 - mapping = ERR_PTR(-ENODEV); 119 117 120 120 - if (IS_ERR(mapping)) 121 121 - return PTR_ERR(mapping); 118 118 + if (!mapping) 119 119 + return -ENODEV; 122 120 priv->mapping = mapping; 123 121 } 124 122

+2

drivers/gpu/drm/exynos/exynos_hdmi.c

reviewed

··· 1861 1861 return ret; 1862 1862 1863 1863 crtc = exynos_drm_crtc_get_by_type(drm_dev, EXYNOS_DISPLAY_TYPE_HDMI); 1864 1864 + if (IS_ERR(crtc)) 1865 1865 + return PTR_ERR(crtc); 1864 1866 crtc->pipe_clk = &hdata->phy_clk; 1865 1867 1866 1868 ret = hdmi_create_connector(encoder);

+7

drivers/gpu/drm/i915/display/icl_dsi.c

reviewed

··· 1440 1440 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1441 1441 struct drm_display_mode *mode) 1442 1442 { 1443 1443 + struct drm_i915_private *i915 = to_i915(connector->dev); 1444 1444 + enum drm_mode_status status; 1445 1445 + 1446 1446 + status = intel_cpu_transcoder_mode_valid(i915, mode); 1447 1447 + if (status != MODE_OK) 1448 1448 + return status; 1449 1449 + 1443 1450 /* FIXME: DSC? */ 1444 1451 return intel_dsi_mode_valid(connector, mode); 1445 1452 }

+5

drivers/gpu/drm/i915/display/intel_crt.c

reviewed

··· 348 348 struct drm_device *dev = connector->dev; 349 349 struct drm_i915_private *dev_priv = to_i915(dev); 350 350 int max_dotclk = dev_priv->max_dotclk_freq; 351 351 + enum drm_mode_status status; 351 352 int max_clock; 353 353 + 354 354 + status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 355 355 + if (status != MODE_OK) 356 356 + return status; 352 357 353 358 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 354 359 return MODE_NO_DBLESCAN;

+23 -1

drivers/gpu/drm/i915/display/intel_display.c

reviewed

··· 906 906 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 907 907 const struct intel_crtc_state *new_crtc_state) 908 908 { 909 909 + if (!new_crtc_state->hw.active) 910 910 + return false; 911 911 + 909 912 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 910 913 } 911 914 912 915 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 913 916 const struct intel_crtc_state *new_crtc_state) 914 917 { 918 918 + if (!old_crtc_state->hw.active) 919 919 + return false; 920 920 + 915 921 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 916 922 } 917 923 ··· 934 928 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, 935 929 const struct intel_crtc_state *new_crtc_state) 936 930 { 931 931 + if (!new_crtc_state->hw.active) 932 932 + return false; 933 933 + 937 934 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) || 938 935 (new_crtc_state->vrr.enable && 939 936 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || ··· 946 937 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, 947 938 const struct intel_crtc_state *new_crtc_state) 948 939 { 940 940 + if (!old_crtc_state->hw.active) 941 941 + return false; 942 942 + 949 943 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) || 950 944 (old_crtc_state->vrr.enable && 951 945 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || ··· 7488 7476 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7489 7477 intel_color_cleanup_commit(new_crtc_state); 7490 7478 7491 7491 - drm_atomic_helper_cleanup_planes(dev, &state->base); 7479 7479 + drm_atomic_helper_unprepare_planes(dev, &state->base); 7492 7480 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7493 7481 return ret; 7494 7482 } ··· 7869 7857 mode->vtotal > vtotal_max) 7870 7858 return MODE_V_ILLEGAL; 7871 7859 7860 7860 + return MODE_OK; 7861 7861 + } 7862 7862 + 7863 7863 + enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv, 7864 7864 + const struct drm_display_mode *mode) 7865 7865 + { 7866 7866 + /* 7867 7867 + * Additional transcoder timing limits, 7868 7868 + * excluding BXT/GLK DSI transcoders. 7869 7869 + */ 7872 7870 if (DISPLAY_VER(dev_priv) >= 5) { 7873 7871 if (mode->hdisplay < 64 || 7874 7872 mode->htotal - mode->hdisplay < 32)

+3

drivers/gpu/drm/i915/display/intel_display.h

reviewed

··· 403 403 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 404 404 const struct drm_display_mode *mode, 405 405 bool bigjoiner); 406 406 + enum drm_mode_status 407 407 + intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915, 408 408 + const struct drm_display_mode *mode); 406 409 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 407 410 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 408 411 bool is_trans_port_sync_master(const struct intel_crtc_state *state);

+4

drivers/gpu/drm/i915/display/intel_dp.c

reviewed

··· 1172 1172 enum drm_mode_status status; 1173 1173 bool dsc = false, bigjoiner = false; 1174 1174 1175 1175 + status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 1176 1176 + if (status != MODE_OK) 1177 1177 + return status; 1178 1178 + 1175 1179 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1176 1180 return MODE_H_ILLEGAL; 1177 1181

+16 -4

drivers/gpu/drm/i915/display/intel_dp_mst.c

reviewed

··· 959 959 return 0; 960 960 } 961 961 962 962 + *status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 963 963 + if (*status != MODE_OK) 964 964 + return 0; 965 965 + 962 966 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 963 967 *status = MODE_NO_DBLESCAN; 964 968 return 0; ··· 997 993 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { 998 994 bigjoiner = true; 999 995 max_dotclk *= 2; 996 996 + 997 997 + /* TODO: add support for bigjoiner */ 998 998 + *status = MODE_CLOCK_HIGH; 999 999 + return 0; 1000 1000 } 1001 1001 1002 1002 if (DISPLAY_VER(dev_priv) >= 10 && ··· 1035 1027 * Big joiner configuration needs DSC for TGL which is not true for 1036 1028 * XE_LPD where uncompressed joiner is supported. 1037 1029 */ 1038 1038 - if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) 1039 1039 - return MODE_CLOCK_HIGH; 1030 1030 + if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) { 1031 1031 + *status = MODE_CLOCK_HIGH; 1032 1032 + return 0; 1033 1033 + } 1040 1034 1041 1041 - if (mode_rate > max_rate && !dsc) 1042 1042 - return MODE_CLOCK_HIGH; 1035 1035 + if (mode_rate > max_rate && !dsc) { 1036 1036 + *status = MODE_CLOCK_HIGH; 1037 1037 + return 0; 1038 1038 + } 1043 1039 1044 1040 *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); 1045 1041 return 0;

+1 -1

drivers/gpu/drm/i915/display/intel_dsb.c

reviewed

··· 340 340 } 341 341 342 342 static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, 343 343 - unsigned int dewake_scanline) 343 343 + int dewake_scanline) 344 344 { 345 345 struct intel_crtc *crtc = dsb->crtc; 346 346 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

+6

drivers/gpu/drm/i915/display/intel_dvo.c

reviewed

··· 217 217 struct drm_display_mode *mode) 218 218 { 219 219 struct intel_connector *connector = to_intel_connector(_connector); 220 220 + struct drm_i915_private *i915 = to_i915(connector->base.dev); 220 221 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 221 222 const struct drm_display_mode *fixed_mode = 222 223 intel_panel_fixed_mode(connector, mode); 223 224 int max_dotclk = to_i915(connector->base.dev)->max_dotclk_freq; 224 225 int target_clock = mode->clock; 226 226 + enum drm_mode_status status; 227 227 + 228 228 + status = intel_cpu_transcoder_mode_valid(i915, mode); 229 229 + if (status != MODE_OK) 230 230 + return status; 225 231 226 232 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 227 233 return MODE_NO_DBLESCAN;

+4

drivers/gpu/drm/i915/display/intel_hdmi.c

reviewed

··· 1983 1983 bool ycbcr_420_only; 1984 1984 enum intel_output_format sink_format; 1985 1985 1986 1986 + status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 1987 1987 + if (status != MODE_OK) 1988 1988 + return status; 1989 1989 + 1986 1990 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1987 1991 clock *= 2; 1988 1992

+5

drivers/gpu/drm/i915/display/intel_lvds.c

reviewed

··· 389 389 struct drm_display_mode *mode) 390 390 { 391 391 struct intel_connector *connector = to_intel_connector(_connector); 392 392 + struct drm_i915_private *i915 = to_i915(connector->base.dev); 392 393 const struct drm_display_mode *fixed_mode = 393 394 intel_panel_fixed_mode(connector, mode); 394 395 int max_pixclk = to_i915(connector->base.dev)->max_dotclk_freq; 395 396 enum drm_mode_status status; 397 397 + 398 398 + status = intel_cpu_transcoder_mode_valid(i915, mode); 399 399 + if (status != MODE_OK) 400 400 + return status; 396 401 397 402 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 398 403 return MODE_NO_DBLESCAN;

+7 -1

drivers/gpu/drm/i915/display/intel_sdvo.c

reviewed

··· 1921 1921 intel_sdvo_mode_valid(struct drm_connector *connector, 1922 1922 struct drm_display_mode *mode) 1923 1923 { 1924 1924 + struct drm_i915_private *i915 = to_i915(connector->dev); 1924 1925 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1925 1926 struct intel_sdvo_connector *intel_sdvo_connector = 1926 1927 to_intel_sdvo_connector(connector); 1927 1927 - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1928 1928 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state); 1929 1929 + int max_dotclk = i915->max_dotclk_freq; 1930 1930 + enum drm_mode_status status; 1929 1931 int clock = mode->clock; 1932 1932 + 1933 1933 + status = intel_cpu_transcoder_mode_valid(i915, mode); 1934 1934 + if (status != MODE_OK) 1935 1935 + return status; 1930 1936 1931 1937 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1932 1938 return MODE_NO_DBLESCAN;

+7 -1

drivers/gpu/drm/i915/display/intel_tv.c

reviewed

··· 958 958 intel_tv_mode_valid(struct drm_connector *connector, 959 959 struct drm_display_mode *mode) 960 960 { 961 961 + struct drm_i915_private *i915 = to_i915(connector->dev); 961 962 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 962 962 - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 963 963 + int max_dotclk = i915->max_dotclk_freq; 964 964 + enum drm_mode_status status; 965 965 + 966 966 + status = intel_cpu_transcoder_mode_valid(i915, mode); 967 967 + if (status != MODE_OK) 968 968 + return status; 963 969 964 970 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 965 971 return MODE_NO_DBLESCAN;

+17 -1

drivers/gpu/drm/i915/display/vlv_dsi.c

reviewed

··· 1541 1541 .destroy = intel_dsi_encoder_destroy, 1542 1542 }; 1543 1543 1544 1544 + static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector, 1545 1545 + struct drm_display_mode *mode) 1546 1546 + { 1547 1547 + struct drm_i915_private *i915 = to_i915(connector->dev); 1548 1548 + 1549 1549 + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 1550 1550 + enum drm_mode_status status; 1551 1551 + 1552 1552 + status = intel_cpu_transcoder_mode_valid(i915, mode); 1553 1553 + if (status != MODE_OK) 1554 1554 + return status; 1555 1555 + } 1556 1556 + 1557 1557 + return intel_dsi_mode_valid(connector, mode); 1558 1558 + } 1559 1559 + 1544 1560 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1545 1561 .get_modes = intel_dsi_get_modes, 1546 1546 - .mode_valid = intel_dsi_mode_valid, 1562 1562 + .mode_valid = vlv_dsi_mode_valid, 1547 1563 .atomic_check = intel_digital_connector_atomic_check, 1548 1564 }; 1549 1565

+1 -1

drivers/gpu/drm/nouveau/dispnv50/disp.c

reviewed

··· 2474 2474 2475 2475 err_cleanup: 2476 2476 if (ret) 2477 2477 - drm_atomic_helper_cleanup_planes(dev, state); 2477 2477 + drm_atomic_helper_unprepare_planes(dev, state); 2478 2478 done: 2479 2479 pm_runtime_put_autosuspend(dev->dev); 2480 2480 return ret;

+51

drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/shared/msgq/inc/msgq/msgq_priv.h

reviewed

··· 26 26 * DEALINGS IN THE SOFTWARE. 27 27 */ 28 28 29 29 + /** 30 30 + * msgqTxHeader -- TX queue data structure 31 31 + * @version: the version of this structure, must be 0 32 32 + * @size: the size of the entire queue, including this header 33 33 + * @msgSize: the padded size of queue element, 16 is minimum 34 34 + * @msgCount: the number of elements in this queue 35 35 + * @writePtr: head index of this queue 36 36 + * @flags: 1 = swap the RX pointers 37 37 + * @rxHdrOff: offset of readPtr in this structure 38 38 + * @entryOff: offset of beginning of queue (msgqRxHeader), relative to 39 39 + * beginning of this structure 40 40 + * 41 41 + * The command queue is a queue of RPCs that are sent from the driver to the 42 42 + * GSP. The status queue is a queue of messages/responses from GSP-RM to the 43 43 + * driver. Although the driver allocates memory for both queues, the command 44 44 + * queue is owned by the driver and the status queue is owned by GSP-RM. In 45 45 + * addition, the headers of the two queues must not share the same 4K page. 46 46 + * 47 47 + * Each queue is prefixed with this data structure. The idea is that a queue 48 48 + * and its header are written to only by their owner. That is, only the 49 49 + * driver writes to the command queue and command queue header, and only the 50 50 + * GSP writes to the status (receive) queue and its header. 51 51 + * 52 52 + * This is enforced by the concept of "swapping" the RX pointers. This is 53 53 + * why the 'flags' field must be set to 1. 'rxHdrOff' is how the GSP knows 54 54 + * where the where the tail pointer of its status queue. 55 55 + * 56 56 + * When the driver writes a new RPC to the command queue, it updates writePtr. 57 57 + * When it reads a new message from the status queue, it updates readPtr. In 58 58 + * this way, the GSP knows when a new command is in the queue (it polls 59 59 + * writePtr) and it knows how much free space is in the status queue (it 60 60 + * checks readPtr). The driver never cares about how much free space is in 61 61 + * the status queue. 62 62 + * 63 63 + * As usual, producers write to the head pointer, and consumers read from the 64 64 + * tail pointer. When head == tail, the queue is empty. 65 65 + * 66 66 + * So to summarize: 67 67 + * command.writePtr = head of command queue 68 68 + * command.readPtr = tail of status queue 69 69 + * status.writePtr = head of status queue 70 70 + * status.readPtr = tail of command queue 71 71 + */ 29 72 typedef struct 30 73 { 31 74 NvU32 version; // queue version ··· 81 38 NvU32 entryOff; // Offset of entries from start of backing store. 82 39 } msgqTxHeader; 83 40 41 41 + /** 42 42 + * msgqRxHeader - RX queue data structure 43 43 + * @readPtr: tail index of the other queue 44 44 + * 45 45 + * Although this is a separate struct, it could easily be merged into 46 46 + * msgqTxHeader. msgqTxHeader.rxHdrOff is simply the offset of readPtr 47 47 + * from the beginning of msgqTxHeader. 48 48 + */ 84 49 typedef struct 85 50 { 86 51 NvU32 readPtr; // message id of last message read

+82

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c

reviewed

··· 1377 1377 return 0; 1378 1378 } 1379 1379 1380 1380 + /** 1381 1381 + * r535_gsp_msg_run_cpu_sequencer() -- process I/O commands from the GSP 1382 1382 + * 1383 1383 + * The GSP sequencer is a list of I/O commands that the GSP can send to 1384 1384 + * the driver to perform for various purposes. The most common usage is to 1385 1385 + * perform a special mid-initialization reset. 1386 1386 + */ 1380 1387 static int 1381 1388 r535_gsp_msg_run_cpu_sequencer(void *priv, u32 fn, void *repv, u32 repc) 1382 1389 { ··· 1723 1716 return id; 1724 1717 } 1725 1718 1719 1719 + /** 1720 1720 + * create_pte_array() - creates a PTE array of a physically contiguous buffer 1721 1721 + * @ptes: pointer to the array 1722 1722 + * @addr: base address of physically contiguous buffer (GSP_PAGE_SIZE aligned) 1723 1723 + * @size: size of the buffer 1724 1724 + * 1725 1725 + * GSP-RM sometimes expects physically-contiguous buffers to have an array of 1726 1726 + * "PTEs" for each page in that buffer. Although in theory that allows for 1727 1727 + * the buffer to be physically discontiguous, GSP-RM does not currently 1728 1728 + * support that. 1729 1729 + * 1730 1730 + * In this case, the PTEs are DMA addresses of each page of the buffer. Since 1731 1731 + * the buffer is physically contiguous, calculating all the PTEs is simple 1732 1732 + * math. 1733 1733 + * 1734 1734 + * See memdescGetPhysAddrsForGpu() 1735 1735 + */ 1726 1736 static void create_pte_array(u64 *ptes, dma_addr_t addr, size_t size) 1727 1737 { 1728 1738 unsigned int num_pages = DIV_ROUND_UP_ULL(size, GSP_PAGE_SIZE); ··· 1749 1725 ptes[i] = (u64)addr + (i << GSP_PAGE_SHIFT); 1750 1726 } 1751 1727 1728 1728 + /** 1729 1729 + * r535_gsp_libos_init() -- create the libos arguments structure 1730 1730 + * 1731 1731 + * The logging buffers are byte queues that contain encoded printf-like 1732 1732 + * messages from GSP-RM. They need to be decoded by a special application 1733 1733 + * that can parse the buffers. 1734 1734 + * 1735 1735 + * The 'loginit' buffer contains logs from early GSP-RM init and 1736 1736 + * exception dumps. The 'logrm' buffer contains the subsequent logs. Both are 1737 1737 + * written to directly by GSP-RM and can be any multiple of GSP_PAGE_SIZE. 1738 1738 + * 1739 1739 + * The physical address map for the log buffer is stored in the buffer 1740 1740 + * itself, starting with offset 1. Offset 0 contains the "put" pointer. 1741 1741 + * 1742 1742 + * The GSP only understands 4K pages (GSP_PAGE_SIZE), so even if the kernel is 1743 1743 + * configured for a larger page size (e.g. 64K pages), we need to give 1744 1744 + * the GSP an array of 4K pages. Fortunately, since the buffer is 1745 1745 + * physically contiguous, it's simple math to calculate the addresses. 1746 1746 + * 1747 1747 + * The buffers must be a multiple of GSP_PAGE_SIZE. GSP-RM also currently 1748 1748 + * ignores the @kind field for LOGINIT, LOGINTR, and LOGRM, but expects the 1749 1749 + * buffers to be physically contiguous anyway. 1750 1750 + * 1751 1751 + * The memory allocated for the arguments must remain until the GSP sends the 1752 1752 + * init_done RPC. 1753 1753 + * 1754 1754 + * See _kgspInitLibosLoggingStructures (allocates memory for buffers) 1755 1755 + * See kgspSetupLibosInitArgs_IMPL (creates pLibosInitArgs[] array) 1756 1756 + */ 1752 1757 static int 1753 1758 r535_gsp_libos_init(struct nvkm_gsp *gsp) 1754 1759 { ··· 1888 1835 nvkm_gsp_mem_dtor(gsp, &rx3->mem[i]); 1889 1836 } 1890 1837 1838 1838 + /** 1839 1839 + * nvkm_gsp_radix3_sg - build a radix3 table from a S/G list 1840 1840 + * 1841 1841 + * The GSP uses a three-level page table, called radix3, to map the firmware. 1842 1842 + * Each 64-bit "pointer" in the table is either the bus address of an entry in 1843 1843 + * the next table (for levels 0 and 1) or the bus address of the next page in 1844 1844 + * the GSP firmware image itself. 1845 1845 + * 1846 1846 + * Level 0 contains a single entry in one page that points to the first page 1847 1847 + * of level 1. 1848 1848 + * 1849 1849 + * Level 1, since it's also only one page in size, contains up to 512 entries, 1850 1850 + * one for each page in Level 2. 1851 1851 + * 1852 1852 + * Level 2 can be up to 512 pages in size, and each of those entries points to 1853 1853 + * the next page of the firmware image. Since there can be up to 512*512 1854 1854 + * pages, that limits the size of the firmware to 512*512*GSP_PAGE_SIZE = 1GB. 1855 1855 + * 1856 1856 + * Internally, the GSP has its window into system memory, but the base 1857 1857 + * physical address of the aperture is not 0. In fact, it varies depending on 1858 1858 + * the GPU architecture. Since the GPU is a PCI device, this window is 1859 1859 + * accessed via DMA and is therefore bound by IOMMU translation. The end 1860 1860 + * result is that GSP-RM must translate the bus addresses in the table to GSP 1861 1861 + * physical addresses. All this should happen transparently. 1862 1862 + * 1863 1863 + * Returns 0 on success, or negative error code 1864 1864 + * 1865 1865 + * See kgspCreateRadix3_IMPL 1866 1866 + */ 1891 1867 static int 1892 1868 nvkm_gsp_radix3_sg(struct nvkm_device *device, struct sg_table *sgt, u64 size, 1893 1869 struct nvkm_gsp_radix3 *rx3)

+1 -1

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c

reviewed

··· 31 31 32 32 type |= 0x00000001; /* PAGE_ALL */ 33 33 if (atomic_read(&vmm->engref[NVKM_SUBDEV_BAR])) 34 34 - type |= 0x00000004; /* HUB_ONLY */ 34 34 + type |= 0x00000006; /* HUB_ONLY | ALL PDB (hack) */ 35 35 36 36 mutex_lock(&vmm->mmu->mutex); 37 37

+15 -2

drivers/gpu/drm/panfrost/panfrost_devfreq.c

reviewed

··· 29 29 static int panfrost_devfreq_target(struct device *dev, unsigned long *freq, 30 30 u32 flags) 31 31 { 32 32 + struct panfrost_device *ptdev = dev_get_drvdata(dev); 32 33 struct dev_pm_opp *opp; 34 34 + int err; 33 35 34 36 opp = devfreq_recommended_opp(dev, freq, flags); 35 37 if (IS_ERR(opp)) 36 38 return PTR_ERR(opp); 37 39 dev_pm_opp_put(opp); 38 40 39 39 - return dev_pm_opp_set_rate(dev, *freq); 41 41 + err = dev_pm_opp_set_rate(dev, *freq); 42 42 + if (!err) 43 43 + ptdev->pfdevfreq.current_frequency = *freq; 44 44 + 45 45 + return err; 40 46 } 41 47 42 48 static void panfrost_devfreq_reset(struct panfrost_devfreq *pfdevfreq) ··· 64 58 spin_lock_irqsave(&pfdevfreq->lock, irqflags); 65 59 66 60 panfrost_devfreq_update_utilization(pfdevfreq); 67 67 - pfdevfreq->current_frequency = status->current_frequency; 68 61 69 62 status->total_time = ktime_to_ns(ktime_add(pfdevfreq->busy_time, 70 63 pfdevfreq->idle_time)); ··· 168 163 return PTR_ERR(opp); 169 164 170 165 panfrost_devfreq_profile.initial_freq = cur_freq; 166 166 + 167 167 + /* 168 168 + * We could wait until panfrost_devfreq_target() to set this value, but 169 169 + * since the simple_ondemand governor works asynchronously, there's a 170 170 + * chance by the time someone opens the device's fdinfo file, current 171 171 + * frequency hasn't been updated yet, so let's just do an early set. 172 172 + */ 173 173 + pfdevfreq->current_frequency = cur_freq; 171 174 172 175 /* 173 176 * Set the recommend OPP this will enable and configure the regulator

+1 -1

drivers/gpu/drm/panfrost/panfrost_gem.c

reviewed

··· 200 200 struct panfrost_gem_object *bo = to_panfrost_bo(obj); 201 201 enum drm_gem_object_status res = 0; 202 202 203 203 - if (bo->base.pages) 203 203 + if (bo->base.base.import_attach || bo->base.pages) 204 204 res |= DRM_GEM_OBJECT_RESIDENT; 205 205 206 206 if (bo->base.madv == PANFROST_MADV_DONTNEED)

+2

include/drm/drm_atomic_helper.h

reviewed

··· 97 97 98 98 int drm_atomic_helper_prepare_planes(struct drm_device *dev, 99 99 struct drm_atomic_state *state); 100 100 + void drm_atomic_helper_unprepare_planes(struct drm_device *dev, 101 101 + struct drm_atomic_state *state); 100 102 101 103 #define DRM_PLANE_COMMIT_ACTIVE_ONLY BIT(0) 102 104 #define DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET BIT(1)