Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2022-06-24' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Fixes for this week, bit larger than normal, but I think the last
couple have been quieter, and it's only rc4.
There are a lot of small msm fixes, and a slightly larger set of vc4
fixes. The vc4 fixes clean up a lot of crashes around the rPI4
hardware differences from earlier ones, and problems in the page flip
and modeset code which assumed earlier hw, so I thought it would be
okay to keep them in.
Otherwise, it's a few amdgpu, i915, sun4i and a panel quirk.
amdgpu:
- Adjust GTT size logic
- eDP fix for RMB
- DCN 3.15 fix
- DP training fix
- Color encoding fix for DCN2+
sun4i:
- multiple suspend fixes
vc4:
- rework driver split for rpi4, fixes mulitple crashers.
panel:
- quirk for Aya Neo Next
i915:
- Revert low voltage SKU check removal to fix display issues
- Apply PLL DCO fraction workaround for ADL-S
- Don't show engine classes not present in client fdinfo
msm:
- Workaround for parade DSI bridge power sequencing
- Fix for multi-planar YUV format offsets
- Limiting WB modes to max sspp linewidth
- Fixing the supported rotations to add 180 back for IGT
- Fix to handle pm_runtime_get_sync() errors to avoid unclocked
access in the bind() path for dpu driver
- Fix the irq_free() without request issue which was a being hit
frequently in CI.
- Fix to add minimum ICC vote in the msm_mdss pm_resume path to
address bootup splats
- Fix to avoid dereferencing without checking in WB encoder
- Fix to avoid crash during suspend in DP driver by ensuring
interrupt mask bits are updated
- Remove unused code from dpu_encoder_virt_atomic_check()
- Fix to remove redundant init of dsc variable
- Fix to ensure mmap offset is initialized to avoid memory corruption
from unpin/evict
- Fix double runpm disable in probe-defer path
- VMA fenced-unpin fixes
- Fix for WB max-width
- Fix for rare dp resolution change issue"
* tag 'drm-fixes-2022-06-24' of git://anongit.freedesktop.org/drm/drm: (41 commits)
amd/display/dc: Fix COLOR_ENCODING and COLOR_RANGE doing nothing for DCN20+
drm/amd/display: Fix typo in override_lane_settings
drm/amd/display: Fix DC warning at driver load
drm/amd: Revert "drm/amd/display: keep eDP Vdd on when eDP stream is already enabled"
drm/amdgpu: Adjust logic around GTT size (v3)
drm/sun4i: Return if frontend is not present
drm/vc4: fix error code in vc4_check_tex_size()
drm/sun4i: Add DMA mask and segment size
drm/vc4: hdmi: Fixed possible integer overflow
drm/i915/display: Re-add check for low voltage sku for max dp source rate
drm/i915/fdinfo: Don't show engine classes not present
drm/i915: Implement w/a 22010492432 for adl-s
drm: panel-orientation-quirks: Add quirk for Aya Neo Next
drm/msm/dp: force link training for display resolution change
drm/msm/dpu: limit wb modes based on max_mixer_width
drm/msm/dp: check core_initialized before disable interrupts at dp_display_unbind()
drm/msm/mdp4: Fix refcount leak in mdp4_modeset_init_intf
drm/msm: Don't overwrite hw fence in hw_init
drm/msm: Drop update_fences()
drm/vc4: Warn if some v3d code is run on BCM2711
...
+672
-270
+14
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+14
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
···
1798
1798
DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1799
1799
(unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1800
1800
1801
-
/* Compute GTT size, either bsaed on 3/4th the size of RAM size
1801
+
/* Compute GTT size, either based on 1/2 the size of RAM size
1802
1802
* or whatever the user passed on module init */
1803
1803
if (amdgpu_gtt_size == -1) {
1804
1804
struct sysinfo si;
1805
1805
1806
1806
si_meminfo(&si);
1807
-
gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1808
-
adev->gmc.mc_vram_size),
1809
-
((uint64_t)si.totalram * si.mem_unit * 3/4));
1810
-
}
1811
-
else
1807
+
/* Certain GL unit tests for large textures can cause problems
1808
+
* with the OOM killer since there is no way to link this memory
1809
+
* to a process. This was originally mitigated (but not necessarily
1810
+
* eliminated) by limiting the GTT size. The problem is this limit
1811
+
* is often too low for many modern games so just make the limit 1/2
1812
+
* of system memory which aligns with TTM. The OOM accounting needs
1813
+
* to be addressed, but we shouldn't prevent common 3D applications
1814
+
* from being usable just to potentially mitigate that corner case.
1815
+
*/
1816
+
gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1817
+
(u64)si.totalram * si.mem_unit / 2);
1818
+
} else {
1812
1819
gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1820
+
}
1813
1821
1814
1822
/* Initialize GTT memory pool */
1815
1823
r = amdgpu_gtt_mgr_init(adev, gtt_size);
+1
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+1
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
···
550
550
if (!bw_params->clk_table.entries[i].dtbclk_mhz)
551
551
bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
552
552
}
553
-
ASSERT(bw_params->clk_table.entries[i].dcfclk_mhz);
553
+
ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
554
554
bw_params->vram_type = bios_info->memory_type;
555
555
bw_params->num_channels = bios_info->ma_channel_number;
556
556
if (!bw_params->num_channels)
+1
-1
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+1
-1
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
···
944
944
945
945
return;
946
946
947
-
for (lane = 1; lane < LANE_COUNT_DP_MAX; lane++) {
947
+
for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
948
948
if (lt_settings->voltage_swing)
949
949
lane_settings[lane].VOLTAGE_SWING = *lt_settings->voltage_swing;
950
950
if (lt_settings->pre_emphasis)
+2
-22
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+2
-22
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
···
1766
1766
break;
1767
1767
}
1768
1768
}
1769
-
1770
-
/*
1771
-
* TO-DO: So far the code logic below only addresses single eDP case.
1772
-
* For dual eDP case, there are a few things that need to be
1773
-
* implemented first:
1774
-
*
1775
-
* 1. Change the fastboot logic above, so eDP link[0 or 1]'s
1776
-
* stream[0 or 1] will all be checked.
1777
-
*
1778
-
* 2. Change keep_edp_vdd_on to an array, and maintain keep_edp_vdd_on
1779
-
* for each eDP.
1780
-
*
1781
-
* Once above 2 things are completed, we can then change the logic below
1782
-
* correspondingly, so dual eDP case will be fully covered.
1783
-
*/
1784
-
1785
-
// We are trying to enable eDP, don't power down VDD if eDP stream is existing
1786
-
if ((edp_stream_num == 1 && edp_streams[0] != NULL) || can_apply_edp_fast_boot) {
1769
+
// We are trying to enable eDP, don't power down VDD
1770
+
if (can_apply_edp_fast_boot)
1787
1771
keep_edp_vdd_on = true;
1788
-
DC_LOG_EVENT_LINK_TRAINING("Keep eDP Vdd on\n");
1789
-
} else {
1790
-
DC_LOG_EVENT_LINK_TRAINING("No eDP stream enabled, turn eDP Vdd off\n");
1791
-
}
1792
1772
}
1793
1773
1794
1774
// Check seamless boot support
+3
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+3
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
···
212
212
break;
213
213
}
214
214
215
+
/* Set default color space based on format if none is given. */
216
+
color_space = input_color_space ? input_color_space : color_space;
217
+
215
218
if (is_2bit == 1 && alpha_2bit_lut != NULL) {
216
219
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
217
220
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
+3
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
+3
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
···
153
153
break;
154
154
}
155
155
156
+
/* Set default color space based on format if none is given. */
157
+
color_space = input_color_space ? input_color_space : color_space;
158
+
156
159
if (is_2bit == 1 && alpha_2bit_lut != NULL) {
157
160
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
158
161
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
+3
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+3
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
···
294
294
break;
295
295
}
296
296
297
+
/* Set default color space based on format if none is given. */
298
+
color_space = input_color_space ? input_color_space : color_space;
299
+
297
300
if (is_2bit == 1 && alpha_2bit_lut != NULL) {
298
301
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
299
302
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
+6
drivers/gpu/drm/drm_panel_orientation_quirks.c
+6
drivers/gpu/drm/drm_panel_orientation_quirks.c
···
152
152
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "AYA NEO 2021"),
153
153
},
154
154
.driver_data = (void *)&lcd800x1280_rightside_up,
155
+
}, { /* AYA NEO NEXT */
156
+
.matches = {
157
+
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AYANEO"),
158
+
DMI_MATCH(DMI_BOARD_NAME, "NEXT"),
159
+
},
160
+
.driver_data = (void *)&lcd800x1280_rightside_up,
155
161
}, { /* Chuwi HiBook (CWI514) */
156
162
.matches = {
157
163
DMI_MATCH(DMI_BOARD_VENDOR, "Hampoo"),
+29
-3
drivers/gpu/drm/i915/display/intel_dp.c
+29
-3
drivers/gpu/drm/i915/display/intel_dp.c
···
388
388
return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
389
389
}
390
390
391
+
static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
392
+
{
393
+
u32 voltage;
394
+
395
+
voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
396
+
397
+
return voltage == VOLTAGE_INFO_0_85V;
398
+
}
399
+
391
400
static int icl_max_source_rate(struct intel_dp *intel_dp)
392
401
{
393
402
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
394
403
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
395
404
enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
396
405
397
-
if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
406
+
if (intel_phy_is_combo(dev_priv, phy) &&
407
+
(is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
398
408
return 540000;
399
409
400
410
return 810000;
···
412
402
413
403
static int ehl_max_source_rate(struct intel_dp *intel_dp)
414
404
{
415
-
if (intel_dp_is_edp(intel_dp))
405
+
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
406
+
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
407
+
enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
408
+
409
+
if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
410
+
return 540000;
411
+
412
+
return 810000;
413
+
}
414
+
415
+
static int dg1_max_source_rate(struct intel_dp *intel_dp)
416
+
{
417
+
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
418
+
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
419
+
enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
420
+
421
+
if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
416
422
return 540000;
417
423
418
424
return 810000;
···
471
445
max_rate = dg2_max_source_rate(intel_dp);
472
446
else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
473
447
IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
474
-
max_rate = 810000;
448
+
max_rate = dg1_max_source_rate(intel_dp);
475
449
else if (IS_JSL_EHL(dev_priv))
476
450
max_rate = ehl_max_source_rate(intel_dp);
477
451
else
+2
-2
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+2
-2
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
2396
2396
}
2397
2397
2398
2398
/*
2399
-
* Display WA #22010492432: ehl, tgl, adl-p
2399
+
* Display WA #22010492432: ehl, tgl, adl-s, adl-p
2400
2400
* Program half of the nominal DCO divider fraction value.
2401
2401
*/
2402
2402
static bool
···
2404
2404
{
2405
2405
return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
2406
2406
IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
2407
-
IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
2407
+
IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
2408
2408
i915->dpll.ref_clks.nssc == 38400;
2409
2409
}
2410
2410
+3
-2
drivers/gpu/drm/i915/i915_drm_client.c
+3
-2
drivers/gpu/drm/i915/i915_drm_client.c
···
116
116
total += busy_add(ctx, class);
117
117
rcu_read_unlock();
118
118
119
-
seq_printf(m, "drm-engine-%s:\t%llu ns\n",
120
-
uabi_class_names[class], total);
119
+
if (capacity)
120
+
seq_printf(m, "drm-engine-%s:\t%llu ns\n",
121
+
uabi_class_names[class], total);
121
122
122
123
if (capacity > 1)
123
124
seq_printf(m, "drm-engine-capacity-%s:\t%u\n",
+10
-4
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+10
-4
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
498
498
499
499
ring->cur = ring->start;
500
500
ring->next = ring->start;
501
-
502
-
/* reset completed fence seqno: */
503
-
ring->memptrs->fence = ring->fctx->completed_fence;
504
501
ring->memptrs->rptr = 0;
502
+
503
+
/* Detect and clean up an impossible fence, ie. if GPU managed
504
+
* to scribble something invalid, we don't want that to confuse
505
+
* us into mistakingly believing that submits have completed.
506
+
*/
507
+
if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) {
508
+
ring->memptrs->fence = ring->fctx->last_fence;
509
+
}
505
510
}
506
511
507
512
return 0;
···
1062
1057
for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1063
1058
release_firmware(adreno_gpu->fw[i]);
1064
1059
1065
-
pm_runtime_disable(&priv->gpu_pdev->dev);
1060
+
if (pm_runtime_enabled(&priv->gpu_pdev->dev))
1061
+
pm_runtime_disable(&priv->gpu_pdev->dev);
1066
1062
1067
1063
msm_gpu_cleanup(&adreno_gpu->base);
1068
1064
}
+8
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
+8
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
···
11
11
struct msm_drm_private *priv = dev->dev_private;
12
12
struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
13
13
14
-
return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_linewidth,
14
+
/*
15
+
* We should ideally be limiting the modes only to the maxlinewidth but
16
+
* on some chipsets this will allow even 4k modes to be added which will
17
+
* fail the per SSPP bandwidth checks. So, till we have dual-SSPP support
18
+
* and source split support added lets limit the modes based on max_mixer_width
19
+
* as 4K modes can then be supported.
20
+
*/
21
+
return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_mixer_width,
15
22
dev->mode_config.max_height);
16
23
}
17
24
+2
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+2
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
···
216
216
encoder = mdp4_lcdc_encoder_init(dev, panel_node);
217
217
if (IS_ERR(encoder)) {
218
218
DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
219
+
of_node_put(panel_node);
219
220
return PTR_ERR(encoder);
220
221
}
221
222
···
226
225
connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
227
226
if (IS_ERR(connector)) {
228
227
DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
228
+
of_node_put(panel_node);
229
229
return PTR_ERR(connector);
230
230
}
231
231
+25
-8
drivers/gpu/drm/msm/dp/dp_ctrl.c
+25
-8
drivers/gpu/drm/msm/dp/dp_ctrl.c
···
1534
1534
return ret;
1535
1535
}
1536
1536
1537
+
static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl);
1538
+
1537
1539
static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
1538
1540
{
1539
1541
int ret = 0;
···
1559
1557
1560
1558
ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
1561
1559
if (!ret)
1562
-
ret = dp_ctrl_on_stream(&ctrl->dp_ctrl);
1560
+
ret = dp_ctrl_on_stream_phy_test_report(&ctrl->dp_ctrl);
1563
1561
else
1564
1562
DRM_ERROR("failed to enable DP link controller\n");
1565
1563
···
1815
1813
return dp_ctrl_setup_main_link(ctrl, &training_step);
1816
1814
}
1817
1815
1818
-
int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
1816
+
static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl)
1817
+
{
1818
+
int ret;
1819
+
struct dp_ctrl_private *ctrl;
1820
+
1821
+
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1822
+
1823
+
ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1824
+
1825
+
ret = dp_ctrl_enable_stream_clocks(ctrl);
1826
+
if (ret) {
1827
+
DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1828
+
return ret;
1829
+
}
1830
+
1831
+
dp_ctrl_send_phy_test_pattern(ctrl);
1832
+
1833
+
return 0;
1834
+
}
1835
+
1836
+
int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
1819
1837
{
1820
1838
int ret = 0;
1821
1839
bool mainlink_ready = false;
···
1871
1849
goto end;
1872
1850
}
1873
1851
1874
-
if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1875
-
dp_ctrl_send_phy_test_pattern(ctrl);
1876
-
return 0;
1877
-
}
1878
-
1879
-
if (!dp_ctrl_channel_eq_ok(ctrl))
1852
+
if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl))
1880
1853
dp_ctrl_link_retrain(ctrl);
1881
1854
1882
1855
/* stop txing train pattern to end link training */
+1
-1
drivers/gpu/drm/msm/dp/dp_ctrl.h
+1
-1
drivers/gpu/drm/msm/dp/dp_ctrl.h
···
21
21
};
22
22
23
23
int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl);
24
-
int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl);
24
+
int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train);
25
25
int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl);
26
26
int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl);
27
27
int dp_ctrl_off(struct dp_ctrl *dp_ctrl);
+8
-8
drivers/gpu/drm/msm/dp/dp_display.c
+8
-8
drivers/gpu/drm/msm/dp/dp_display.c
···
309
309
struct msm_drm_private *priv = dev_get_drvdata(master);
310
310
311
311
/* disable all HPD interrupts */
312
-
dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, false);
312
+
if (dp->core_initialized)
313
+
dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, false);
313
314
314
315
kthread_stop(dp->ev_tsk);
315
316
···
873
872
return 0;
874
873
}
875
874
876
-
rc = dp_ctrl_on_stream(dp->ctrl);
875
+
rc = dp_ctrl_on_stream(dp->ctrl, data);
877
876
if (!rc)
878
877
dp_display->power_on = true;
879
878
···
1660
1659
int rc = 0;
1661
1660
struct dp_display_private *dp_display;
1662
1661
u32 state;
1662
+
bool force_link_train = false;
1663
1663
1664
1664
dp_display = container_of(dp, struct dp_display_private, dp_display);
1665
1665
if (!dp_display->dp_mode.drm_mode.clock) {
···
1695
1693
1696
1694
state = dp_display->hpd_state;
1697
1695
1698
-
if (state == ST_DISPLAY_OFF)
1696
+
if (state == ST_DISPLAY_OFF) {
1699
1697
dp_display_host_phy_init(dp_display);
1698
+
force_link_train = true;
1699
+
}
1700
1700
1701
-
dp_display_enable(dp_display, 0);
1701
+
dp_display_enable(dp_display, force_link_train);
1702
1702
1703
1703
rc = dp_display_post_enable(dp);
1704
1704
if (rc) {
···
1708
1704
dp_display_disable(dp_display, 0);
1709
1705
dp_display_unprepare(dp);
1710
1706
}
1711
-
1712
-
/* manual kick off plug event to train link */
1713
-
if (state == ST_DISPLAY_OFF)
1714
-
dp_add_event(dp_display, EV_IRQ_HPD_INT, 0, 0);
1715
1707
1716
1708
/* completed connection */
1717
1709
dp_display->hpd_state = ST_CONNECTED;
+1
-1
drivers/gpu/drm/msm/msm_drv.c
+1
-1
drivers/gpu/drm/msm/msm_drv.c
···
964
964
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
965
965
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
966
966
.gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
967
-
.gem_prime_mmap = drm_gem_prime_mmap,
967
+
.gem_prime_mmap = msm_gem_prime_mmap,
968
968
#ifdef CONFIG_DEBUG_FS
969
969
.debugfs_init = msm_debugfs_init,
970
970
#endif
+1
drivers/gpu/drm/msm/msm_drv.h
+1
drivers/gpu/drm/msm/msm_drv.h
···
246
246
void msm_gem_shrinker_init(struct drm_device *dev);
247
247
void msm_gem_shrinker_cleanup(struct drm_device *dev);
248
248
249
+
int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
249
250
struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
250
251
int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
251
252
void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
+5
-3
drivers/gpu/drm/msm/msm_fence.c
+5
-3
drivers/gpu/drm/msm/msm_fence.c
···
46
46
(int32_t)(*fctx->fenceptr - fence) >= 0;
47
47
}
48
48
49
-
/* called from workqueue */
49
+
/* called from irq handler and workqueue (in recover path) */
50
50
void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence)
51
51
{
52
-
spin_lock(&fctx->spinlock);
52
+
unsigned long flags;
53
+
54
+
spin_lock_irqsave(&fctx->spinlock, flags);
53
55
fctx->completed_fence = max(fence, fctx->completed_fence);
54
-
spin_unlock(&fctx->spinlock);
56
+
spin_unlock_irqrestore(&fctx->spinlock, flags);
55
57
}
56
58
57
59
struct msm_fence {
+3
-4
drivers/gpu/drm/msm/msm_gem.c
+3
-4
drivers/gpu/drm/msm/msm_gem.c
···
439
439
return ret;
440
440
}
441
441
442
-
void msm_gem_unpin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma)
442
+
void msm_gem_unpin_locked(struct drm_gem_object *obj)
443
443
{
444
444
struct msm_gem_object *msm_obj = to_msm_bo(obj);
445
445
446
446
GEM_WARN_ON(!msm_gem_is_locked(obj));
447
-
448
-
msm_gem_unpin_vma(vma);
449
447
450
448
msm_obj->pin_count--;
451
449
GEM_WARN_ON(msm_obj->pin_count < 0);
···
584
586
msm_gem_lock(obj);
585
587
vma = lookup_vma(obj, aspace);
586
588
if (!GEM_WARN_ON(!vma)) {
587
-
msm_gem_unpin_vma_locked(obj, vma);
589
+
msm_gem_unpin_vma(vma);
590
+
msm_gem_unpin_locked(obj);
588
591
}
589
592
msm_gem_unlock(obj);
590
593
}
+6
-5
drivers/gpu/drm/msm/msm_gem.h
+6
-5
drivers/gpu/drm/msm/msm_gem.h
···
145
145
146
146
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
147
147
int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma);
148
-
void msm_gem_unpin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma);
148
+
void msm_gem_unpin_locked(struct drm_gem_object *obj);
149
149
struct msm_gem_vma *msm_gem_get_vma_locked(struct drm_gem_object *obj,
150
150
struct msm_gem_address_space *aspace);
151
151
int msm_gem_get_iova(struct drm_gem_object *obj,
···
377
377
} *cmd; /* array of size nr_cmds */
378
378
struct {
379
379
/* make sure these don't conflict w/ MSM_SUBMIT_BO_x */
380
-
#define BO_VALID 0x8000 /* is current addr in cmdstream correct/valid? */
381
-
#define BO_LOCKED 0x4000 /* obj lock is held */
382
-
#define BO_ACTIVE 0x2000 /* active refcnt is held */
383
-
#define BO_PINNED 0x1000 /* obj is pinned and on active list */
380
+
#define BO_VALID 0x8000 /* is current addr in cmdstream correct/valid? */
381
+
#define BO_LOCKED 0x4000 /* obj lock is held */
382
+
#define BO_ACTIVE 0x2000 /* active refcnt is held */
383
+
#define BO_OBJ_PINNED 0x1000 /* obj (pages) is pinned and on active list */
384
+
#define BO_VMA_PINNED 0x0800 /* vma (virtual address) is pinned */
384
385
uint32_t flags;
385
386
union {
386
387
struct msm_gem_object *obj;
+15
drivers/gpu/drm/msm/msm_gem_prime.c
+15
drivers/gpu/drm/msm/msm_gem_prime.c
···
11
11
#include "msm_drv.h"
12
12
#include "msm_gem.h"
13
13
14
+
int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
15
+
{
16
+
int ret;
17
+
18
+
/* Ensure the mmap offset is initialized. We lazily initialize it,
19
+
* so if it has not been first mmap'd directly as a GEM object, the
20
+
* mmap offset will not be already initialized.
21
+
*/
22
+
ret = drm_gem_create_mmap_offset(obj);
23
+
if (ret)
24
+
return ret;
25
+
26
+
return drm_gem_prime_mmap(obj, vma);
27
+
}
28
+
14
29
struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj)
15
30
{
16
31
struct msm_gem_object *msm_obj = to_msm_bo(obj);
+12
-6
drivers/gpu/drm/msm/msm_gem_submit.c
+12
-6
drivers/gpu/drm/msm/msm_gem_submit.c
···
232
232
*/
233
233
submit->bos[i].flags &= ~cleanup_flags;
234
234
235
-
if (flags & BO_PINNED)
236
-
msm_gem_unpin_vma_locked(obj, submit->bos[i].vma);
235
+
if (flags & BO_VMA_PINNED)
236
+
msm_gem_unpin_vma(submit->bos[i].vma);
237
+
238
+
if (flags & BO_OBJ_PINNED)
239
+
msm_gem_unpin_locked(obj);
237
240
238
241
if (flags & BO_ACTIVE)
239
242
msm_gem_active_put(obj);
···
247
244
248
245
static void submit_unlock_unpin_bo(struct msm_gem_submit *submit, int i)
249
246
{
250
-
submit_cleanup_bo(submit, i, BO_PINNED | BO_ACTIVE | BO_LOCKED);
247
+
unsigned cleanup_flags = BO_VMA_PINNED | BO_OBJ_PINNED |
248
+
BO_ACTIVE | BO_LOCKED;
249
+
submit_cleanup_bo(submit, i, cleanup_flags);
251
250
252
251
if (!(submit->bos[i].flags & BO_VALID))
253
252
submit->bos[i].iova = 0;
···
380
375
if (ret)
381
376
break;
382
377
383
-
submit->bos[i].flags |= BO_PINNED;
378
+
submit->bos[i].flags |= BO_OBJ_PINNED | BO_VMA_PINNED;
384
379
submit->bos[i].vma = vma;
385
380
386
381
if (vma->iova == submit->bos[i].iova) {
···
516
511
unsigned i;
517
512
518
513
if (error)
519
-
cleanup_flags |= BO_PINNED | BO_ACTIVE;
514
+
cleanup_flags |= BO_VMA_PINNED | BO_OBJ_PINNED | BO_ACTIVE;
520
515
521
516
for (i = 0; i < submit->nr_bos; i++) {
522
517
struct msm_gem_object *msm_obj = submit->bos[i].obj;
···
534
529
struct drm_gem_object *obj = &submit->bos[i].obj->base;
535
530
536
531
msm_gem_lock(obj);
537
-
submit_cleanup_bo(submit, i, BO_PINNED | BO_ACTIVE);
532
+
/* Note, VMA already fence-unpinned before submit: */
533
+
submit_cleanup_bo(submit, i, BO_OBJ_PINNED | BO_ACTIVE);
538
534
msm_gem_unlock(obj);
539
535
drm_gem_object_put(obj);
540
536
}
+2
-4
drivers/gpu/drm/msm/msm_gem_vma.c
+2
-4
drivers/gpu/drm/msm/msm_gem_vma.c
···
62
62
unsigned size = vma->node.size;
63
63
64
64
/* Print a message if we try to purge a vma in use */
65
-
if (GEM_WARN_ON(msm_gem_vma_inuse(vma)))
66
-
return;
65
+
GEM_WARN_ON(msm_gem_vma_inuse(vma));
67
66
68
67
/* Don't do anything if the memory isn't mapped */
69
68
if (!vma->mapped)
···
127
128
void msm_gem_close_vma(struct msm_gem_address_space *aspace,
128
129
struct msm_gem_vma *vma)
129
130
{
130
-
if (GEM_WARN_ON(msm_gem_vma_inuse(vma) || vma->mapped))
131
-
return;
131
+
GEM_WARN_ON(msm_gem_vma_inuse(vma) || vma->mapped);
132
132
133
133
spin_lock(&aspace->lock);
134
134
if (vma->iova)
+5
-22
drivers/gpu/drm/msm/msm_gpu.c
+5
-22
drivers/gpu/drm/msm/msm_gpu.c
···
164
164
return ret;
165
165
}
166
166
167
-
static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
168
-
uint32_t fence)
169
-
{
170
-
struct msm_gem_submit *submit;
171
-
unsigned long flags;
172
-
173
-
spin_lock_irqsave(&ring->submit_lock, flags);
174
-
list_for_each_entry(submit, &ring->submits, node) {
175
-
if (fence_after(submit->seqno, fence))
176
-
break;
177
-
178
-
msm_update_fence(submit->ring->fctx,
179
-
submit->hw_fence->seqno);
180
-
dma_fence_signal(submit->hw_fence);
181
-
}
182
-
spin_unlock_irqrestore(&ring->submit_lock, flags);
183
-
}
184
-
185
167
#ifdef CONFIG_DEV_COREDUMP
186
168
static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
187
169
size_t count, void *data, size_t datalen)
···
418
436
* one more to clear the faulting submit
419
437
*/
420
438
if (ring == cur_ring)
421
-
fence++;
439
+
ring->memptrs->fence = ++fence;
422
440
423
-
update_fences(gpu, ring, fence);
441
+
msm_update_fence(ring->fctx, fence);
424
442
}
425
443
426
444
if (msm_gpu_active(gpu)) {
···
654
672
msm_submit_retire(submit);
655
673
656
674
pm_runtime_mark_last_busy(&gpu->pdev->dev);
657
-
pm_runtime_put_autosuspend(&gpu->pdev->dev);
658
675
659
676
spin_lock_irqsave(&ring->submit_lock, flags);
660
677
list_del(&submit->node);
···
666
685
if (!gpu->active_submits)
667
686
msm_devfreq_idle(gpu);
668
687
mutex_unlock(&gpu->active_lock);
688
+
689
+
pm_runtime_put_autosuspend(&gpu->pdev->dev);
669
690
670
691
msm_gem_submit_put(submit);
671
692
}
···
718
735
int i;
719
736
720
737
for (i = 0; i < gpu->nr_rings; i++)
721
-
update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
738
+
msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
722
739
723
740
kthread_queue_work(gpu->worker, &gpu->retire_work);
724
741
update_sw_cntrs(gpu);
+1
-1
drivers/gpu/drm/msm/msm_iommu.c
+1
-1
drivers/gpu/drm/msm/msm_iommu.c
+1
-1
drivers/gpu/drm/msm/msm_ringbuffer.c
+1
-1
drivers/gpu/drm/msm/msm_ringbuffer.c
+11
-1
drivers/gpu/drm/sun4i/sun4i_drv.c
+11
-1
drivers/gpu/drm/sun4i/sun4i_drv.c
···
7
7
*/
8
8
9
9
#include <linux/component.h>
10
+
#include <linux/dma-mapping.h>
10
11
#include <linux/kfifo.h>
11
12
#include <linux/module.h>
12
13
#include <linux/of_graph.h>
···
74
73
goto free_drm;
75
74
}
76
75
77
-
dev_set_drvdata(dev, drm);
78
76
drm->dev_private = drv;
79
77
INIT_LIST_HEAD(&drv->frontend_list);
80
78
INIT_LIST_HEAD(&drv->engine_list);
···
114
114
115
115
drm_fbdev_generic_setup(drm, 32);
116
116
117
+
dev_set_drvdata(dev, drm);
118
+
117
119
return 0;
118
120
119
121
finish_poll:
···
132
130
{
133
131
struct drm_device *drm = dev_get_drvdata(dev);
134
132
133
+
dev_set_drvdata(dev, NULL);
135
134
drm_dev_unregister(drm);
136
135
drm_kms_helper_poll_fini(drm);
137
136
drm_atomic_helper_shutdown(drm);
···
369
366
int i, ret, count = 0;
370
367
371
368
INIT_KFIFO(list.fifo);
369
+
370
+
/*
371
+
* DE2 and DE3 cores actually supports 40-bit addresses, but
372
+
* driver does not.
373
+
*/
374
+
dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
375
+
dma_set_max_seg_size(&pdev->dev, UINT_MAX);
372
376
373
377
for (i = 0;; i++) {
374
378
struct device_node *pipeline = of_parse_phandle(np,
+1
-1
drivers/gpu/drm/sun4i/sun4i_layer.c
+1
-1
drivers/gpu/drm/sun4i/sun4i_layer.c
···
117
117
struct sun4i_layer *layer = plane_to_sun4i_layer(plane);
118
118
119
119
if (IS_ERR_OR_NULL(layer->backend->frontend))
120
-
sun4i_backend_format_is_supported(format, modifier);
120
+
return sun4i_backend_format_is_supported(format, modifier);
121
121
122
122
return sun4i_backend_format_is_supported(format, modifier) ||
123
123
sun4i_frontend_format_is_supported(format, modifier);
+4
-50
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+4
-50
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
···
93
93
return crtcs;
94
94
}
95
95
96
-
static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev,
97
-
struct platform_device **pdev_out)
98
-
{
99
-
struct platform_device *pdev;
100
-
struct device_node *remote;
101
-
102
-
remote = of_graph_get_remote_node(dev->of_node, 1, -1);
103
-
if (!remote)
104
-
return -ENODEV;
105
-
106
-
if (!of_device_is_compatible(remote, "hdmi-connector")) {
107
-
of_node_put(remote);
108
-
return -ENODEV;
109
-
}
110
-
111
-
pdev = of_find_device_by_node(remote);
112
-
of_node_put(remote);
113
-
if (!pdev)
114
-
return -ENODEV;
115
-
116
-
*pdev_out = pdev;
117
-
return 0;
118
-
}
119
-
120
96
static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
121
97
void *data)
122
98
{
123
-
struct platform_device *pdev = to_platform_device(dev), *connector_pdev;
99
+
struct platform_device *pdev = to_platform_device(dev);
124
100
struct dw_hdmi_plat_data *plat_data;
125
101
struct drm_device *drm = data;
126
102
struct device_node *phy_node;
···
143
167
return dev_err_probe(dev, PTR_ERR(hdmi->regulator),
144
168
"Couldn't get regulator\n");
145
169
146
-
ret = sun8i_dw_hdmi_find_connector_pdev(dev, &connector_pdev);
147
-
if (!ret) {
148
-
hdmi->ddc_en = gpiod_get_optional(&connector_pdev->dev,
149
-
"ddc-en", GPIOD_OUT_HIGH);
150
-
platform_device_put(connector_pdev);
151
-
152
-
if (IS_ERR(hdmi->ddc_en)) {
153
-
dev_err(dev, "Couldn't get ddc-en gpio\n");
154
-
return PTR_ERR(hdmi->ddc_en);
155
-
}
156
-
}
157
-
158
170
ret = regulator_enable(hdmi->regulator);
159
171
if (ret) {
160
172
dev_err(dev, "Failed to enable regulator\n");
161
-
goto err_unref_ddc_en;
173
+
return ret;
162
174
}
163
-
164
-
gpiod_set_value(hdmi->ddc_en, 1);
165
175
166
176
ret = reset_control_deassert(hdmi->rst_ctrl);
167
177
if (ret) {
168
178
dev_err(dev, "Could not deassert ctrl reset control\n");
169
-
goto err_disable_ddc_en;
179
+
goto err_disable_regulator;
170
180
}
171
181
172
182
ret = clk_prepare_enable(hdmi->clk_tmds);
···
207
245
clk_disable_unprepare(hdmi->clk_tmds);
208
246
err_assert_ctrl_reset:
209
247
reset_control_assert(hdmi->rst_ctrl);
210
-
err_disable_ddc_en:
211
-
gpiod_set_value(hdmi->ddc_en, 0);
248
+
err_disable_regulator:
212
249
regulator_disable(hdmi->regulator);
213
-
err_unref_ddc_en:
214
-
if (hdmi->ddc_en)
215
-
gpiod_put(hdmi->ddc_en);
216
250
217
251
return ret;
218
252
}
···
222
264
sun8i_hdmi_phy_deinit(hdmi->phy);
223
265
clk_disable_unprepare(hdmi->clk_tmds);
224
266
reset_control_assert(hdmi->rst_ctrl);
225
-
gpiod_set_value(hdmi->ddc_en, 0);
226
267
regulator_disable(hdmi->regulator);
227
-
228
-
if (hdmi->ddc_en)
229
-
gpiod_put(hdmi->ddc_en);
230
268
}
231
269
232
270
static const struct component_ops sun8i_dw_hdmi_ops = {
-2
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-2
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
···
9
9
#include <drm/bridge/dw_hdmi.h>
10
10
#include <drm/drm_encoder.h>
11
11
#include <linux/clk.h>
12
-
#include <linux/gpio/consumer.h>
13
12
#include <linux/regmap.h>
14
13
#include <linux/regulator/consumer.h>
15
14
#include <linux/reset.h>
···
192
193
struct regulator *regulator;
193
194
const struct sun8i_dw_hdmi_quirks *quirks;
194
195
struct reset_control *rst_ctrl;
195
-
struct gpio_desc *ddc_en;
196
196
};
197
197
198
198
extern struct platform_driver sun8i_hdmi_phy_driver;
+54
-8
drivers/gpu/drm/vc4/vc4_bo.c
+54
-8
drivers/gpu/drm/vc4/vc4_bo.c
···
248
248
{
249
249
struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
250
250
251
+
if (WARN_ON_ONCE(vc4->is_vc5))
252
+
return;
253
+
251
254
mutex_lock(&vc4->purgeable.lock);
252
255
list_add_tail(&bo->size_head, &vc4->purgeable.list);
253
256
vc4->purgeable.num++;
···
261
258
static void vc4_bo_remove_from_purgeable_pool_locked(struct vc4_bo *bo)
262
259
{
263
260
struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
261
+
262
+
if (WARN_ON_ONCE(vc4->is_vc5))
263
+
return;
264
264
265
265
/* list_del_init() is used here because the caller might release
266
266
* the purgeable lock in order to acquire the madv one and update the
···
393
387
struct vc4_dev *vc4 = to_vc4_dev(dev);
394
388
struct vc4_bo *bo;
395
389
390
+
if (WARN_ON_ONCE(vc4->is_vc5))
391
+
return ERR_PTR(-ENODEV);
392
+
396
393
bo = kzalloc(sizeof(*bo), GFP_KERNEL);
397
394
if (!bo)
398
395
return ERR_PTR(-ENOMEM);
···
421
412
struct vc4_dev *vc4 = to_vc4_dev(dev);
422
413
struct drm_gem_cma_object *cma_obj;
423
414
struct vc4_bo *bo;
415
+
416
+
if (WARN_ON_ONCE(vc4->is_vc5))
417
+
return ERR_PTR(-ENODEV);
424
418
425
419
if (size == 0)
426
420
return ERR_PTR(-EINVAL);
···
483
471
return bo;
484
472
}
485
473
486
-
int vc4_dumb_create(struct drm_file *file_priv,
487
-
struct drm_device *dev,
488
-
struct drm_mode_create_dumb *args)
474
+
int vc4_bo_dumb_create(struct drm_file *file_priv,
475
+
struct drm_device *dev,
476
+
struct drm_mode_create_dumb *args)
489
477
{
490
-
int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
478
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
491
479
struct vc4_bo *bo = NULL;
492
480
int ret;
493
481
494
-
if (args->pitch < min_pitch)
495
-
args->pitch = min_pitch;
482
+
if (WARN_ON_ONCE(vc4->is_vc5))
483
+
return -ENODEV;
496
484
497
-
if (args->size < args->pitch * args->height)
498
-
args->size = args->pitch * args->height;
485
+
ret = vc4_dumb_fixup_args(args);
486
+
if (ret)
487
+
return ret;
499
488
500
489
bo = vc4_bo_create(dev, args->size, false, VC4_BO_TYPE_DUMB);
501
490
if (IS_ERR(bo))
···
614
601
615
602
int vc4_bo_inc_usecnt(struct vc4_bo *bo)
616
603
{
604
+
struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
617
605
int ret;
606
+
607
+
if (WARN_ON_ONCE(vc4->is_vc5))
608
+
return -ENODEV;
618
609
619
610
/* Fast path: if the BO is already retained by someone, no need to
620
611
* check the madv status.
···
654
637
655
638
void vc4_bo_dec_usecnt(struct vc4_bo *bo)
656
639
{
640
+
struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
641
+
642
+
if (WARN_ON_ONCE(vc4->is_vc5))
643
+
return;
644
+
657
645
/* Fast path: if the BO is still retained by someone, no need to test
658
646
* the madv value.
659
647
*/
···
778
756
struct vc4_bo *bo = NULL;
779
757
int ret;
780
758
759
+
if (WARN_ON_ONCE(vc4->is_vc5))
760
+
return -ENODEV;
761
+
781
762
ret = vc4_grab_bin_bo(vc4, vc4file);
782
763
if (ret)
783
764
return ret;
···
804
779
int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
805
780
struct drm_file *file_priv)
806
781
{
782
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
807
783
struct drm_vc4_mmap_bo *args = data;
808
784
struct drm_gem_object *gem_obj;
785
+
786
+
if (WARN_ON_ONCE(vc4->is_vc5))
787
+
return -ENODEV;
809
788
810
789
gem_obj = drm_gem_object_lookup(file_priv, args->handle);
811
790
if (!gem_obj) {
···
833
804
struct vc4_dev *vc4 = to_vc4_dev(dev);
834
805
struct vc4_bo *bo = NULL;
835
806
int ret;
807
+
808
+
if (WARN_ON_ONCE(vc4->is_vc5))
809
+
return -ENODEV;
836
810
837
811
if (args->size == 0)
838
812
return -EINVAL;
···
907
875
int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
908
876
struct drm_file *file_priv)
909
877
{
878
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
910
879
struct drm_vc4_set_tiling *args = data;
911
880
struct drm_gem_object *gem_obj;
912
881
struct vc4_bo *bo;
913
882
bool t_format;
883
+
884
+
if (WARN_ON_ONCE(vc4->is_vc5))
885
+
return -ENODEV;
914
886
915
887
if (args->flags != 0)
916
888
return -EINVAL;
···
954
918
int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
955
919
struct drm_file *file_priv)
956
920
{
921
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
957
922
struct drm_vc4_get_tiling *args = data;
958
923
struct drm_gem_object *gem_obj;
959
924
struct vc4_bo *bo;
925
+
926
+
if (WARN_ON_ONCE(vc4->is_vc5))
927
+
return -ENODEV;
960
928
961
929
if (args->flags != 0 || args->modifier != 0)
962
930
return -EINVAL;
···
987
947
{
988
948
struct vc4_dev *vc4 = to_vc4_dev(dev);
989
949
int i;
950
+
951
+
if (WARN_ON_ONCE(vc4->is_vc5))
952
+
return -ENODEV;
990
953
991
954
/* Create the initial set of BO labels that the kernel will
992
955
* use. This lets us avoid a bunch of string reallocation in
···
1049
1006
char *name;
1050
1007
struct drm_gem_object *gem_obj;
1051
1008
int ret = 0, label;
1009
+
1010
+
if (WARN_ON_ONCE(vc4->is_vc5))
1011
+
return -ENODEV;
1052
1012
1053
1013
if (!args->len)
1054
1014
return -EINVAL;
+147
-53
drivers/gpu/drm/vc4/vc4_crtc.c
+147
-53
drivers/gpu/drm/vc4/vc4_crtc.c
···
256
256
* Removing 1 from the FIFO full level however
257
257
* seems to completely remove that issue.
258
258
*/
259
-
if (!vc4->hvs->hvs5)
259
+
if (!vc4->is_vc5)
260
260
return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
261
261
262
262
return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
···
389
389
if (is_dsi)
390
390
CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
391
391
392
-
if (vc4->hvs->hvs5)
392
+
if (vc4->is_vc5)
393
393
CRTC_WRITE(PV_MUX_CFG,
394
394
VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
395
395
PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
···
775
775
struct drm_framebuffer *old_fb;
776
776
struct drm_pending_vblank_event *event;
777
777
778
-
struct vc4_seqno_cb cb;
778
+
union {
779
+
struct dma_fence_cb fence;
780
+
struct vc4_seqno_cb seqno;
781
+
} cb;
779
782
};
780
783
781
784
/* Called when the V3D execution for the BO being flipped to is done, so that
782
785
* we can actually update the plane's address to point to it.
783
786
*/
784
787
static void
785
-
vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
788
+
vc4_async_page_flip_complete(struct vc4_async_flip_state *flip_state)
786
789
{
787
-
struct vc4_async_flip_state *flip_state =
788
-
container_of(cb, struct vc4_async_flip_state, cb);
789
790
struct drm_crtc *crtc = flip_state->crtc;
790
791
struct drm_device *dev = crtc->dev;
791
792
struct drm_plane *plane = crtc->primary;
···
803
802
drm_crtc_vblank_put(crtc);
804
803
drm_framebuffer_put(flip_state->fb);
805
804
806
-
/* Decrement the BO usecnt in order to keep the inc/dec calls balanced
807
-
* when the planes are updated through the async update path.
808
-
* FIXME: we should move to generic async-page-flip when it's
809
-
* available, so that we can get rid of this hand-made cleanup_fb()
810
-
* logic.
811
-
*/
812
-
if (flip_state->old_fb) {
813
-
struct drm_gem_cma_object *cma_bo;
814
-
struct vc4_bo *bo;
815
-
816
-
cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
817
-
bo = to_vc4_bo(&cma_bo->base);
818
-
vc4_bo_dec_usecnt(bo);
805
+
if (flip_state->old_fb)
819
806
drm_framebuffer_put(flip_state->old_fb);
820
-
}
821
807
822
808
kfree(flip_state);
823
809
}
824
810
825
-
/* Implements async (non-vblank-synced) page flips.
826
-
*
827
-
* The page flip ioctl needs to return immediately, so we grab the
828
-
* modeset semaphore on the pipe, and queue the address update for
829
-
* when V3D is done with the BO being flipped to.
830
-
*/
831
-
static int vc4_async_page_flip(struct drm_crtc *crtc,
832
-
struct drm_framebuffer *fb,
833
-
struct drm_pending_vblank_event *event,
834
-
uint32_t flags)
811
+
static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
835
812
{
836
-
struct drm_device *dev = crtc->dev;
837
-
struct drm_plane *plane = crtc->primary;
838
-
int ret = 0;
839
-
struct vc4_async_flip_state *flip_state;
840
-
struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
841
-
struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
813
+
struct vc4_async_flip_state *flip_state =
814
+
container_of(cb, struct vc4_async_flip_state, cb.seqno);
815
+
struct vc4_bo *bo = NULL;
842
816
843
-
/* Increment the BO usecnt here, so that we never end up with an
844
-
* unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
845
-
* plane is later updated through the non-async path.
846
-
* FIXME: we should move to generic async-page-flip when it's
847
-
* available, so that we can get rid of this hand-made prepare_fb()
848
-
* logic.
817
+
if (flip_state->old_fb) {
818
+
struct drm_gem_cma_object *cma_bo =
819
+
drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
820
+
bo = to_vc4_bo(&cma_bo->base);
821
+
}
822
+
823
+
vc4_async_page_flip_complete(flip_state);
824
+
825
+
/*
826
+
* Decrement the BO usecnt in order to keep the inc/dec
827
+
* calls balanced when the planes are updated through
828
+
* the async update path.
829
+
*
830
+
* FIXME: we should move to generic async-page-flip when
831
+
* it's available, so that we can get rid of this
832
+
* hand-made cleanup_fb() logic.
849
833
*/
850
-
ret = vc4_bo_inc_usecnt(bo);
834
+
if (bo)
835
+
vc4_bo_dec_usecnt(bo);
836
+
}
837
+
838
+
static void vc4_async_page_flip_fence_complete(struct dma_fence *fence,
839
+
struct dma_fence_cb *cb)
840
+
{
841
+
struct vc4_async_flip_state *flip_state =
842
+
container_of(cb, struct vc4_async_flip_state, cb.fence);
843
+
844
+
vc4_async_page_flip_complete(flip_state);
845
+
dma_fence_put(fence);
846
+
}
847
+
848
+
static int vc4_async_set_fence_cb(struct drm_device *dev,
849
+
struct vc4_async_flip_state *flip_state)
850
+
{
851
+
struct drm_framebuffer *fb = flip_state->fb;
852
+
struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
853
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
854
+
struct dma_fence *fence;
855
+
int ret;
856
+
857
+
if (!vc4->is_vc5) {
858
+
struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
859
+
860
+
return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
861
+
vc4_async_page_flip_seqno_complete);
862
+
}
863
+
864
+
ret = dma_resv_get_singleton(cma_bo->base.resv, DMA_RESV_USAGE_READ, &fence);
851
865
if (ret)
852
866
return ret;
853
867
854
-
flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
855
-
if (!flip_state) {
856
-
vc4_bo_dec_usecnt(bo);
857
-
return -ENOMEM;
868
+
/* If there's no fence, complete the page flip immediately */
869
+
if (!fence) {
870
+
vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
871
+
return 0;
858
872
}
873
+
874
+
/* If the fence has already been completed, complete the page flip */
875
+
if (dma_fence_add_callback(fence, &flip_state->cb.fence,
876
+
vc4_async_page_flip_fence_complete))
877
+
vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
878
+
879
+
return 0;
880
+
}
881
+
882
+
static int
883
+
vc4_async_page_flip_common(struct drm_crtc *crtc,
884
+
struct drm_framebuffer *fb,
885
+
struct drm_pending_vblank_event *event,
886
+
uint32_t flags)
887
+
{
888
+
struct drm_device *dev = crtc->dev;
889
+
struct drm_plane *plane = crtc->primary;
890
+
struct vc4_async_flip_state *flip_state;
891
+
892
+
flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
893
+
if (!flip_state)
894
+
return -ENOMEM;
859
895
860
896
drm_framebuffer_get(fb);
861
897
flip_state->fb = fb;
···
919
881
*/
920
882
drm_atomic_set_fb_for_plane(plane->state, fb);
921
883
922
-
vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
923
-
vc4_async_page_flip_complete);
884
+
vc4_async_set_fence_cb(dev, flip_state);
924
885
925
886
/* Driver takes ownership of state on successful async commit. */
926
887
return 0;
888
+
}
889
+
890
+
/* Implements async (non-vblank-synced) page flips.
891
+
*
892
+
* The page flip ioctl needs to return immediately, so we grab the
893
+
* modeset semaphore on the pipe, and queue the address update for
894
+
* when V3D is done with the BO being flipped to.
895
+
*/
896
+
static int vc4_async_page_flip(struct drm_crtc *crtc,
897
+
struct drm_framebuffer *fb,
898
+
struct drm_pending_vblank_event *event,
899
+
uint32_t flags)
900
+
{
901
+
struct drm_device *dev = crtc->dev;
902
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
903
+
struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
904
+
struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
905
+
int ret;
906
+
907
+
if (WARN_ON_ONCE(vc4->is_vc5))
908
+
return -ENODEV;
909
+
910
+
/*
911
+
* Increment the BO usecnt here, so that we never end up with an
912
+
* unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
913
+
* plane is later updated through the non-async path.
914
+
*
915
+
* FIXME: we should move to generic async-page-flip when
916
+
* it's available, so that we can get rid of this
917
+
* hand-made prepare_fb() logic.
918
+
*/
919
+
ret = vc4_bo_inc_usecnt(bo);
920
+
if (ret)
921
+
return ret;
922
+
923
+
ret = vc4_async_page_flip_common(crtc, fb, event, flags);
924
+
if (ret) {
925
+
vc4_bo_dec_usecnt(bo);
926
+
return ret;
927
+
}
928
+
929
+
return 0;
930
+
}
931
+
932
+
static int vc5_async_page_flip(struct drm_crtc *crtc,
933
+
struct drm_framebuffer *fb,
934
+
struct drm_pending_vblank_event *event,
935
+
uint32_t flags)
936
+
{
937
+
return vc4_async_page_flip_common(crtc, fb, event, flags);
927
938
}
928
939
929
940
int vc4_page_flip(struct drm_crtc *crtc,
···
981
894
uint32_t flags,
982
895
struct drm_modeset_acquire_ctx *ctx)
983
896
{
984
-
if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
985
-
return vc4_async_page_flip(crtc, fb, event, flags);
986
-
else
897
+
if (flags & DRM_MODE_PAGE_FLIP_ASYNC) {
898
+
struct drm_device *dev = crtc->dev;
899
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
900
+
901
+
if (vc4->is_vc5)
902
+
return vc5_async_page_flip(crtc, fb, event, flags);
903
+
else
904
+
return vc4_async_page_flip(crtc, fb, event, flags);
905
+
} else {
987
906
return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
907
+
}
988
908
}
989
909
990
910
struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
···
1243
1149
crtc_funcs, NULL);
1244
1150
drm_crtc_helper_add(crtc, crtc_helper_funcs);
1245
1151
1246
-
if (!vc4->hvs->hvs5) {
1152
+
if (!vc4->is_vc5) {
1247
1153
drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1248
1154
1249
1155
drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
+81
-16
drivers/gpu/drm/vc4/vc4_drv.c
+81
-16
drivers/gpu/drm/vc4/vc4_drv.c
···
63
63
return map;
64
64
}
65
65
66
+
int vc4_dumb_fixup_args(struct drm_mode_create_dumb *args)
67
+
{
68
+
int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
69
+
70
+
if (args->pitch < min_pitch)
71
+
args->pitch = min_pitch;
72
+
73
+
if (args->size < args->pitch * args->height)
74
+
args->size = args->pitch * args->height;
75
+
76
+
return 0;
77
+
}
78
+
79
+
static int vc5_dumb_create(struct drm_file *file_priv,
80
+
struct drm_device *dev,
81
+
struct drm_mode_create_dumb *args)
82
+
{
83
+
int ret;
84
+
85
+
ret = vc4_dumb_fixup_args(args);
86
+
if (ret)
87
+
return ret;
88
+
89
+
return drm_gem_cma_dumb_create_internal(file_priv, dev, args);
90
+
}
91
+
66
92
static int vc4_get_param_ioctl(struct drm_device *dev, void *data,
67
93
struct drm_file *file_priv)
68
94
{
···
98
72
99
73
if (args->pad != 0)
100
74
return -EINVAL;
75
+
76
+
if (WARN_ON_ONCE(vc4->is_vc5))
77
+
return -ENODEV;
101
78
102
79
if (!vc4->v3d)
103
80
return -ENODEV;
···
145
116
146
117
static int vc4_open(struct drm_device *dev, struct drm_file *file)
147
118
{
119
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
148
120
struct vc4_file *vc4file;
121
+
122
+
if (WARN_ON_ONCE(vc4->is_vc5))
123
+
return -ENODEV;
149
124
150
125
vc4file = kzalloc(sizeof(*vc4file), GFP_KERNEL);
151
126
if (!vc4file)
152
127
return -ENOMEM;
128
+
vc4file->dev = vc4;
153
129
154
130
vc4_perfmon_open_file(vc4file);
155
131
file->driver_priv = vc4file;
···
165
131
{
166
132
struct vc4_dev *vc4 = to_vc4_dev(dev);
167
133
struct vc4_file *vc4file = file->driver_priv;
134
+
135
+
if (WARN_ON_ONCE(vc4->is_vc5))
136
+
return;
168
137
169
138
if (vc4file->bin_bo_used)
170
139
vc4_v3d_bin_bo_put(vc4);
···
197
160
DRM_IOCTL_DEF_DRV(VC4_PERFMON_GET_VALUES, vc4_perfmon_get_values_ioctl, DRM_RENDER_ALLOW),
198
161
};
199
162
200
-
static struct drm_driver vc4_drm_driver = {
163
+
static const struct drm_driver vc4_drm_driver = {
201
164
.driver_features = (DRIVER_MODESET |
202
165
DRIVER_ATOMIC |
203
166
DRIVER_GEM |
···
212
175
213
176
.gem_create_object = vc4_create_object,
214
177
215
-
DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(vc4_dumb_create),
178
+
DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(vc4_bo_dumb_create),
216
179
217
180
.ioctls = vc4_drm_ioctls,
218
181
.num_ioctls = ARRAY_SIZE(vc4_drm_ioctls),
182
+
.fops = &vc4_drm_fops,
183
+
184
+
.name = DRIVER_NAME,
185
+
.desc = DRIVER_DESC,
186
+
.date = DRIVER_DATE,
187
+
.major = DRIVER_MAJOR,
188
+
.minor = DRIVER_MINOR,
189
+
.patchlevel = DRIVER_PATCHLEVEL,
190
+
};
191
+
192
+
static const struct drm_driver vc5_drm_driver = {
193
+
.driver_features = (DRIVER_MODESET |
194
+
DRIVER_ATOMIC |
195
+
DRIVER_GEM),
196
+
197
+
#if defined(CONFIG_DEBUG_FS)
198
+
.debugfs_init = vc4_debugfs_init,
199
+
#endif
200
+
201
+
DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(vc5_dumb_create),
202
+
219
203
.fops = &vc4_drm_fops,
220
204
221
205
.name = DRIVER_NAME,
···
270
212
static int vc4_drm_bind(struct device *dev)
271
213
{
272
214
struct platform_device *pdev = to_platform_device(dev);
215
+
const struct drm_driver *driver;
273
216
struct rpi_firmware *firmware = NULL;
274
217
struct drm_device *drm;
275
218
struct vc4_dev *vc4;
276
219
struct device_node *node;
277
220
struct drm_crtc *crtc;
221
+
bool is_vc5;
278
222
int ret = 0;
279
223
280
224
dev->coherent_dma_mask = DMA_BIT_MASK(32);
281
225
282
-
/* If VC4 V3D is missing, don't advertise render nodes. */
283
-
node = of_find_matching_node_and_match(NULL, vc4_v3d_dt_match, NULL);
284
-
if (!node || !of_device_is_available(node))
285
-
vc4_drm_driver.driver_features &= ~DRIVER_RENDER;
286
-
of_node_put(node);
226
+
is_vc5 = of_device_is_compatible(dev->of_node, "brcm,bcm2711-vc5");
227
+
if (is_vc5)
228
+
driver = &vc5_drm_driver;
229
+
else
230
+
driver = &vc4_drm_driver;
287
231
288
-
vc4 = devm_drm_dev_alloc(dev, &vc4_drm_driver, struct vc4_dev, base);
232
+
vc4 = devm_drm_dev_alloc(dev, driver, struct vc4_dev, base);
289
233
if (IS_ERR(vc4))
290
234
return PTR_ERR(vc4);
235
+
vc4->is_vc5 = is_vc5;
291
236
292
237
drm = &vc4->base;
293
238
platform_set_drvdata(pdev, drm);
294
239
INIT_LIST_HEAD(&vc4->debugfs_list);
295
240
296
-
mutex_init(&vc4->bin_bo_lock);
241
+
if (!is_vc5) {
242
+
mutex_init(&vc4->bin_bo_lock);
297
243
298
-
ret = vc4_bo_cache_init(drm);
299
-
if (ret)
300
-
return ret;
244
+
ret = vc4_bo_cache_init(drm);
245
+
if (ret)
246
+
return ret;
247
+
}
301
248
302
249
ret = drmm_mode_config_init(drm);
303
250
if (ret)
304
251
return ret;
305
252
306
-
ret = vc4_gem_init(drm);
307
-
if (ret)
308
-
return ret;
253
+
if (!is_vc5) {
254
+
ret = vc4_gem_init(drm);
255
+
if (ret)
256
+
return ret;
257
+
}
309
258
310
259
node = of_find_compatible_node(NULL, NULL, "raspberrypi,bcm2835-firmware");
311
260
if (node) {
···
323
258
return -EPROBE_DEFER;
324
259
}
325
260
326
-
ret = drm_aperture_remove_framebuffers(false, &vc4_drm_driver);
261
+
ret = drm_aperture_remove_framebuffers(false, driver);
327
262
if (ret)
328
263
return ret;
329
264
+13
-6
drivers/gpu/drm/vc4/vc4_drv.h
+13
-6
drivers/gpu/drm/vc4/vc4_drv.h
···
48
48
* done. This way, only events related to a specific job will be counted.
49
49
*/
50
50
struct vc4_perfmon {
51
+
struct vc4_dev *dev;
52
+
51
53
/* Tracks the number of users of the perfmon, when this counter reaches
52
54
* zero the perfmon is destroyed.
53
55
*/
···
75
73
76
74
struct vc4_dev {
77
75
struct drm_device base;
76
+
77
+
bool is_vc5;
78
78
79
79
unsigned int irq;
80
80
···
320
316
};
321
317
322
318
struct vc4_hvs {
319
+
struct vc4_dev *vc4;
323
320
struct platform_device *pdev;
324
321
void __iomem *regs;
325
322
u32 __iomem *dlist;
···
338
333
struct drm_mm_node mitchell_netravali_filter;
339
334
340
335
struct debugfs_regset32 regset;
341
-
342
-
/* HVS version 5 flag, therefore requires updated dlist structures */
343
-
bool hvs5;
344
336
};
345
337
346
338
struct vc4_plane {
···
582
580
#define VC4_REG32(reg) { .name = #reg, .offset = reg }
583
581
584
582
struct vc4_exec_info {
583
+
struct vc4_dev *dev;
584
+
585
585
/* Sequence number for this bin/render job. */
586
586
uint64_t seqno;
587
587
···
705
701
* released when the DRM file is closed should be placed here.
706
702
*/
707
703
struct vc4_file {
704
+
struct vc4_dev *dev;
705
+
708
706
struct {
709
707
struct idr idr;
710
708
struct mutex lock;
···
820
814
struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
821
815
struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
822
816
bool from_cache, enum vc4_kernel_bo_type type);
823
-
int vc4_dumb_create(struct drm_file *file_priv,
824
-
struct drm_device *dev,
825
-
struct drm_mode_create_dumb *args);
817
+
int vc4_bo_dumb_create(struct drm_file *file_priv,
818
+
struct drm_device *dev,
819
+
struct drm_mode_create_dumb *args);
826
820
int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
827
821
struct drm_file *file_priv);
828
822
int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
···
891
885
892
886
/* vc4_drv.c */
893
887
void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
888
+
int vc4_dumb_fixup_args(struct drm_mode_create_dumb *args);
894
889
895
890
/* vc4_dpi.c */
896
891
extern struct platform_driver vc4_dpi_driver;
+40
drivers/gpu/drm/vc4/vc4_gem.c
+40
drivers/gpu/drm/vc4/vc4_gem.c
···
76
76
u32 i;
77
77
int ret = 0;
78
78
79
+
if (WARN_ON_ONCE(vc4->is_vc5))
80
+
return -ENODEV;
81
+
79
82
if (!vc4->v3d) {
80
83
DRM_DEBUG("VC4_GET_HANG_STATE with no VC4 V3D probed\n");
81
84
return -ENODEV;
···
389
386
unsigned long timeout_expire;
390
387
DEFINE_WAIT(wait);
391
388
389
+
if (WARN_ON_ONCE(vc4->is_vc5))
390
+
return -ENODEV;
391
+
392
392
if (vc4->finished_seqno >= seqno)
393
393
return 0;
394
394
···
474
468
struct vc4_dev *vc4 = to_vc4_dev(dev);
475
469
struct vc4_exec_info *exec;
476
470
471
+
if (WARN_ON_ONCE(vc4->is_vc5))
472
+
return;
473
+
477
474
again:
478
475
exec = vc4_first_bin_job(vc4);
479
476
if (!exec)
···
522
513
if (!exec)
523
514
return;
524
515
516
+
if (WARN_ON_ONCE(vc4->is_vc5))
517
+
return;
518
+
525
519
/* A previous RCL may have written to one of our textures, and
526
520
* our full cache flush at bin time may have occurred before
527
521
* that RCL completed. Flush the texture cache now, but not
···
542
530
{
543
531
struct vc4_dev *vc4 = to_vc4_dev(dev);
544
532
bool was_empty = list_empty(&vc4->render_job_list);
533
+
534
+
if (WARN_ON_ONCE(vc4->is_vc5))
535
+
return;
545
536
546
537
list_move_tail(&exec->head, &vc4->render_job_list);
547
538
if (was_empty)
···
1012
997
unsigned long irqflags;
1013
998
struct vc4_seqno_cb *cb, *cb_temp;
1014
999
1000
+
if (WARN_ON_ONCE(vc4->is_vc5))
1001
+
return;
1002
+
1015
1003
spin_lock_irqsave(&vc4->job_lock, irqflags);
1016
1004
while (!list_empty(&vc4->job_done_list)) {
1017
1005
struct vc4_exec_info *exec =
···
1050
1032
{
1051
1033
struct vc4_dev *vc4 = to_vc4_dev(dev);
1052
1034
unsigned long irqflags;
1035
+
1036
+
if (WARN_ON_ONCE(vc4->is_vc5))
1037
+
return -ENODEV;
1053
1038
1054
1039
cb->func = func;
1055
1040
INIT_WORK(&cb->work, vc4_seqno_cb_work);
···
1104
1083
vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
1105
1084
struct drm_file *file_priv)
1106
1085
{
1086
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
1107
1087
struct drm_vc4_wait_seqno *args = data;
1088
+
1089
+
if (WARN_ON_ONCE(vc4->is_vc5))
1090
+
return -ENODEV;
1108
1091
1109
1092
return vc4_wait_for_seqno_ioctl_helper(dev, args->seqno,
1110
1093
&args->timeout_ns);
···
1118
1093
vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
1119
1094
struct drm_file *file_priv)
1120
1095
{
1096
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
1121
1097
int ret;
1122
1098
struct drm_vc4_wait_bo *args = data;
1123
1099
struct drm_gem_object *gem_obj;
1124
1100
struct vc4_bo *bo;
1101
+
1102
+
if (WARN_ON_ONCE(vc4->is_vc5))
1103
+
return -ENODEV;
1125
1104
1126
1105
if (args->pad != 0)
1127
1106
return -EINVAL;
···
1173
1144
args->shader_rec_size,
1174
1145
args->bo_handle_count);
1175
1146
1147
+
if (WARN_ON_ONCE(vc4->is_vc5))
1148
+
return -ENODEV;
1149
+
1176
1150
if (!vc4->v3d) {
1177
1151
DRM_DEBUG("VC4_SUBMIT_CL with no VC4 V3D probed\n");
1178
1152
return -ENODEV;
···
1199
1167
DRM_ERROR("malloc failure on exec struct\n");
1200
1168
return -ENOMEM;
1201
1169
}
1170
+
exec->dev = vc4;
1202
1171
1203
1172
ret = vc4_v3d_pm_get(vc4);
1204
1173
if (ret) {
···
1309
1276
{
1310
1277
struct vc4_dev *vc4 = to_vc4_dev(dev);
1311
1278
1279
+
if (WARN_ON_ONCE(vc4->is_vc5))
1280
+
return -ENODEV;
1281
+
1312
1282
vc4->dma_fence_context = dma_fence_context_alloc(1);
1313
1283
1314
1284
INIT_LIST_HEAD(&vc4->bin_job_list);
···
1357
1321
int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
1358
1322
struct drm_file *file_priv)
1359
1323
{
1324
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
1360
1325
struct drm_vc4_gem_madvise *args = data;
1361
1326
struct drm_gem_object *gem_obj;
1362
1327
struct vc4_bo *bo;
1363
1328
int ret;
1329
+
1330
+
if (WARN_ON_ONCE(vc4->is_vc5))
1331
+
return -ENODEV;
1364
1332
1365
1333
switch (args->madv) {
1366
1334
case VC4_MADV_DONTNEED:
+1
-1
drivers/gpu/drm/vc4/vc4_hdmi.c
+1
-1
drivers/gpu/drm/vc4/vc4_hdmi.c
+9
-9
drivers/gpu/drm/vc4/vc4_hvs.c
+9
-9
drivers/gpu/drm/vc4/vc4_hvs.c
···
220
220
221
221
int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output)
222
222
{
223
+
struct vc4_dev *vc4 = hvs->vc4;
223
224
u32 reg;
224
225
int ret;
225
226
226
-
if (!hvs->hvs5)
227
+
if (!vc4->is_vc5)
227
228
return output;
228
229
229
230
switch (output) {
···
274
273
static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
275
274
struct drm_display_mode *mode, bool oneshot)
276
275
{
276
+
struct vc4_dev *vc4 = hvs->vc4;
277
277
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
278
278
struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
279
279
unsigned int chan = vc4_crtc_state->assigned_channel;
···
293
291
*/
294
292
dispctrl = SCALER_DISPCTRLX_ENABLE;
295
293
296
-
if (!hvs->hvs5)
294
+
if (!vc4->is_vc5)
297
295
dispctrl |= VC4_SET_FIELD(mode->hdisplay,
298
296
SCALER_DISPCTRLX_WIDTH) |
299
297
VC4_SET_FIELD(mode->vdisplay,
···
314
312
315
313
HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
316
314
SCALER_DISPBKGND_AUTOHS |
317
-
((!hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
315
+
((!vc4->is_vc5) ? SCALER_DISPBKGND_GAMMA : 0) |
318
316
(interlace ? SCALER_DISPBKGND_INTERLACE : 0));
319
317
320
318
/* Reload the LUT, since the SRAMs would have been disabled if
···
619
617
if (!hvs)
620
618
return -ENOMEM;
621
619
620
+
hvs->vc4 = vc4;
622
621
hvs->pdev = pdev;
623
-
624
-
if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
625
-
hvs->hvs5 = true;
626
622
627
623
hvs->regs = vc4_ioremap_regs(pdev, 0);
628
624
if (IS_ERR(hvs->regs))
···
630
630
hvs->regset.regs = hvs_regs;
631
631
hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
632
632
633
-
if (hvs->hvs5) {
633
+
if (vc4->is_vc5) {
634
634
hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
635
635
if (IS_ERR(hvs->core_clk)) {
636
636
dev_err(&pdev->dev, "Couldn't get core clock\n");
···
644
644
}
645
645
}
646
646
647
-
if (!hvs->hvs5)
647
+
if (!vc4->is_vc5)
648
648
hvs->dlist = hvs->regs + SCALER_DLIST_START;
649
649
else
650
650
hvs->dlist = hvs->regs + SCALER5_DLIST_START;
···
665
665
* between planes when they don't overlap on the screen, but
666
666
* for now we just allocate globally.
667
667
*/
668
-
if (!hvs->hvs5)
668
+
if (!vc4->is_vc5)
669
669
/* 48k words of 2x12-bit pixels */
670
670
drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
671
671
else
+16
drivers/gpu/drm/vc4/vc4_irq.c
+16
drivers/gpu/drm/vc4/vc4_irq.c
···
265
265
{
266
266
struct vc4_dev *vc4 = to_vc4_dev(dev);
267
267
268
+
if (WARN_ON_ONCE(vc4->is_vc5))
269
+
return;
270
+
268
271
if (!vc4->v3d)
269
272
return;
270
273
···
281
278
vc4_irq_disable(struct drm_device *dev)
282
279
{
283
280
struct vc4_dev *vc4 = to_vc4_dev(dev);
281
+
282
+
if (WARN_ON_ONCE(vc4->is_vc5))
283
+
return;
284
284
285
285
if (!vc4->v3d)
286
286
return;
···
302
296
303
297
int vc4_irq_install(struct drm_device *dev, int irq)
304
298
{
299
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
305
300
int ret;
301
+
302
+
if (WARN_ON_ONCE(vc4->is_vc5))
303
+
return -ENODEV;
306
304
307
305
if (irq == IRQ_NOTCONNECTED)
308
306
return -ENOTCONN;
···
326
316
{
327
317
struct vc4_dev *vc4 = to_vc4_dev(dev);
328
318
319
+
if (WARN_ON_ONCE(vc4->is_vc5))
320
+
return;
321
+
329
322
vc4_irq_disable(dev);
330
323
free_irq(vc4->irq, dev);
331
324
}
···
338
325
{
339
326
struct vc4_dev *vc4 = to_vc4_dev(dev);
340
327
unsigned long irqflags;
328
+
329
+
if (WARN_ON_ONCE(vc4->is_vc5))
330
+
return;
341
331
342
332
/* Acknowledge any stale IRQs. */
343
333
V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
+16
-8
drivers/gpu/drm/vc4/vc4_kms.c
+16
-8
drivers/gpu/drm/vc4/vc4_kms.c
···
393
393
old_hvs_state->fifo_state[channel].pending_commit = NULL;
394
394
}
395
395
396
-
if (vc4->hvs->hvs5) {
396
+
if (vc4->is_vc5) {
397
397
unsigned long state_rate = max(old_hvs_state->core_clock_rate,
398
398
new_hvs_state->core_clock_rate);
399
399
unsigned long core_rate = max_t(unsigned long,
···
412
412
413
413
vc4_ctm_commit(vc4, state);
414
414
415
-
if (vc4->hvs->hvs5)
415
+
if (vc4->is_vc5)
416
416
vc5_hvs_pv_muxing_commit(vc4, state);
417
417
else
418
418
vc4_hvs_pv_muxing_commit(vc4, state);
···
430
430
431
431
drm_atomic_helper_cleanup_planes(dev, state);
432
432
433
-
if (vc4->hvs->hvs5) {
433
+
if (vc4->is_vc5) {
434
434
drm_dbg(dev, "Running the core clock at %lu Hz\n",
435
435
new_hvs_state->core_clock_rate);
436
436
···
479
479
struct drm_file *file_priv,
480
480
const struct drm_mode_fb_cmd2 *mode_cmd)
481
481
{
482
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
482
483
struct drm_mode_fb_cmd2 mode_cmd_local;
484
+
485
+
if (WARN_ON_ONCE(vc4->is_vc5))
486
+
return ERR_PTR(-ENODEV);
483
487
484
488
/* If the user didn't specify a modifier, use the
485
489
* vc4_set_tiling_ioctl() state for the BO.
···
1001
997
.fb_create = vc4_fb_create,
1002
998
};
1003
999
1000
+
static const struct drm_mode_config_funcs vc5_mode_funcs = {
1001
+
.atomic_check = vc4_atomic_check,
1002
+
.atomic_commit = drm_atomic_helper_commit,
1003
+
.fb_create = drm_gem_fb_create,
1004
+
};
1005
+
1004
1006
int vc4_kms_load(struct drm_device *dev)
1005
1007
{
1006
1008
struct vc4_dev *vc4 = to_vc4_dev(dev);
1007
-
bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
1008
-
"brcm,bcm2711-vc5");
1009
1009
int ret;
1010
1010
1011
1011
/*
···
1017
1009
* the BCM2711, but the load tracker computations are used for
1018
1010
* the core clock rate calculation.
1019
1011
*/
1020
-
if (!is_vc5) {
1012
+
if (!vc4->is_vc5) {
1021
1013
/* Start with the load tracker enabled. Can be
1022
1014
* disabled through the debugfs load_tracker file.
1023
1015
*/
···
1033
1025
return ret;
1034
1026
}
1035
1027
1036
-
if (is_vc5) {
1028
+
if (vc4->is_vc5) {
1037
1029
dev->mode_config.max_width = 7680;
1038
1030
dev->mode_config.max_height = 7680;
1039
1031
} else {
···
1041
1033
dev->mode_config.max_height = 2048;
1042
1034
}
1043
1035
1044
-
dev->mode_config.funcs = &vc4_mode_funcs;
1036
+
dev->mode_config.funcs = vc4->is_vc5 ? &vc5_mode_funcs : &vc4_mode_funcs;
1045
1037
dev->mode_config.helper_private = &vc4_mode_config_helpers;
1046
1038
dev->mode_config.preferred_depth = 24;
1047
1039
dev->mode_config.async_page_flip = true;
+46
-1
drivers/gpu/drm/vc4/vc4_perfmon.c
+46
-1
drivers/gpu/drm/vc4/vc4_perfmon.c
···
17
17
18
18
void vc4_perfmon_get(struct vc4_perfmon *perfmon)
19
19
{
20
+
struct vc4_dev *vc4 = perfmon->dev;
21
+
22
+
if (WARN_ON_ONCE(vc4->is_vc5))
23
+
return;
24
+
20
25
if (perfmon)
21
26
refcount_inc(&perfmon->refcnt);
22
27
}
23
28
24
29
void vc4_perfmon_put(struct vc4_perfmon *perfmon)
25
30
{
26
-
if (perfmon && refcount_dec_and_test(&perfmon->refcnt))
31
+
struct vc4_dev *vc4;
32
+
33
+
if (!perfmon)
34
+
return;
35
+
36
+
vc4 = perfmon->dev;
37
+
if (WARN_ON_ONCE(vc4->is_vc5))
38
+
return;
39
+
40
+
if (refcount_dec_and_test(&perfmon->refcnt))
27
41
kfree(perfmon);
28
42
}
29
43
···
45
31
{
46
32
unsigned int i;
47
33
u32 mask;
34
+
35
+
if (WARN_ON_ONCE(vc4->is_vc5))
36
+
return;
48
37
49
38
if (WARN_ON_ONCE(!perfmon || vc4->active_perfmon))
50
39
return;
···
66
49
{
67
50
unsigned int i;
68
51
52
+
if (WARN_ON_ONCE(vc4->is_vc5))
53
+
return;
54
+
69
55
if (WARN_ON_ONCE(!vc4->active_perfmon ||
70
56
perfmon != vc4->active_perfmon))
71
57
return;
···
84
64
85
65
struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id)
86
66
{
67
+
struct vc4_dev *vc4 = vc4file->dev;
87
68
struct vc4_perfmon *perfmon;
69
+
70
+
if (WARN_ON_ONCE(vc4->is_vc5))
71
+
return NULL;
88
72
89
73
mutex_lock(&vc4file->perfmon.lock);
90
74
perfmon = idr_find(&vc4file->perfmon.idr, id);
···
100
76
101
77
void vc4_perfmon_open_file(struct vc4_file *vc4file)
102
78
{
79
+
struct vc4_dev *vc4 = vc4file->dev;
80
+
81
+
if (WARN_ON_ONCE(vc4->is_vc5))
82
+
return;
83
+
103
84
mutex_init(&vc4file->perfmon.lock);
104
85
idr_init_base(&vc4file->perfmon.idr, VC4_PERFMONID_MIN);
86
+
vc4file->dev = vc4;
105
87
}
106
88
107
89
static int vc4_perfmon_idr_del(int id, void *elem, void *data)
···
121
91
122
92
void vc4_perfmon_close_file(struct vc4_file *vc4file)
123
93
{
94
+
struct vc4_dev *vc4 = vc4file->dev;
95
+
96
+
if (WARN_ON_ONCE(vc4->is_vc5))
97
+
return;
98
+
124
99
mutex_lock(&vc4file->perfmon.lock);
125
100
idr_for_each(&vc4file->perfmon.idr, vc4_perfmon_idr_del, NULL);
126
101
idr_destroy(&vc4file->perfmon.idr);
···
141
106
struct vc4_perfmon *perfmon;
142
107
unsigned int i;
143
108
int ret;
109
+
110
+
if (WARN_ON_ONCE(vc4->is_vc5))
111
+
return -ENODEV;
144
112
145
113
if (!vc4->v3d) {
146
114
DRM_DEBUG("Creating perfmon no VC4 V3D probed\n");
···
165
127
GFP_KERNEL);
166
128
if (!perfmon)
167
129
return -ENOMEM;
130
+
perfmon->dev = vc4;
168
131
169
132
for (i = 0; i < req->ncounters; i++)
170
133
perfmon->events[i] = req->events[i];
···
196
157
struct drm_vc4_perfmon_destroy *req = data;
197
158
struct vc4_perfmon *perfmon;
198
159
160
+
if (WARN_ON_ONCE(vc4->is_vc5))
161
+
return -ENODEV;
162
+
199
163
if (!vc4->v3d) {
200
164
DRM_DEBUG("Destroying perfmon no VC4 V3D probed\n");
201
165
return -ENODEV;
···
223
181
struct drm_vc4_perfmon_get_values *req = data;
224
182
struct vc4_perfmon *perfmon;
225
183
int ret;
184
+
185
+
if (WARN_ON_ONCE(vc4->is_vc5))
186
+
return -ENODEV;
226
187
227
188
if (!vc4->v3d) {
228
189
DRM_DEBUG("Getting perfmon no VC4 V3D probed\n");
+21
-8
drivers/gpu/drm/vc4/vc4_plane.c
+21
-8
drivers/gpu/drm/vc4/vc4_plane.c
···
489
489
}
490
490
491
491
/* Align it to 64 or 128 (hvs5) bytes */
492
-
lbm = roundup(lbm, vc4->hvs->hvs5 ? 128 : 64);
492
+
lbm = roundup(lbm, vc4->is_vc5 ? 128 : 64);
493
493
494
494
/* Each "word" of the LBM memory contains 2 or 4 (hvs5) pixels */
495
-
lbm /= vc4->hvs->hvs5 ? 4 : 2;
495
+
lbm /= vc4->is_vc5 ? 4 : 2;
496
496
497
497
return lbm;
498
498
}
···
608
608
ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
609
609
&vc4_state->lbm,
610
610
lbm_size,
611
-
vc4->hvs->hvs5 ? 64 : 32,
611
+
vc4->is_vc5 ? 64 : 32,
612
612
0, 0);
613
613
spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
614
614
···
917
917
mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
918
918
fb->format->has_alpha;
919
919
920
-
if (!vc4->hvs->hvs5) {
920
+
if (!vc4->is_vc5) {
921
921
/* Control word */
922
922
vc4_dlist_write(vc4_state,
923
923
SCALER_CTL0_VALID |
···
1321
1321
1322
1322
old_vc4_state = to_vc4_plane_state(plane->state);
1323
1323
new_vc4_state = to_vc4_plane_state(new_plane_state);
1324
+
1325
+
if (!new_vc4_state->hw_dlist)
1326
+
return -EINVAL;
1327
+
1324
1328
if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
1325
1329
old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
1326
1330
old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
···
1385
1381
.atomic_update = vc4_plane_atomic_update,
1386
1382
.prepare_fb = vc4_prepare_fb,
1387
1383
.cleanup_fb = vc4_cleanup_fb,
1384
+
.atomic_async_check = vc4_plane_atomic_async_check,
1385
+
.atomic_async_update = vc4_plane_atomic_async_update,
1386
+
};
1387
+
1388
+
static const struct drm_plane_helper_funcs vc5_plane_helper_funcs = {
1389
+
.atomic_check = vc4_plane_atomic_check,
1390
+
.atomic_update = vc4_plane_atomic_update,
1388
1391
.atomic_async_check = vc4_plane_atomic_async_check,
1389
1392
.atomic_async_update = vc4_plane_atomic_async_update,
1390
1393
};
···
1464
1453
struct drm_plane *vc4_plane_init(struct drm_device *dev,
1465
1454
enum drm_plane_type type)
1466
1455
{
1456
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
1467
1457
struct drm_plane *plane = NULL;
1468
1458
struct vc4_plane *vc4_plane;
1469
1459
u32 formats[ARRAY_SIZE(hvs_formats)];
1470
1460
int num_formats = 0;
1471
1461
int ret = 0;
1472
1462
unsigned i;
1473
-
bool hvs5 = of_device_is_compatible(dev->dev->of_node,
1474
-
"brcm,bcm2711-vc5");
1475
1463
static const uint64_t modifiers[] = {
1476
1464
DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
1477
1465
DRM_FORMAT_MOD_BROADCOM_SAND128,
···
1486
1476
return ERR_PTR(-ENOMEM);
1487
1477
1488
1478
for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
1489
-
if (!hvs_formats[i].hvs5_only || hvs5) {
1479
+
if (!hvs_formats[i].hvs5_only || vc4->is_vc5) {
1490
1480
formats[num_formats] = hvs_formats[i].drm;
1491
1481
num_formats++;
1492
1482
}
···
1500
1490
if (ret)
1501
1491
return ERR_PTR(ret);
1502
1492
1503
-
drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1493
+
if (vc4->is_vc5)
1494
+
drm_plane_helper_add(plane, &vc5_plane_helper_funcs);
1495
+
else
1496
+
drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1504
1497
1505
1498
drm_plane_create_alpha_property(plane);
1506
1499
drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
+4
drivers/gpu/drm/vc4/vc4_render_cl.c
+4
drivers/gpu/drm/vc4/vc4_render_cl.c
···
593
593
594
594
int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
595
595
{
596
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
596
597
struct vc4_rcl_setup setup = {0};
597
598
struct drm_vc4_submit_cl *args = exec->args;
598
599
bool has_bin = args->bin_cl_size != 0;
599
600
int ret;
601
+
602
+
if (WARN_ON_ONCE(vc4->is_vc5))
603
+
return -ENODEV;
600
604
601
605
if (args->min_x_tile > args->max_x_tile ||
602
606
args->min_y_tile > args->max_y_tile) {
+15
drivers/gpu/drm/vc4/vc4_v3d.c
+15
drivers/gpu/drm/vc4/vc4_v3d.c
···
127
127
int
128
128
vc4_v3d_pm_get(struct vc4_dev *vc4)
129
129
{
130
+
if (WARN_ON_ONCE(vc4->is_vc5))
131
+
return -ENODEV;
132
+
130
133
mutex_lock(&vc4->power_lock);
131
134
if (vc4->power_refcount++ == 0) {
132
135
int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
···
148
145
void
149
146
vc4_v3d_pm_put(struct vc4_dev *vc4)
150
147
{
148
+
if (WARN_ON_ONCE(vc4->is_vc5))
149
+
return;
150
+
151
151
mutex_lock(&vc4->power_lock);
152
152
if (--vc4->power_refcount == 0) {
153
153
pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
···
177
171
int slot;
178
172
uint64_t seqno = 0;
179
173
struct vc4_exec_info *exec;
174
+
175
+
if (WARN_ON_ONCE(vc4->is_vc5))
176
+
return -ENODEV;
180
177
181
178
try_again:
182
179
spin_lock_irqsave(&vc4->job_lock, irqflags);
···
325
316
{
326
317
int ret = 0;
327
318
319
+
if (WARN_ON_ONCE(vc4->is_vc5))
320
+
return -ENODEV;
321
+
328
322
mutex_lock(&vc4->bin_bo_lock);
329
323
330
324
if (used && *used)
···
360
348
361
349
void vc4_v3d_bin_bo_put(struct vc4_dev *vc4)
362
350
{
351
+
if (WARN_ON_ONCE(vc4->is_vc5))
352
+
return;
353
+
363
354
mutex_lock(&vc4->bin_bo_lock);
364
355
kref_put(&vc4->bin_bo_kref, bin_bo_release);
365
356
mutex_unlock(&vc4->bin_bo_lock);
+16
drivers/gpu/drm/vc4/vc4_validate.c
+16
drivers/gpu/drm/vc4/vc4_validate.c
···
105
105
struct drm_gem_cma_object *
106
106
vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex)
107
107
{
108
+
struct vc4_dev *vc4 = exec->dev;
108
109
struct drm_gem_cma_object *obj;
109
110
struct vc4_bo *bo;
111
+
112
+
if (WARN_ON_ONCE(vc4->is_vc5))
113
+
return NULL;
110
114
111
115
if (hindex >= exec->bo_count) {
112
116
DRM_DEBUG("BO index %d greater than BO count %d\n",
···
164
160
uint32_t offset, uint8_t tiling_format,
165
161
uint32_t width, uint32_t height, uint8_t cpp)
166
162
{
163
+
struct vc4_dev *vc4 = exec->dev;
167
164
uint32_t aligned_width, aligned_height, stride, size;
168
165
uint32_t utile_w = utile_width(cpp);
169
166
uint32_t utile_h = utile_height(cpp);
167
+
168
+
if (WARN_ON_ONCE(vc4->is_vc5))
169
+
return false;
170
170
171
171
/* The shaded vertex format stores signed 12.4 fixed point
172
172
* (-2048,2047) offsets from the viewport center, so we should
···
490
482
void *unvalidated,
491
483
struct vc4_exec_info *exec)
492
484
{
485
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
493
486
uint32_t len = exec->args->bin_cl_size;
494
487
uint32_t dst_offset = 0;
495
488
uint32_t src_offset = 0;
489
+
490
+
if (WARN_ON_ONCE(vc4->is_vc5))
491
+
return -ENODEV;
496
492
497
493
while (src_offset < len) {
498
494
void *dst_pkt = validated + dst_offset;
···
938
926
vc4_validate_shader_recs(struct drm_device *dev,
939
927
struct vc4_exec_info *exec)
940
928
{
929
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
941
930
uint32_t i;
942
931
int ret = 0;
932
+
933
+
if (WARN_ON_ONCE(vc4->is_vc5))
934
+
return -ENODEV;
943
935
944
936
for (i = 0; i < exec->shader_state_count; i++) {
945
937
ret = validate_gl_shader_rec(dev, exec, &exec->shader_state[i]);
+4
drivers/gpu/drm/vc4/vc4_validate_shaders.c
+4
drivers/gpu/drm/vc4/vc4_validate_shaders.c
···
778
778
struct vc4_validated_shader_info *
779
779
vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
780
780
{
781
+
struct vc4_dev *vc4 = to_vc4_dev(shader_obj->base.dev);
781
782
bool found_shader_end = false;
782
783
int shader_end_ip = 0;
783
784
uint32_t last_thread_switch_ip = -3;
784
785
uint32_t ip;
785
786
struct vc4_validated_shader_info *validated_shader = NULL;
786
787
struct vc4_shader_validation_state validation_state;
788
+
789
+
if (WARN_ON_ONCE(vc4->is_vc5))
790
+
return NULL;
787
791
788
792
memset(&validation_state, 0, sizeof(validation_state));
789
793
validation_state.shader = shader_obj->vaddr;