Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v4.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
- Driver fixes for Freescale i.MX7D, Intel, Broadcom 2835
- One MAINTAINERS entry
* tag 'pinctrl-v4.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
MAINTAINERS: pinctrl: Add maintainers for pinctrl-single
pinctrl: bcm2835: Fix initial value for direction_output
pinctrl: intel: fix offset calculation issue of register PAD_OWN
pinctrl: intel: fix bug of register offset calculation
pinctrl: freescale: add ZERO_OFFSET_VALID flag for vf610 pinctrl
+41
-28
+8
MAINTAINERS
+8
MAINTAINERS
···
8380
8380
S: Maintained
8381
8381
F: drivers/pinctrl/samsung/
8382
8382
8383
+
PIN CONTROLLER - SINGLE
8384
+
M: Tony Lindgren <tony@atomide.com>
8385
+
M: Haojian Zhuang <haojian.zhuang@linaro.org>
8386
+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
8387
+
L: linux-omap@vger.kernel.org
8388
+
S: Maintained
8389
+
F: drivers/pinctrl/pinctrl-single.c
8390
+
8383
8391
PIN CONTROLLER - ST SPEAR
8384
8392
M: Viresh Kumar <vireshk@kernel.org>
8385
8393
L: spear-devel@list.st.com
+7
-6
drivers/pinctrl/bcm/pinctrl-bcm2835.c
+7
-6
drivers/pinctrl/bcm/pinctrl-bcm2835.c
···
342
342
return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
343
343
}
344
344
345
-
static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
346
-
unsigned offset, int value)
347
-
{
348
-
return pinctrl_gpio_direction_output(chip->base + offset);
349
-
}
350
-
351
345
static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
352
346
{
353
347
struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
354
348
355
349
bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
350
+
}
351
+
352
+
static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
353
+
unsigned offset, int value)
354
+
{
355
+
bcm2835_gpio_set(chip, offset, value);
356
+
return pinctrl_gpio_direction_output(chip->base + offset);
356
357
}
357
358
358
359
static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+1
-1
drivers/pinctrl/freescale/pinctrl-vf610.c
+1
-1
drivers/pinctrl/freescale/pinctrl-vf610.c
···
299
299
static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
300
300
.pins = vf610_pinctrl_pads,
301
301
.npins = ARRAY_SIZE(vf610_pinctrl_pads),
302
-
.flags = SHARE_MUX_CONF_REG,
302
+
.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
303
303
};
304
304
305
305
static const struct of_device_id vf610_pinctrl_of_match[] = {
+1
drivers/pinctrl/intel/pinctrl-broxton.c
+1
drivers/pinctrl/intel/pinctrl-broxton.c
+20
-21
drivers/pinctrl/intel/pinctrl-intel.c
+20
-21
drivers/pinctrl/intel/pinctrl-intel.c
···
25
25
26
26
#include "pinctrl-intel.h"
27
27
28
-
/* Maximum number of pads in each group */
29
-
#define NPADS_IN_GPP 24
30
-
31
28
/* Offset from regs */
32
29
#define PADBAR 0x00c
33
30
#define GPI_IS 0x100
···
34
37
#define PADOWN_BITS 4
35
38
#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
36
39
#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
40
+
#define PADOWN_GPP(p) ((p) / 8)
37
41
38
42
/* Offset from pad_regs */
39
43
#define PADCFG0 0x000
···
140
142
static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
141
143
{
142
144
const struct intel_community *community;
143
-
unsigned padno, gpp, gpp_offset, offset;
145
+
unsigned padno, gpp, offset, group;
144
146
void __iomem *padown;
145
147
146
148
community = intel_get_community(pctrl, pin);
···
150
152
return true;
151
153
152
154
padno = pin_to_padno(community, pin);
153
-
gpp = padno / NPADS_IN_GPP;
154
-
gpp_offset = padno % NPADS_IN_GPP;
155
-
offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4;
155
+
group = padno / community->gpp_size;
156
+
gpp = PADOWN_GPP(padno % community->gpp_size);
157
+
offset = community->padown_offset + 0x10 * group + gpp * 4;
156
158
padown = community->regs + offset;
157
159
158
160
return !(readl(padown) & PADOWN_MASK(padno));
···
171
173
return false;
172
174
173
175
padno = pin_to_padno(community, pin);
174
-
gpp = padno / NPADS_IN_GPP;
176
+
gpp = padno / community->gpp_size;
175
177
offset = community->hostown_offset + gpp * 4;
176
178
hostown = community->regs + offset;
177
179
178
-
return !(readl(hostown) & BIT(padno % NPADS_IN_GPP));
180
+
return !(readl(hostown) & BIT(padno % community->gpp_size));
179
181
}
180
182
181
183
static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
···
191
193
return false;
192
194
193
195
padno = pin_to_padno(community, pin);
194
-
gpp = padno / NPADS_IN_GPP;
196
+
gpp = padno / community->gpp_size;
195
197
196
198
/*
197
199
* If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
···
200
202
*/
201
203
offset = community->padcfglock_offset + gpp * 8;
202
204
value = readl(community->regs + offset);
203
-
if (value & BIT(pin % NPADS_IN_GPP))
205
+
if (value & BIT(pin % community->gpp_size))
204
206
return true;
205
207
206
208
offset = community->padcfglock_offset + 4 + gpp * 8;
207
209
value = readl(community->regs + offset);
208
-
if (value & BIT(pin % NPADS_IN_GPP))
210
+
if (value & BIT(pin % community->gpp_size))
209
211
return true;
210
212
211
213
return false;
···
661
663
community = intel_get_community(pctrl, pin);
662
664
if (community) {
663
665
unsigned padno = pin_to_padno(community, pin);
664
-
unsigned gpp_offset = padno % NPADS_IN_GPP;
665
-
unsigned gpp = padno / NPADS_IN_GPP;
666
+
unsigned gpp_offset = padno % community->gpp_size;
667
+
unsigned gpp = padno / community->gpp_size;
666
668
667
669
writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
668
670
}
···
683
685
community = intel_get_community(pctrl, pin);
684
686
if (community) {
685
687
unsigned padno = pin_to_padno(community, pin);
686
-
unsigned gpp_offset = padno % NPADS_IN_GPP;
687
-
unsigned gpp = padno / NPADS_IN_GPP;
688
+
unsigned gpp_offset = padno % community->gpp_size;
689
+
unsigned gpp = padno / community->gpp_size;
688
690
void __iomem *reg;
689
691
u32 value;
690
692
···
778
780
return -EINVAL;
779
781
780
782
padno = pin_to_padno(community, pin);
781
-
gpp = padno / NPADS_IN_GPP;
782
-
gpp_offset = padno % NPADS_IN_GPP;
783
+
gpp = padno / community->gpp_size;
784
+
gpp_offset = padno % community->gpp_size;
783
785
784
786
/* Clear the existing wake status */
785
787
writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
···
817
819
/* Only interrupts that are enabled */
818
820
pending &= enabled;
819
821
820
-
for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) {
822
+
for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
821
823
unsigned padno, irq;
822
824
823
825
/*
824
826
* The last group in community can have less pins
825
827
* than NPADS_IN_GPP.
826
828
*/
827
-
padno = gpp_offset + gpp * NPADS_IN_GPP;
829
+
padno = gpp_offset + gpp * community->gpp_size;
828
830
if (padno >= community->npins)
829
831
break;
830
832
···
1000
1002
1001
1003
community->regs = regs;
1002
1004
community->pad_regs = regs + padbar;
1003
-
community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP);
1005
+
community->ngpps = DIV_ROUND_UP(community->npins,
1006
+
community->gpp_size);
1004
1007
}
1005
1008
1006
1009
irq = platform_get_irq(pdev, 0);
+3
drivers/pinctrl/intel/pinctrl-intel.h
+3
drivers/pinctrl/intel/pinctrl-intel.h
···
55
55
* ACPI).
56
56
* @ie_offset: Register offset of GPI_IE from @regs.
57
57
* @pin_base: Starting pin of pins in this community
58
+
* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
59
+
* HOSTSW_OWN, GPI_IS, GPI_IE, etc.
58
60
* @npins: Number of pins in this community
59
61
* @regs: Community specific common registers (reserved for core driver)
60
62
* @pad_regs: Community specific pad registers (reserved for core driver)
···
70
68
unsigned hostown_offset;
71
69
unsigned ie_offset;
72
70
unsigned pin_base;
71
+
unsigned gpp_size;
73
72
size_t npins;
74
73
void __iomem *regs;
75
74
void __iomem *pad_regs;