tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2023-02-10' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Weekly fixes.

The amdgpu had a few small fixes to display flicker on certain
configurations, however it was found the the flicker was lessened but
there were other unintended consequences, so for now they've been
reverted and replaced with an option for users to test with so future
fixes can be developed.

Otherwise apart from the usual bunch of i915 and amdgpu, there's a
client, virtio-gpu and an nvidiafb fix that reorders its loading to
avoid failure.

client:
- refcount fix

amdgpu:
- a bunch of attempted flicker fixes that regressed turned into a
user workaround option for now
- Properly fix S/G display with AGP aperture enabled
- Fix cursor offset with 180 rotation
- SMU13 fixes
- Use TGID for GPUVM traces
- Fix oops on in fence error path
- Don't run IB tests on hw rings when sw rings are in use
- memory leak fix

i915:
- Display watermark fix
- fbdev fix for PSR, FBC, DRRS
- Move fd_install after last use of fence
- Initialize the obj flags for shmem objects
- Fix VBT DSI DVO port handling

virtio-gpu:
- fence fix

nvidiafb:
- regression fix for driver load when no hw supported"

* tag 'drm-fixes-2023-02-10' of git://anongit.freedesktop.org/drm/drm: (27 commits)
Revert "drm/amd/display: disable S/G display on DCN 3.1.5"
Revert "drm/amd/display: disable S/G display on DCN 2.1.0"
Revert "drm/amd/display: disable S/G display on DCN 3.1.2/3"
drm/amdgpu: add S/G display parameter
drm/amdgpu/smu: skip pptable init under sriov
amd/amdgpu: remove test ib on hw ring
drm/amdgpu/fence: Fix oops due to non-matching drm_sched init/fini
drm/amdgpu: Use the TGID for trace_amdgpu_vm_update_ptes
drm/amdgpu: Add unique_id support for GC 11.0.1/2
drm/amd/pm: bump SMU 13.0.7 driver_if header version
drm/amd/pm: bump SMU 13.0.0 driver_if header version
drm/amd/pm: add SMU 13.0.7 missing GetPptLimit message mapping
drm/amd/display: fix cursor offset on rotation 180
drm/amd/amdgpu: enable athub cg 11.0.3
Revert "drm/amd/display: disable S/G display on DCN 3.1.4"
drm/amd/display: properly handling AGP aperture in vm setup
drm/amd/display: disable S/G display on DCN 3.1.2/3
drm/amd/display: disable S/G display on DCN 2.1.0
drm/i915: Fix VBT DSI DVO port handling
drm/client: fix circular reference counting issue
...

Linus Torvalds 38c1e0c6 1424c3e3

+200 -119
+1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 243 243 244 244 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 245 245 extern int amdgpu_vcnfw_log; 246 + extern int amdgpu_sg_display; 246 247 247 248 #define AMDGPU_VM_MAX_NUM_CTX 4096 248 249 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
+4 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
··· 1220 1220 * next job actually sees the results from the previous one 1221 1221 * before we start executing on the same scheduler ring. 1222 1222 */ 1223 - if (!s_fence || s_fence->sched != sched) 1223 + if (!s_fence || s_fence->sched != sched) { 1224 + dma_fence_put(fence); 1224 1225 continue; 1226 + } 1225 1227 1226 1228 r = amdgpu_sync_fence(&p->gang_leader->explicit_sync, fence); 1229 + dma_fence_put(fence); 1227 1230 if (r) 1228 1231 return r; 1229 1232 }
+11
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 186 186 int amdgpu_smartshift_bias; 187 187 int amdgpu_use_xgmi_p2p = 1; 188 188 int amdgpu_vcnfw_log; 189 + int amdgpu_sg_display = -1; /* auto */ 189 190 190 191 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 191 192 ··· 931 930 */ 932 931 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 933 932 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 933 + 934 + /** 935 + * DOC: sg_display (int) 936 + * Disable S/G (scatter/gather) display (i.e., display from system memory). 937 + * This option is only relevant on APUs. Set this option to 0 to disable 938 + * S/G display if you experience flickering or other issues under memory 939 + * pressure and report the issue. 940 + */ 941 + MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 942 + module_param_named(sg_display, amdgpu_sg_display, int, 0444); 934 943 935 944 /** 936 945 * DOC: smu_pptable_id (int)
+7 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
··· 618 618 if (!ring || !ring->fence_drv.initialized) 619 619 continue; 620 620 621 - if (!ring->no_scheduler) 621 + /* 622 + * Notice we check for sched.ops since there's some 623 + * override on the meaning of sched.ready by amdgpu. 624 + * The natural check would be sched.ready, which is 625 + * set as drm_sched_init() finishes... 626 + */ 627 + if (ring->sched.ops) 622 628 drm_sched_fini(&ring->sched); 623 629 624 630 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
··· 295 295 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib))) 296 296 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib))) 297 297 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 298 - #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 298 + #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0) 299 299 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 300 300 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 301 301 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
··· 974 974 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end, 975 975 min(nptes, 32u), dst, incr, 976 976 upd_flags, 977 - vm->task_info.pid, 977 + vm->task_info.tgid, 978 978 vm->immediate.fence_context); 979 979 amdgpu_vm_pte_update_flags(params, to_amdgpu_bo_vm(pt), 980 980 cursor.level, pe_start, dst,
-1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 6877 6877 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6878 6878 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6879 6879 .test_ring = gfx_v9_0_ring_test_ring, 6880 - .test_ib = gfx_v9_0_ring_test_ib, 6881 6880 .insert_nop = amdgpu_ring_insert_nop, 6882 6881 .pad_ib = amdgpu_ring_generic_pad_ib, 6883 6882 .emit_switch_buffer = gfx_v9_ring_emit_sb,
+3 -1
drivers/gpu/drm/amd/amdgpu/soc21.c
··· 641 641 AMD_CG_SUPPORT_GFX_CGLS | 642 642 AMD_CG_SUPPORT_REPEATER_FGCG | 643 643 AMD_CG_SUPPORT_GFX_MGCG | 644 - AMD_CG_SUPPORT_HDP_SD; 644 + AMD_CG_SUPPORT_HDP_SD | 645 + AMD_CG_SUPPORT_ATHUB_MGCG | 646 + AMD_CG_SUPPORT_ATHUB_LS; 645 647 adev->pg_flags = AMD_PG_SUPPORT_VCN | 646 648 AMD_PG_SUPPORT_VCN_DPG | 647 649 AMD_PG_SUPPORT_JPEG;
+33 -14
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 1184 1184 1185 1185 memset(pa_config, 0, sizeof(*pa_config)); 1186 1186 1187 - logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1188 - pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1189 - 1190 - if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1191 - /* 1192 - * Raven2 has a HW issue that it is unable to use the vram which 1193 - * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1194 - * workaround that increase system aperture high address (add 1) 1195 - * to get rid of the VM fault and hardware hang. 1196 - */ 1197 - logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1198 - else 1199 - logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1200 - 1201 1187 agp_base = 0; 1202 1188 agp_bot = adev->gmc.agp_start >> 24; 1203 1189 agp_top = adev->gmc.agp_end >> 24; 1204 1190 1191 + /* AGP aperture is disabled */ 1192 + if (agp_bot == agp_top) { 1193 + logical_addr_low = adev->gmc.vram_start >> 18; 1194 + if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1195 + /* 1196 + * Raven2 has a HW issue that it is unable to use the vram which 1197 + * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1198 + * workaround that increase system aperture high address (add 1) 1199 + * to get rid of the VM fault and hardware hang. 1200 + */ 1201 + logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 1202 + else 1203 + logical_addr_high = adev->gmc.vram_end >> 18; 1204 + } else { 1205 + logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1206 + if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1207 + /* 1208 + * Raven2 has a HW issue that it is unable to use the vram which 1209 + * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1210 + * workaround that increase system aperture high address (add 1) 1211 + * to get rid of the VM fault and hardware hang. 1212 + */ 1213 + logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1214 + else 1215 + logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1216 + } 1217 + 1218 + pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1205 1219 1206 1220 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; 1207 1221 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); ··· 1517 1503 case IP_VERSION(3, 0, 1): 1518 1504 case IP_VERSION(3, 1, 2): 1519 1505 case IP_VERSION(3, 1, 3): 1506 + case IP_VERSION(3, 1, 4): 1507 + case IP_VERSION(3, 1, 5): 1520 1508 case IP_VERSION(3, 1, 6): 1521 1509 init_data.flags.gpu_vm_support = true; 1522 1510 break; ··· 1527 1511 } 1528 1512 break; 1529 1513 } 1514 + if (init_data.flags.gpu_vm_support && 1515 + (amdgpu_sg_display == 0)) 1516 + init_data.flags.gpu_vm_support = false; 1530 1517 1531 1518 if (init_data.flags.gpu_vm_support) 1532 1519 adev->mode_info.gpu_vm_support = true;
+1 -1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
··· 3626 3626 (int)hubp->curs_attr.width || pos_cpy.x 3627 3627 <= (int)hubp->curs_attr.width + 3628 3628 pipe_ctx->plane_state->src_rect.x) { 3629 - pos_cpy.x = temp_x + viewport_width; 3629 + pos_cpy.x = 2 * viewport_width - temp_x; 3630 3630 } 3631 3631 } 3632 3632 } else {
+2
drivers/gpu/drm/amd/pm/amdgpu_pm.c
··· 1991 1991 case IP_VERSION(9, 4, 2): 1992 1992 case IP_VERSION(10, 3, 0): 1993 1993 case IP_VERSION(11, 0, 0): 1994 + case IP_VERSION(11, 0, 1): 1995 + case IP_VERSION(11, 0, 2): 1994 1996 *states = ATTR_STATE_SUPPORTED; 1995 1997 break; 1996 1998 default:
+3 -2
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
··· 123 123 (1 << FEATURE_DS_FCLK_BIT) | \ 124 124 (1 << FEATURE_DS_LCLK_BIT) | \ 125 125 (1 << FEATURE_DS_DCFCLK_BIT) | \ 126 - (1 << FEATURE_DS_UCLK_BIT)) 126 + (1 << FEATURE_DS_UCLK_BIT) | \ 127 + (1ULL << FEATURE_DS_VCN_BIT)) 127 128 128 129 //For use with feature control messages 129 130 typedef enum { ··· 523 522 TEMP_HOTSPOT_M, 524 523 TEMP_MEM, 525 524 TEMP_VR_GFX, 526 - TEMP_VR_SOC, 527 525 TEMP_VR_MEM0, 528 526 TEMP_VR_MEM1, 527 + TEMP_VR_SOC, 529 528 TEMP_VR_U, 530 529 TEMP_LIQUID0, 531 530 TEMP_LIQUID1,
+15 -14
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
··· 113 113 #define NUM_FEATURES 64 114 114 115 115 #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 116 - #define ALLOWED_FEATURE_CTRL_SCPM (1 << FEATURE_DPM_GFXCLK_BIT) | \ 117 - (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 118 - (1 << FEATURE_DPM_UCLK_BIT) | \ 119 - (1 << FEATURE_DPM_FCLK_BIT) | \ 120 - (1 << FEATURE_DPM_SOCCLK_BIT) | \ 121 - (1 << FEATURE_DPM_MP0CLK_BIT) | \ 122 - (1 << FEATURE_DPM_LINK_BIT) | \ 123 - (1 << FEATURE_DPM_DCN_BIT) | \ 124 - (1 << FEATURE_DS_GFXCLK_BIT) | \ 125 - (1 << FEATURE_DS_SOCCLK_BIT) | \ 126 - (1 << FEATURE_DS_FCLK_BIT) | \ 127 - (1 << FEATURE_DS_LCLK_BIT) | \ 128 - (1 << FEATURE_DS_DCFCLK_BIT) | \ 129 - (1 << FEATURE_DS_UCLK_BIT) 116 + #define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \ 117 + (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 118 + (1 << FEATURE_DPM_UCLK_BIT) | \ 119 + (1 << FEATURE_DPM_FCLK_BIT) | \ 120 + (1 << FEATURE_DPM_SOCCLK_BIT) | \ 121 + (1 << FEATURE_DPM_MP0CLK_BIT) | \ 122 + (1 << FEATURE_DPM_LINK_BIT) | \ 123 + (1 << FEATURE_DPM_DCN_BIT) | \ 124 + (1 << FEATURE_DS_GFXCLK_BIT) | \ 125 + (1 << FEATURE_DS_SOCCLK_BIT) | \ 126 + (1 << FEATURE_DS_FCLK_BIT) | \ 127 + (1 << FEATURE_DS_LCLK_BIT) | \ 128 + (1 << FEATURE_DS_DCFCLK_BIT) | \ 129 + (1 << FEATURE_DS_UCLK_BIT) | \ 130 + (1ULL << FEATURE_DS_VCN_BIT)) 130 131 131 132 //For use with feature control messages 132 133 typedef enum {
+2 -2
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
··· 28 28 #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29 29 #define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04 30 30 #define SMU13_DRIVER_IF_VERSION_ALDE 0x08 31 - #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0 0x34 31 + #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0 0x37 32 32 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x07 33 33 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04 34 34 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10 0x32 35 - #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x35 35 + #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x37 36 36 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_10 0x1D 37 37 38 38 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
+6
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
··· 407 407 struct amdgpu_device *adev = smu->adev; 408 408 int ret = 0; 409 409 410 + if (amdgpu_sriov_vf(smu->adev)) 411 + return 0; 412 + 410 413 ret = smu_v13_0_0_get_pptable_from_pmfw(smu, 411 414 &smu_table->power_play_table, 412 415 &smu_table->power_play_table_size); ··· 1259 1256 struct smu_13_0_0_powerplay_table *powerplay_table = 1260 1257 table_context->power_play_table; 1261 1258 PPTable_t *pptable = smu->smu_table.driver_pptable; 1259 + 1260 + if (amdgpu_sriov_vf(smu->adev)) 1261 + return 0; 1262 1262 1263 1263 if (!range) 1264 1264 return -EINVAL;
+1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
··· 124 124 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0), 125 125 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 126 126 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0), 127 + MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 127 128 }; 128 129 129 130 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
+20 -13
drivers/gpu/drm/drm_client.c
··· 233 233 234 234 static void drm_client_buffer_delete(struct drm_client_buffer *buffer) 235 235 { 236 - struct drm_device *dev = buffer->client->dev; 237 - 238 236 if (buffer->gem) { 239 237 drm_gem_vunmap_unlocked(buffer->gem, &buffer->map); 240 238 drm_gem_object_put(buffer->gem); 241 239 } 242 240 243 - if (buffer->handle) 244 - drm_mode_destroy_dumb(dev, buffer->handle, buffer->client->file); 245 - 246 241 kfree(buffer); 247 242 } 248 243 249 244 static struct drm_client_buffer * 250 - drm_client_buffer_create(struct drm_client_dev *client, u32 width, u32 height, u32 format) 245 + drm_client_buffer_create(struct drm_client_dev *client, u32 width, u32 height, 246 + u32 format, u32 *handle) 251 247 { 252 248 const struct drm_format_info *info = drm_format_info(format); 253 249 struct drm_mode_create_dumb dumb_args = { }; ··· 265 269 if (ret) 266 270 goto err_delete; 267 271 268 - buffer->handle = dumb_args.handle; 269 - buffer->pitch = dumb_args.pitch; 270 - 271 272 obj = drm_gem_object_lookup(client->file, dumb_args.handle); 272 273 if (!obj) { 273 274 ret = -ENOENT; 274 275 goto err_delete; 275 276 } 276 277 278 + buffer->pitch = dumb_args.pitch; 277 279 buffer->gem = obj; 280 + *handle = dumb_args.handle; 278 281 279 282 return buffer; 280 283 ··· 360 365 } 361 366 362 367 static int drm_client_buffer_addfb(struct drm_client_buffer *buffer, 363 - u32 width, u32 height, u32 format) 368 + u32 width, u32 height, u32 format, 369 + u32 handle) 364 370 { 365 371 struct drm_client_dev *client = buffer->client; 366 372 struct drm_mode_fb_cmd fb_req = { }; ··· 373 377 fb_req.depth = info->depth; 374 378 fb_req.width = width; 375 379 fb_req.height = height; 376 - fb_req.handle = buffer->handle; 380 + fb_req.handle = handle; 377 381 fb_req.pitch = buffer->pitch; 378 382 379 383 ret = drm_mode_addfb(client->dev, &fb_req, client->file); ··· 410 414 drm_client_framebuffer_create(struct drm_client_dev *client, u32 width, u32 height, u32 format) 411 415 { 412 416 struct drm_client_buffer *buffer; 417 + u32 handle; 413 418 int ret; 414 419 415 - buffer = drm_client_buffer_create(client, width, height, format); 420 + buffer = drm_client_buffer_create(client, width, height, format, 421 + &handle); 416 422 if (IS_ERR(buffer)) 417 423 return buffer; 418 424 419 - ret = drm_client_buffer_addfb(buffer, width, height, format); 425 + ret = drm_client_buffer_addfb(buffer, width, height, format, handle); 426 + 427 + /* 428 + * The handle is only needed for creating the framebuffer, destroy it 429 + * again to solve a circular dependency should anybody export the GEM 430 + * object as DMA-buf. The framebuffer and our buffer structure are still 431 + * holding references to the GEM object to prevent its destruction. 432 + */ 433 + drm_mode_destroy_dumb(client->dev, handle, client->file); 434 + 420 435 if (ret) { 421 436 drm_client_buffer_delete(buffer); 422 437 return ERR_PTR(ret);
+23 -10
drivers/gpu/drm/i915/display/intel_bios.c
··· 2466 2466 dvo_port); 2467 2467 } 2468 2468 2469 + static enum port 2470 + dsi_dvo_port_to_port(struct drm_i915_private *i915, u8 dvo_port) 2471 + { 2472 + switch (dvo_port) { 2473 + case DVO_PORT_MIPIA: 2474 + return PORT_A; 2475 + case DVO_PORT_MIPIC: 2476 + if (DISPLAY_VER(i915) >= 11) 2477 + return PORT_B; 2478 + else 2479 + return PORT_C; 2480 + default: 2481 + return PORT_NONE; 2482 + } 2483 + } 2484 + 2469 2485 static int parse_bdb_230_dp_max_link_rate(const int vbt_max_link_rate) 2470 2486 { 2471 2487 switch (vbt_max_link_rate) { ··· 3430 3414 3431 3415 dvo_port = child->dvo_port; 3432 3416 3433 - if (dvo_port == DVO_PORT_MIPIA || 3434 - (dvo_port == DVO_PORT_MIPIB && DISPLAY_VER(i915) >= 11) || 3435 - (dvo_port == DVO_PORT_MIPIC && DISPLAY_VER(i915) < 11)) { 3436 - if (port) 3437 - *port = dvo_port - DVO_PORT_MIPIA; 3438 - return true; 3439 - } else if (dvo_port == DVO_PORT_MIPIB || 3440 - dvo_port == DVO_PORT_MIPIC || 3441 - dvo_port == DVO_PORT_MIPID) { 3417 + if (dsi_dvo_port_to_port(i915, dvo_port) == PORT_NONE) { 3442 3418 drm_dbg_kms(&i915->drm, 3443 3419 "VBT has unsupported DSI port %c\n", 3444 3420 port_name(dvo_port - DVO_PORT_MIPIA)); 3421 + continue; 3445 3422 } 3423 + 3424 + if (port) 3425 + *port = dsi_dvo_port_to_port(i915, dvo_port); 3426 + return true; 3446 3427 } 3447 3428 3448 3429 return false; ··· 3524 3511 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) 3525 3512 continue; 3526 3513 3527 - if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) { 3514 + if (dsi_dvo_port_to_port(i915, child->dvo_port) == encoder->port) { 3528 3515 if (!devdata->dsc) 3529 3516 return false; 3530 3517
+12
drivers/gpu/drm/i915/display/intel_fbdev.c
··· 328 328 return ret; 329 329 } 330 330 331 + static int intelfb_dirty(struct drm_fb_helper *helper, struct drm_clip_rect *clip) 332 + { 333 + if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2)) 334 + return 0; 335 + 336 + if (helper->fb->funcs->dirty) 337 + return helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1); 338 + 339 + return 0; 340 + } 341 + 331 342 static const struct drm_fb_helper_funcs intel_fb_helper_funcs = { 332 343 .fb_probe = intelfb_create, 344 + .fb_dirty = intelfb_dirty, 333 345 }; 334 346 335 347 static void intel_fbdev_destroy(struct intel_fbdev *ifbdev)
+2 -1
drivers/gpu/drm/i915/display/skl_watermark.c
··· 1587 1587 skl_check_wm_level(&wm->wm[level], ddb); 1588 1588 1589 1589 if (icl_need_wm1_wa(i915, plane_id) && 1590 - level == 1 && wm->wm[0].enable) { 1590 + level == 1 && !wm->wm[level].enable && 1591 + wm->wm[0].enable) { 1591 1592 wm->wm[level].blocks = wm->wm[0].blocks; 1592 1593 wm->wm[level].lines = wm->wm[0].lines; 1593 1594 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+7 -7
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
··· 3483 3483 eb.composite_fence : 3484 3484 &eb.requests[0]->fence); 3485 3485 3486 + if (unlikely(eb.gem_context->syncobj)) { 3487 + drm_syncobj_replace_fence(eb.gem_context->syncobj, 3488 + eb.composite_fence ? 3489 + eb.composite_fence : 3490 + &eb.requests[0]->fence); 3491 + } 3492 + 3486 3493 if (out_fence) { 3487 3494 if (err == 0) { 3488 3495 fd_install(out_fence_fd, out_fence->file); ··· 3499 3492 } else { 3500 3493 fput(out_fence->file); 3501 3494 } 3502 - } 3503 - 3504 - if (unlikely(eb.gem_context->syncobj)) { 3505 - drm_syncobj_replace_fence(eb.gem_context->syncobj, 3506 - eb.composite_fence ? 3507 - eb.composite_fence : 3508 - &eb.requests[0]->fence); 3509 3495 } 3510 3496 3511 3497 if (!out_fence && eb.composite_fence)
+1 -1
drivers/gpu/drm/i915/gem/i915_gem_shmem.c
··· 579 579 mapping_set_gfp_mask(mapping, mask); 580 580 GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM)); 581 581 582 - i915_gem_object_init(obj, &i915_gem_shmem_ops, &lock_class, 0); 582 + i915_gem_object_init(obj, &i915_gem_shmem_ops, &lock_class, flags); 583 583 obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE; 584 584 obj->write_domain = I915_GEM_DOMAIN_CPU; 585 585 obj->read_domains = I915_GEM_DOMAIN_CPU;
+1 -4
drivers/gpu/drm/virtio/virtgpu_ioctl.c
··· 126 126 void __user *user_bo_handles = NULL; 127 127 struct virtio_gpu_object_array *buflist = NULL; 128 128 struct sync_file *sync_file; 129 - int in_fence_fd = exbuf->fence_fd; 130 129 int out_fence_fd = -1; 131 130 void *buf; 132 131 uint64_t fence_ctx; ··· 151 152 ring_idx = exbuf->ring_idx; 152 153 } 153 154 154 - exbuf->fence_fd = -1; 155 - 156 155 virtio_gpu_create_context(dev, file); 157 156 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) { 158 157 struct dma_fence *in_fence; 159 158 160 - in_fence = sync_file_get_fence(in_fence_fd); 159 + in_fence = sync_file_get_fence(exbuf->fence_fd); 161 160 162 161 if (!in_fence) 163 162 return -EINVAL;
+42 -39
drivers/video/fbdev/nvidia/nvidia.c
··· 1197 1197 return nvidiafb_check_var(&info->var, info); 1198 1198 } 1199 1199 1200 - static u32 nvidia_get_chipset(struct fb_info *info) 1200 + static u32 nvidia_get_chipset(struct pci_dev *pci_dev, 1201 + volatile u32 __iomem *REGS) 1201 1202 { 1202 - struct nvidia_par *par = info->par; 1203 - u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device; 1203 + u32 id = (pci_dev->vendor << 16) | pci_dev->device; 1204 1204 1205 1205 printk(KERN_INFO PFX "Device ID: %x \n", id); 1206 1206 1207 1207 if ((id & 0xfff0) == 0x00f0 || 1208 1208 (id & 0xfff0) == 0x02e0) { 1209 1209 /* pci-e */ 1210 - id = NV_RD32(par->REGS, 0x1800); 1210 + id = NV_RD32(REGS, 0x1800); 1211 1211 1212 1212 if ((id & 0x0000ffff) == 0x000010DE) 1213 1213 id = 0x10DE0000 | (id >> 16); ··· 1220 1220 return id; 1221 1221 } 1222 1222 1223 - static u32 nvidia_get_arch(struct fb_info *info) 1223 + static u32 nvidia_get_arch(u32 Chipset) 1224 1224 { 1225 - struct nvidia_par *par = info->par; 1226 1225 u32 arch = 0; 1227 1226 1228 - switch (par->Chipset & 0x0ff0) { 1227 + switch (Chipset & 0x0ff0) { 1229 1228 case 0x0100: /* GeForce 256 */ 1230 1229 case 0x0110: /* GeForce2 MX */ 1231 1230 case 0x0150: /* GeForce2 */ ··· 1277 1278 struct fb_info *info; 1278 1279 unsigned short cmd; 1279 1280 int ret; 1281 + volatile u32 __iomem *REGS; 1282 + int Chipset; 1283 + u32 Architecture; 1280 1284 1281 1285 NVTRACE_ENTER(); 1282 1286 assert(pd != NULL); 1283 1287 1288 + if (pci_enable_device(pd)) { 1289 + printk(KERN_ERR PFX "cannot enable PCI device\n"); 1290 + return -ENODEV; 1291 + } 1292 + 1293 + /* enable IO and mem if not already done */ 1294 + pci_read_config_word(pd, PCI_COMMAND, &cmd); 1295 + cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1296 + pci_write_config_word(pd, PCI_COMMAND, cmd); 1297 + 1298 + nvidiafb_fix.mmio_start = pci_resource_start(pd, 0); 1299 + nvidiafb_fix.mmio_len = pci_resource_len(pd, 0); 1300 + 1301 + REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); 1302 + if (!REGS) { 1303 + printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1304 + return -ENODEV; 1305 + } 1306 + 1307 + Chipset = nvidia_get_chipset(pd, REGS); 1308 + Architecture = nvidia_get_arch(Chipset); 1309 + if (Architecture == 0) { 1310 + printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1311 + goto err_out; 1312 + } 1313 + 1284 1314 ret = aperture_remove_conflicting_pci_devices(pd, "nvidiafb"); 1285 1315 if (ret) 1286 - return ret; 1316 + goto err_out; 1287 1317 1288 1318 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev); 1289 - 1290 1319 if (!info) 1291 1320 goto err_out; 1292 1321 ··· 1324 1297 1325 1298 if (info->pixmap.addr == NULL) 1326 1299 goto err_out_kfree; 1327 - 1328 - if (pci_enable_device(pd)) { 1329 - printk(KERN_ERR PFX "cannot enable PCI device\n"); 1330 - goto err_out_enable; 1331 - } 1332 1300 1333 1301 if (pci_request_regions(pd, "nvidiafb")) { 1334 1302 printk(KERN_ERR PFX "cannot request PCI regions\n"); ··· 1340 1318 par->paneltweak = paneltweak; 1341 1319 par->reverse_i2c = reverse_i2c; 1342 1320 1343 - /* enable IO and mem if not already done */ 1344 - pci_read_config_word(pd, PCI_COMMAND, &cmd); 1345 - cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1346 - pci_write_config_word(pd, PCI_COMMAND, cmd); 1347 - 1348 - nvidiafb_fix.mmio_start = pci_resource_start(pd, 0); 1349 1321 nvidiafb_fix.smem_start = pci_resource_start(pd, 1); 1350 - nvidiafb_fix.mmio_len = pci_resource_len(pd, 0); 1351 1322 1352 - par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); 1323 + par->REGS = REGS; 1353 1324 1354 - if (!par->REGS) { 1355 - printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1356 - goto err_out_free_base0; 1357 - } 1358 - 1359 - par->Chipset = nvidia_get_chipset(info); 1360 - par->Architecture = nvidia_get_arch(info); 1361 - 1362 - if (par->Architecture == 0) { 1363 - printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1364 - goto err_out_arch; 1365 - } 1325 + par->Chipset = Chipset; 1326 + par->Architecture = Architecture; 1366 1327 1367 1328 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1368 1329 1369 1330 if (NVCommonSetup(info)) 1370 - goto err_out_arch; 1331 + goto err_out_free_base0; 1371 1332 1372 1333 par->FbAddress = nvidiafb_fix.smem_start; 1373 1334 par->FbMapSize = par->RamAmountKBytes * 1024; ··· 1406 1401 goto err_out_iounmap_fb; 1407 1402 } 1408 1403 1409 - 1410 1404 printk(KERN_INFO PFX 1411 1405 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n", 1412 1406 info->fix.id, ··· 1419 1415 err_out_free_base1: 1420 1416 fb_destroy_modedb(info->monspecs.modedb); 1421 1417 nvidia_delete_i2c_busses(par); 1422 - err_out_arch: 1423 - iounmap(par->REGS); 1424 - err_out_free_base0: 1418 + err_out_free_base0: 1425 1419 pci_release_regions(pd); 1426 1420 err_out_enable: 1427 1421 kfree(info->pixmap.addr); 1428 1422 err_out_kfree: 1429 1423 framebuffer_release(info); 1430 1424 err_out: 1425 + iounmap(REGS); 1431 1426 return -ENODEV; 1432 1427 } 1433 1428
-5
include/drm/drm_client.h
··· 127 127 struct drm_client_dev *client; 128 128 129 129 /** 130 - * @handle: Buffer handle 131 - */ 132 - u32 handle; 133 - 134 - /** 135 130 * @pitch: Buffer pitch 136 131 */ 137 132 u32 pitch;
+1
include/uapi/drm/virtgpu_drm.h
··· 64 64 __u32 pad; 65 65 }; 66 66 67 + /* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */ 67 68 struct drm_virtgpu_execbuffer { 68 69 __u32 flags; 69 70 __u32 size;