tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2022-04-29' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Another relatively quiet week, amdgpu leads the way, some i915 display
fixes, and a single sunxi fix.

amdgpu:
- Runtime pm fix
- DCN memory leak fix in error path
- SI DPM deadlock fix
- S0ix fix

amdkfd:
- GWS fix
- GWS support for CRIU

i915:
- Fix #5284: Backlight control regression on XMG Core 15 e21
- Fix black display plane on Acer One AO532h
- Two smaller display fixes

sunxi:
- Single fix removing applying PHYS_OFFSET twice"

* tag 'drm-fixes-2022-04-29' of git://anongit.freedesktop.org/drm/drm:
drm/amdgpu: keep mmhub clock gating being enabled during s2idle suspend
drm/amd/pm: fix the deadlock issue observed on SI
drm/amd/display: Fix memory leak in dcn21_clock_source_create
drm/amdgpu: don't runtime suspend if there are displays attached (v3)
drm/amdkfd: CRIU add support for GWS queues
drm/amdkfd: Fix GWS queue count
drm/sun4i: Remove obsolete references to PHYS_OFFSET
drm/i915/fbc: Consult hw.crtc instead of uapi.crtc
drm/i915: Fix SEL_FETCH_PLANE_*(PIPE_B+) register addresses
drm/i915: Check EDID for HDR static metadata when choosing blc
drm/i915: Fix DISP_POS_Y and DISP_HEIGHT defines

Linus Torvalds 38d741cb 249aca0d

+195 -155
+70 -35
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 2395 2395 return amdgpu_device_resume(drm_dev, true); 2396 2396 } 2397 2397 2398 + static int amdgpu_runtime_idle_check_display(struct device *dev) 2399 + { 2400 + struct pci_dev *pdev = to_pci_dev(dev); 2401 + struct drm_device *drm_dev = pci_get_drvdata(pdev); 2402 + struct amdgpu_device *adev = drm_to_adev(drm_dev); 2403 + 2404 + if (adev->mode_info.num_crtc) { 2405 + struct drm_connector *list_connector; 2406 + struct drm_connector_list_iter iter; 2407 + int ret = 0; 2408 + 2409 + /* XXX: Return busy if any displays are connected to avoid 2410 + * possible display wakeups after runtime resume due to 2411 + * hotplug events in case any displays were connected while 2412 + * the GPU was in suspend. Remove this once that is fixed. 2413 + */ 2414 + mutex_lock(&drm_dev->mode_config.mutex); 2415 + drm_connector_list_iter_begin(drm_dev, &iter); 2416 + drm_for_each_connector_iter(list_connector, &iter) { 2417 + if (list_connector->status == connector_status_connected) { 2418 + ret = -EBUSY; 2419 + break; 2420 + } 2421 + } 2422 + drm_connector_list_iter_end(&iter); 2423 + mutex_unlock(&drm_dev->mode_config.mutex); 2424 + 2425 + if (ret) 2426 + return ret; 2427 + 2428 + if (amdgpu_device_has_dc_support(adev)) { 2429 + struct drm_crtc *crtc; 2430 + 2431 + drm_for_each_crtc(crtc, drm_dev) { 2432 + drm_modeset_lock(&crtc->mutex, NULL); 2433 + if (crtc->state->active) 2434 + ret = -EBUSY; 2435 + drm_modeset_unlock(&crtc->mutex); 2436 + if (ret < 0) 2437 + break; 2438 + } 2439 + } else { 2440 + mutex_lock(&drm_dev->mode_config.mutex); 2441 + drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2442 + 2443 + drm_connector_list_iter_begin(drm_dev, &iter); 2444 + drm_for_each_connector_iter(list_connector, &iter) { 2445 + if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2446 + ret = -EBUSY; 2447 + break; 2448 + } 2449 + } 2450 + 2451 + drm_connector_list_iter_end(&iter); 2452 + 2453 + drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2454 + mutex_unlock(&drm_dev->mode_config.mutex); 2455 + } 2456 + if (ret) 2457 + return ret; 2458 + } 2459 + 2460 + return 0; 2461 + } 2462 + 2398 2463 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2399 2464 { 2400 2465 struct pci_dev *pdev = to_pci_dev(dev); ··· 2471 2406 pm_runtime_forbid(dev); 2472 2407 return -EBUSY; 2473 2408 } 2409 + 2410 + ret = amdgpu_runtime_idle_check_display(dev); 2411 + if (ret) 2412 + return ret; 2474 2413 2475 2414 /* wait for all rings to drain before suspending */ 2476 2415 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { ··· 2585 2516 return -EBUSY; 2586 2517 } 2587 2518 2588 - if (amdgpu_device_has_dc_support(adev)) { 2589 - struct drm_crtc *crtc; 2590 - 2591 - drm_for_each_crtc(crtc, drm_dev) { 2592 - drm_modeset_lock(&crtc->mutex, NULL); 2593 - if (crtc->state->active) 2594 - ret = -EBUSY; 2595 - drm_modeset_unlock(&crtc->mutex); 2596 - if (ret < 0) 2597 - break; 2598 - } 2599 - 2600 - } else { 2601 - struct drm_connector *list_connector; 2602 - struct drm_connector_list_iter iter; 2603 - 2604 - mutex_lock(&drm_dev->mode_config.mutex); 2605 - drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2606 - 2607 - drm_connector_list_iter_begin(drm_dev, &iter); 2608 - drm_for_each_connector_iter(list_connector, &iter) { 2609 - if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2610 - ret = -EBUSY; 2611 - break; 2612 - } 2613 - } 2614 - 2615 - drm_connector_list_iter_end(&iter); 2616 - 2617 - drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2618 - mutex_unlock(&drm_dev->mode_config.mutex); 2619 - } 2620 - 2621 - if (ret == -EBUSY) 2622 - DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 2519 + ret = amdgpu_runtime_idle_check_display(dev); 2623 2520 2624 2521 pm_runtime_mark_last_busy(dev); 2625 2522 pm_runtime_autosuspend(dev);
+10
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
··· 1151 1151 int r; 1152 1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1153 1153 1154 + /* 1155 + * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1156 + * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1157 + * seen any issue on the DF 3.0.2 series platform. 1158 + */ 1159 + if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) { 1160 + dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1161 + return 0; 1162 + } 1163 + 1154 1164 r = adev->mmhub.funcs->set_clockgating(adev, state); 1155 1165 if (r) 1156 1166 return r;
+37 -46
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
··· 130 130 } 131 131 132 132 static void increment_queue_count(struct device_queue_manager *dqm, 133 - enum kfd_queue_type type) 133 + struct qcm_process_device *qpd, 134 + struct queue *q) 134 135 { 135 136 dqm->active_queue_count++; 136 - if (type == KFD_QUEUE_TYPE_COMPUTE || type == KFD_QUEUE_TYPE_DIQ) 137 + if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 138 + q->properties.type == KFD_QUEUE_TYPE_DIQ) 137 139 dqm->active_cp_queue_count++; 140 + 141 + if (q->properties.is_gws) { 142 + dqm->gws_queue_count++; 143 + qpd->mapped_gws_queue = true; 144 + } 138 145 } 139 146 140 147 static void decrement_queue_count(struct device_queue_manager *dqm, 141 - enum kfd_queue_type type) 148 + struct qcm_process_device *qpd, 149 + struct queue *q) 142 150 { 143 151 dqm->active_queue_count--; 144 - if (type == KFD_QUEUE_TYPE_COMPUTE || type == KFD_QUEUE_TYPE_DIQ) 152 + if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 153 + q->properties.type == KFD_QUEUE_TYPE_DIQ) 145 154 dqm->active_cp_queue_count--; 155 + 156 + if (q->properties.is_gws) { 157 + dqm->gws_queue_count--; 158 + qpd->mapped_gws_queue = false; 159 + } 146 160 } 147 161 148 162 /* ··· 426 412 list_add(&q->list, &qpd->queues_list); 427 413 qpd->queue_count++; 428 414 if (q->properties.is_active) 429 - increment_queue_count(dqm, q->properties.type); 415 + increment_queue_count(dqm, qpd, q); 430 416 431 417 /* 432 418 * Unconditionally increment this counter, regardless of the queue's ··· 615 601 deallocate_vmid(dqm, qpd, q); 616 602 } 617 603 qpd->queue_count--; 618 - if (q->properties.is_active) { 619 - decrement_queue_count(dqm, q->properties.type); 620 - if (q->properties.is_gws) { 621 - dqm->gws_queue_count--; 622 - qpd->mapped_gws_queue = false; 623 - } 624 - } 604 + if (q->properties.is_active) 605 + decrement_queue_count(dqm, qpd, q); 625 606 626 607 return retval; 627 608 } ··· 709 700 * dqm->active_queue_count to determine whether a new runlist must be 710 701 * uploaded. 711 702 */ 712 - if (q->properties.is_active && !prev_active) 713 - increment_queue_count(dqm, q->properties.type); 714 - else if (!q->properties.is_active && prev_active) 715 - decrement_queue_count(dqm, q->properties.type); 716 - 717 - if (q->gws && !q->properties.is_gws) { 703 + if (q->properties.is_active && !prev_active) { 704 + increment_queue_count(dqm, &pdd->qpd, q); 705 + } else if (!q->properties.is_active && prev_active) { 706 + decrement_queue_count(dqm, &pdd->qpd, q); 707 + } else if (q->gws && !q->properties.is_gws) { 718 708 if (q->properties.is_active) { 719 709 dqm->gws_queue_count++; 720 710 pdd->qpd.mapped_gws_queue = true; ··· 775 767 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 776 768 q->properties.type)]; 777 769 q->properties.is_active = false; 778 - decrement_queue_count(dqm, q->properties.type); 779 - if (q->properties.is_gws) { 780 - dqm->gws_queue_count--; 781 - qpd->mapped_gws_queue = false; 782 - } 770 + decrement_queue_count(dqm, qpd, q); 783 771 784 772 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n")) 785 773 continue; ··· 821 817 continue; 822 818 823 819 q->properties.is_active = false; 824 - decrement_queue_count(dqm, q->properties.type); 820 + decrement_queue_count(dqm, qpd, q); 825 821 } 826 822 pdd->last_evict_timestamp = get_jiffies_64(); 827 823 retval = execute_queues_cpsch(dqm, ··· 892 888 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 893 889 q->properties.type)]; 894 890 q->properties.is_active = true; 895 - increment_queue_count(dqm, q->properties.type); 896 - if (q->properties.is_gws) { 897 - dqm->gws_queue_count++; 898 - qpd->mapped_gws_queue = true; 899 - } 891 + increment_queue_count(dqm, qpd, q); 900 892 901 893 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n")) 902 894 continue; ··· 950 950 continue; 951 951 952 952 q->properties.is_active = true; 953 - increment_queue_count(dqm, q->properties.type); 953 + increment_queue_count(dqm, &pdd->qpd, q); 954 954 } 955 955 retval = execute_queues_cpsch(dqm, 956 956 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); ··· 1378 1378 dqm->total_queue_count); 1379 1379 1380 1380 list_add(&kq->list, &qpd->priv_queue_list); 1381 - increment_queue_count(dqm, kq->queue->properties.type); 1381 + increment_queue_count(dqm, qpd, kq->queue); 1382 1382 qpd->is_debug = true; 1383 1383 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1384 1384 dqm_unlock(dqm); ··· 1392 1392 { 1393 1393 dqm_lock(dqm); 1394 1394 list_del(&kq->list); 1395 - decrement_queue_count(dqm, kq->queue->properties.type); 1395 + decrement_queue_count(dqm, qpd, kq->queue); 1396 1396 qpd->is_debug = false; 1397 1397 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); 1398 1398 /* ··· 1467 1467 qpd->queue_count++; 1468 1468 1469 1469 if (q->properties.is_active) { 1470 - increment_queue_count(dqm, q->properties.type); 1470 + increment_queue_count(dqm, qpd, q); 1471 1471 1472 1472 execute_queues_cpsch(dqm, 1473 1473 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); ··· 1683 1683 list_del(&q->list); 1684 1684 qpd->queue_count--; 1685 1685 if (q->properties.is_active) { 1686 - decrement_queue_count(dqm, q->properties.type); 1686 + decrement_queue_count(dqm, qpd, q); 1687 1687 retval = execute_queues_cpsch(dqm, 1688 1688 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1689 1689 if (retval == -ETIME) 1690 1690 qpd->reset_wavefronts = true; 1691 - if (q->properties.is_gws) { 1692 - dqm->gws_queue_count--; 1693 - qpd->mapped_gws_queue = false; 1694 - } 1695 1691 } 1696 1692 1697 1693 /* ··· 1928 1932 /* Clean all kernel queues */ 1929 1933 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) { 1930 1934 list_del(&kq->list); 1931 - decrement_queue_count(dqm, kq->queue->properties.type); 1935 + decrement_queue_count(dqm, qpd, kq->queue); 1932 1936 qpd->is_debug = false; 1933 1937 dqm->total_queue_count--; 1934 1938 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES; ··· 1941 1945 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 1942 1946 deallocate_sdma_queue(dqm, q); 1943 1947 1944 - if (q->properties.is_active) { 1945 - decrement_queue_count(dqm, q->properties.type); 1946 - if (q->properties.is_gws) { 1947 - dqm->gws_queue_count--; 1948 - qpd->mapped_gws_queue = false; 1949 - } 1950 - } 1948 + if (q->properties.is_active) 1949 + decrement_queue_count(dqm, qpd, q); 1951 1950 1952 1951 dqm->total_queue_count--; 1953 1952 }
+1 -1
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
··· 1103 1103 uint32_t priority; 1104 1104 uint32_t q_percent; 1105 1105 uint32_t doorbell_id; 1106 - uint32_t is_gws; 1106 + uint32_t gws; 1107 1107 uint32_t sdma_id; 1108 1108 uint32_t eop_ring_buffer_size; 1109 1109 uint32_t ctx_save_restore_area_size;
+7 -3
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
··· 636 636 q_data->ctx_save_restore_area_size = 637 637 q->properties.ctx_save_restore_area_size; 638 638 639 + q_data->gws = !!q->gws; 640 + 639 641 ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack); 640 642 if (ret) { 641 643 pr_err("Failed checkpoint queue_mqd (%d)\n", ret); ··· 745 743 struct kfd_criu_queue_priv_data *q_data) 746 744 { 747 745 qp->is_interop = false; 748 - qp->is_gws = q_data->is_gws; 749 746 qp->queue_percent = q_data->q_percent; 750 747 qp->priority = q_data->priority; 751 748 qp->queue_address = q_data->q_address; ··· 827 826 NULL); 828 827 if (ret) { 829 828 pr_err("Failed to create new queue err:%d\n", ret); 830 - ret = -EINVAL; 829 + goto exit; 831 830 } 831 + 832 + if (q_data->gws) 833 + ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws); 832 834 833 835 exit: 834 836 if (ret) 835 - pr_err("Failed to create queue (%d)\n", ret); 837 + pr_err("Failed to restore queue (%d)\n", ret); 836 838 else 837 839 pr_debug("Queue id %d was restored successfully\n", queue_id); 838 840
+1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
··· 997 997 return &clk_src->base; 998 998 } 999 999 1000 + kfree(clk_src); 1000 1001 BREAK_TO_DEBUGGER(); 1001 1002 return NULL; 1002 1003 }
+39
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
··· 427 427 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) 428 428 { 429 429 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 430 + int i; 430 431 431 432 if (!adev->pm.dpm_enabled) 432 433 return; 433 434 434 435 if (!pp_funcs->pm_compute_clocks) 435 436 return; 437 + 438 + if (adev->mode_info.num_crtc) 439 + amdgpu_display_bandwidth_update(adev); 440 + 441 + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 442 + struct amdgpu_ring *ring = adev->rings[i]; 443 + if (ring && ring->sched.ready) 444 + amdgpu_fence_wait_empty(ring); 445 + } 436 446 437 447 mutex_lock(&adev->pm.mutex); 438 448 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); ··· 453 443 { 454 444 int ret = 0; 455 445 446 + if (adev->family == AMDGPU_FAMILY_SI) { 447 + mutex_lock(&adev->pm.mutex); 448 + if (enable) { 449 + adev->pm.dpm.uvd_active = true; 450 + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; 451 + } else { 452 + adev->pm.dpm.uvd_active = false; 453 + } 454 + mutex_unlock(&adev->pm.mutex); 455 + 456 + amdgpu_dpm_compute_clocks(adev); 457 + return; 458 + } 459 + 456 460 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); 457 461 if (ret) 458 462 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", ··· 476 452 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) 477 453 { 478 454 int ret = 0; 455 + 456 + if (adev->family == AMDGPU_FAMILY_SI) { 457 + mutex_lock(&adev->pm.mutex); 458 + if (enable) { 459 + adev->pm.dpm.vce_active = true; 460 + /* XXX select vce level based on ring/task */ 461 + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; 462 + } else { 463 + adev->pm.dpm.vce_active = false; 464 + } 465 + mutex_unlock(&adev->pm.mutex); 466 + 467 + amdgpu_dpm_compute_clocks(adev); 468 + return; 469 + } 479 470 480 471 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); 481 472 if (ret)
-10
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
··· 1028 1028 void amdgpu_legacy_dpm_compute_clocks(void *handle) 1029 1029 { 1030 1030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1031 - int i = 0; 1032 - 1033 - if (adev->mode_info.num_crtc) 1034 - amdgpu_display_bandwidth_update(adev); 1035 - 1036 - for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1037 - struct amdgpu_ring *ring = adev->rings[i]; 1038 - if (ring && ring->sched.ready) 1039 - amdgpu_fence_wait_empty(ring); 1040 - } 1041 1031 1042 1032 amdgpu_dpm_get_active_displays(adev); 1043 1033
-35
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
··· 3892 3892 } 3893 3893 #endif 3894 3894 3895 - static int si_set_powergating_by_smu(void *handle, 3896 - uint32_t block_type, 3897 - bool gate) 3898 - { 3899 - struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3900 - 3901 - switch (block_type) { 3902 - case AMD_IP_BLOCK_TYPE_UVD: 3903 - if (!gate) { 3904 - adev->pm.dpm.uvd_active = true; 3905 - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; 3906 - } else { 3907 - adev->pm.dpm.uvd_active = false; 3908 - } 3909 - 3910 - amdgpu_legacy_dpm_compute_clocks(handle); 3911 - break; 3912 - case AMD_IP_BLOCK_TYPE_VCE: 3913 - if (!gate) { 3914 - adev->pm.dpm.vce_active = true; 3915 - /* XXX select vce level based on ring/task */ 3916 - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; 3917 - } else { 3918 - adev->pm.dpm.vce_active = false; 3919 - } 3920 - 3921 - amdgpu_legacy_dpm_compute_clocks(handle); 3922 - break; 3923 - default: 3924 - break; 3925 - } 3926 - return 0; 3927 - } 3928 - 3929 3895 static int si_set_sw_state(struct amdgpu_device *adev) 3930 3896 { 3931 3897 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? ··· 8091 8125 .print_power_state = &si_dpm_print_power_state, 8092 8126 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 8093 8127 .force_performance_level = &si_dpm_force_performance_level, 8094 - .set_powergating_by_smu = &si_set_powergating_by_smu, 8095 8128 .vblank_too_short = &si_dpm_vblank_too_short, 8096 8129 .set_fan_control_mode = &si_dpm_set_fan_control_mode, 8097 8130 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
-10
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
··· 1487 1487 { 1488 1488 struct pp_hwmgr *hwmgr = handle; 1489 1489 struct amdgpu_device *adev = hwmgr->adev; 1490 - int i = 0; 1491 - 1492 - if (adev->mode_info.num_crtc) 1493 - amdgpu_display_bandwidth_update(adev); 1494 - 1495 - for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1496 - struct amdgpu_ring *ring = adev->rings[i]; 1497 - if (ring && ring->sched.ready) 1498 - amdgpu_fence_wait_empty(ring); 1499 - } 1500 1490 1501 1491 if (!amdgpu_device_has_dc_support(adev)) { 1502 1492 amdgpu_dpm_get_active_displays(adev);
+26 -8
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
··· 97 97 98 98 #define INTEL_EDP_BRIGHTNESS_OPTIMIZATION_1 0x359 99 99 100 + enum intel_dp_aux_backlight_modparam { 101 + INTEL_DP_AUX_BACKLIGHT_AUTO = -1, 102 + INTEL_DP_AUX_BACKLIGHT_OFF = 0, 103 + INTEL_DP_AUX_BACKLIGHT_ON = 1, 104 + INTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2, 105 + INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3, 106 + }; 107 + 100 108 /* Intel EDP backlight callbacks */ 101 109 static bool 102 110 intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector) ··· 131 123 } else { 132 124 drm_dbg_kms(&i915->drm, "Detected unsupported HDR backlight interface version %d\n", 133 125 tcon_cap[0]); 126 + return false; 127 + } 128 + 129 + /* 130 + * If we don't have HDR static metadata there is no way to 131 + * runtime detect used range for nits based control. For now 132 + * do not use Intel proprietary eDP backlight control if we 133 + * don't have this data in panel EDID. In case we find panel 134 + * which supports only nits based control, but doesn't provide 135 + * HDR static metadata we need to start maintaining table of 136 + * ranges for such panels. 137 + */ 138 + if (i915->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL && 139 + !(connector->base.hdr_sink_metadata.hdmi_type1.metadata_type & 140 + BIT(HDMI_STATIC_METADATA_TYPE1))) { 141 + drm_info(&i915->drm, 142 + "Panel is missing HDR static metadata. Possible support for Intel HDR backlight interface is not used. If your backlight controls don't work try booting with i915.enable_dpcd_backlight=%d. needs this, please file a _new_ bug report on drm/i915, see " FDO_BUG_URL " for details.\n", 143 + INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL); 134 144 return false; 135 145 } 136 146 ··· 437 411 .disable = intel_dp_aux_vesa_disable_backlight, 438 412 .set = intel_dp_aux_vesa_set_backlight, 439 413 .get = intel_dp_aux_vesa_get_backlight, 440 - }; 441 - 442 - enum intel_dp_aux_backlight_modparam { 443 - INTEL_DP_AUX_BACKLIGHT_AUTO = -1, 444 - INTEL_DP_AUX_BACKLIGHT_OFF = 0, 445 - INTEL_DP_AUX_BACKLIGHT_ON = 1, 446 - INTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2, 447 - INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3, 448 414 }; 449 415 450 416 int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
+1 -1
drivers/gpu/drm/i915/display/intel_fbc.c
··· 1037 1037 struct intel_plane_state *plane_state = 1038 1038 intel_atomic_get_new_plane_state(state, plane); 1039 1039 const struct drm_framebuffer *fb = plane_state->hw.fb; 1040 - struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc); 1040 + struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); 1041 1041 const struct intel_crtc_state *crtc_state; 1042 1042 struct intel_fbc *fbc = plane->fbc; 1043 1043
+3 -3
drivers/gpu/drm/i915/i915_reg.h
··· 4345 4345 #define _DSPAADDR 0x70184 4346 4346 #define _DSPASTRIDE 0x70188 4347 4347 #define _DSPAPOS 0x7018C /* reserved */ 4348 - #define DISP_POS_Y_MASK REG_GENMASK(31, 0) 4348 + #define DISP_POS_Y_MASK REG_GENMASK(31, 16) 4349 4349 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 4350 4350 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 4351 4351 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 4352 4352 #define _DSPASIZE 0x70190 4353 - #define DISP_HEIGHT_MASK REG_GENMASK(31, 0) 4353 + #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) 4354 4354 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 4355 4355 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 4356 4356 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) ··· 5152 5152 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 5153 5153 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 5154 5154 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 5155 - #define _SEL_FETCH_PLANE_BASE_1_B 0x70990 5155 + #define _SEL_FETCH_PLANE_BASE_1_B 0x71890 5156 5156 5157 5157 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 5158 5158 _SEL_FETCH_PLANE_BASE_1_A, \
-3
drivers/gpu/drm/sun4i/sun4i_frontend.c
··· 222 222 223 223 /* Set the physical address of the buffer in memory */ 224 224 paddr = drm_fb_cma_get_gem_addr(fb, state, 0); 225 - paddr -= PHYS_OFFSET; 226 225 DRM_DEBUG_DRIVER("Setting buffer #0 address to %pad\n", &paddr); 227 226 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR0_REG, paddr); 228 227 229 228 if (fb->format->num_planes > 1) { 230 229 paddr = drm_fb_cma_get_gem_addr(fb, state, swap ? 2 : 1); 231 - paddr -= PHYS_OFFSET; 232 230 DRM_DEBUG_DRIVER("Setting buffer #1 address to %pad\n", &paddr); 233 231 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR1_REG, 234 232 paddr); ··· 234 236 235 237 if (fb->format->num_planes > 2) { 236 238 paddr = drm_fb_cma_get_gem_addr(fb, state, swap ? 1 : 2); 237 - paddr -= PHYS_OFFSET; 238 239 DRM_DEBUG_DRIVER("Setting buffer #2 address to %pad\n", &paddr); 239 240 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR2_REG, 240 241 paddr);