Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
i2c: designware: Combine the init functions
Providing a single function for controller initialisation.
The controller initialisation has the same steps for master
and slave modes, except the timing parameters are only
needed in master mode.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20260120130729.1679560-3-heikki.krogerus@linux.intel.com
authored by
Heikki Krogerus
and committed by
Andi Shyti
38fa29b0
6062443a
+85
-117
+2
-2
drivers/i2c/busses/i2c-designware-amdisp.c
+2
-2
drivers/i2c/busses/i2c-designware-amdisp.c
+79
-2
drivers/i2c/busses/i2c-designware-common.c
+79
-2
drivers/i2c/busses/i2c-designware-common.c
···
359
359
360
360
#endif /* CONFIG_ACPI */
361
361
362
+
static void i2c_dw_configure_mode(struct dw_i2c_dev *dev)
363
+
{
364
+
switch (dev->mode) {
365
+
case DW_IC_MASTER:
366
+
regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
367
+
regmap_write(dev->map, DW_IC_RX_TL, 0);
368
+
regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
369
+
break;
370
+
case DW_IC_SLAVE:
371
+
regmap_write(dev->map, DW_IC_TX_TL, 0);
372
+
regmap_write(dev->map, DW_IC_RX_TL, 0);
373
+
regmap_write(dev->map, DW_IC_CON, dev->slave_cfg);
374
+
regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK);
375
+
break;
376
+
default:
377
+
return;
378
+
}
379
+
}
380
+
381
+
static void i2c_dw_write_timings(struct dw_i2c_dev *dev)
382
+
{
383
+
/* Write standard speed timing parameters */
384
+
regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
385
+
regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
386
+
387
+
/* Write fast mode/fast mode plus timing parameters */
388
+
regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
389
+
regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
390
+
391
+
/* Write high speed timing parameters if supported */
392
+
if (dev->hs_hcnt && dev->hs_lcnt) {
393
+
regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
394
+
regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
395
+
}
396
+
}
397
+
398
+
/**
399
+
* i2c_dw_init() - Initialize the DesignWare I2C hardware
400
+
* @dev: device private data
401
+
*
402
+
* This functions configures and enables the DesigWare I2C hardware.
403
+
*
404
+
* Return: 0 on success, or negative errno otherwise.
405
+
*/
406
+
int i2c_dw_init(struct dw_i2c_dev *dev)
407
+
{
408
+
int ret;
409
+
410
+
ret = i2c_dw_acquire_lock(dev);
411
+
if (ret)
412
+
return ret;
413
+
414
+
/* Disable the adapter */
415
+
__i2c_dw_disable(dev);
416
+
417
+
/*
418
+
* Mask SMBus interrupts to block storms from broken
419
+
* firmware that leaves IC_SMBUS=1; the handler never
420
+
* services them.
421
+
*/
422
+
regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0);
423
+
424
+
if (dev->mode == DW_IC_MASTER)
425
+
i2c_dw_write_timings(dev);
426
+
427
+
/* Write SDA hold time if supported */
428
+
if (dev->sda_hold_time)
429
+
regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
430
+
431
+
i2c_dw_configure_mode(dev);
432
+
433
+
i2c_dw_release_lock(dev);
434
+
435
+
return 0;
436
+
}
437
+
EXPORT_SYMBOL_GPL(i2c_dw_init);
438
+
362
439
static void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
363
440
{
364
441
u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
···
878
801
if (ret)
879
802
return ret;
880
803
881
-
ret = dev->init(dev);
804
+
ret = i2c_dw_init(dev);
882
805
if (ret)
883
806
return ret;
884
807
···
971
894
if (!dev->shared_with_punit)
972
895
i2c_dw_prepare_clk(dev, true);
973
896
974
-
dev->init(dev);
897
+
i2c_dw_init(dev);
975
898
976
899
return 0;
977
900
}
+1
-2
drivers/i2c/busses/i2c-designware-core.h
+1
-2
drivers/i2c/busses/i2c-designware-core.h
···
253
253
* @semaphore_idx: Index of table with semaphore type attached to the bus. It's
254
254
* -1 if there is no semaphore.
255
255
* @shared_with_punit: true if this bus is shared with the SoC's PUNIT
256
-
* @init: function to initialize the I2C hardware
257
256
* @set_sda_hold_time: callback to retrieve IP specific SDA hold timing
258
257
* @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
259
258
* @rinfo: I²C GPIO recovery information
···
313
314
void (*release_lock)(void);
314
315
int semaphore_idx;
315
316
bool shared_with_punit;
316
-
int (*init)(struct dw_i2c_dev *dev);
317
317
int (*set_sda_hold_time)(struct dw_i2c_dev *dev);
318
318
int mode;
319
319
struct i2c_bus_recovery_info rinfo;
···
417
419
}
418
420
419
421
int i2c_dw_probe(struct dw_i2c_dev *dev);
422
+
int i2c_dw_init(struct dw_i2c_dev *dev);
420
423
421
424
#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
422
425
int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev);
+3
-67
drivers/i2c/busses/i2c-designware-master.c
+3
-67
drivers/i2c/busses/i2c-designware-master.c
···
31
31
#define AMD_TIMEOUT_MAX_US 250
32
32
#define AMD_MASTERCFG_MASK GENMASK(15, 0)
33
33
34
-
static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
35
-
{
36
-
/* Configure Tx/Rx FIFO threshold levels */
37
-
regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
38
-
regmap_write(dev->map, DW_IC_RX_TL, 0);
39
-
40
-
/* Configure the I2C master */
41
-
regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
42
-
}
43
-
44
34
static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
45
35
{
46
36
unsigned int comp_param1;
···
182
192
}
183
193
184
194
dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz));
185
-
return 0;
186
-
}
187
-
188
-
/**
189
-
* i2c_dw_init_master() - Initialize the DesignWare I2C master hardware
190
-
* @dev: device private data
191
-
*
192
-
* This functions configures and enables the I2C master.
193
-
* This function is called during I2C init function, and in case of timeout at
194
-
* run time.
195
-
*
196
-
* Return: 0 on success, or negative errno otherwise.
197
-
*/
198
-
static int i2c_dw_init_master(struct dw_i2c_dev *dev)
199
-
{
200
-
int ret;
201
-
202
-
ret = i2c_dw_acquire_lock(dev);
203
-
if (ret)
204
-
return ret;
205
-
206
-
/* Disable the adapter */
207
-
__i2c_dw_disable(dev);
208
-
209
-
/*
210
-
* Mask SMBus interrupts to block storms from broken
211
-
* firmware that leaves IC_SMBUS=1; the handler never
212
-
* services them.
213
-
*/
214
-
regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0);
215
-
216
-
/* Write standard speed timing parameters */
217
-
regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
218
-
regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
219
-
220
-
/* Write fast mode/fast mode plus timing parameters */
221
-
regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
222
-
regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
223
-
224
-
/* Write high speed timing parameters if supported */
225
-
if (dev->hs_hcnt && dev->hs_lcnt) {
226
-
regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
227
-
regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
228
-
}
229
-
230
-
/* Write SDA hold time if supported */
231
-
if (dev->sda_hold_time)
232
-
regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
233
-
234
-
i2c_dw_configure_fifo_master(dev);
235
-
i2c_dw_release_lock(dev);
236
-
237
195
return 0;
238
196
}
239
197
···
781
843
ret = i2c_dw_wait_transfer(dev);
782
844
if (ret) {
783
845
dev_err(dev->dev, "controller timed out\n");
784
-
/* i2c_dw_init_master() implicitly disables the adapter */
846
+
/* i2c_dw_init() implicitly disables the adapter */
785
847
i2c_recover_bus(&dev->adapter);
786
-
i2c_dw_init_master(dev);
848
+
i2c_dw_init(dev);
787
849
goto done;
788
850
}
789
851
···
888
950
889
951
i2c_dw_prepare_clk(dev, true);
890
952
reset_control_deassert(dev->rst);
891
-
i2c_dw_init_master(dev);
953
+
i2c_dw_init(dev);
892
954
}
893
955
894
956
static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
···
936
998
int ret;
937
999
938
1000
init_completion(&dev->cmd_complete);
939
-
940
-
dev->init = i2c_dw_init_master;
941
1001
942
1002
ret = i2c_dw_set_timings_master(dev);
943
1003
if (ret)
-44
drivers/i2c/busses/i2c-designware-slave.c
-44
drivers/i2c/busses/i2c-designware-slave.c
···
21
21
22
22
#include "i2c-designware-core.h"
23
23
24
-
static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev)
25
-
{
26
-
/* Configure Tx/Rx FIFO threshold levels. */
27
-
regmap_write(dev->map, DW_IC_TX_TL, 0);
28
-
regmap_write(dev->map, DW_IC_RX_TL, 0);
29
-
30
-
/* Configure the I2C slave. */
31
-
regmap_write(dev->map, DW_IC_CON, dev->slave_cfg);
32
-
regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK);
33
-
}
34
-
35
-
/**
36
-
* i2c_dw_init_slave() - Initialize the DesignWare i2c slave hardware
37
-
* @dev: device private data
38
-
*
39
-
* This function configures and enables the I2C in slave mode.
40
-
* This function is called during I2C init function, and in case of timeout at
41
-
* run time.
42
-
*
43
-
* Return: 0 on success, or negative errno otherwise.
44
-
*/
45
-
static int i2c_dw_init_slave(struct dw_i2c_dev *dev)
46
-
{
47
-
int ret;
48
-
49
-
ret = i2c_dw_acquire_lock(dev);
50
-
if (ret)
51
-
return ret;
52
-
53
-
/* Disable the adapter. */
54
-
__i2c_dw_disable(dev);
55
-
56
-
/* Write SDA hold time if supported */
57
-
if (dev->sda_hold_time)
58
-
regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
59
-
60
-
i2c_dw_configure_fifo_slave(dev);
61
-
i2c_dw_release_lock(dev);
62
-
63
-
return 0;
64
-
}
65
-
66
24
int i2c_dw_reg_slave(struct i2c_client *slave)
67
25
{
68
26
struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
···
189
231
{
190
232
if (dev->flags & ACCESS_POLLING)
191
233
return -EOPNOTSUPP;
192
-
193
-
dev->init = i2c_dw_init_slave;
194
234
195
235
return 0;
196
236
}