Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: add 64bit doorbell assignments
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Ken Wang
and committed by
Alex Deucher
39807b93
d0e95758
+68
+68
drivers/gpu/drm/amd/amdgpu/amdgpu.h
+68
drivers/gpu/drm/amd/amdgpu/amdgpu.h
···
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u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
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};
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/*
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* 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
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*/
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typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
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{
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/*
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* All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
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* a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
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* Compute related doorbells are allocated from 0x00 to 0x8a
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*/
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/* kernel scheduling */
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AMDGPU_DOORBELL64_KIQ = 0x00,
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/* HSA interface queue and debug queue */
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AMDGPU_DOORBELL64_HIQ = 0x01,
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AMDGPU_DOORBELL64_DIQ = 0x02,
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/* Compute engines */
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AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
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AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
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AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
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AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
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AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
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AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
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AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
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AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
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/* User queue doorbell range (128 doorbells) */
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AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
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AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
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/* Graphics engine */
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AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
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/*
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* Other graphics doorbells can be allocated here: from 0x8c to 0xef
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* Graphics voltage island aperture 1
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* default non-graphics QWORD index is 0xF0 - 0xFF inclusive
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*/
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/* sDMA engines */
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AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
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AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
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/* Interrupt handler */
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AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
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AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
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AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
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/* VCN engine */
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AMDGPU_DOORBELL64_VCN0 = 0xF8,
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AMDGPU_DOORBELL64_VCN1 = 0xF9,
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AMDGPU_DOORBELL64_VCN2 = 0xFA,
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AMDGPU_DOORBELL64_VCN3 = 0xFB,
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AMDGPU_DOORBELL64_VCN4 = 0xFC,
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AMDGPU_DOORBELL64_VCN5 = 0xFD,
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AMDGPU_DOORBELL64_VCN6 = 0xFE,
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AMDGPU_DOORBELL64_VCN7 = 0xFF,
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AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
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AMDGPU_DOORBELL64_INVALID = 0xFFFF
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} AMDGPU_DOORBELL64_ASSIGNMENT;
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void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
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phys_addr_t *aperture_base,
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size_t *aperture_size,