Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
x86, AMD: Fix ARAT feature setting again
Revert "x86, AMD: Fix APIC timer erratum 400 affecting K8 Rev.A-E processors"
x86, apic: Fix spurious error interrupts triggering on all non-boot APs
x86, mce, AMD: Fix leaving freed data in a list
x86: Fix UV BAU for non-consecutive nasids
x86, UV: Fix NMI handler for UV platforms
+148
-47
+1
arch/x86/include/asm/apicdef.h
+1
arch/x86/include/asm/apicdef.h
+13
-4
arch/x86/include/asm/uv/uv_bau.h
+13
-4
arch/x86/include/asm/uv/uv_bau.h
···
94
94
/* after this # consecutive successes, bump up the throttle if it was lowered */
95
95
#define COMPLETE_THRESHOLD 5
96
96
97
+
#define UV_LB_SUBNODEID 0x10
98
+
97
99
/*
98
100
* number of entries in the destination side payload queue
99
101
*/
···
126
124
* The distribution specification (32 bytes) is interpreted as a 256-bit
127
125
* distribution vector. Adjacent bits correspond to consecutive even numbered
128
126
* nodeIDs. The result of adding the index of a given bit to the 15-bit
129
-
* 'base_dest_nodeid' field of the header corresponds to the
127
+
* 'base_dest_nasid' field of the header corresponds to the
130
128
* destination nodeID associated with that specified bit.
131
129
*/
132
130
struct bau_target_uvhubmask {
···
178
176
struct bau_msg_header {
179
177
unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
180
178
/* bits 5:0 */
181
-
unsigned int base_dest_nodeid:15; /* nasid of the */
179
+
unsigned int base_dest_nasid:15; /* nasid of the */
182
180
/* bits 20:6 */ /* first bit in uvhub map */
183
181
unsigned int command:8; /* message type */
184
182
/* bits 28:21 */
···
380
378
unsigned long d_rcanceled; /* number of messages canceled by resets */
381
379
};
382
380
381
+
struct hub_and_pnode {
382
+
short uvhub;
383
+
short pnode;
384
+
};
383
385
/*
384
386
* one per-cpu; to locate the software tables
385
387
*/
···
405
399
int baudisabled;
406
400
int set_bau_off;
407
401
short cpu;
402
+
short osnode;
408
403
short uvhub_cpu;
409
404
short uvhub;
410
405
short cpus_in_socket;
411
406
short cpus_in_uvhub;
407
+
short partition_base_pnode;
412
408
unsigned short message_number;
413
409
unsigned short uvhub_quiesce;
414
410
short socket_acknowledge_count[DEST_Q_SIZE];
···
430
422
int congested_period;
431
423
cycles_t period_time;
432
424
long period_requests;
425
+
struct hub_and_pnode *target_hub_and_pnode;
433
426
};
434
427
435
428
static inline int bau_uvhub_isset(int uvhub, struct bau_target_uvhubmask *dstp)
436
429
{
437
430
return constant_test_bit(uvhub, &dstp->bits[0]);
438
431
}
439
-
static inline void bau_uvhub_set(int uvhub, struct bau_target_uvhubmask *dstp)
432
+
static inline void bau_uvhub_set(int pnode, struct bau_target_uvhubmask *dstp)
440
433
{
441
-
__set_bit(uvhub, &dstp->bits[0]);
434
+
__set_bit(pnode, &dstp->bits[0]);
442
435
}
443
436
static inline void bau_uvhubs_clear(struct bau_target_uvhubmask *dstp,
444
437
int nbits)
+2
arch/x86/include/asm/uv/uv_hub.h
+2
arch/x86/include/asm/uv/uv_hub.h
+15
-1
arch/x86/include/asm/uv/uv_mmrs.h
+15
-1
arch/x86/include/asm/uv/uv_mmrs.h
···
5
5
*
6
6
* SGI UV MMR definitions
7
7
*
8
-
* Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
8
+
* Copyright (C) 2007-2011 Silicon Graphics, Inc. All rights reserved.
9
9
*/
10
10
11
11
#ifndef _ASM_X86_UV_UV_MMRS_H
···
1099
1099
} s;
1100
1100
};
1101
1101
1102
+
/* ========================================================================= */
1103
+
/* UVH_SCRATCH5 */
1104
+
/* ========================================================================= */
1105
+
#define UVH_SCRATCH5 0x2d0200UL
1106
+
#define UVH_SCRATCH5_32 0x00778
1107
+
1108
+
#define UVH_SCRATCH5_SCRATCH5_SHFT 0
1109
+
#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
1110
+
union uvh_scratch5_u {
1111
+
unsigned long v;
1112
+
struct uvh_scratch5_s {
1113
+
unsigned long scratch5 : 64; /* RW, W1CS */
1114
+
} s;
1115
+
};
1102
1116
1103
1117
#endif /* __ASM_UV_MMRS_X86_H__ */
+43
-5
arch/x86/kernel/apic/x2apic_uv_x.c
+43
-5
arch/x86/kernel/apic/x2apic_uv_x.c
···
37
37
#include <asm/smp.h>
38
38
#include <asm/x86_init.h>
39
39
#include <asm/emergency-restart.h>
40
+
#include <asm/nmi.h>
41
+
42
+
/* BMC sets a bit this MMR non-zero before sending an NMI */
43
+
#define UVH_NMI_MMR UVH_SCRATCH5
44
+
#define UVH_NMI_MMR_CLEAR (UVH_NMI_MMR + 8)
45
+
#define UV_NMI_PENDING_MASK (1UL << 63)
46
+
DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count);
40
47
41
48
DEFINE_PER_CPU(int, x2apic_extra_bits);
42
49
···
649
642
*/
650
643
int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
651
644
{
645
+
unsigned long real_uv_nmi;
646
+
int bid;
647
+
652
648
if (reason != DIE_NMIUNKNOWN)
653
649
return NOTIFY_OK;
654
650
655
651
if (in_crash_kexec)
656
652
/* do nothing if entering the crash kernel */
657
653
return NOTIFY_OK;
654
+
658
655
/*
659
-
* Use a lock so only one cpu prints at a time
660
-
* to prevent intermixed output.
656
+
* Each blade has an MMR that indicates when an NMI has been sent
657
+
* to cpus on the blade. If an NMI is detected, atomically
658
+
* clear the MMR and update a per-blade NMI count used to
659
+
* cause each cpu on the blade to notice a new NMI.
660
+
*/
661
+
bid = uv_numa_blade_id();
662
+
real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
663
+
664
+
if (unlikely(real_uv_nmi)) {
665
+
spin_lock(&uv_blade_info[bid].nmi_lock);
666
+
real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
667
+
if (real_uv_nmi) {
668
+
uv_blade_info[bid].nmi_count++;
669
+
uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK);
670
+
}
671
+
spin_unlock(&uv_blade_info[bid].nmi_lock);
672
+
}
673
+
674
+
if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count))
675
+
return NOTIFY_DONE;
676
+
677
+
__get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count;
678
+
679
+
/*
680
+
* Use a lock so only one cpu prints at a time.
681
+
* This prevents intermixed output.
661
682
*/
662
683
spin_lock(&uv_nmi_lock);
663
-
pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
684
+
pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id());
664
685
dump_stack();
665
686
spin_unlock(&uv_nmi_lock);
666
687
···
696
661
}
697
662
698
663
static struct notifier_block uv_dump_stack_nmi_nb = {
699
-
.notifier_call = uv_handle_nmi
664
+
.notifier_call = uv_handle_nmi,
665
+
.priority = NMI_LOCAL_LOW_PRIOR - 1,
700
666
};
701
667
702
668
void uv_register_nmi_notifier(void)
···
756
720
printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
757
721
758
722
bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
759
-
uv_blade_info = kmalloc(bytes, GFP_KERNEL);
723
+
uv_blade_info = kzalloc(bytes, GFP_KERNEL);
760
724
BUG_ON(!uv_blade_info);
725
+
761
726
for (blade = 0; blade < uv_num_possible_blades(); blade++)
762
727
uv_blade_info[blade].memory_nid = -1;
763
728
···
784
747
uv_blade_info[blade].pnode = pnode;
785
748
uv_blade_info[blade].nr_possible_cpus = 0;
786
749
uv_blade_info[blade].nr_online_cpus = 0;
750
+
spin_lock_init(&uv_blade_info[blade].nmi_lock);
787
751
max_pnode = max(pnode, max_pnode);
788
752
blade++;
789
753
}
+2
-2
arch/x86/kernel/cpu/amd.c
+2
-2
arch/x86/kernel/cpu/amd.c
···
613
613
#endif
614
614
615
615
/* As a rule processors have APIC timer running in deep C states */
616
-
if (c->x86 >= 0xf && !cpu_has_amd_erratum(amd_erratum_400))
616
+
if (c->x86 > 0xf && !cpu_has_amd_erratum(amd_erratum_400))
617
617
set_cpu_cap(c, X86_FEATURE_ARAT);
618
618
619
619
/*
···
698
698
*/
699
699
700
700
const int amd_erratum_400[] =
701
-
AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0x0f, 0x4, 0x2, 0xff, 0xf),
701
+
AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
702
702
AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
703
703
EXPORT_SYMBOL_GPL(amd_erratum_400);
704
704
+1
arch/x86/kernel/cpu/mcheck/mce_amd.c
+1
arch/x86/kernel/cpu/mcheck/mce_amd.c
+7
-5
arch/x86/kernel/cpu/mcheck/therm_throt.c
+7
-5
arch/x86/kernel/cpu/mcheck/therm_throt.c
···
446
446
*/
447
447
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
448
448
449
+
h = lvtthmr_init;
449
450
/*
450
451
* The initial value of thermal LVT entries on all APs always reads
451
452
* 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
452
453
* sequence to them and LVT registers are reset to 0s except for
453
454
* the mask bits which are set to 1s when APs receive INIT IPI.
454
-
* Always restore the value that BIOS has programmed on AP based on
455
-
* BSP's info we saved since BIOS is always setting the same value
456
-
* for all threads/cores
455
+
* If BIOS takes over the thermal interrupt and sets its interrupt
456
+
* delivery mode to SMI (not fixed), it restores the value that the
457
+
* BIOS has programmed on AP based on BSP's info we saved since BIOS
458
+
* is always setting the same value for all threads/cores.
457
459
*/
458
-
apic_write(APIC_LVTTHMR, lvtthmr_init);
460
+
if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
461
+
apic_write(APIC_LVTTHMR, lvtthmr_init);
459
462
460
-
h = lvtthmr_init;
461
463
462
464
if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
463
465
printk(KERN_DEBUG
+64
-30
arch/x86/platform/uv/tlb_uv.c
+64
-30
arch/x86/platform/uv/tlb_uv.c
···
699
699
struct mm_struct *mm,
700
700
unsigned long va, unsigned int cpu)
701
701
{
702
-
int tcpu;
703
-
int uvhub;
704
702
int locals = 0;
705
703
int remotes = 0;
706
704
int hubs = 0;
705
+
int tcpu;
706
+
int tpnode;
707
707
struct bau_desc *bau_desc;
708
708
struct cpumask *flush_mask;
709
709
struct ptc_stats *stat;
710
710
struct bau_control *bcp;
711
711
struct bau_control *tbcp;
712
+
struct hub_and_pnode *hpp;
712
713
713
714
/* kernel was booted 'nobau' */
714
715
if (nobau)
···
751
750
bau_desc += UV_ITEMS_PER_DESCRIPTOR * bcp->uvhub_cpu;
752
751
bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
753
752
754
-
/* cpu statistics */
755
753
for_each_cpu(tcpu, flush_mask) {
756
-
uvhub = uv_cpu_to_blade_id(tcpu);
757
-
bau_uvhub_set(uvhub, &bau_desc->distribution);
758
-
if (uvhub == bcp->uvhub)
754
+
/*
755
+
* The distribution vector is a bit map of pnodes, relative
756
+
* to the partition base pnode (and the partition base nasid
757
+
* in the header).
758
+
* Translate cpu to pnode and hub using an array stored
759
+
* in local memory.
760
+
*/
761
+
hpp = &bcp->socket_master->target_hub_and_pnode[tcpu];
762
+
tpnode = hpp->pnode - bcp->partition_base_pnode;
763
+
bau_uvhub_set(tpnode, &bau_desc->distribution);
764
+
if (hpp->uvhub == bcp->uvhub)
759
765
locals++;
760
766
else
761
767
remotes++;
···
863
855
* an interrupt, but causes an error message to be returned to
864
856
* the sender.
865
857
*/
866
-
static void uv_enable_timeouts(void)
858
+
static void __init uv_enable_timeouts(void)
867
859
{
868
860
int uvhub;
869
861
int nuvhubs;
···
1334
1326
}
1335
1327
1336
1328
/*
1337
-
* initialize the sending side's sending buffers
1329
+
* Initialize the sending side's sending buffers.
1338
1330
*/
1339
1331
static void
1340
-
uv_activation_descriptor_init(int node, int pnode)
1332
+
uv_activation_descriptor_init(int node, int pnode, int base_pnode)
1341
1333
{
1342
1334
int i;
1343
1335
int cpu;
···
1360
1352
n = pa >> uv_nshift;
1361
1353
m = pa & uv_mmask;
1362
1354
1355
+
/* the 14-bit pnode */
1363
1356
uv_write_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE,
1364
1357
(n << UV_DESC_BASE_PNODE_SHIFT | m));
1365
-
1366
1358
/*
1367
-
* initializing all 8 (UV_ITEMS_PER_DESCRIPTOR) descriptors for each
1359
+
* Initializing all 8 (UV_ITEMS_PER_DESCRIPTOR) descriptors for each
1368
1360
* cpu even though we only use the first one; one descriptor can
1369
1361
* describe a broadcast to 256 uv hubs.
1370
1362
*/
···
1373
1365
memset(bd2, 0, sizeof(struct bau_desc));
1374
1366
bd2->header.sw_ack_flag = 1;
1375
1367
/*
1376
-
* base_dest_nodeid is the nasid of the first uvhub
1377
-
* in the partition. The bit map will indicate uvhub numbers,
1378
-
* which are 0-N in a partition. Pnodes are unique system-wide.
1368
+
* The base_dest_nasid set in the message header is the nasid
1369
+
* of the first uvhub in the partition. The bit map will
1370
+
* indicate destination pnode numbers relative to that base.
1371
+
* They may not be consecutive if nasid striding is being used.
1379
1372
*/
1380
-
bd2->header.base_dest_nodeid = UV_PNODE_TO_NASID(uv_partition_base_pnode);
1381
-
bd2->header.dest_subnodeid = 0x10; /* the LB */
1373
+
bd2->header.base_dest_nasid = UV_PNODE_TO_NASID(base_pnode);
1374
+
bd2->header.dest_subnodeid = UV_LB_SUBNODEID;
1382
1375
bd2->header.command = UV_NET_ENDPOINT_INTD;
1383
1376
bd2->header.int_both = 1;
1384
1377
/*
···
1451
1442
/*
1452
1443
* Initialization of each UV hub's structures
1453
1444
*/
1454
-
static void __init uv_init_uvhub(int uvhub, int vector)
1445
+
static void __init uv_init_uvhub(int uvhub, int vector, int base_pnode)
1455
1446
{
1456
1447
int node;
1457
1448
int pnode;
···
1459
1450
1460
1451
node = uvhub_to_first_node(uvhub);
1461
1452
pnode = uv_blade_to_pnode(uvhub);
1462
-
uv_activation_descriptor_init(node, pnode);
1453
+
uv_activation_descriptor_init(node, pnode, base_pnode);
1463
1454
uv_payload_queue_init(node, pnode);
1464
1455
/*
1465
-
* the below initialization can't be in firmware because the
1466
-
* messaging IRQ will be determined by the OS
1456
+
* The below initialization can't be in firmware because the
1457
+
* messaging IRQ will be determined by the OS.
1467
1458
*/
1468
1459
apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
1469
1460
uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
···
1500
1491
/*
1501
1492
* initialize the bau_control structure for each cpu
1502
1493
*/
1503
-
static int __init uv_init_per_cpu(int nuvhubs)
1494
+
static int __init uv_init_per_cpu(int nuvhubs, int base_part_pnode)
1504
1495
{
1505
1496
int i;
1506
1497
int cpu;
1498
+
int tcpu;
1507
1499
int pnode;
1508
1500
int uvhub;
1509
1501
int have_hmaster;
···
1538
1528
bcp = &per_cpu(bau_control, cpu);
1539
1529
memset(bcp, 0, sizeof(struct bau_control));
1540
1530
pnode = uv_cpu_hub_info(cpu)->pnode;
1531
+
if ((pnode - base_part_pnode) >= UV_DISTRIBUTION_SIZE) {
1532
+
printk(KERN_EMERG
1533
+
"cpu %d pnode %d-%d beyond %d; BAU disabled\n",
1534
+
cpu, pnode, base_part_pnode,
1535
+
UV_DISTRIBUTION_SIZE);
1536
+
return 1;
1537
+
}
1538
+
bcp->osnode = cpu_to_node(cpu);
1539
+
bcp->partition_base_pnode = uv_partition_base_pnode;
1541
1540
uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
1542
1541
*(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
1543
1542
bdp = &uvhub_descs[uvhub];
···
1555
1536
bdp->pnode = pnode;
1556
1537
/* kludge: 'assuming' one node per socket, and assuming that
1557
1538
disabling a socket just leaves a gap in node numbers */
1558
-
socket = (cpu_to_node(cpu) & 1);
1539
+
socket = bcp->osnode & 1;
1559
1540
bdp->socket_mask |= (1 << socket);
1560
1541
sdp = &bdp->socket[socket];
1561
1542
sdp->cpu_number[sdp->num_cpus] = cpu;
···
1604
1585
nextsocket:
1605
1586
socket++;
1606
1587
socket_mask = (socket_mask >> 1);
1588
+
/* each socket gets a local array of pnodes/hubs */
1589
+
bcp = smaster;
1590
+
bcp->target_hub_and_pnode = kmalloc_node(
1591
+
sizeof(struct hub_and_pnode) *
1592
+
num_possible_cpus(), GFP_KERNEL, bcp->osnode);
1593
+
memset(bcp->target_hub_and_pnode, 0,
1594
+
sizeof(struct hub_and_pnode) *
1595
+
num_possible_cpus());
1596
+
for_each_present_cpu(tcpu) {
1597
+
bcp->target_hub_and_pnode[tcpu].pnode =
1598
+
uv_cpu_hub_info(tcpu)->pnode;
1599
+
bcp->target_hub_and_pnode[tcpu].uvhub =
1600
+
uv_cpu_hub_info(tcpu)->numa_blade_id;
1601
+
}
1607
1602
}
1608
1603
}
1609
1604
kfree(uvhub_descs);
···
1670
1637
spin_lock_init(&disable_lock);
1671
1638
congested_cycles = microsec_2_cycles(congested_response_us);
1672
1639
1673
-
if (uv_init_per_cpu(nuvhubs)) {
1640
+
uv_partition_base_pnode = 0x7fffffff;
1641
+
for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
1642
+
if (uv_blade_nr_possible_cpus(uvhub) &&
1643
+
(uv_blade_to_pnode(uvhub) < uv_partition_base_pnode))
1644
+
uv_partition_base_pnode = uv_blade_to_pnode(uvhub);
1645
+
}
1646
+
1647
+
if (uv_init_per_cpu(nuvhubs, uv_partition_base_pnode)) {
1674
1648
nobau = 1;
1675
1649
return 0;
1676
1650
}
1677
1651
1678
-
uv_partition_base_pnode = 0x7fffffff;
1679
-
for (uvhub = 0; uvhub < nuvhubs; uvhub++)
1680
-
if (uv_blade_nr_possible_cpus(uvhub) &&
1681
-
(uv_blade_to_pnode(uvhub) < uv_partition_base_pnode))
1682
-
uv_partition_base_pnode = uv_blade_to_pnode(uvhub);
1683
-
1684
1652
vector = UV_BAU_MESSAGE;
1685
1653
for_each_possible_blade(uvhub)
1686
1654
if (uv_blade_nr_possible_cpus(uvhub))
1687
-
uv_init_uvhub(uvhub, vector);
1655
+
uv_init_uvhub(uvhub, vector, uv_partition_base_pnode);
1688
1656
1689
1657
uv_enable_timeouts();
1690
1658
alloc_intr_gate(vector, uv_bau_message_intr1);