Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-6.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- A fix for FPU probing in XIP kernels
- Always enable the alternative framework for non-XIP kernels
* tag 'riscv-for-linus-6.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels
RISC-V: add non-alternative fallback for riscv_has_extension_[un]likely()
+38
-30
+6
-6
arch/riscv/Kconfig
+6
-6
arch/riscv/Kconfig
···
126
126
select OF_IRQ
127
127
select PCI_DOMAINS_GENERIC if PCI
128
128
select PCI_MSI if PCI
129
+
select RISCV_ALTERNATIVE if !XIP_KERNEL
129
130
select RISCV_INTC
130
131
select RISCV_TIMER if RISCV_SBI
131
132
select SIFIVE_PLIC
···
402
401
config RISCV_ISA_SVPBMT
403
402
bool "SVPBMT extension support"
404
403
depends on 64BIT && MMU
405
-
depends on !XIP_KERNEL
404
+
depends on RISCV_ALTERNATIVE
406
405
default y
407
-
select RISCV_ALTERNATIVE
408
406
help
409
407
Adds support to dynamically detect the presence of the SVPBMT
410
408
ISA-extension (Supervisor-mode: page-based memory types) and
···
428
428
config RISCV_ISA_ZBB
429
429
bool "Zbb extension support for bit manipulation instructions"
430
430
depends on TOOLCHAIN_HAS_ZBB
431
-
depends on !XIP_KERNEL && MMU
432
-
select RISCV_ALTERNATIVE
431
+
depends on MMU
432
+
depends on RISCV_ALTERNATIVE
433
433
default y
434
434
help
435
435
Adds support to dynamically detect the presence of the ZBB
···
443
443
444
444
config RISCV_ISA_ZICBOM
445
445
bool "Zicbom extension support for non-coherent DMA operation"
446
-
depends on !XIP_KERNEL && MMU
446
+
depends on MMU
447
+
depends on RISCV_ALTERNATIVE
447
448
default y
448
-
select RISCV_ALTERNATIVE
449
449
select RISCV_DMA_NONCOHERENT
450
450
help
451
451
Adds support to dynamically detect the presence of the ZICBOM
+2
-4
arch/riscv/Kconfig.erratas
+2
-4
arch/riscv/Kconfig.erratas
···
2
2
3
3
config ERRATA_SIFIVE
4
4
bool "SiFive errata"
5
-
depends on !XIP_KERNEL
6
-
select RISCV_ALTERNATIVE
5
+
depends on RISCV_ALTERNATIVE
7
6
help
8
7
All SiFive errata Kconfig depend on this Kconfig. Disabling
9
8
this Kconfig will disable all SiFive errata. Please say "Y"
···
34
35
35
36
config ERRATA_THEAD
36
37
bool "T-HEAD errata"
37
-
depends on !XIP_KERNEL
38
-
select RISCV_ALTERNATIVE
38
+
depends on RISCV_ALTERNATIVE
39
39
help
40
40
All T-HEAD errata Kconfig depend on this Kconfig. Disabling
41
41
this Kconfig will disable all T-HEAD errata. Please say "Y"
+30
-20
arch/riscv/include/asm/hwcap.h
+30
-20
arch/riscv/include/asm/hwcap.h
···
57
57
unsigned int isa_ext_id;
58
58
};
59
59
60
+
unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
61
+
62
+
#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
63
+
64
+
bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
65
+
#define riscv_isa_extension_available(isa_bitmap, ext) \
66
+
__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
67
+
60
68
static __always_inline bool
61
69
riscv_has_extension_likely(const unsigned long ext)
62
70
{
63
71
compiletime_assert(ext < RISCV_ISA_EXT_MAX,
64
72
"ext must be < RISCV_ISA_EXT_MAX");
65
73
66
-
asm_volatile_goto(
67
-
ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
68
-
:
69
-
: [ext] "i" (ext)
70
-
:
71
-
: l_no);
74
+
if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
75
+
asm_volatile_goto(
76
+
ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
77
+
:
78
+
: [ext] "i" (ext)
79
+
:
80
+
: l_no);
81
+
} else {
82
+
if (!__riscv_isa_extension_available(NULL, ext))
83
+
goto l_no;
84
+
}
72
85
73
86
return true;
74
87
l_no:
···
94
81
compiletime_assert(ext < RISCV_ISA_EXT_MAX,
95
82
"ext must be < RISCV_ISA_EXT_MAX");
96
83
97
-
asm_volatile_goto(
98
-
ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
99
-
:
100
-
: [ext] "i" (ext)
101
-
:
102
-
: l_yes);
84
+
if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
85
+
asm_volatile_goto(
86
+
ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
87
+
:
88
+
: [ext] "i" (ext)
89
+
:
90
+
: l_yes);
91
+
} else {
92
+
if (__riscv_isa_extension_available(NULL, ext))
93
+
goto l_yes;
94
+
}
103
95
104
96
return false;
105
97
l_yes:
106
98
return true;
107
99
}
108
-
109
-
unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
110
-
111
-
#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
112
-
113
-
bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
114
-
#define riscv_isa_extension_available(isa_bitmap, ext) \
115
-
__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
116
100
117
101
#endif
118
102