Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mfd: sec: Add support for S2MPG11 PMIC via ACPM
Add support for Samsung's S2MPG11 PMIC, which is a Power Management IC
for mobile applications with buck converters, various LDOs, power
meters, NTC thermistor inputs, and additional GPIO interfaces. It
typically complements an S2MPG10 PMIC in a main/sub configuration as
the sub-PMIC.
Like S2MPG10, communication is not via I2C, but via the Samsung ACPM
firmware.
While at it, we can also switch to asynchronous probe, which helps with
probe performance, as the drivers for s2mpg10 and s2mpg11 can probe in
parallel.
Note: The firmware uses the ACPM channel ID and the Speedy channel ID
to select the PMIC address. Since these are firmware properties, they
can not be retrieved from DT, but instead are deducted from the
compatible for now.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20260122-s2mpg1x-regulators-v7-9-3b1f9831fffd@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>
authored by
André Draszik
and committed by
Lee Jones
3a17ba65
fa72a842
+808
-6
+167
-4
drivers/mfd/sec-acpm.c
+167
-4
drivers/mfd/sec-acpm.c
···
13
13
#include <linux/mfd/samsung/core.h>
14
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#include <linux/mfd/samsung/rtc.h>
15
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#include <linux/mfd/samsung/s2mpg10.h>
16
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#include <linux/mfd/samsung/s2mpg11.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of.h>
···
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.cache_type = REGCACHE_FLAT,
218
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};
219
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219
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static const struct regmap_range s2mpg11_common_registers[] = {
220
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regmap_reg_range(0x00, 0x02), /* CHIP_ID_S, INT, INT_MASK */
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regmap_reg_range(0x0a, 0x0c), /* Speedy control */
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regmap_reg_range(0x1a, 0x27), /* Debug */
223
+
};
224
+
225
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static const struct regmap_range s2mpg11_common_ro_registers[] = {
226
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regmap_reg_range(0x00, 0x01), /* CHIP_ID_S, INT */
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regmap_reg_range(0x25, 0x27), /* Debug */
228
+
};
229
+
230
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static const struct regmap_range s2mpg11_common_nonvolatile_registers[] = {
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regmap_reg_range(0x00, 0x00), /* CHIP_ID_S */
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regmap_reg_range(0x02, 0x02), /* INT_MASK */
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regmap_reg_range(0x0a, 0x0c), /* Speedy control */
234
+
};
235
+
236
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static const struct regmap_range s2mpg11_common_precious_registers[] = {
237
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regmap_reg_range(0x01, 0x01), /* INT */
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+
};
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static const struct regmap_access_table s2mpg11_common_wr_table = {
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.yes_ranges = s2mpg11_common_registers,
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.n_yes_ranges = ARRAY_SIZE(s2mpg11_common_registers),
243
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.no_ranges = s2mpg11_common_ro_registers,
244
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.n_no_ranges = ARRAY_SIZE(s2mpg11_common_ro_registers),
245
+
};
246
+
247
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static const struct regmap_access_table s2mpg11_common_rd_table = {
248
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.yes_ranges = s2mpg11_common_registers,
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.n_yes_ranges = ARRAY_SIZE(s2mpg11_common_registers),
250
+
};
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+
252
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static const struct regmap_access_table s2mpg11_common_volatile_table = {
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.no_ranges = s2mpg11_common_nonvolatile_registers,
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.n_no_ranges = ARRAY_SIZE(s2mpg11_common_nonvolatile_registers),
255
+
};
256
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static const struct regmap_access_table s2mpg11_common_precious_table = {
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.yes_ranges = s2mpg11_common_precious_registers,
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.n_yes_ranges = ARRAY_SIZE(s2mpg11_common_precious_registers),
260
+
};
261
+
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static const struct regmap_config s2mpg11_regmap_config_common = {
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.name = "common",
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.reg_bits = ACPM_ADDR_BITS,
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.val_bits = 8,
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.max_register = S2MPG11_COMMON_SPD_DEBUG4,
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.wr_table = &s2mpg11_common_wr_table,
268
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.rd_table = &s2mpg11_common_rd_table,
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.volatile_table = &s2mpg11_common_volatile_table,
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.precious_table = &s2mpg11_common_precious_table,
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.num_reg_defaults_raw = S2MPG11_COMMON_SPD_DEBUG4 + 1,
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.cache_type = REGCACHE_FLAT,
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};
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static const struct regmap_range s2mpg11_pmic_registers[] = {
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regmap_reg_range(0x00, 0x5a), /* All PMIC registers */
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regmap_reg_range(0x5c, 0xb7), /* All PMIC registers */
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};
279
+
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static const struct regmap_range s2mpg11_pmic_ro_registers[] = {
281
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regmap_reg_range(0x00, 0x05), /* INTx */
282
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regmap_reg_range(0x0c, 0x0d), /* STATUS OFFSRC */
283
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regmap_reg_range(0x98, 0x98), /* GPIO input */
284
+
};
285
+
286
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static const struct regmap_range s2mpg11_pmic_nonvolatile_registers[] = {
287
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regmap_reg_range(0x06, 0x0b), /* INTxM */
288
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};
289
+
290
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static const struct regmap_range s2mpg11_pmic_precious_registers[] = {
291
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regmap_reg_range(0x00, 0x05), /* INTx */
292
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};
293
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294
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static const struct regmap_access_table s2mpg11_pmic_wr_table = {
295
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.yes_ranges = s2mpg11_pmic_registers,
296
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.n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_registers),
297
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.no_ranges = s2mpg11_pmic_ro_registers,
298
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.n_no_ranges = ARRAY_SIZE(s2mpg11_pmic_ro_registers),
299
+
};
300
+
301
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static const struct regmap_access_table s2mpg11_pmic_rd_table = {
302
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.yes_ranges = s2mpg11_pmic_registers,
303
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.n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_registers),
304
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};
305
+
306
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static const struct regmap_access_table s2mpg11_pmic_volatile_table = {
307
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.no_ranges = s2mpg11_pmic_nonvolatile_registers,
308
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.n_no_ranges = ARRAY_SIZE(s2mpg11_pmic_nonvolatile_registers),
309
+
};
310
+
311
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static const struct regmap_access_table s2mpg11_pmic_precious_table = {
312
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.yes_ranges = s2mpg11_pmic_precious_registers,
313
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.n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_precious_registers),
314
+
};
315
+
316
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static const struct regmap_config s2mpg11_regmap_config_pmic = {
317
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.name = "pmic",
318
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.reg_bits = ACPM_ADDR_BITS,
319
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.val_bits = 8,
320
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.max_register = S2MPG11_PMIC_LDO_SENSE2,
321
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.wr_table = &s2mpg11_pmic_wr_table,
322
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.rd_table = &s2mpg11_pmic_rd_table,
323
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.volatile_table = &s2mpg11_pmic_volatile_table,
324
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.precious_table = &s2mpg11_pmic_precious_table,
325
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.num_reg_defaults_raw = S2MPG11_PMIC_LDO_SENSE2 + 1,
326
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.cache_type = REGCACHE_FLAT,
327
+
};
328
+
329
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static const struct regmap_range s2mpg11_meter_registers[] = {
330
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regmap_reg_range(0x00, 0x3e), /* Meter config */
331
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regmap_reg_range(0x40, 0x8a), /* Meter data */
332
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regmap_reg_range(0x8d, 0x9c), /* Meter data */
333
+
};
334
+
335
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static const struct regmap_range s2mpg11_meter_ro_registers[] = {
336
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regmap_reg_range(0x40, 0x9c), /* Meter data */
337
+
};
338
+
339
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static const struct regmap_access_table s2mpg11_meter_wr_table = {
340
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.yes_ranges = s2mpg11_meter_registers,
341
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.n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_registers),
342
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.no_ranges = s2mpg11_meter_ro_registers,
343
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.n_no_ranges = ARRAY_SIZE(s2mpg11_meter_ro_registers),
344
+
};
345
+
346
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static const struct regmap_access_table s2mpg11_meter_rd_table = {
347
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.yes_ranges = s2mpg11_meter_registers,
348
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.n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_registers),
349
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};
350
+
351
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static const struct regmap_access_table s2mpg11_meter_volatile_table = {
352
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.yes_ranges = s2mpg11_meter_ro_registers,
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.n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_ro_registers),
354
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};
355
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356
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static const struct regmap_config s2mpg11_regmap_config_meter = {
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.name = "meter",
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.reg_bits = ACPM_ADDR_BITS,
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.val_bits = 8,
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.max_register = S2MPG11_METER_LPF_DATA_NTC7_2,
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.wr_table = &s2mpg11_meter_wr_table,
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.rd_table = &s2mpg11_meter_rd_table,
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.volatile_table = &s2mpg11_meter_volatile_table,
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.num_reg_defaults_raw = S2MPG11_METER_LPF_DATA_NTC7_2 + 1,
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.cache_type = REGCACHE_FLAT,
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};
367
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368
struct sec_pmic_acpm_shared_bus_context {
221
369
const struct acpm_handle *acpm;
222
370
unsigned int acpm_chan_id;
···
514
364
if (IS_ERR(regmap_pmic))
515
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return PTR_ERR(regmap_pmic);
516
366
517
-
regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_RTC,
518
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pdata->regmap_cfg_rtc, true);
519
-
if (IS_ERR(regmap))
520
-
return PTR_ERR(regmap);
367
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if (pdata->regmap_cfg_rtc) {
368
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regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_RTC,
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pdata->regmap_cfg_rtc, true);
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if (IS_ERR(regmap))
371
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return PTR_ERR(regmap);
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}
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regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_METER,
523
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pdata->regmap_cfg_meter, true);
···
551
399
.regmap_cfg_meter = &s2mpg10_regmap_config_meter,
552
400
};
553
401
402
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static const struct sec_pmic_acpm_platform_data s2mpg11_data = {
403
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.device_type = S2MPG11,
404
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.acpm_chan_id = 2,
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.speedy_channel = 1,
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.regmap_cfg_common = &s2mpg11_regmap_config_common,
407
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.regmap_cfg_pmic = &s2mpg11_regmap_config_pmic,
408
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.regmap_cfg_meter = &s2mpg11_regmap_config_meter,
409
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};
410
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554
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static const struct of_device_id sec_pmic_acpm_of_match[] = {
555
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{ .compatible = "samsung,s2mpg10-pmic", .data = &s2mpg10_data, },
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{ .compatible = "samsung,s2mpg11-pmic", .data = &s2mpg11_data, },
556
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{ },
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};
558
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MODULE_DEVICE_TABLE(of, sec_pmic_acpm_of_match);
···
570
408
static struct platform_driver sec_pmic_acpm_driver = {
571
409
.driver = {
572
410
.name = "sec-pmic-acpm",
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
573
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.pm = pm_sleep_ptr(&sec_pmic_pm_ops),
574
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.of_match_table = sec_pmic_acpm_of_match,
575
414
},
+16
-1
drivers/mfd/sec-common.c
+16
-1
drivers/mfd/sec-common.c
···
49
49
MFD_CELL_OF("s2mpg10-gpio", NULL, NULL, 0, 0, "samsung,s2mpg10-gpio"),
50
50
};
51
51
52
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static const struct mfd_cell s2mpg11_devs[] = {
53
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MFD_CELL_NAME("s2mpg11-meter"),
54
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MFD_CELL_NAME("s2mpg11-regulator"),
55
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MFD_CELL_OF("s2mpg11-gpio", NULL, NULL, 0, 0, "samsung,s2mpg11-gpio"),
56
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};
57
+
52
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static const struct resource s2mps11_rtc_resources[] = {
53
59
DEFINE_RES_IRQ_NAMED(S2MPS11_IRQ_RTCA0, "alarm"),
54
60
};
···
110
104
unsigned int val;
111
105
112
106
/* For s2mpg1x, the revision is in a different regmap */
113
-
if (sec_pmic->device_type == S2MPG10)
107
+
switch (sec_pmic->device_type) {
108
+
case S2MPG10:
109
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case S2MPG11:
114
110
return;
111
+
default:
112
+
break;
113
+
}
115
114
116
115
/* For each device type, the REG_ID is always the first register */
117
116
if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val))
···
221
210
case S2MPG10:
222
211
sec_devs = s2mpg10_devs;
223
212
num_sec_devs = ARRAY_SIZE(s2mpg10_devs);
213
+
break;
214
+
case S2MPG11:
215
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sec_devs = s2mpg11_devs;
216
+
num_sec_devs = ARRAY_SIZE(s2mpg11_devs);
224
217
break;
225
218
case S2MPS11X:
226
219
sec_devs = s2mps11_devs;
+85
-1
drivers/mfd/sec-irq.c
+85
-1
drivers/mfd/sec-irq.c
···
11
11
#include <linux/mfd/samsung/core.h>
12
12
#include <linux/mfd/samsung/irq.h>
13
13
#include <linux/mfd/samsung/s2mpg10.h>
14
+
#include <linux/mfd/samsung/s2mpg11.h>
14
15
#include <linux/mfd/samsung/s2mps11.h>
15
16
#include <linux/mfd/samsung/s2mps14.h>
16
17
#include <linux/mfd/samsung/s2mpu02.h>
···
78
77
REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH5, 5, S2MPG10_IRQ_PWR_WARN_CH5_MASK),
79
78
REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH6, 5, S2MPG10_IRQ_PWR_WARN_CH6_MASK),
80
79
REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH7, 5, S2MPG10_IRQ_PWR_WARN_CH7_MASK),
80
+
};
81
+
82
+
static const struct regmap_irq s2mpg11_irqs[] = {
83
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REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_PMIC, 0, S2MPG11_COMMON_INT_SRC_PMIC),
84
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/* No documentation or other reference for remaining bits */
85
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REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_UNUSED, 0, GENMASK(7, 1)),
86
+
};
87
+
88
+
static const struct regmap_irq s2mpg11_pmic_irqs[] = {
89
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONF, 0, S2MPG11_IRQ_PWRONF_MASK),
90
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONR, 0, S2MPG11_IRQ_PWRONR_MASK),
91
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUT_MIF, 0, S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK),
92
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUTS, 0, S2MPG11_IRQ_PIF_TIMEOUTS_MASK),
93
+
REGMAP_IRQ_REG(S2MPG11_IRQ_WTSR, 0, S2MPG11_IRQ_WTSR_MASK),
94
+
REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_ABNORMAL_STOP, 0, S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK),
95
+
REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_PARITY_ERR, 0, S2MPG11_IRQ_SPD_PARITY_ERR_MASK),
96
+
97
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REGMAP_IRQ_REG(S2MPG11_IRQ_140C, 1, S2MPG11_IRQ_INT140C_MASK),
98
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REGMAP_IRQ_REG(S2MPG11_IRQ_120C, 1, S2MPG11_IRQ_INT120C_MASK),
99
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REGMAP_IRQ_REG(S2MPG11_IRQ_TSD, 1, S2MPG11_IRQ_TSD_MASK),
100
+
REGMAP_IRQ_REG(S2MPG11_IRQ_WRST, 1, S2MPG11_IRQ_WRST_MASK),
101
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_CYCLE_DONE, 1, S2MPG11_IRQ_NTC_CYCLE_DONE_MASK),
102
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PMETER_OVERF, 1, S2MPG11_IRQ_PMETER_OVERF_MASK),
103
+
104
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REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B1S, 2, S2MPG11_IRQ_OCP_B1S_MASK),
105
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B2S, 2, S2MPG11_IRQ_OCP_B2S_MASK),
106
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B3S, 2, S2MPG11_IRQ_OCP_B3S_MASK),
107
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B4S, 2, S2MPG11_IRQ_OCP_B4S_MASK),
108
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B5S, 2, S2MPG11_IRQ_OCP_B5S_MASK),
109
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B6S, 2, S2MPG11_IRQ_OCP_B6S_MASK),
110
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B7S, 2, S2MPG11_IRQ_OCP_B7S_MASK),
111
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B8S, 2, S2MPG11_IRQ_OCP_B8S_MASK),
112
+
113
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B9S, 3, S2MPG11_IRQ_OCP_B9S_MASK),
114
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B10S, 3, S2MPG11_IRQ_OCP_B10S_MASK),
115
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BDS, 3, S2MPG11_IRQ_OCP_BDS_MASK),
116
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BAS, 3, S2MPG11_IRQ_OCP_BAS_MASK),
117
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BBS, 3, S2MPG11_IRQ_OCP_BBS_MASK),
118
+
REGMAP_IRQ_REG(S2MPG11_IRQ_WLWP_ACC, 3, S2MPG11_IRQ_WLWP_ACC_MASK),
119
+
REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_SRP_PKT_RST, 3, S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK),
120
+
121
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH0, 4, S2MPG11_IRQ_PWR_WARN_CH0_MASK),
122
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH1, 4, S2MPG11_IRQ_PWR_WARN_CH1_MASK),
123
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH2, 4, S2MPG11_IRQ_PWR_WARN_CH2_MASK),
124
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH3, 4, S2MPG11_IRQ_PWR_WARN_CH3_MASK),
125
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH4, 4, S2MPG11_IRQ_PWR_WARN_CH4_MASK),
126
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH5, 4, S2MPG11_IRQ_PWR_WARN_CH5_MASK),
127
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH6, 4, S2MPG11_IRQ_PWR_WARN_CH6_MASK),
128
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH7, 4, S2MPG11_IRQ_PWR_WARN_CH7_MASK),
129
+
130
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH0, 5, S2MPG11_IRQ_NTC_WARN_CH0_MASK),
131
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH1, 5, S2MPG11_IRQ_NTC_WARN_CH1_MASK),
132
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH2, 5, S2MPG11_IRQ_NTC_WARN_CH2_MASK),
133
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH3, 5, S2MPG11_IRQ_NTC_WARN_CH3_MASK),
134
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH4, 5, S2MPG11_IRQ_NTC_WARN_CH4_MASK),
135
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH5, 5, S2MPG11_IRQ_NTC_WARN_CH5_MASK),
136
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH6, 5, S2MPG11_IRQ_NTC_WARN_CH6_MASK),
137
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH7, 5, S2MPG11_IRQ_NTC_WARN_CH7_MASK),
81
138
};
82
139
83
140
static const struct regmap_irq s2mps11_irqs[] = {
···
245
186
REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK),
246
187
};
247
188
248
-
/* All S2MPG10 interrupt sources are read-only and don't require clearing */
189
+
/* All S2MPG1x interrupt sources are read-only and don't require clearing */
249
190
static const struct regmap_irq_chip s2mpg10_irq_chip = {
250
191
.name = "s2mpg10",
251
192
.status_base = S2MPG10_COMMON_INT,
···
262
203
.num_regs = 6,
263
204
.irqs = s2mpg10_pmic_irqs,
264
205
.num_irqs = ARRAY_SIZE(s2mpg10_pmic_irqs),
206
+
};
207
+
208
+
static const struct regmap_irq_chip s2mpg11_irq_chip = {
209
+
.name = "s2mpg11",
210
+
.status_base = S2MPG11_COMMON_INT,
211
+
.mask_base = S2MPG11_COMMON_INT_MASK,
212
+
.num_regs = 1,
213
+
.irqs = s2mpg11_irqs,
214
+
.num_irqs = ARRAY_SIZE(s2mpg11_irqs),
215
+
};
216
+
217
+
static const struct regmap_irq_chip s2mpg11_irq_chip_pmic = {
218
+
.name = "s2mpg11-pmic",
219
+
.domain_suffix = "pmic",
220
+
.status_base = S2MPG11_PMIC_INT1,
221
+
.mask_base = S2MPG11_PMIC_INT1M,
222
+
.num_regs = 6,
223
+
.irqs = s2mpg11_pmic_irqs,
224
+
.num_irqs = ARRAY_SIZE(s2mpg11_pmic_irqs),
265
225
};
266
226
267
227
static const struct regmap_irq_chip s2mps11_irq_chip = {
···
381
303
chained_irq_chip = &s2mpg10_irq_chip_pmic;
382
304
chained_pirq = S2MPG10_COMMON_IRQ_PMIC;
383
305
break;
306
+
case S2MPG11:
307
+
irq_chip = &s2mpg11_irq_chip;
308
+
chained_irq_chip = &s2mpg11_irq_chip_pmic;
309
+
chained_pirq = S2MPG11_COMMON_IRQ_PMIC;
310
+
break;
384
311
default:
385
312
return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n",
386
313
sec_pmic->device_type);
···
421
338
sec_irq_chip = &s2mps14_irq_chip;
422
339
break;
423
340
case S2MPG10:
341
+
case S2MPG11:
424
342
return sec_irq_init_s2mpg1x(sec_pmic);
425
343
case S2MPS11X:
426
344
sec_irq_chip = &s2mps11_irq_chip;
+1
include/linux/mfd/samsung/core.h
+1
include/linux/mfd/samsung/core.h
+105
include/linux/mfd/samsung/irq.h
+105
include/linux/mfd/samsung/irq.h
···
166
166
S2MPG10_IRQ_NR,
167
167
};
168
168
169
+
enum s2mpg11_common_irq {
170
+
/* Top-level (common) block */
171
+
S2MPG11_COMMON_IRQ_PMIC,
172
+
S2MPG11_COMMON_IRQ_UNUSED,
173
+
};
174
+
175
+
enum s2mpg11_irq {
176
+
/* PMIC */
177
+
S2MPG11_IRQ_PWRONF,
178
+
S2MPG11_IRQ_PWRONR,
179
+
S2MPG11_IRQ_PIF_TIMEOUT_MIF,
180
+
S2MPG11_IRQ_PIF_TIMEOUTS,
181
+
S2MPG11_IRQ_WTSR,
182
+
S2MPG11_IRQ_SPD_ABNORMAL_STOP,
183
+
S2MPG11_IRQ_SPD_PARITY_ERR,
184
+
#define S2MPG11_IRQ_PWRONF_MASK BIT(0)
185
+
#define S2MPG11_IRQ_PWRONR_MASK BIT(1)
186
+
#define S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK BIT(3)
187
+
#define S2MPG11_IRQ_PIF_TIMEOUTS_MASK BIT(4)
188
+
#define S2MPG11_IRQ_WTSR_MASK BIT(5)
189
+
#define S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6)
190
+
#define S2MPG11_IRQ_SPD_PARITY_ERR_MASK BIT(7)
191
+
192
+
S2MPG11_IRQ_140C,
193
+
S2MPG11_IRQ_120C,
194
+
S2MPG11_IRQ_TSD,
195
+
S2MPG11_IRQ_WRST,
196
+
S2MPG11_IRQ_NTC_CYCLE_DONE,
197
+
S2MPG11_IRQ_PMETER_OVERF,
198
+
#define S2MPG11_IRQ_INT140C_MASK BIT(0)
199
+
#define S2MPG11_IRQ_INT120C_MASK BIT(1)
200
+
#define S2MPG11_IRQ_TSD_MASK BIT(2)
201
+
#define S2MPG11_IRQ_WRST_MASK BIT(5)
202
+
#define S2MPG11_IRQ_NTC_CYCLE_DONE_MASK BIT(6)
203
+
#define S2MPG11_IRQ_PMETER_OVERF_MASK BIT(7)
204
+
205
+
S2MPG11_IRQ_OCP_B1S,
206
+
S2MPG11_IRQ_OCP_B2S,
207
+
S2MPG11_IRQ_OCP_B3S,
208
+
S2MPG11_IRQ_OCP_B4S,
209
+
S2MPG11_IRQ_OCP_B5S,
210
+
S2MPG11_IRQ_OCP_B6S,
211
+
S2MPG11_IRQ_OCP_B7S,
212
+
S2MPG11_IRQ_OCP_B8S,
213
+
#define S2MPG11_IRQ_OCP_B1S_MASK BIT(0)
214
+
#define S2MPG11_IRQ_OCP_B2S_MASK BIT(1)
215
+
#define S2MPG11_IRQ_OCP_B3S_MASK BIT(2)
216
+
#define S2MPG11_IRQ_OCP_B4S_MASK BIT(3)
217
+
#define S2MPG11_IRQ_OCP_B5S_MASK BIT(4)
218
+
#define S2MPG11_IRQ_OCP_B6S_MASK BIT(5)
219
+
#define S2MPG11_IRQ_OCP_B7S_MASK BIT(6)
220
+
#define S2MPG11_IRQ_OCP_B8S_MASK BIT(7)
221
+
222
+
S2MPG11_IRQ_OCP_B9S,
223
+
S2MPG11_IRQ_OCP_B10S,
224
+
S2MPG11_IRQ_OCP_BDS,
225
+
S2MPG11_IRQ_OCP_BAS,
226
+
S2MPG11_IRQ_OCP_BBS,
227
+
S2MPG11_IRQ_WLWP_ACC,
228
+
S2MPG11_IRQ_SPD_SRP_PKT_RST,
229
+
#define S2MPG11_IRQ_OCP_B9S_MASK BIT(0)
230
+
#define S2MPG11_IRQ_OCP_B10S_MASK BIT(1)
231
+
#define S2MPG11_IRQ_OCP_BDS_MASK BIT(2)
232
+
#define S2MPG11_IRQ_OCP_BAS_MASK BIT(3)
233
+
#define S2MPG11_IRQ_OCP_BBS_MASK BIT(4)
234
+
#define S2MPG11_IRQ_WLWP_ACC_MASK BIT(5)
235
+
#define S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK BIT(7)
236
+
237
+
S2MPG11_IRQ_PWR_WARN_CH0,
238
+
S2MPG11_IRQ_PWR_WARN_CH1,
239
+
S2MPG11_IRQ_PWR_WARN_CH2,
240
+
S2MPG11_IRQ_PWR_WARN_CH3,
241
+
S2MPG11_IRQ_PWR_WARN_CH4,
242
+
S2MPG11_IRQ_PWR_WARN_CH5,
243
+
S2MPG11_IRQ_PWR_WARN_CH6,
244
+
S2MPG11_IRQ_PWR_WARN_CH7,
245
+
#define S2MPG11_IRQ_PWR_WARN_CH0_MASK BIT(0)
246
+
#define S2MPG11_IRQ_PWR_WARN_CH1_MASK BIT(1)
247
+
#define S2MPG11_IRQ_PWR_WARN_CH2_MASK BIT(2)
248
+
#define S2MPG11_IRQ_PWR_WARN_CH3_MASK BIT(3)
249
+
#define S2MPG11_IRQ_PWR_WARN_CH4_MASK BIT(4)
250
+
#define S2MPG11_IRQ_PWR_WARN_CH5_MASK BIT(5)
251
+
#define S2MPG11_IRQ_PWR_WARN_CH6_MASK BIT(6)
252
+
#define S2MPG11_IRQ_PWR_WARN_CH7_MASK BIT(7)
253
+
254
+
S2MPG11_IRQ_NTC_WARN_CH0,
255
+
S2MPG11_IRQ_NTC_WARN_CH1,
256
+
S2MPG11_IRQ_NTC_WARN_CH2,
257
+
S2MPG11_IRQ_NTC_WARN_CH3,
258
+
S2MPG11_IRQ_NTC_WARN_CH4,
259
+
S2MPG11_IRQ_NTC_WARN_CH5,
260
+
S2MPG11_IRQ_NTC_WARN_CH6,
261
+
S2MPG11_IRQ_NTC_WARN_CH7,
262
+
#define S2MPG11_IRQ_NTC_WARN_CH0_MASK BIT(0)
263
+
#define S2MPG11_IRQ_NTC_WARN_CH1_MASK BIT(1)
264
+
#define S2MPG11_IRQ_NTC_WARN_CH2_MASK BIT(2)
265
+
#define S2MPG11_IRQ_NTC_WARN_CH3_MASK BIT(3)
266
+
#define S2MPG11_IRQ_NTC_WARN_CH4_MASK BIT(4)
267
+
#define S2MPG11_IRQ_NTC_WARN_CH5_MASK BIT(5)
268
+
#define S2MPG11_IRQ_NTC_WARN_CH6_MASK BIT(6)
269
+
#define S2MPG11_IRQ_NTC_WARN_CH7_MASK BIT(7)
270
+
271
+
S2MPG11_IRQ_NR,
272
+
};
273
+
169
274
enum s2mps11_irq {
170
275
S2MPS11_IRQ_PWRONF,
171
276
S2MPS11_IRQ_PWRONR,
+434
include/linux/mfd/samsung/s2mpg11.h
+434
include/linux/mfd/samsung/s2mpg11.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/*
3
+
* Copyright 2015 Samsung Electronics
4
+
* Copyright 2020 Google Inc
5
+
* Copyright 2025 Linaro Ltd.
6
+
*/
7
+
8
+
#ifndef __LINUX_MFD_S2MPG11_H
9
+
#define __LINUX_MFD_S2MPG11_H
10
+
11
+
/* Common registers (type 0x000) */
12
+
enum s2mpg11_common_reg {
13
+
S2MPG11_COMMON_CHIPID,
14
+
S2MPG11_COMMON_INT,
15
+
S2MPG11_COMMON_INT_MASK,
16
+
S2MPG11_COMMON_SPD_CTRL1 = 0x0a,
17
+
S2MPG11_COMMON_SPD_CTRL2,
18
+
S2MPG11_COMMON_SPD_CTRL3,
19
+
S2MPG11_COMMON_MON1SEL = 0x1a,
20
+
S2MPG11_COMMON_MON2SEL,
21
+
S2MPG11_COMMON_MONR,
22
+
S2MPG11_COMMON_DEBUG_CTRL1,
23
+
S2MPG11_COMMON_DEBUG_CTRL2,
24
+
S2MPG11_COMMON_DEBUG_CTRL3,
25
+
S2MPG11_COMMON_DEBUG_CTRL4,
26
+
S2MPG11_COMMON_DEBUG_CTRL5,
27
+
S2MPG11_COMMON_DEBUG_CTRL6,
28
+
S2MPG11_COMMON_TEST_MODE1,
29
+
S2MPG11_COMMON_SPD_DEBUG1,
30
+
S2MPG11_COMMON_SPD_DEBUG2,
31
+
S2MPG11_COMMON_SPD_DEBUG3,
32
+
S2MPG11_COMMON_SPD_DEBUG4,
33
+
};
34
+
35
+
/* For S2MPG11_COMMON_INT and S2MPG11_COMMON_INT_MASK */
36
+
#define S2MPG11_COMMON_INT_SRC GENMASK(2, 0)
37
+
#define S2MPG11_COMMON_INT_SRC_PMIC BIT(0)
38
+
39
+
/* PMIC registers (type 0x100) */
40
+
enum s2mpg11_pmic_reg {
41
+
S2MPG11_PMIC_INT1,
42
+
S2MPG11_PMIC_INT2,
43
+
S2MPG11_PMIC_INT3,
44
+
S2MPG11_PMIC_INT4,
45
+
S2MPG11_PMIC_INT5,
46
+
S2MPG11_PMIC_INT6,
47
+
S2MPG11_PMIC_INT1M,
48
+
S2MPG11_PMIC_INT2M,
49
+
S2MPG11_PMIC_INT3M,
50
+
S2MPG11_PMIC_INT4M,
51
+
S2MPG11_PMIC_INT5M,
52
+
S2MPG11_PMIC_INT6M,
53
+
S2MPG11_PMIC_STATUS1,
54
+
S2MPG11_PMIC_OFFSRC,
55
+
S2MPG11_PMIC_COMMON_CTRL1,
56
+
S2MPG11_PMIC_COMMON_CTRL2,
57
+
S2MPG11_PMIC_COMMON_CTRL3,
58
+
S2MPG11_PMIC_MIMICKING_CTRL,
59
+
S2MPG11_PMIC_B1S_CTRL,
60
+
S2MPG11_PMIC_B1S_OUT1,
61
+
S2MPG11_PMIC_B1S_OUT2,
62
+
S2MPG11_PMIC_B2S_CTRL,
63
+
S2MPG11_PMIC_B2S_OUT1,
64
+
S2MPG11_PMIC_B2S_OUT2,
65
+
S2MPG11_PMIC_B3S_CTRL,
66
+
S2MPG11_PMIC_B3S_OUT1,
67
+
S2MPG11_PMIC_B3S_OUT2,
68
+
S2MPG11_PMIC_B4S_CTRL,
69
+
S2MPG11_PMIC_B4S_OUT,
70
+
S2MPG11_PMIC_B5S_CTRL,
71
+
S2MPG11_PMIC_B5S_OUT,
72
+
S2MPG11_PMIC_B6S_CTRL,
73
+
S2MPG11_PMIC_B6S_OUT1,
74
+
S2MPG11_PMIC_B6S_OUT2,
75
+
S2MPG11_PMIC_B7S_CTRL,
76
+
S2MPG11_PMIC_B7S_OUT1,
77
+
S2MPG11_PMIC_B7S_OUT2,
78
+
S2MPG11_PMIC_B8S_CTRL,
79
+
S2MPG11_PMIC_B8S_OUT1,
80
+
S2MPG11_PMIC_B8S_OUT2,
81
+
S2MPG11_PMIC_B9S_CTRL,
82
+
S2MPG11_PMIC_B9S_OUT1,
83
+
S2MPG11_PMIC_B9S_OUT2,
84
+
S2MPG11_PMIC_B10S_CTRL,
85
+
S2MPG11_PMIC_B10S_OUT,
86
+
S2MPG11_PMIC_BUCKD_CTRL,
87
+
S2MPG11_PMIC_BUCKD_OUT,
88
+
S2MPG11_PMIC_BUCKA_CTRL,
89
+
S2MPG11_PMIC_BUCKA_OUT,
90
+
S2MPG11_PMIC_BB_CTRL,
91
+
S2MPG11_PMIC_BB_OUT1,
92
+
S2MPG11_PMIC_BB_OUT2,
93
+
S2MPG11_PMIC_BUCK1S_USONIC,
94
+
S2MPG11_PMIC_BUCK2S_USONIC,
95
+
S2MPG11_PMIC_BUCK3S_USONIC,
96
+
S2MPG11_PMIC_BUCK4S_USONIC,
97
+
S2MPG11_PMIC_BUCK5S_USONIC,
98
+
S2MPG11_PMIC_BUCK6S_USONIC,
99
+
S2MPG11_PMIC_BUCK7S_USONIC,
100
+
S2MPG11_PMIC_BUCK8S_USONIC,
101
+
S2MPG11_PMIC_BUCK9S_USONIC,
102
+
S2MPG11_PMIC_BUCK10S_USONIC,
103
+
S2MPG11_PMIC_BUCKD_USONIC,
104
+
S2MPG11_PMIC_BUCKA_USONIC,
105
+
S2MPG11_PMIC_BB_USONIC,
106
+
S2MPG11_PMIC_L1S_CTRL1,
107
+
S2MPG11_PMIC_L1S_CTRL2,
108
+
S2MPG11_PMIC_L2S_CTRL1,
109
+
S2MPG11_PMIC_L2S_CTRL2,
110
+
S2MPG11_PMIC_L3S_CTRL,
111
+
S2MPG11_PMIC_L4S_CTRL,
112
+
S2MPG11_PMIC_L5S_CTRL,
113
+
S2MPG11_PMIC_L6S_CTRL,
114
+
S2MPG11_PMIC_L7S_CTRL,
115
+
S2MPG11_PMIC_L8S_CTRL,
116
+
S2MPG11_PMIC_L9S_CTRL,
117
+
S2MPG11_PMIC_L10S_CTRL,
118
+
S2MPG11_PMIC_L11S_CTRL,
119
+
S2MPG11_PMIC_L12S_CTRL,
120
+
S2MPG11_PMIC_L13S_CTRL,
121
+
S2MPG11_PMIC_L14S_CTRL,
122
+
S2MPG11_PMIC_L15S_CTRL,
123
+
S2MPG11_PMIC_LDO_CTRL1,
124
+
S2MPG11_PMIC_LDO_DSCH1,
125
+
S2MPG11_PMIC_LDO_DSCH2,
126
+
S2MPG11_PMIC_DVS_RAMP1,
127
+
S2MPG11_PMIC_DVS_RAMP2,
128
+
S2MPG11_PMIC_DVS_RAMP3,
129
+
S2MPG11_PMIC_DVS_RAMP4,
130
+
S2MPG11_PMIC_DVS_RAMP5,
131
+
S2MPG11_PMIC_DVS_RAMP6,
132
+
/* Nothing @ 0x5a */
133
+
S2MPG11_PMIC_DVS_SYNC_CTRL1 = 0x5c,
134
+
S2MPG11_PMIC_DVS_SYNC_CTRL2,
135
+
S2MPG11_PMIC_OFF_CTRL1,
136
+
S2MPG11_PMIC_OFF_CTRL2,
137
+
S2MPG11_PMIC_OFF_CTRL3,
138
+
S2MPG11_PMIC_SEQ_CTRL1,
139
+
S2MPG11_PMIC_SEQ_CTRL2,
140
+
S2MPG11_PMIC_SEQ_CTRL3,
141
+
S2MPG11_PMIC_SEQ_CTRL4,
142
+
S2MPG11_PMIC_SEQ_CTRL5,
143
+
S2MPG11_PMIC_SEQ_CTRL6,
144
+
S2MPG11_PMIC_SEQ_CTRL7,
145
+
S2MPG11_PMIC_SEQ_CTRL8,
146
+
S2MPG11_PMIC_SEQ_CTRL9,
147
+
S2MPG11_PMIC_SEQ_CTRL10,
148
+
S2MPG11_PMIC_SEQ_CTRL11,
149
+
S2MPG11_PMIC_SEQ_CTRL12,
150
+
S2MPG11_PMIC_SEQ_CTRL13,
151
+
S2MPG11_PMIC_SEQ_CTRL14,
152
+
S2MPG11_PMIC_SEQ_CTRL15,
153
+
S2MPG11_PMIC_SEQ_CTRL16,
154
+
S2MPG11_PMIC_SEQ_CTRL17,
155
+
S2MPG11_PMIC_SEQ_CTRL18,
156
+
S2MPG11_PMIC_SEQ_CTRL19,
157
+
S2MPG11_PMIC_SEQ_CTRL20,
158
+
S2MPG11_PMIC_SEQ_CTRL21,
159
+
S2MPG11_PMIC_SEQ_CTRL22,
160
+
S2MPG11_PMIC_SEQ_CTRL23,
161
+
S2MPG11_PMIC_SEQ_CTRL24,
162
+
S2MPG11_PMIC_SEQ_CTRL25,
163
+
S2MPG11_PMIC_SEQ_CTRL26,
164
+
S2MPG11_PMIC_SEQ_CTRL27,
165
+
S2MPG11_PMIC_OFF_SEQ_CTRL1,
166
+
S2MPG11_PMIC_OFF_SEQ_CTRL2,
167
+
S2MPG11_PMIC_OFF_SEQ_CTRL3,
168
+
S2MPG11_PMIC_OFF_SEQ_CTRL4,
169
+
S2MPG11_PMIC_OFF_SEQ_CTRL5,
170
+
S2MPG11_PMIC_OFF_SEQ_CTRL6,
171
+
S2MPG11_PMIC_OFF_SEQ_CTRL7,
172
+
S2MPG11_PMIC_OFF_SEQ_CTRL8,
173
+
S2MPG11_PMIC_OFF_SEQ_CTRL9,
174
+
S2MPG11_PMIC_OFF_SEQ_CTRL10,
175
+
S2MPG11_PMIC_OFF_SEQ_CTRL11,
176
+
S2MPG11_PMIC_OFF_SEQ_CTRL12,
177
+
S2MPG11_PMIC_OFF_SEQ_CTRL13,
178
+
S2MPG11_PMIC_OFF_SEQ_CTRL14,
179
+
S2MPG11_PMIC_OFF_SEQ_CTRL15,
180
+
S2MPG11_PMIC_OFF_SEQ_CTRL16,
181
+
S2MPG11_PMIC_OFF_SEQ_CTRL17,
182
+
S2MPG11_PMIC_PCTRLSEL1,
183
+
S2MPG11_PMIC_PCTRLSEL2,
184
+
S2MPG11_PMIC_PCTRLSEL3,
185
+
S2MPG11_PMIC_PCTRLSEL4,
186
+
S2MPG11_PMIC_PCTRLSEL5,
187
+
S2MPG11_PMIC_PCTRLSEL6,
188
+
S2MPG11_PMIC_DCTRLSEL1,
189
+
S2MPG11_PMIC_DCTRLSEL2,
190
+
S2MPG11_PMIC_DCTRLSEL3,
191
+
S2MPG11_PMIC_DCTRLSEL4,
192
+
S2MPG11_PMIC_DCTRLSEL5,
193
+
S2MPG11_PMIC_GPIO_CTRL1,
194
+
S2MPG11_PMIC_GPIO_CTRL2,
195
+
S2MPG11_PMIC_GPIO_CTRL3,
196
+
S2MPG11_PMIC_GPIO_CTRL4,
197
+
S2MPG11_PMIC_GPIO_CTRL5,
198
+
S2MPG11_PMIC_GPIO_CTRL6,
199
+
S2MPG11_PMIC_GPIO_CTRL7,
200
+
S2MPG11_PMIC_B2S_OCP_WARN,
201
+
S2MPG11_PMIC_B2S_OCP_WARN_X,
202
+
S2MPG11_PMIC_B2S_OCP_WARN_Y,
203
+
S2MPG11_PMIC_B2S_OCP_WARN_Z,
204
+
S2MPG11_PMIC_B2S_SOFT_OCP_WARN,
205
+
S2MPG11_PMIC_B2S_SOFT_OCP_WARN_X,
206
+
S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Y,
207
+
S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Z,
208
+
S2MPG11_PMIC_BUCK_OCP_EN1,
209
+
S2MPG11_PMIC_BUCK_OCP_EN2,
210
+
S2MPG11_PMIC_BUCK_OCP_PD_EN1,
211
+
S2MPG11_PMIC_BUCK_OCP_PD_EN2,
212
+
S2MPG11_PMIC_BUCK_OCP_CTRL1,
213
+
S2MPG11_PMIC_BUCK_OCP_CTRL2,
214
+
S2MPG11_PMIC_BUCK_OCP_CTRL3,
215
+
S2MPG11_PMIC_BUCK_OCP_CTRL4,
216
+
S2MPG11_PMIC_BUCK_OCP_CTRL5,
217
+
S2MPG11_PMIC_BUCK_OCP_CTRL6,
218
+
S2MPG11_PMIC_BUCK_OCP_CTRL7,
219
+
S2MPG11_PMIC_PIF_CTRL,
220
+
S2MPG11_PMIC_BUCK_HR_MODE1,
221
+
S2MPG11_PMIC_BUCK_HR_MODE2,
222
+
S2MPG11_PMIC_FAULTOUT_CTRL,
223
+
S2MPG11_PMIC_LDO_SENSE1,
224
+
S2MPG11_PMIC_LDO_SENSE2,
225
+
};
226
+
227
+
/* For S2MPG11_PMIC_PCTRLSELx */
228
+
#define S2MPG11_PCTRLSEL_PWREN 0x1 /* PWREN pin */
229
+
#define S2MPG11_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKING_CTRL */
230
+
#define S2MPG11_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */
231
+
#define S2MPG11_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMICKING_CTRL */
232
+
#define S2MPG11_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */
233
+
#define S2MPG11_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in MIMICKING_CTRL */
234
+
#define S2MPG11_PCTRLSEL_G3D_EN 0x7 /* G3D_EN pin */
235
+
#define S2MPG11_PCTRLSEL_G3D_EN2 0x8 /* G3D_EN & ~AP_ACTIVE_N pins */
236
+
#define S2MPG11_PCTRLSEL_AOC_VDD 0x9 /* AOC_VDD pin */
237
+
#define S2MPG11_PCTRLSEL_AOC_RET 0xa /* AOC_RET pin */
238
+
#define S2MPG11_PCTRLSEL_UFS_EN 0xb /* UFS_EN pin */
239
+
#define S2MPG11_PCTRLSEL_LDO13S_EN 0xc /* VLDO13S_EN pin */
240
+
241
+
/* Meter registers (type 0xa00) */
242
+
enum s2mpg11_meter_reg {
243
+
S2MPG11_METER_CTRL1,
244
+
S2MPG11_METER_CTRL2,
245
+
S2MPG11_METER_CTRL3,
246
+
S2MPG11_METER_CTRL4,
247
+
S2MPG11_METER_CTRL5,
248
+
S2MPG11_METER_BUCKEN1,
249
+
S2MPG11_METER_BUCKEN2,
250
+
S2MPG11_METER_MUXSEL0,
251
+
S2MPG11_METER_MUXSEL1,
252
+
S2MPG11_METER_MUXSEL2,
253
+
S2MPG11_METER_MUXSEL3,
254
+
S2MPG11_METER_MUXSEL4,
255
+
S2MPG11_METER_MUXSEL5,
256
+
S2MPG11_METER_MUXSEL6,
257
+
S2MPG11_METER_MUXSEL7,
258
+
S2MPG11_METER_LPF_C0_0,
259
+
S2MPG11_METER_LPF_C0_1,
260
+
S2MPG11_METER_LPF_C0_2,
261
+
S2MPG11_METER_LPF_C0_3,
262
+
S2MPG11_METER_LPF_C0_4,
263
+
S2MPG11_METER_LPF_C0_5,
264
+
S2MPG11_METER_LPF_C0_6,
265
+
S2MPG11_METER_LPF_C0_7,
266
+
S2MPG11_METER_NTC_LPF_C0_0,
267
+
S2MPG11_METER_NTC_LPF_C0_1,
268
+
S2MPG11_METER_NTC_LPF_C0_2,
269
+
S2MPG11_METER_NTC_LPF_C0_3,
270
+
S2MPG11_METER_NTC_LPF_C0_4,
271
+
S2MPG11_METER_NTC_LPF_C0_5,
272
+
S2MPG11_METER_NTC_LPF_C0_6,
273
+
S2MPG11_METER_NTC_LPF_C0_7,
274
+
S2MPG11_METER_PWR_WARN0,
275
+
S2MPG11_METER_PWR_WARN1,
276
+
S2MPG11_METER_PWR_WARN2,
277
+
S2MPG11_METER_PWR_WARN3,
278
+
S2MPG11_METER_PWR_WARN4,
279
+
S2MPG11_METER_PWR_WARN5,
280
+
S2MPG11_METER_PWR_WARN6,
281
+
S2MPG11_METER_PWR_WARN7,
282
+
S2MPG11_METER_NTC_L_WARN0,
283
+
S2MPG11_METER_NTC_L_WARN1,
284
+
S2MPG11_METER_NTC_L_WARN2,
285
+
S2MPG11_METER_NTC_L_WARN3,
286
+
S2MPG11_METER_NTC_L_WARN4,
287
+
S2MPG11_METER_NTC_L_WARN5,
288
+
S2MPG11_METER_NTC_L_WARN6,
289
+
S2MPG11_METER_NTC_L_WARN7,
290
+
S2MPG11_METER_NTC_H_WARN0,
291
+
S2MPG11_METER_NTC_H_WARN1,
292
+
S2MPG11_METER_NTC_H_WARN2,
293
+
S2MPG11_METER_NTC_H_WARN3,
294
+
S2MPG11_METER_NTC_H_WARN4,
295
+
S2MPG11_METER_NTC_H_WARN5,
296
+
S2MPG11_METER_NTC_H_WARN6,
297
+
S2MPG11_METER_NTC_H_WARN7,
298
+
S2MPG11_METER_PWR_HYS1,
299
+
S2MPG11_METER_PWR_HYS2,
300
+
S2MPG11_METER_PWR_HYS3,
301
+
S2MPG11_METER_PWR_HYS4,
302
+
S2MPG11_METER_NTC_HYS1,
303
+
S2MPG11_METER_NTC_HYS2,
304
+
S2MPG11_METER_NTC_HYS3,
305
+
S2MPG11_METER_NTC_HYS4,
306
+
/* Nothing @ 0x3f */
307
+
S2MPG11_METER_ACC_DATA_CH0_1 = 0x40,
308
+
S2MPG11_METER_ACC_DATA_CH0_2,
309
+
S2MPG11_METER_ACC_DATA_CH0_3,
310
+
S2MPG11_METER_ACC_DATA_CH0_4,
311
+
S2MPG11_METER_ACC_DATA_CH0_5,
312
+
S2MPG11_METER_ACC_DATA_CH0_6,
313
+
S2MPG11_METER_ACC_DATA_CH1_1,
314
+
S2MPG11_METER_ACC_DATA_CH1_2,
315
+
S2MPG11_METER_ACC_DATA_CH1_3,
316
+
S2MPG11_METER_ACC_DATA_CH1_4,
317
+
S2MPG11_METER_ACC_DATA_CH1_5,
318
+
S2MPG11_METER_ACC_DATA_CH1_6,
319
+
S2MPG11_METER_ACC_DATA_CH2_1,
320
+
S2MPG11_METER_ACC_DATA_CH2_2,
321
+
S2MPG11_METER_ACC_DATA_CH2_3,
322
+
S2MPG11_METER_ACC_DATA_CH2_4,
323
+
S2MPG11_METER_ACC_DATA_CH2_5,
324
+
S2MPG11_METER_ACC_DATA_CH2_6,
325
+
S2MPG11_METER_ACC_DATA_CH3_1,
326
+
S2MPG11_METER_ACC_DATA_CH3_2,
327
+
S2MPG11_METER_ACC_DATA_CH3_3,
328
+
S2MPG11_METER_ACC_DATA_CH3_4,
329
+
S2MPG11_METER_ACC_DATA_CH3_5,
330
+
S2MPG11_METER_ACC_DATA_CH3_6,
331
+
S2MPG11_METER_ACC_DATA_CH4_1,
332
+
S2MPG11_METER_ACC_DATA_CH4_2,
333
+
S2MPG11_METER_ACC_DATA_CH4_3,
334
+
S2MPG11_METER_ACC_DATA_CH4_4,
335
+
S2MPG11_METER_ACC_DATA_CH4_5,
336
+
S2MPG11_METER_ACC_DATA_CH4_6,
337
+
S2MPG11_METER_ACC_DATA_CH5_1,
338
+
S2MPG11_METER_ACC_DATA_CH5_2,
339
+
S2MPG11_METER_ACC_DATA_CH5_3,
340
+
S2MPG11_METER_ACC_DATA_CH5_4,
341
+
S2MPG11_METER_ACC_DATA_CH5_5,
342
+
S2MPG11_METER_ACC_DATA_CH5_6,
343
+
S2MPG11_METER_ACC_DATA_CH6_1,
344
+
S2MPG11_METER_ACC_DATA_CH6_2,
345
+
S2MPG11_METER_ACC_DATA_CH6_3,
346
+
S2MPG11_METER_ACC_DATA_CH6_4,
347
+
S2MPG11_METER_ACC_DATA_CH6_5,
348
+
S2MPG11_METER_ACC_DATA_CH6_6,
349
+
S2MPG11_METER_ACC_DATA_CH7_1,
350
+
S2MPG11_METER_ACC_DATA_CH7_2,
351
+
S2MPG11_METER_ACC_DATA_CH7_3,
352
+
S2MPG11_METER_ACC_DATA_CH7_4,
353
+
S2MPG11_METER_ACC_DATA_CH7_5,
354
+
S2MPG11_METER_ACC_DATA_CH7_6,
355
+
S2MPG11_METER_ACC_COUNT_1,
356
+
S2MPG11_METER_ACC_COUNT_2,
357
+
S2MPG11_METER_ACC_COUNT_3,
358
+
S2MPG11_METER_LPF_DATA_CH0_1,
359
+
S2MPG11_METER_LPF_DATA_CH0_2,
360
+
S2MPG11_METER_LPF_DATA_CH0_3,
361
+
S2MPG11_METER_LPF_DATA_CH1_1,
362
+
S2MPG11_METER_LPF_DATA_CH1_2,
363
+
S2MPG11_METER_LPF_DATA_CH1_3,
364
+
S2MPG11_METER_LPF_DATA_CH2_1,
365
+
S2MPG11_METER_LPF_DATA_CH2_2,
366
+
S2MPG11_METER_LPF_DATA_CH2_3,
367
+
S2MPG11_METER_LPF_DATA_CH3_1,
368
+
S2MPG11_METER_LPF_DATA_CH3_2,
369
+
S2MPG11_METER_LPF_DATA_CH3_3,
370
+
S2MPG11_METER_LPF_DATA_CH4_1,
371
+
S2MPG11_METER_LPF_DATA_CH4_2,
372
+
S2MPG11_METER_LPF_DATA_CH4_3,
373
+
S2MPG11_METER_LPF_DATA_CH5_1,
374
+
S2MPG11_METER_LPF_DATA_CH5_2,
375
+
S2MPG11_METER_LPF_DATA_CH5_3,
376
+
S2MPG11_METER_LPF_DATA_CH6_1,
377
+
S2MPG11_METER_LPF_DATA_CH6_2,
378
+
S2MPG11_METER_LPF_DATA_CH6_3,
379
+
S2MPG11_METER_LPF_DATA_CH7_1,
380
+
S2MPG11_METER_LPF_DATA_CH7_2,
381
+
S2MPG11_METER_LPF_DATA_CH7_3,
382
+
/* Nothing @ 0x8b 0x8c */
383
+
S2MPG11_METER_LPF_DATA_NTC0_1 = 0x8d,
384
+
S2MPG11_METER_LPF_DATA_NTC0_2,
385
+
S2MPG11_METER_LPF_DATA_NTC1_1,
386
+
S2MPG11_METER_LPF_DATA_NTC1_2,
387
+
S2MPG11_METER_LPF_DATA_NTC2_1,
388
+
S2MPG11_METER_LPF_DATA_NTC2_2,
389
+
S2MPG11_METER_LPF_DATA_NTC3_1,
390
+
S2MPG11_METER_LPF_DATA_NTC3_2,
391
+
S2MPG11_METER_LPF_DATA_NTC4_1,
392
+
S2MPG11_METER_LPF_DATA_NTC4_2,
393
+
S2MPG11_METER_LPF_DATA_NTC5_1,
394
+
S2MPG11_METER_LPF_DATA_NTC5_2,
395
+
S2MPG11_METER_LPF_DATA_NTC6_1,
396
+
S2MPG11_METER_LPF_DATA_NTC6_2,
397
+
S2MPG11_METER_LPF_DATA_NTC7_1,
398
+
S2MPG11_METER_LPF_DATA_NTC7_2,
399
+
};
400
+
401
+
/* S2MPG11 regulator IDs */
402
+
enum s2mpg11_regulators {
403
+
S2MPG11_BUCKBOOST,
404
+
S2MPG11_BUCK1,
405
+
S2MPG11_BUCK2,
406
+
S2MPG11_BUCK3,
407
+
S2MPG11_BUCK4,
408
+
S2MPG11_BUCK5,
409
+
S2MPG11_BUCK6,
410
+
S2MPG11_BUCK7,
411
+
S2MPG11_BUCK8,
412
+
S2MPG11_BUCK9,
413
+
S2MPG11_BUCK10,
414
+
S2MPG11_BUCKD,
415
+
S2MPG11_BUCKA,
416
+
S2MPG11_LDO1,
417
+
S2MPG11_LDO2,
418
+
S2MPG11_LDO3,
419
+
S2MPG11_LDO4,
420
+
S2MPG11_LDO5,
421
+
S2MPG11_LDO6,
422
+
S2MPG11_LDO7,
423
+
S2MPG11_LDO8,
424
+
S2MPG11_LDO9,
425
+
S2MPG11_LDO10,
426
+
S2MPG11_LDO11,
427
+
S2MPG11_LDO12,
428
+
S2MPG11_LDO13,
429
+
S2MPG11_LDO14,
430
+
S2MPG11_LDO15,
431
+
S2MPG11_REGULATOR_MAX,
432
+
};
433
+
434
+
#endif /* __LINUX_MFD_S2MPG11_H */