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Merge tag 'pci-v6.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull pci updates from Bjorn Helgaas:
"Enumeration:

- Wait for device readiness after reset by polling Vendor ID and
looking for Configuration RRS instead of polling the Command
register and looking for non-error completions, to avoid hardware
retries done for RRS on non-Vendor ID reads (Bjorn Helgaas)

- Rename CRS Completion Status to RRS ('Request Retry Status') to
match PCIe r6.0 spec usage (Bjorn Helgaas)

- Clear LBMS bit after a manual link retrain so we don't try to
retrain a link when there's no downstream device anymore (Maciej W.
Rozycki)

- Revert to the original link speed after retraining fails instead of
leaving it restricted to 2.5GT/s, so a future device has a chance
to use higher speeds (Maciej W. Rozycki)

- Wait for each level of downstream bus, not just the first, to
become accessible before restoring devices on that bus (Ilpo
Järvinen)

- Add ARCH_PCI_DEV_GROUPS so s390 can add its own attribute_groups
without having to stomp on the core's pdev->dev.groups (Lukas
Wunner)

Driver binding:

- Export pcim_request_region(), a managed counterpart of
pci_request_region(), for use by drivers (Philipp Stanner)

- Export pcim_iomap_region() and deprecate pcim_iomap_regions()
(Philipp Stanner)

- Request the PCI BAR used by xboxvideo (Philipp Stanner)

- Request and map drm/ast BARs with pcim_iomap_region() (Philipp
Stanner)

MSI:

- Add MSI_FLAG_NO_AFFINITY flag for devices that mux MSIs onto a
single IRQ line and cannot set the affinity of each MSI to a
specific CPU core (Marek Vasut)

- Use MSI_FLAG_NO_AFFINITY and remove unnecessary .irq_set_affinity()
implementations in aardvark, altera, brcmstb, dwc, mediatek-gen3,
mediatek, mobiveil, plda, rcar, tegra, vmd, xilinx-nwl,
xilinx-xdma, and xilinx drivers to avoid 'IRQ: set affinity failed'
warnings (Marek Vasut)

Power management:

- Add pwrctl support for ATH11K inside the WCN6855 package (Konrad
Dybcio)

PCI device hotplug:

- Remove unnecessary hpc_ops struct from shpchp (ngn)

- Check for PCI_POSSIBLE_ERROR(), not 0xffffffff, in cpqphp
(weiyufeng)

Virtualization:

- Mark Creative Labs EMU20k2 INTx masking as broken (Alex Williamson)

- Add an ACS quirk for Qualcomm SA8775P, which doesn't advertise ACS
but does provide ACS-like features (Subramanian Ananthanarayanan)

IOMMU:

- Add function 0 DMA alias quirk for Glenfly Arise audio function,
which uses the function 0 Requester ID (WangYuli)

NPEM:

- Add Native PCIe Enclosure Management (NPEM) support for sysfs
control of NVMe RAID storage indicators (ok/fail/locate/
rebuild/etc) (Mariusz Tkaczyk)

- Add support for the ACPI _DSM PCIe SSD status LED management, which
is functionally similar to NPEM but mediated by platform firmware
(Mariusz Tkaczyk)

Device trees:

- Drop minItems and maxItems from ranges in PCI generic host binding
since host bridges may have several MMIO and I/O port apertures
(Frank Li)

- Add kirin, rcar-gen2, uniphier DT binding top-level constraints for
clocks (Krzysztof Kozlowski)

Altera PCIe controller driver:

- Convert altera DT bindings from text to YAML (Matthew Gerlach)

- Replace TLP_REQ_ID() with macro PCI_DEVID(), which does the same
thing and is what other drivers use (Jinjie Ruan)

Broadcom STB PCIe controller driver:

- Add DT binding maxItems for reset controllers (Jim Quinlan)

- Use the 'bridge' reset method if described in the DT (Jim Quinlan)

- Use the 'swinit' reset method if described in the DT (Jim Quinlan)

- Add 'has_phy' so the existence of a 'rescal' reset controller
doesn't imply software control of it (Jim Quinlan)

- Add support for many inbound DMA windows (Jim Quinlan)

- Rename SoC 'type' to 'soc_base' express the fact that SoCs come in
families of multiple similar devices (Jim Quinlan)

- Add Broadcom 7712 DT description and driver support (Jim Quinlan)

- Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings for
maintainability (Bjorn Helgaas)

Freescale i.MX6 PCIe controller driver:

- Add imx6q-pcie 'dbi2' and 'atu' reg-names for i.MX8M Endpoints
(Richard Zhu)

- Fix a code restructuring error that caused i.MX8MM and i.MX8MP
Endpoints to fail to establish link (Richard Zhu)

- Fix i.MX8MP Endpoint occasional failure to trigger MSI by enforcing
outbound alignment requirement (Richard Zhu)

- Call phy_power_off() in the .probe() error path (Frank Li)

- Rename internal names from imx6_* to imx_* since i.MX7/8/9 are also
supported (Frank Li)

- Manage Refclk by using SoC-specific callbacks instead of switch
statements (Frank Li)

- Manage core reset by using SoC-specific callbacks instead of switch
statements (Frank Li)

- Expand comments for erratum ERR010728 workaround (Frank Li)

- Use generic PHY APIs to configure mode, speed, and submode, which
is harmless for devices that implement their own internal PHY
management and don't set the generic imx_pcie->phy (Frank Li)

- Add i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) DT binding and driver
Root Complex support (Richard Zhu)

Freescale Layerscape PCIe controller driver:

- Replace layerscape-pcie DT binding compatible fsl,lx2160a-pcie with
fsl,lx2160ar2-pcie (Frank Li)

- Add layerscape-pcie DT binding deprecated 'num-viewport' property
to address a DT checker warning (Frank Li)

- Change layerscape-pcie DT binding 'fsl,pcie-scfg' to phandle-array
(Frank Li)

Loongson PCIe controller driver:

- Increase max PCI hosts to 8 for Loongson-3C6000 and newer chipsets
(Huacai Chen)

Marvell Aardvark PCIe controller driver:

- Fix issue with emulating Configuration RRS for two-byte reads of
Vendor ID; previously it only worked for four-byte reads (Bjorn
Helgaas)

MediaTek PCIe Gen3 controller driver:

- Add per-SoC struct mtk_gen3_pcie_pdata to support multiple SoC
types (Lorenzo Bianconi)

- Use reset_bulk APIs to manage PHY reset lines (Lorenzo Bianconi)

- Add DT and driver support for Airoha EN7581 PCIe controller
(Lorenzo Bianconi)

Qualcomm PCIe controller driver:

- Update qcom,pcie-sc7280 DT binding with eight interrupts (Rayyan
Ansari)

- Add back DT 'vddpe-3v3-supply', which was incorrectly removed
earlier (Johan Hovold)

- Drop endpoint redundant masking of global IRQ events (Manivannan
Sadhasivam)

- Clarify unknown global IRQ message and only log it once to avoid a
flood (Manivannan Sadhasivam)

- Add 'linux,pci-domain' property to endpoint DT binding (Manivannan
Sadhasivam)

- Assign PCI domain number for endpoint controllers (Manivannan
Sadhasivam)

- Add 'qcom_pcie_ep' and the PCI domain number to IRQ names for
endpoint controller (Manivannan Sadhasivam)

- Add global SPI interrupt for PCIe link events to DT binding
(Manivannan Sadhasivam)

- Add global RC interrupt handler to handle 'Link up' events and
automatically enumerate hot-added devices (Manivannan Sadhasivam)

- Avoid mirroring of DBI and iATU register space so it doesn't
overlap BAR MMIO space (Prudhvi Yarlagadda)

- Enable controller resources like PHY only after PERST# is
deasserted to partially avoid the problem that the endpoint SoC
crashes when accessing things when Refclk is absent (Manivannan
Sadhasivam)

- Add 16.0 GT/s equalization and RX lane margining settings (Shashank
Babu Chinta Venkata)

- Pass domain number to pci_bus_release_domain_nr() explicitly to
avoid a NULL pointer dereference (Manivannan Sadhasivam)

Renesas R-Car PCIe controller driver:

- Make the read-only const array 'check_addr' static (Colin Ian King)

- Add R-Car V4M (R8A779H0) PCIe host and endpoint to DT binding
(Yoshihiro Shimoda)

TI DRA7xx PCIe controller driver:

- Request IRQF_ONESHOT for 'dra7xx-pcie-main' IRQ since the primary
handler is NULL (Siddharth Vadapalli)

- Handle IRQ request errors during root port and endpoint probe
(Siddharth Vadapalli)

TI J721E PCIe driver:

- Add DT 'ti,syscon-acspcie-proxy-ctrl' and driver support to enable
the ACSPCIE module to drive Refclk for the Endpoint (Siddharth
Vadapalli)

- Extract the cadence link setup from cdns_pcie_host_setup() so link
setup can be done separately during resume (Thomas Richard)

- Add T_PERST_CLK_US definition for the mandatory delay between
Refclk becoming stable and PERST# being deasserted (Thomas Richard)

- Add j721e suspend and resume support (Théo Lebrun)

TI Keystone PCIe controller driver:

- Fix NULL pointer checking when applying MRRS limitation quirk for
AM65x SR 1.0 Errata #i2037 (Dan Carpenter)

Xilinx NWL PCIe controller driver:

- Fix off-by-one error in INTx IRQ handler that caused INTx
interrupts to be lost or delivered as the wrong interrupt (Sean
Anderson)

- Rate-limit misc interrupt messages (Sean Anderson)

- Turn off the clock on probe failure and device removal (Sean
Anderson)

- Add DT binding and driver support for enabling/disabling PHYs (Sean
Anderson)

- Add PCIe phy bindings for the ZCU102 (Sean Anderson)

Xilinx XDMA PCIe controller driver:

- Add support for Xilinx QDMA Soft IP PCIe Root Port Bridge to DT
binding and xilinx-dma-pl driver (Thippeswamy Havalige)

Miscellaneous:

- Fix buffer overflow in kirin_pcie_parse_port() (Alexandra Diupina)

- Fix minor kerneldoc issues and typos (Bjorn Helgaas)

- Use PCI_DEVID() macro in aer_inject() instead of open-coding it
(Jinjie Ruan)

- Check pcie_find_root_port() return in x86 fixups to avoid NULL
pointer dereferences (Samasth Norway Ananda)

- Make pci_bus_type constant (Kunwu Chan)

- Remove unused declarations of __pci_pme_wakeup() and
pci_vpd_release() (Yue Haibing)

- Remove any leftover .*.cmd files with make clean (zhang jiao)

- Remove unused BILLION macro (zhang jiao)"

* tag 'pci-v6.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (132 commits)
PCI: Fix typos
dt-bindings: PCI: qcom: Allow 'vddpe-3v3-supply' again
tools: PCI: Remove unused BILLION macro
tools: PCI: Remove .*.cmd files with make clean
PCI: Pass domain number to pci_bus_release_domain_nr() explicitly
PCI: dra7xx: Fix error handling when IRQ request fails in probe
PCI: dra7xx: Fix threaded IRQ request for "dra7xx-pcie-main" IRQ
PCI: qcom: Add RX lane margining settings for 16.0 GT/s
PCI: qcom: Add equalization settings for 16.0 GT/s
PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
PCI: Mark Creative Labs EMU20k2 INTx masking as broken
dt-bindings: PCI: imx6q-pcie: Add reg-name "dbi2" and "atu" for i.MX8M PCIe Endpoint
dt-bindings: PCI: altera: msi: Convert to YAML
PCI: imx6: Add i.MX8Q PCIe Root Complex (RC) support
PCI: Rename CRS Completion Status to RRS
PCI: aardvark: Correct Configuration RRS checking
PCI: Wait for device readiness with Configuration RRS
PCI: brcmstb: Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings
...

+3369 -1339
+72
Documentation/ABI/testing/sysfs-bus-pci
··· 500 500 console drivers from the device. Raw users of pci-sysfs 501 501 resourceN attributes must be terminated prior to resizing. 502 502 Success of the resizing operation is not guaranteed. 503 + 504 + What: /sys/bus/pci/devices/.../leds/*:enclosure:*/brightness 505 + What: /sys/class/leds/*:enclosure:*/brightness 506 + Date: August 2024 507 + KernelVersion: 6.12 508 + Description: 509 + LED indications on PCIe storage enclosures which are controlled 510 + through the NPEM interface (Native PCIe Enclosure Management, 511 + PCIe r6.1 sec 6.28) are accessible as led class devices, both 512 + below /sys/class/leds and below NPEM-capable PCI devices. 513 + 514 + Although these led class devices could be manipulated manually, 515 + in practice they are typically manipulated automatically by an 516 + application such as ledmon(8). 517 + 518 + The name of a led class device is as follows: 519 + <bdf>:enclosure:<indication> 520 + where: 521 + 522 + - <bdf> is the domain, bus, device and function number 523 + (e.g. 10000:02:05.0) 524 + - <indication> is a short description of the LED indication 525 + 526 + Valid indications per PCIe r6.1 table 6-27 are: 527 + 528 + - ok (drive is functioning normally) 529 + - locate (drive is being identified by an admin) 530 + - fail (drive is not functioning properly) 531 + - rebuild (drive is part of an array that is rebuilding) 532 + - pfa (drive is predicted to fail soon) 533 + - hotspare (drive is marked to be used as a replacement) 534 + - ica (drive is part of an array that is degraded) 535 + - ifa (drive is part of an array that is failed) 536 + - idt (drive is not the right type for the connector) 537 + - disabled (drive is disabled, removal is safe) 538 + - specific0 to specific7 (enclosure-specific indications) 539 + 540 + Broadly, the indications fall into one of these categories: 541 + 542 + - to signify drive state (ok, locate, fail, idt, disabled) 543 + - to signify drive role or state in a software RAID array 544 + (rebuild, pfa, hotspare, ica, ifa) 545 + - to signify any other role or state (specific0 to specific7) 546 + 547 + Mandatory indications per PCIe r6.1 sec 7.9.19.2 comprise: 548 + ok, locate, fail, rebuild. All others are optional. 549 + A led class device is only visible if the corresponding 550 + indication is supported by the device. 551 + 552 + To manipulate the indications, write 0 (LED_OFF) or 1 (LED_ON) 553 + to the "brightness" file. Note that manipulating an indication 554 + may implicitly manipulate other indications at the vendor's 555 + discretion. E.g. when the user lights up the "ok" indication, 556 + the vendor may choose to automatically turn off the "fail" 557 + indication. The current state of an indication can be 558 + retrieved by reading its "brightness" file. 559 + 560 + The PCIe Base Specification allows vendors leeway to choose 561 + different colors or blinking patterns for the indications, 562 + but they typically follow the IBPI standard. E.g. the "locate" 563 + indication is usually presented as one or two LEDs blinking at 564 + 4 Hz frequency: 565 + https://en.wikipedia.org/wiki/International_Blinking_Pattern_Interpretation 566 + 567 + PCI Firmware Specification r3.3 sec 4.7 defines a DSM interface 568 + to facilitate shared access by operating system and platform 569 + firmware to a device's NPEM registers. The kernel will use 570 + this DSM interface where available, instead of accessing NPEM 571 + registers directly. The DSM interface does not support the 572 + enclosure-specific indications "specific0" to "specific7", 573 + hence the corresponding led class devices are unavailable if 574 + the DSM interface is used.
-27
Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
··· 1 - * Altera PCIe MSI controller 2 - 3 - Required properties: 4 - - compatible: should contain "altr,msi-1.0" 5 - - reg: specifies the physical base address of the controller and 6 - the length of the memory mapped region. 7 - - reg-names: must include the following entries: 8 - "csr": CSR registers 9 - "vector_slave": vectors slave port region 10 - - interrupts: specifies the interrupt source of the parent interrupt 11 - controller. The format of the interrupt specifier depends on the 12 - parent interrupt controller. 13 - - num-vectors: number of vectors, range 1 to 32. 14 - - msi-controller: indicates that this is MSI controller node 15 - 16 - 17 - Example 18 - msi0: msi@0xFF200000 { 19 - compatible = "altr,msi-1.0"; 20 - reg = <0xFF200000 0x00000010 21 - 0xFF200010 0x00000080>; 22 - reg-names = "csr", "vector_slave"; 23 - interrupt-parent = <&hps_0_arm_gic_0>; 24 - interrupts = <0 42 4>; 25 - msi-controller; 26 - num-vectors = <32>; 27 - };
-50
Documentation/devicetree/bindings/pci/altera-pcie.txt
··· 1 - * Altera PCIe controller 2 - 3 - Required properties: 4 - - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" 5 - - reg: a list of physical base address and length for TXS and CRA. 6 - For "altr,pcie-root-port-2.0", additional HIP base address and length. 7 - - reg-names: must include the following entries: 8 - "Txs": TX slave port region 9 - "Cra": Control register access region 10 - "Hip": Hard IP region (if "altr,pcie-root-port-2.0") 11 - - interrupts: specifies the interrupt source of the parent interrupt 12 - controller. The format of the interrupt specifier depends 13 - on the parent interrupt controller. 14 - - device_type: must be "pci" 15 - - #address-cells: set to <3> 16 - - #size-cells: set to <2> 17 - - #interrupt-cells: set to <1> 18 - - ranges: describes the translation of addresses for root ports and 19 - standard PCI regions. 20 - - interrupt-map-mask and interrupt-map: standard PCI properties to define the 21 - mapping of the PCIe interface to interrupt numbers. 22 - 23 - Optional properties: 24 - - msi-parent: Link to the hardware entity that serves as the MSI controller 25 - for this PCIe controller. 26 - - bus-range: PCI bus numbers covered 27 - 28 - Example 29 - pcie_0: pcie@c00000000 { 30 - compatible = "altr,pcie-root-port-1.0"; 31 - reg = <0xc0000000 0x20000000>, 32 - <0xff220000 0x00004000>; 33 - reg-names = "Txs", "Cra"; 34 - interrupt-parent = <&hps_0_arm_gic_0>; 35 - interrupts = <0 40 4>; 36 - interrupt-controller; 37 - #interrupt-cells = <1>; 38 - bus-range = <0x0 0xFF>; 39 - device_type = "pci"; 40 - msi-parent = <&msi_to_gic_gen_0>; 41 - #address-cells = <3>; 42 - #size-cells = <2>; 43 - interrupt-map-mask = <0 0 0 7>; 44 - interrupt-map = <0 0 0 1 &pcie_0 1>, 45 - <0 0 0 2 &pcie_0 2>, 46 - <0 0 0 3 &pcie_0 3>, 47 - <0 0 0 4 &pcie_0 4>; 48 - ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000 49 - 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>; 50 - };
+65
Documentation/devicetree/bindings/pci/altr,msi-controller.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + # Copyright (C) 2015, 2024, Intel Corporation 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/altr,msi-controller.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: Altera PCIe MSI controller 9 + 10 + maintainers: 11 + - Matthew Gerlach <matthew.gerlach@linux.intel.com> 12 + 13 + properties: 14 + compatible: 15 + enum: 16 + - altr,msi-1.0 17 + 18 + reg: 19 + items: 20 + - description: CSR registers 21 + - description: Vectors slave port region 22 + 23 + reg-names: 24 + items: 25 + - const: csr 26 + - const: vector_slave 27 + 28 + interrupts: 29 + maxItems: 1 30 + 31 + msi-controller: true 32 + 33 + num-vectors: 34 + description: number of vectors 35 + $ref: /schemas/types.yaml#/definitions/uint32 36 + minimum: 1 37 + maximum: 32 38 + 39 + required: 40 + - compatible 41 + - reg 42 + - reg-names 43 + - interrupts 44 + - msi-controller 45 + - num-vectors 46 + 47 + allOf: 48 + - $ref: /schemas/interrupt-controller/msi-controller.yaml# 49 + 50 + unevaluatedProperties: false 51 + 52 + examples: 53 + - | 54 + #include <dt-bindings/interrupt-controller/arm-gic.h> 55 + #include <dt-bindings/interrupt-controller/irq.h> 56 + msi@ff200000 { 57 + compatible = "altr,msi-1.0"; 58 + reg = <0xff200000 0x00000010>, 59 + <0xff200010 0x00000080>; 60 + reg-names = "csr", "vector_slave"; 61 + interrupt-parent = <&hps_0_arm_gic_0>; 62 + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 63 + msi-controller; 64 + num-vectors = <32>; 65 + };
+114
Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + # Copyright (C) 2015, 2019, 2024, Intel Corporation 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/altr,pcie-root-port.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: Altera PCIe Root Port 9 + 10 + maintainers: 11 + - Matthew Gerlach <matthew.gerlach@linux.intel.com> 12 + 13 + properties: 14 + compatible: 15 + enum: 16 + - altr,pcie-root-port-1.0 17 + - altr,pcie-root-port-2.0 18 + 19 + reg: 20 + items: 21 + - description: TX slave port region 22 + - description: Control register access region 23 + - description: Hard IP region 24 + minItems: 2 25 + 26 + reg-names: 27 + items: 28 + - const: Txs 29 + - const: Cra 30 + - const: Hip 31 + minItems: 2 32 + 33 + interrupts: 34 + maxItems: 1 35 + 36 + interrupt-controller: true 37 + 38 + interrupt-map-mask: 39 + items: 40 + - const: 0 41 + - const: 0 42 + - const: 0 43 + - const: 7 44 + 45 + interrupt-map: 46 + maxItems: 4 47 + 48 + "#interrupt-cells": 49 + const: 1 50 + 51 + msi-parent: true 52 + 53 + required: 54 + - compatible 55 + - reg 56 + - reg-names 57 + - interrupts 58 + - "#interrupt-cells" 59 + - interrupt-controller 60 + - interrupt-map 61 + - interrupt-map-mask 62 + 63 + allOf: 64 + - $ref: /schemas/pci/pci-host-bridge.yaml# 65 + - if: 66 + properties: 67 + compatible: 68 + enum: 69 + - altr,pcie-root-port-1.0 70 + then: 71 + properties: 72 + reg: 73 + maxItems: 2 74 + 75 + reg-names: 76 + maxItems: 2 77 + 78 + else: 79 + properties: 80 + reg: 81 + minItems: 3 82 + 83 + reg-names: 84 + minItems: 3 85 + 86 + 87 + unevaluatedProperties: false 88 + 89 + examples: 90 + - | 91 + #include <dt-bindings/interrupt-controller/arm-gic.h> 92 + #include <dt-bindings/interrupt-controller/irq.h> 93 + pcie_0: pcie@c00000000 { 94 + compatible = "altr,pcie-root-port-1.0"; 95 + reg = <0xc0000000 0x20000000>, 96 + <0xff220000 0x00004000>; 97 + reg-names = "Txs", "Cra"; 98 + interrupt-parent = <&hps_0_arm_gic_0>; 99 + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 100 + interrupt-controller; 101 + #interrupt-cells = <1>; 102 + bus-range = <0x0 0xff>; 103 + device_type = "pci"; 104 + msi-parent = <&msi_to_gic_gen_0>; 105 + #address-cells = <3>; 106 + #size-cells = <2>; 107 + interrupt-map-mask = <0 0 0 7>; 108 + interrupt-map = <0 0 0 1 &pcie_0 0 0 0 1>, 109 + <0 0 0 2 &pcie_0 0 0 0 2>, 110 + <0 0 0 3 &pcie_0 0 0 0 3>, 111 + <0 0 0 4 &pcie_0 0 0 0 4>; 112 + ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000>, 113 + <0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>; 114 + };
+35 -7
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
··· 7 7 title: Brcmstb PCIe Host Controller 8 8 9 9 maintainers: 10 - - Nicolas Saenz Julienne <nsaenzjulienne@suse.de> 10 + - Jim Quinlan <james.quinlan@broadcom.com> 11 11 12 12 properties: 13 13 compatible: ··· 16 16 - brcm,bcm2711-pcie # The Raspberry Pi 4 17 17 - brcm,bcm4908-pcie 18 18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4 19 - - brcm,bcm7278-pcie # Broadcom 7278 Arm 20 19 - brcm,bcm7216-pcie # Broadcom 7216 Arm 21 - - brcm,bcm7445-pcie # Broadcom 7445 Arm 20 + - brcm,bcm7278-pcie # Broadcom 7278 Arm 22 21 - brcm,bcm7425-pcie # Broadcom 7425 MIPs 23 22 - brcm,bcm7435-pcie # Broadcom 7435 MIPs 23 + - brcm,bcm7445-pcie # Broadcom 7445 Arm 24 + - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5 24 25 25 26 reg: 26 27 maxItems: 1 ··· 96 95 minItems: 1 97 96 maxItems: 3 98 97 98 + resets: 99 + minItems: 1 100 + maxItems: 3 101 + 102 + reset-names: 103 + minItems: 1 104 + maxItems: 3 105 + 99 106 required: 100 107 - compatible 101 108 - reg ··· 127 118 then: 128 119 properties: 129 120 resets: 130 - items: 131 - - description: reset controller handling the PERST# signal 121 + maxItems: 1 132 122 133 123 reset-names: 134 124 items: ··· 144 136 then: 145 137 properties: 146 138 resets: 147 - items: 148 - - description: phandle pointing to the RESCAL reset controller 139 + maxItems: 1 149 140 150 141 reset-names: 151 142 items: 152 143 - const: rescal 144 + 145 + required: 146 + - resets 147 + - reset-names 148 + 149 + - if: 150 + properties: 151 + compatible: 152 + contains: 153 + const: brcm,bcm7712-pcie 154 + then: 155 + properties: 156 + resets: 157 + minItems: 3 158 + maxItems: 3 159 + 160 + reset-names: 161 + items: 162 + - const: rescal 163 + - const: bridge 164 + - const: swinit 153 165 154 166 required: 155 167 - resets
+9 -4
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
··· 65 65 then: 66 66 properties: 67 67 reg: 68 - minItems: 2 69 - maxItems: 2 68 + minItems: 4 69 + maxItems: 4 70 70 reg-names: 71 71 items: 72 72 - const: dbi 73 73 - const: addr_space 74 + - const: dbi2 75 + - const: atu 74 76 75 77 - if: 76 78 properties: ··· 131 129 132 130 pcie_ep: pcie-ep@33800000 { 133 131 compatible = "fsl,imx8mp-pcie-ep"; 134 - reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; 135 - reg-names = "dbi", "addr_space"; 132 + reg = <0x33800000 0x100000>, 133 + <0x18000000 0x8000000>, 134 + <0x33900000 0x100000>, 135 + <0x33b00000 0x100000>; 136 + reg-names = "dbi", "addr_space", "dbi2", "atu"; 136 137 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 137 138 <&clk IMX8MP_CLK_HSIO_AXI>, 138 139 <&clk IMX8MP_CLK_PCIE_ROOT>;
+16
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
··· 30 30 - fsl,imx8mm-pcie 31 31 - fsl,imx8mp-pcie 32 32 - fsl,imx95-pcie 33 + - fsl,imx8q-pcie 33 34 34 35 clocks: 35 36 minItems: 3 ··· 184 183 - const: pcie 185 184 - const: pcie_bus 186 185 - const: pcie_aux 186 + 187 + - if: 188 + properties: 189 + compatible: 190 + enum: 191 + - fsl,imx8q-pcie 192 + then: 193 + properties: 194 + clocks: 195 + maxItems: 3 196 + clock-names: 197 + items: 198 + - const: dbi 199 + - const: mstr 200 + - const: slv 187 201 188 202 unevaluatedProperties: false 189 203
+28 -13
Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
··· 22 22 23 23 properties: 24 24 compatible: 25 - enum: 26 - - fsl,ls1021a-pcie 27 - - fsl,ls2080a-pcie 28 - - fsl,ls2085a-pcie 29 - - fsl,ls2088a-pcie 30 - - fsl,ls1088a-pcie 31 - - fsl,ls1046a-pcie 32 - - fsl,ls1043a-pcie 33 - - fsl,ls1012a-pcie 34 - - fsl,ls1028a-pcie 35 - - fsl,lx2160a-pcie 36 - 25 + oneOf: 26 + - enum: 27 + - fsl,ls1012a-pcie 28 + - fsl,ls1021a-pcie 29 + - fsl,ls1028a-pcie 30 + - fsl,ls1043a-pcie 31 + - fsl,ls1046a-pcie 32 + - fsl,ls1088a-pcie 33 + - fsl,ls2080a-pcie 34 + - fsl,ls2085a-pcie 35 + - fsl,ls2088a-pcie 36 + - items: 37 + - const: fsl,lx2160ar2-pcie 38 + - const: fsl,ls2088a-pcie 37 39 reg: 38 40 maxItems: 2 39 41 ··· 45 43 - const: config 46 44 47 45 fsl,pcie-scfg: 48 - $ref: /schemas/types.yaml#/definitions/phandle 46 + $ref: /schemas/types.yaml#/definitions/phandle-array 49 47 description: A phandle to the SCFG device node. The second entry is the 50 48 physical PCIe controller index starting from '0'. This is used to get 51 49 SCFG PEXN registers. 50 + items: 51 + items: 52 + - description: A phandle to the SCFG device node 53 + - description: PCIe controller index starting from '0' 54 + maxItems: 1 52 55 53 56 big-endian: 54 57 $ref: /schemas/types.yaml#/definitions/flag ··· 73 66 interrupt-names: 74 67 minItems: 1 75 68 maxItems: 2 69 + 70 + num-viewport: 71 + $ref: /schemas/types.yaml#/definitions/uint32 72 + deprecated: true 73 + description: 74 + Number of outbound view ports configured in hardware. It's the same as 75 + the number of outbound AT windows. 76 + maximum: 256 76 77 77 78 required: 78 79 - compatible
+2 -1
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
··· 37 37 minItems: 3 38 38 maxItems: 4 39 39 40 - clocks: true 40 + clocks: 41 + maxItems: 5 41 42 42 43 clock-names: 43 44 items:
-2
Documentation/devicetree/bindings/pci/host-generic-pci.yaml
··· 102 102 As described in IEEE Std 1275-1994, but must provide at least a 103 103 definition of non-prefetchable memory. One or both of prefetchable Memory 104 104 and IO Space may also be provided. 105 - minItems: 1 106 - maxItems: 3 107 105 108 106 dma-coherent: true 109 107 iommu-map: true
+63 -5
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
··· 53 53 - mediatek,mt8195-pcie 54 54 - const: mediatek,mt8192-pcie 55 55 - const: mediatek,mt8192-pcie 56 + - const: airoha,en7581-pcie 56 57 57 58 reg: 58 59 maxItems: 1 ··· 77 76 78 77 resets: 79 78 minItems: 1 80 - maxItems: 2 79 + maxItems: 3 81 80 82 81 reset-names: 83 82 minItems: 1 84 - maxItems: 2 83 + maxItems: 3 85 84 items: 86 - enum: [ phy, mac ] 85 + enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ] 87 86 88 87 clocks: 89 - minItems: 4 88 + minItems: 1 90 89 maxItems: 6 91 90 92 91 clock-names: 93 - minItems: 4 92 + minItems: 1 94 93 maxItems: 6 95 94 96 95 assigned-clocks: ··· 148 147 const: mediatek,mt8192-pcie 149 148 then: 150 149 properties: 150 + clocks: 151 + minItems: 4 152 + 151 153 clock-names: 152 154 items: 153 155 - const: pl_250m ··· 159 155 - const: tl_32k 160 156 - const: peri_26m 161 157 - const: top_133m 158 + 159 + resets: 160 + minItems: 1 161 + maxItems: 2 162 + 163 + reset-names: 164 + minItems: 1 165 + maxItems: 2 166 + 162 167 - if: 163 168 properties: 164 169 compatible: ··· 177 164 - mediatek,mt8195-pcie 178 165 then: 179 166 properties: 167 + clocks: 168 + minItems: 4 169 + 180 170 clock-names: 181 171 items: 182 172 - const: pl_250m ··· 188 172 - const: tl_32k 189 173 - const: peri_26m 190 174 - const: peri_mem 175 + 176 + resets: 177 + minItems: 1 178 + maxItems: 2 179 + 180 + reset-names: 181 + minItems: 1 182 + maxItems: 2 183 + 191 184 - if: 192 185 properties: 193 186 compatible: ··· 205 180 - mediatek,mt7986-pcie 206 181 then: 207 182 properties: 183 + clocks: 184 + minItems: 4 185 + 208 186 clock-names: 209 187 items: 210 188 - const: pl_250m 211 189 - const: tl_26m 212 190 - const: peri_26m 213 191 - const: top_133m 192 + 193 + resets: 194 + minItems: 1 195 + maxItems: 2 196 + 197 + reset-names: 198 + minItems: 1 199 + maxItems: 2 200 + 201 + - if: 202 + properties: 203 + compatible: 204 + const: airoha,en7581-pcie 205 + then: 206 + properties: 207 + clocks: 208 + maxItems: 1 209 + 210 + clock-names: 211 + items: 212 + - const: sys-ck 213 + 214 + resets: 215 + minItems: 3 216 + 217 + reset-names: 218 + items: 219 + - const: phy-lane0 220 + - const: phy-lane1 221 + - const: phy-lane2 214 222 215 223 unevaluatedProperties: false 216 224
+13 -1
Documentation/devicetree/bindings/pci/pci-ep.yaml
··· 10 10 Common properties for PCI Endpoint Controller Nodes. 11 11 12 12 maintainers: 13 - - Kishon Vijay Abraham I <kishon@ti.com> 13 + - Kishon Vijay Abraham I <kishon@kernel.org> 14 + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 14 15 15 16 properties: 16 17 $nodename: ··· 41 40 minimum: 1 42 41 default: 1 43 42 maximum: 16 43 + 44 + linux,pci-domain: 45 + description: 46 + If present this property assigns a fixed PCI domain number to a PCI 47 + Endpoint Controller, otherwise an unstable (across boots) unique number 48 + will be assigned. It is required to either not set this property at all 49 + or set it for all PCI endpoint controllers in the system, otherwise 50 + potentially conflicting domain numbers may be assigned to endpoint 51 + controllers. The domain number for each endpoint controller in the system 52 + must be unique. 53 + $ref: /schemas/types.yaml#/definitions/uint32 44 54 45 55 required: 46 56 - compatible
+5 -2
Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
··· 21 21 22 22 interrupts: 23 23 minItems: 1 24 - maxItems: 8 24 + maxItems: 9 25 25 26 26 interrupt-names: 27 27 minItems: 1 28 - maxItems: 8 28 + maxItems: 9 29 29 30 30 iommu-map: 31 31 minItems: 1 ··· 77 77 wake-gpios: 78 78 description: GPIO controlled connection to WAKE# signal 79 79 maxItems: 1 80 + 81 + vddpe-3v3-supply: 82 + description: PCIe endpoint power supply 80 83 81 84 required: 82 85 - reg
+1
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
··· 280 280 phy-names = "pciephy"; 281 281 max-link-speed = <3>; 282 282 num-lanes = <2>; 283 + linux,pci-domain = <0>; 283 284 };
+20 -7
Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml
··· 53 53 - const: aggre1 # Aggre NoC PCIe1 AXI clock 54 54 55 55 interrupts: 56 - maxItems: 1 56 + minItems: 8 57 + maxItems: 8 57 58 58 59 interrupt-names: 59 60 items: 60 - - const: msi 61 + - const: msi0 62 + - const: msi1 63 + - const: msi2 64 + - const: msi3 65 + - const: msi4 66 + - const: msi5 67 + - const: msi6 68 + - const: msi7 61 69 62 70 resets: 63 71 maxItems: 1 ··· 73 65 reset-names: 74 66 items: 75 67 - const: pci 76 - 77 - vddpe-3v3-supply: 78 - description: PCIe endpoint power supply 79 68 80 69 allOf: 81 70 - $ref: qcom,pcie-common.yaml# ··· 142 137 143 138 dma-coherent; 144 139 145 - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 146 - interrupt-names = "msi"; 140 + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 141 + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 142 + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 143 + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 144 + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 145 + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 146 + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 147 + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 148 + interrupt-names = "msi0", "msi1", "msi2", "msi3", 149 + "msi4", "msi5", "msi6", "msi7"; 147 150 #interrupt-cells = <1>; 148 151 interrupt-map-mask = <0 0 0 0x7>; 149 152 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
-3
Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml
··· 58 58 items: 59 59 - const: pci 60 60 61 - vddpe-3v3-supply: 62 - description: A phandle to the PCIe endpoint power supply 63 - 64 61 required: 65 62 - interconnects 66 63 - interconnect-names
+6 -4
Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
··· 55 55 - const: aggre1 # Aggre NoC PCIe1 AXI clock 56 56 57 57 interrupts: 58 - minItems: 8 59 - maxItems: 8 58 + minItems: 9 59 + maxItems: 9 60 60 61 61 interrupt-names: 62 62 items: ··· 68 68 - const: msi5 69 69 - const: msi6 70 70 - const: msi7 71 + - const: global 71 72 72 73 operating-points-v2: true 73 74 opp-table: ··· 150 149 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 151 150 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 152 151 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 153 - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 152 + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 153 + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 154 154 interrupt-names = "msi0", "msi1", "msi2", "msi3", 155 - "msi4", "msi5", "msi6", "msi7"; 155 + "msi4", "msi5", "msi6", "msi7", "global"; 156 156 #interrupt-cells = <1>; 157 157 interrupt-map-mask = <0 0 0 0x7>; 158 158 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+3
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
··· 91 91 vdda_refclk-supply: 92 92 description: A phandle to the core analog power supply for IC which generates reference clock 93 93 94 + vddpe-3v3-supply: 95 + description: A phandle to the PCIe endpoint power supply 96 + 94 97 phys: 95 98 maxItems: 1 96 99
+1
Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
··· 19 19 - enum: 20 20 - renesas,r8a779f0-pcie-ep # R-Car S4-8 21 21 - renesas,r8a779g0-pcie-ep # R-Car V4H 22 + - renesas,r8a779h0-pcie-ep # R-Car V4M 22 23 - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4 23 24 24 25 reg:
+1
Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
··· 19 19 - enum: 20 20 - renesas,r8a779f0-pcie # R-Car S4-8 21 21 - renesas,r8a779g0-pcie # R-Car V4H 22 + - renesas,r8a779h0-pcie # R-Car V4M 22 23 - const: renesas,rcar-gen4-pcie # R-Car Gen4 23 24 24 25 reg:
+6 -2
Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
··· 42 42 interrupts: 43 43 maxItems: 1 44 44 45 - clocks: true 45 + clocks: 46 + minItems: 1 47 + maxItems: 3 46 48 47 - clock-names: true 49 + clock-names: 50 + minItems: 1 51 + maxItems: 3 48 52 49 53 resets: 50 54 maxItems: 1
+6 -2
Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
··· 38 38 minItems: 1 39 39 maxItems: 2 40 40 41 - clock-names: true 41 + clock-names: 42 + minItems: 1 43 + maxItems: 2 42 44 43 45 resets: 44 46 minItems: 1 45 47 maxItems: 2 46 48 47 - reset-names: true 49 + reset-names: 50 + minItems: 1 51 + maxItems: 2 48 52 49 53 num-ib-windows: 50 54 const: 16
+10
Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
··· 38 38 - const: reg 39 39 - const: cfg 40 40 41 + ti,syscon-acspcie-proxy-ctrl: 42 + $ref: /schemas/types.yaml#/definitions/phandle-array 43 + items: 44 + - items: 45 + - description: Phandle to the ACSPCIE Proxy Control Register 46 + - description: Bitmask corresponding to the PAD IO Buffer 47 + output enable fields (Active Low). 48 + description: Specifier for enabling the ACSPCIE PAD outputs to drive 49 + the reference clock to the Endpoint device. 50 + 41 51 ti,syscon-pcie-ctrl: 42 52 $ref: /schemas/types.yaml#/definitions/phandle-array 43 53 items:
+7
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
··· 61 61 interrupt-map: 62 62 maxItems: 4 63 63 64 + phys: 65 + minItems: 1 66 + maxItems: 4 67 + description: One phy per logical lane, in order 68 + 64 69 power-domains: 65 70 maxItems: 1 66 71 ··· 115 110 - | 116 111 #include <dt-bindings/interrupt-controller/arm-gic.h> 117 112 #include <dt-bindings/interrupt-controller/irq.h> 113 + #include <dt-bindings/phy/phy.h> 118 114 #include <dt-bindings/power/xlnx-zynqmp-power.h> 119 115 soc { 120 116 #address-cells = <2>; ··· 144 138 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 145 139 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 146 140 msi-parent = <&nwl_pcie>; 141 + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; 147 142 power-domains = <&zynqmp_firmware PD_PCIE>; 148 143 iommus = <&smmu 0x4d0>; 149 144 pcie_intc: legacy-interrupt-controller {
+34 -2
Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
··· 14 14 15 15 properties: 16 16 compatible: 17 - const: xlnx,xdma-host-3.00 17 + enum: 18 + - xlnx,xdma-host-3.00 19 + - xlnx,qdma-host-3.00 18 20 19 21 reg: 20 - maxItems: 1 22 + items: 23 + - description: configuration region and XDMA bridge register. 24 + - description: QDMA bridge register. 25 + minItems: 1 26 + 27 + reg-names: 28 + items: 29 + - const: cfg 30 + - const: breg 31 + minItems: 1 21 32 22 33 ranges: 23 34 maxItems: 2 ··· 86 75 - interrupt-map-mask 87 76 - "#interrupt-cells" 88 77 - interrupt-controller 78 + 79 + if: 80 + properties: 81 + compatible: 82 + contains: 83 + enum: 84 + - xlnx,qdma-host-3.00 85 + then: 86 + properties: 87 + reg: 88 + minItems: 2 89 + reg-names: 90 + minItems: 2 91 + required: 92 + - reg-names 93 + else: 94 + properties: 95 + reg: 96 + maxItems: 1 97 + reg-names: 98 + maxItems: 1 89 99 90 100 unevaluatedProperties: false 91 101
+5 -3
MAINTAINERS
··· 2793 2793 F: drivers/mfd/ssbi.c 2794 2794 F: drivers/mmc/host/mmci_qcom* 2795 2795 F: drivers/mmc/host/sdhci-msm.c 2796 - F: drivers/pci/controller/dwc/pcie-qcom.c 2796 + F: drivers/pci/controller/dwc/pcie-qcom* 2797 2797 F: drivers/phy/qualcomm/ 2798 2798 F: drivers/power/*/msm* 2799 2799 F: drivers/reset/reset-qcom-* ··· 17544 17544 M: Joyce Ooi <joyce.ooi@intel.com> 17545 17545 L: linux-pci@vger.kernel.org 17546 17546 S: Supported 17547 - F: Documentation/devicetree/bindings/pci/altera-pcie.txt 17547 + F: Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml 17548 17548 F: drivers/pci/controller/pcie-altera.c 17549 17549 17550 17550 PCI DRIVER FOR APPLIEDMICRO XGENE ··· 17776 17776 M: Joyce Ooi <joyce.ooi@intel.com> 17777 17777 L: linux-pci@vger.kernel.org 17778 17778 S: Supported 17779 - F: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt 17779 + F: Documentation/devicetree/bindings/pci/altr,msi-controller.yaml 17780 17780 F: drivers/pci/controller/pcie-altera-msi.c 17781 17781 17782 17782 PCI MSI DRIVER FOR APPLIEDMICRO XGENE ··· 17929 17929 L: linux-pci@vger.kernel.org 17930 17930 L: linux-arm-msm@vger.kernel.org 17931 17931 S: Maintained 17932 + F: drivers/pci/controller/dwc/pcie-qcom-common.c 17932 17933 F: drivers/pci/controller/dwc/pcie-qcom.c 17933 17934 17934 17935 PCIE DRIVER FOR ROCKCHIP ··· 17966 17965 L: linux-arm-msm@vger.kernel.org 17967 17966 S: Maintained 17968 17967 F: Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml 17968 + F: drivers/pci/controller/dwc/pcie-qcom-common.c 17969 17969 F: drivers/pci/controller/dwc/pcie-qcom-ep.c 17970 17970 17971 17971 PCMCIA SUBSYSTEM
+1
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
··· 941 941 942 942 &pcie { 943 943 status = "okay"; 944 + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; 944 945 }; 945 946 946 947 &psgtr {
+8 -1
arch/s390/include/asm/pci.h
··· 191 191 return (zdev->fh & (1UL << 31)) ? true : false; 192 192 } 193 193 194 - extern const struct attribute_group *zpci_attr_groups[]; 194 + extern const struct attribute_group zpci_attr_group; 195 + extern const struct attribute_group pfip_attr_group; 196 + extern const struct attribute_group zpci_ident_attr_group; 197 + 198 + #define ARCH_PCI_DEV_GROUPS &zpci_attr_group, \ 199 + &pfip_attr_group, \ 200 + &zpci_ident_attr_group, 201 + 195 202 extern unsigned int s390_pci_force_floating __initdata; 196 203 extern unsigned int s390_pci_no_rid; 197 204
+2 -1
arch/s390/pci/Makefile
··· 3 3 # Makefile for the s390 PCI subsystem. 4 4 # 5 5 6 - obj-$(CONFIG_PCI) += pci.o pci_irq.o pci_clp.o pci_sysfs.o \ 6 + obj-$(CONFIG_PCI) += pci.o pci_irq.o pci_clp.o \ 7 7 pci_event.o pci_debug.o pci_insn.o pci_mmio.o \ 8 8 pci_bus.o pci_kvm_hook.o 9 9 obj-$(CONFIG_PCI_IOV) += pci_iov.o 10 + obj-$(CONFIG_SYSFS) += pci_sysfs.o
-1
arch/s390/pci/pci.c
··· 587 587 if (pdev->is_physfn) 588 588 pdev->no_vf_scan = 1; 589 589 590 - pdev->dev.groups = zpci_attr_groups; 591 590 zpci_map_resources(pdev); 592 591 593 592 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
+4 -10
arch/s390/pci/pci_sysfs.c
··· 197 197 NULL, 198 198 }; 199 199 200 - static struct attribute_group zpci_ident_attr_group = { 200 + const struct attribute_group zpci_ident_attr_group = { 201 201 .attrs = zpci_ident_attrs, 202 202 .is_visible = zpci_index_is_visible, 203 203 }; ··· 223 223 NULL, 224 224 }; 225 225 226 - static struct attribute_group zpci_attr_group = { 226 + const struct attribute_group zpci_attr_group = { 227 227 .attrs = zpci_dev_attrs, 228 228 .bin_attrs = zpci_bin_attrs, 229 229 }; ··· 235 235 &dev_attr_segment3.attr, 236 236 NULL, 237 237 }; 238 - static struct attribute_group pfip_attr_group = { 238 + 239 + const struct attribute_group pfip_attr_group = { 239 240 .name = "pfip", 240 241 .attrs = pfip_attrs, 241 - }; 242 - 243 - const struct attribute_group *zpci_attr_groups[] = { 244 - &zpci_attr_group, 245 - &pfip_attr_group, 246 - &zpci_ident_attr_group, 247 - NULL, 248 242 };
+2 -2
arch/x86/pci/fixup.c
··· 980 980 return; 981 981 982 982 rp = pcie_find_root_port(dev); 983 - if (!rp->pm_cap) 983 + if (!rp || !rp->pm_cap) 984 984 return; 985 985 986 986 rp->pme_support &= ~((PCI_PM_CAP_PME_D3hot|PCI_PM_CAP_PME_D3cold) >> ··· 994 994 u16 pmc; 995 995 996 996 rp = pcie_find_root_port(dev); 997 - if (!rp->pm_cap) 997 + if (!rp || !rp->pm_cap) 998 998 return; 999 999 1000 1000 pci_read_config_word(rp, rp->pm_cap + PCI_PM_PMC, &pmc);
+3 -1
drivers/Makefile
··· 17 17 obj-$(CONFIG_GPIOLIB) += gpio/ 18 18 obj-y += pwm/ 19 19 20 + # LEDs must come before PCI, it is needed by NPEM driver 21 + obj-y += leds/ 22 + 20 23 obj-y += pci/ 21 24 22 25 obj-$(CONFIG_PARISC) += parisc/ ··· 133 130 obj-y += mmc/ 134 131 obj-y += ufs/ 135 132 obj-$(CONFIG_MEMSTICK) += memstick/ 136 - obj-y += leds/ 137 133 obj-$(CONFIG_INFINIBAND) += infiniband/ 138 134 obj-y += firmware/ 139 135 obj-$(CONFIG_CRYPTO) += crypto/
+12
drivers/acpi/pci_mcfg.c
··· 181 181 LOONGSON_ECAM_MCFG("LOONGSON", 0), 182 182 LOONGSON_ECAM_MCFG("\0", 1), 183 183 LOONGSON_ECAM_MCFG("LOONGSON", 1), 184 + LOONGSON_ECAM_MCFG("\0", 2), 185 + LOONGSON_ECAM_MCFG("LOONGSON", 2), 186 + LOONGSON_ECAM_MCFG("\0", 3), 187 + LOONGSON_ECAM_MCFG("LOONGSON", 3), 188 + LOONGSON_ECAM_MCFG("\0", 4), 189 + LOONGSON_ECAM_MCFG("LOONGSON", 4), 190 + LOONGSON_ECAM_MCFG("\0", 5), 191 + LOONGSON_ECAM_MCFG("LOONGSON", 5), 192 + LOONGSON_ECAM_MCFG("\0", 6), 193 + LOONGSON_ECAM_MCFG("LOONGSON", 6), 194 + LOONGSON_ECAM_MCFG("\0", 7), 195 + LOONGSON_ECAM_MCFG("LOONGSON", 7), 184 196 #endif /* LOONGARCH */ 185 197 }; 186 198
+5 -5
drivers/bcma/driver_pci_host.c
··· 334 334 } 335 335 336 336 /* If the root port is capable of returning Config Request 337 - * Retry Status (CRS) Completion Status to software then 337 + * Retry Status (RRS) Completion Status to software then 338 338 * enable the feature. 339 339 */ 340 340 static void bcma_core_pci_enable_crs(struct bcma_drv_pci *pc) ··· 348 348 NULL); 349 349 root_cap = cap_ptr + PCI_EXP_RTCAP; 350 350 bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16)); 351 - if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) { 352 - /* Enable CRS software visibility */ 351 + if (val16 & BCMA_CORE_PCI_RC_RRS_VISIBILITY) { 352 + /* Enable Configuration RRS Software Visibility */ 353 353 root_ctrl = cap_ptr + PCI_EXP_RTCTL; 354 - val16 = PCI_EXP_RTCTL_CRSSVE; 354 + val16 = PCI_EXP_RTCTL_RRS_SVE; 355 355 bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16, 356 356 sizeof(u16)); 357 357 ··· 360 360 * 100 ms wait time from the end of Reset. If the device is 361 361 * not done with its internal initialization, it must at 362 362 * least return a completion TLP, with a completion status 363 - * of "Configuration Request Retry Status (CRS)". The root 363 + * of "Configuration Request Retry Status (RRS)". The root 364 364 * complex must complete the request to the host by returning 365 365 * a read-data value of 0001h for the Vendor ID field and 366 366 * all 1s for any additional bytes included in the request.
+6 -6
drivers/gpu/drm/ast/ast_drv.c
··· 287 287 if (ret) 288 288 return ret; 289 289 290 - regs = pcim_iomap(pdev, 1, 0); 291 - if (!regs) 292 - return -EIO; 290 + regs = pcim_iomap_region(pdev, 1, "ast"); 291 + if (IS_ERR(regs)) 292 + return PTR_ERR(regs); 293 293 294 294 if (pdev->revision >= 0x40) { 295 295 /* ··· 311 311 312 312 if (len < AST_IO_MM_LENGTH) 313 313 return -EIO; 314 - ioregs = pcim_iomap(pdev, 2, 0); 315 - if (!ioregs) 316 - return -EIO; 314 + ioregs = pcim_iomap_region(pdev, 2, "ast"); 315 + if (IS_ERR(ioregs)) 316 + return PTR_ERR(ioregs); 317 317 } else { 318 318 /* 319 319 * Anything else is best effort.
+4
drivers/gpu/drm/vboxvideo/vbox_main.c
··· 114 114 115 115 DRM_INFO("VRAM %08x\n", vbox->full_vram_size); 116 116 117 + ret = pcim_request_region(pdev, 0, "vboxvideo"); 118 + if (ret) 119 + return ret; 120 + 117 121 /* Map guest-heap at end of vram */ 118 122 vbox->guest_heap = pcim_iomap_range(pdev, 0, 119 123 GUEST_HEAP_OFFSET(vbox), GUEST_HEAP_SIZE);
+9
drivers/pci/Kconfig
··· 143 143 144 144 If unsure, say N. 145 145 146 + config PCI_NPEM 147 + bool "Native PCIe Enclosure Management" 148 + depends on LEDS_CLASS=y 149 + help 150 + Support for Native PCIe Enclosure Management. It allows managing LED 151 + indications in storage enclosures. Enclosure must support following 152 + indications: OK, Locate, Fail, Rebuild, other indications are 153 + optional. 154 + 146 155 config PCI_PRI 147 156 bool "PCI PRI support" 148 157 select PCI_ATS
+1
drivers/pci/Makefile
··· 35 35 obj-$(CONFIG_VGA_ARB) += vgaarb.o 36 36 obj-$(CONFIG_PCI_DOE) += doe.o 37 37 obj-$(CONFIG_PCI_DYNAMIC_OF_NODES) += of_property.o 38 + obj-$(CONFIG_PCI_NPEM) += npem.o 38 39 39 40 # Endpoint library must be initialized before its users 40 41 obj-$(CONFIG_PCI_ENDPOINT) += endpoint/
+2 -2
drivers/pci/ats.c
··· 488 488 * pci_pasid_features - Check which PASID features are supported 489 489 * @pdev: PCI device structure 490 490 * 491 - * Returns a negative value when no PASI capability is present. 492 - * Otherwise is returns a bitmask with supported features. Current 491 + * Return a negative value when no PASID capability is present. 492 + * Otherwise return a bitmask with supported features. Current 493 493 * features reported are: 494 494 * PCI_PASID_CAP_EXEC - Execute permission supported 495 495 * PCI_PASID_CAP_PRIV - Privileged mode supported
+1 -1
drivers/pci/controller/Kconfig
··· 196 196 197 197 config PCIE_MEDIATEK_GEN3 198 198 tristate "MediaTek Gen3 PCIe controller" 199 - depends on ARCH_MEDIATEK || COMPILE_TEST 199 + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST 200 200 depends on PCI_MSI 201 201 help 202 202 Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+1 -1
drivers/pci/controller/cadence/Kconfig
··· 38 38 select PCIE_CADENCE_EP 39 39 select PCIE_CADENCE_PLAT 40 40 help 41 - Say Y here if you want to support the Cadence PCIe platform controller in 41 + Say Y here if you want to support the Cadence PCIe platform controller in 42 42 endpoint mode. This PCIe controller may be embedded into many 43 43 different vendors SoCs. 44 44
+141 -19
drivers/pci/controller/cadence/pci-j721e.c
··· 7 7 */ 8 8 9 9 #include <linux/clk.h> 10 + #include <linux/clk-provider.h> 11 + #include <linux/container_of.h> 10 12 #include <linux/delay.h> 11 13 #include <linux/gpio/consumer.h> 12 14 #include <linux/io.h> ··· 23 21 24 22 #include "../../pci.h" 25 23 #include "pcie-cadence.h" 24 + 25 + #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie) 26 26 27 27 #define ENABLE_REG_SYS_2 0x108 28 28 #define STATUS_REG_SYS_2 0x508 ··· 48 44 #define J721E_MODE_RC BIT(7) 49 45 #define LANE_COUNT(n) ((n) << 8) 50 46 47 + #define ACSPCIE_PAD_DISABLE_MASK GENMASK(1, 0) 51 48 #define GENERATION_SEL_MASK GENMASK(1, 0) 52 49 53 50 struct j721e_pcie { ··· 57 52 u32 mode; 58 53 u32 num_lanes; 59 54 u32 max_lanes; 55 + struct gpio_desc *reset_gpio; 60 56 void __iomem *user_cfg_base; 61 57 void __iomem *intd_cfg_base; 62 58 u32 linkdown_irq_regfield; ··· 226 220 return ret; 227 221 } 228 222 223 + static int j721e_enable_acspcie_refclk(struct j721e_pcie *pcie, 224 + struct regmap *syscon) 225 + { 226 + struct device *dev = pcie->cdns_pcie->dev; 227 + struct device_node *node = dev->of_node; 228 + u32 mask = ACSPCIE_PAD_DISABLE_MASK; 229 + struct of_phandle_args args; 230 + u32 val; 231 + int ret; 232 + 233 + ret = of_parse_phandle_with_fixed_args(node, 234 + "ti,syscon-acspcie-proxy-ctrl", 235 + 1, 0, &args); 236 + if (ret) { 237 + dev_err(dev, 238 + "ti,syscon-acspcie-proxy-ctrl has invalid arguments\n"); 239 + return ret; 240 + } 241 + 242 + /* Clear PAD IO disable bits to enable refclk output */ 243 + val = ~(args.args[0]); 244 + ret = regmap_update_bits(syscon, 0, mask, val); 245 + if (ret) { 246 + dev_err(dev, "failed to enable ACSPCIE refclk: %d\n", ret); 247 + return ret; 248 + } 249 + 250 + return 0; 251 + } 252 + 229 253 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 230 254 { 231 255 struct device *dev = pcie->cdns_pcie->dev; ··· 295 259 return ret; 296 260 } 297 261 298 - return 0; 262 + /* Enable ACSPCIE refclk output if the optional property exists */ 263 + syscon = syscon_regmap_lookup_by_phandle_optional(node, 264 + "ti,syscon-acspcie-proxy-ctrl"); 265 + if (!syscon) 266 + return 0; 267 + 268 + return j721e_enable_acspcie_refclk(pcie, syscon); 299 269 } 300 270 301 271 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, ··· 524 482 pm_runtime_enable(dev); 525 483 ret = pm_runtime_get_sync(dev); 526 484 if (ret < 0) { 527 - dev_err(dev, "pm_runtime_get_sync failed\n"); 485 + dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n"); 528 486 goto err_get_sync; 529 487 } 530 488 531 489 ret = j721e_pcie_ctrl_init(pcie); 532 490 if (ret < 0) { 533 - dev_err(dev, "pm_runtime_get_sync failed\n"); 491 + dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n"); 534 492 goto err_get_sync; 535 493 } 536 494 537 495 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, 538 496 "j721e-pcie-link-down-irq", pcie); 539 497 if (ret < 0) { 540 - dev_err(dev, "failed to request link state IRQ %d\n", irq); 498 + dev_err_probe(dev, ret, "failed to request link state IRQ %d\n", irq); 541 499 goto err_get_sync; 542 500 } 543 501 ··· 547 505 case PCI_MODE_RC: 548 506 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 549 507 if (IS_ERR(gpiod)) { 550 - ret = PTR_ERR(gpiod); 551 - if (ret != -EPROBE_DEFER) 552 - dev_err(dev, "Failed to get reset GPIO\n"); 508 + ret = dev_err_probe(dev, PTR_ERR(gpiod), "Failed to get reset GPIO\n"); 553 509 goto err_get_sync; 554 510 } 511 + pcie->reset_gpio = gpiod; 555 512 556 513 ret = cdns_pcie_init_phy(dev, cdns_pcie); 557 514 if (ret) { 558 - dev_err(dev, "Failed to init phy\n"); 515 + dev_err_probe(dev, ret, "Failed to init phy\n"); 559 516 goto err_get_sync; 560 517 } 561 518 562 519 clk = devm_clk_get_optional(dev, "pcie_refclk"); 563 520 if (IS_ERR(clk)) { 564 - ret = PTR_ERR(clk); 565 - dev_err(dev, "failed to get pcie_refclk\n"); 521 + ret = dev_err_probe(dev, PTR_ERR(clk), "failed to get pcie_refclk\n"); 566 522 goto err_pcie_setup; 567 523 } 568 524 569 525 ret = clk_prepare_enable(clk); 570 526 if (ret) { 571 - dev_err(dev, "failed to enable pcie_refclk\n"); 527 + dev_err_probe(dev, ret, "failed to enable pcie_refclk\n"); 572 528 goto err_pcie_setup; 573 529 } 574 530 pcie->refclk = clk; 575 531 576 532 /* 577 - * "Power Sequencing and Reset Signal Timings" table in 578 - * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 579 - * indicates PERST# should be deasserted after minimum of 100us 580 - * once REFCLK is stable. The REFCLK to the connector in RC 581 - * mode is selected while enabling the PHY. So deassert PERST# 582 - * after 100 us. 533 + * The "Power Sequencing and Reset Signal Timings" table of the 534 + * PCI Express Card Electromechanical Specification, Revision 535 + * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST# 536 + * should be deasserted after minimum of 100us once REFCLK is 537 + * stable. The REFCLK to the connector in RC mode is selected 538 + * while enabling the PHY. So deassert PERST# after 100 us. 583 539 */ 584 540 if (gpiod) { 585 - usleep_range(100, 200); 541 + fsleep(PCIE_T_PERST_CLK_US); 586 542 gpiod_set_value_cansleep(gpiod, 1); 587 543 } 588 544 ··· 594 554 case PCI_MODE_EP: 595 555 ret = cdns_pcie_init_phy(dev, cdns_pcie); 596 556 if (ret) { 597 - dev_err(dev, "Failed to init phy\n"); 557 + dev_err_probe(dev, ret, "Failed to init phy\n"); 598 558 goto err_get_sync; 599 559 } 600 560 ··· 629 589 pm_runtime_disable(dev); 630 590 } 631 591 592 + static int j721e_pcie_suspend_noirq(struct device *dev) 593 + { 594 + struct j721e_pcie *pcie = dev_get_drvdata(dev); 595 + 596 + if (pcie->mode == PCI_MODE_RC) { 597 + gpiod_set_value_cansleep(pcie->reset_gpio, 0); 598 + clk_disable_unprepare(pcie->refclk); 599 + } 600 + 601 + cdns_pcie_disable_phy(pcie->cdns_pcie); 602 + 603 + return 0; 604 + } 605 + 606 + static int j721e_pcie_resume_noirq(struct device *dev) 607 + { 608 + struct j721e_pcie *pcie = dev_get_drvdata(dev); 609 + struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 610 + int ret; 611 + 612 + ret = j721e_pcie_ctrl_init(pcie); 613 + if (ret < 0) 614 + return ret; 615 + 616 + j721e_pcie_config_link_irq(pcie); 617 + 618 + /* 619 + * This is not called explicitly in the probe, it is called by 620 + * cdns_pcie_init_phy(). 621 + */ 622 + ret = cdns_pcie_enable_phy(pcie->cdns_pcie); 623 + if (ret < 0) 624 + return ret; 625 + 626 + if (pcie->mode == PCI_MODE_RC) { 627 + struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie); 628 + 629 + ret = clk_prepare_enable(pcie->refclk); 630 + if (ret < 0) 631 + return ret; 632 + 633 + /* 634 + * The "Power Sequencing and Reset Signal Timings" table of the 635 + * PCI Express Card Electromechanical Specification, Revision 636 + * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST# 637 + * should be deasserted after minimum of 100us once REFCLK is 638 + * stable. The REFCLK to the connector in RC mode is selected 639 + * while enabling the PHY. So deassert PERST# after 100 us. 640 + */ 641 + if (pcie->reset_gpio) { 642 + fsleep(PCIE_T_PERST_CLK_US); 643 + gpiod_set_value_cansleep(pcie->reset_gpio, 1); 644 + } 645 + 646 + ret = cdns_pcie_host_link_setup(rc); 647 + if (ret < 0) { 648 + clk_disable_unprepare(pcie->refclk); 649 + return ret; 650 + } 651 + 652 + /* 653 + * Reset internal status of BARs to force reinitialization in 654 + * cdns_pcie_host_init(). 655 + */ 656 + for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++) 657 + rc->avail_ib_bar[bar] = true; 658 + 659 + ret = cdns_pcie_host_init(rc); 660 + if (ret) { 661 + clk_disable_unprepare(pcie->refclk); 662 + return ret; 663 + } 664 + } 665 + 666 + return 0; 667 + } 668 + 669 + static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops, 670 + j721e_pcie_suspend_noirq, 671 + j721e_pcie_resume_noirq); 672 + 632 673 static struct platform_driver j721e_pcie_driver = { 633 674 .probe = j721e_pcie_probe, 634 675 .remove_new = j721e_pcie_remove, ··· 717 596 .name = "j721e-pcie", 718 597 .of_match_table = of_j721e_pcie_match, 719 598 .suppress_bind_attrs = true, 599 + .pm = pm_sleep_ptr(&j721e_pcie_pm_ops), 720 600 }, 721 601 }; 722 602 builtin_platform_driver(j721e_pcie_driver);
+28 -16
drivers/pci/controller/cadence/pcie-cadence-host.c
··· 485 485 return cdns_pcie_host_map_dma_ranges(rc); 486 486 } 487 487 488 - static int cdns_pcie_host_init(struct device *dev, 489 - struct cdns_pcie_rc *rc) 488 + int cdns_pcie_host_init(struct cdns_pcie_rc *rc) 490 489 { 491 490 int err; 492 491 ··· 494 495 return err; 495 496 496 497 return cdns_pcie_host_init_address_translation(rc); 498 + } 499 + 500 + int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) 501 + { 502 + struct cdns_pcie *pcie = &rc->pcie; 503 + struct device *dev = rc->pcie.dev; 504 + int ret; 505 + 506 + if (rc->quirk_detect_quiet_flag) 507 + cdns_pcie_detect_quiet_min_delay_set(&rc->pcie); 508 + 509 + cdns_pcie_host_enable_ptm_response(pcie); 510 + 511 + ret = cdns_pcie_start_link(pcie); 512 + if (ret) { 513 + dev_err(dev, "Failed to start link\n"); 514 + return ret; 515 + } 516 + 517 + ret = cdns_pcie_host_start_link(rc); 518 + if (ret) 519 + dev_dbg(dev, "PCIe link never came up\n"); 520 + 521 + return 0; 497 522 } 498 523 499 524 int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) ··· 556 533 return PTR_ERR(rc->cfg_base); 557 534 rc->cfg_res = res; 558 535 559 - if (rc->quirk_detect_quiet_flag) 560 - cdns_pcie_detect_quiet_min_delay_set(&rc->pcie); 561 - 562 - cdns_pcie_host_enable_ptm_response(pcie); 563 - 564 - ret = cdns_pcie_start_link(pcie); 565 - if (ret) { 566 - dev_err(dev, "Failed to start link\n"); 567 - return ret; 568 - } 569 - 570 - ret = cdns_pcie_host_start_link(rc); 536 + ret = cdns_pcie_host_link_setup(rc); 571 537 if (ret) 572 - dev_dbg(dev, "PCIe link never came up\n"); 538 + return ret; 573 539 574 540 for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) 575 541 rc->avail_ib_bar[bar] = true; 576 542 577 - ret = cdns_pcie_host_init(dev, rc); 543 + ret = cdns_pcie_host_init(rc); 578 544 if (ret) 579 545 return ret; 580 546
+12 -1
drivers/pci/controller/cadence/pcie-cadence.h
··· 314 314 /** 315 315 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver 316 316 * @pcie: Cadence PCIe controller 317 - * @dev: pointer to PCIe device 318 317 * @cfg_res: start/end offsets in the physical system memory to map PCI 319 318 * configuration space accesses 320 319 * @cfg_base: IO mapped window to access the PCI configuration space of a ··· 520 521 } 521 522 522 523 #ifdef CONFIG_PCIE_CADENCE_HOST 524 + int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc); 525 + int cdns_pcie_host_init(struct cdns_pcie_rc *rc); 523 526 int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); 524 527 void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, 525 528 int where); 526 529 #else 530 + static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) 531 + { 532 + return 0; 533 + } 534 + 535 + static inline int cdns_pcie_host_init(struct cdns_pcie_rc *rc) 536 + { 537 + return 0; 538 + } 539 + 527 540 static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) 528 541 { 529 542 return 0;
+5
drivers/pci/controller/dwc/Kconfig
··· 265 265 order to enable device-specific features PCI_DW_PLAT_EP must be 266 266 selected. 267 267 268 + config PCIE_QCOM_COMMON 269 + bool 270 + 268 271 config PCIE_QCOM 269 272 bool "Qualcomm PCIe controller (host mode)" 270 273 depends on OF && (ARCH_QCOM || COMPILE_TEST) 271 274 depends on PCI_MSI 272 275 select PCIE_DW_HOST 273 276 select CRC8 277 + select PCIE_QCOM_COMMON 274 278 help 275 279 Say Y here to enable PCIe controller support on Qualcomm SoCs. The 276 280 PCIe controller uses the DesignWare core plus Qualcomm-specific ··· 285 281 depends on OF && (ARCH_QCOM || COMPILE_TEST) 286 282 depends on PCI_ENDPOINT 287 283 select PCIE_DW_EP 284 + select PCIE_QCOM_COMMON 288 285 help 289 286 Say Y here to enable support for the PCIe controllers on Qualcomm SoCs 290 287 to work in endpoint mode. The PCIe controller uses the DesignWare core
+1
drivers/pci/controller/dwc/Makefile
··· 12 12 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o 13 13 obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o 14 14 obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o 15 + obj-$(CONFIG_PCIE_QCOM_COMMON) += pcie-qcom-common.o 15 16 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o 16 17 obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o 17 18 obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
+9 -2
drivers/pci/controller/dwc/pci-dra7xx.c
··· 850 850 dra7xx->mode = mode; 851 851 852 852 ret = devm_request_threaded_irq(dev, irq, NULL, dra7xx_pcie_irq_handler, 853 - IRQF_SHARED, "dra7xx-pcie-main", dra7xx); 853 + IRQF_SHARED | IRQF_ONESHOT, 854 + "dra7xx-pcie-main", dra7xx); 854 855 if (ret) { 855 856 dev_err(dev, "failed to request irq\n"); 856 - goto err_gpio; 857 + goto err_deinit; 857 858 } 858 859 859 860 return 0; 861 + 862 + err_deinit: 863 + if (dra7xx->mode == DW_PCIE_RC_TYPE) 864 + dw_pcie_host_deinit(&dra7xx->pci->pp); 865 + else 866 + dw_pcie_ep_deinit(&dra7xx->pci->ep); 860 867 861 868 err_gpio: 862 869 err_get_sync:
+531 -469
drivers/pci/controller/dwc/pci-imx6.c
··· 28 28 #include <linux/types.h> 29 29 #include <linux/interrupt.h> 30 30 #include <linux/reset.h> 31 + #include <linux/phy/pcie.h> 31 32 #include <linux/phy/phy.h> 32 33 #include <linux/pm_domain.h> 33 34 #include <linux/pm_runtime.h> ··· 55 54 #define IMX95_PE0_GEN_CTRL_3 0x1058 56 55 #define IMX95_PCIE_LTSSM_EN BIT(0) 57 56 58 - #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 57 + #define to_imx_pcie(x) dev_get_drvdata((x)->dev) 59 58 60 - enum imx6_pcie_variants { 59 + enum imx_pcie_variants { 61 60 IMX6Q, 62 61 IMX6SX, 63 62 IMX6QP, ··· 65 64 IMX8MQ, 66 65 IMX8MM, 67 66 IMX8MP, 67 + IMX8Q, 68 68 IMX95, 69 69 IMX8MQ_EP, 70 70 IMX8MM_EP, ··· 73 71 IMX95_EP, 74 72 }; 75 73 76 - #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) 77 - #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) 78 - #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) 79 - #define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3) 80 - #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) 81 - #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) 82 - #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) 83 - #define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) 74 + #define IMX_PCIE_FLAG_IMX_PHY BIT(0) 75 + #define IMX_PCIE_FLAG_IMX_SPEED_CHANGE BIT(1) 76 + #define IMX_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) 77 + #define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3) 78 + #define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4) 79 + #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) 80 + #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) 81 + #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) 82 + #define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) 84 83 85 - #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) 84 + #define imx_check_flag(pci, val) (pci->drvdata->flags & val) 86 85 87 - #define IMX6_PCIE_MAX_CLKS 6 86 + #define IMX_PCIE_MAX_CLKS 6 87 + #define IMX_PCIE_MAX_INSTANCES 2 88 88 89 - #define IMX6_PCIE_MAX_INSTANCES 2 89 + struct imx_pcie; 90 90 91 - struct imx6_pcie; 92 - 93 - struct imx6_pcie_drvdata { 94 - enum imx6_pcie_variants variant; 91 + struct imx_pcie_drvdata { 92 + enum imx_pcie_variants variant; 95 93 enum dw_pcie_device_mode mode; 96 94 u32 flags; 97 95 int dbi_length; ··· 100 98 const u32 clks_cnt; 101 99 const u32 ltssm_off; 102 100 const u32 ltssm_mask; 103 - const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; 104 - const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; 101 + const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; 102 + const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; 105 103 const struct pci_epc_features *epc_features; 106 - int (*init_phy)(struct imx6_pcie *pcie); 104 + int (*init_phy)(struct imx_pcie *pcie); 105 + int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); 106 + int (*core_reset)(struct imx_pcie *pcie, bool assert); 107 107 }; 108 108 109 - struct imx6_pcie { 109 + struct imx_pcie { 110 110 struct dw_pcie *pci; 111 111 struct gpio_desc *reset_gpiod; 112 112 bool link_is_up; 113 - struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS]; 113 + struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS]; 114 114 struct regmap *iomuxc_gpr; 115 115 u16 msi_ctrl; 116 116 u32 controller_id; ··· 133 129 /* power domain for pcie phy */ 134 130 struct device *pd_pcie_phy; 135 131 struct phy *phy; 136 - const struct imx6_pcie_drvdata *drvdata; 132 + const struct imx_pcie_drvdata *drvdata; 137 133 }; 138 134 139 135 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ ··· 188 184 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) 189 185 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) 190 186 191 - static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) 187 + static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie) 192 188 { 193 - WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && 194 - imx6_pcie->drvdata->variant != IMX8MQ_EP && 195 - imx6_pcie->drvdata->variant != IMX8MM && 196 - imx6_pcie->drvdata->variant != IMX8MM_EP && 197 - imx6_pcie->drvdata->variant != IMX8MP && 198 - imx6_pcie->drvdata->variant != IMX8MP_EP); 199 - return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; 189 + WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && 190 + imx_pcie->drvdata->variant != IMX8MQ_EP && 191 + imx_pcie->drvdata->variant != IMX8MM && 192 + imx_pcie->drvdata->variant != IMX8MM_EP && 193 + imx_pcie->drvdata->variant != IMX8MP && 194 + imx_pcie->drvdata->variant != IMX8MP_EP); 195 + return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; 200 196 } 201 197 202 - static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) 198 + static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) 203 199 { 204 - regmap_update_bits(imx6_pcie->iomuxc_gpr, 200 + regmap_update_bits(imx_pcie->iomuxc_gpr, 205 201 IMX95_PCIE_SS_RW_REG_0, 206 202 IMX95_PCIE_PHY_CR_PARA_SEL, 207 203 IMX95_PCIE_PHY_CR_PARA_SEL); 208 204 209 - regmap_update_bits(imx6_pcie->iomuxc_gpr, 205 + regmap_update_bits(imx_pcie->iomuxc_gpr, 210 206 IMX95_PCIE_PHY_GEN_CTRL, 211 207 IMX95_PCIE_REF_USE_PAD, 0); 212 - regmap_update_bits(imx6_pcie->iomuxc_gpr, 208 + regmap_update_bits(imx_pcie->iomuxc_gpr, 213 209 IMX95_PCIE_SS_RW_REG_0, 214 210 IMX95_PCIE_REF_CLKEN, 215 211 IMX95_PCIE_REF_CLKEN); ··· 217 213 return 0; 218 214 } 219 215 220 - static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) 216 + static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) 221 217 { 222 - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 218 + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; 223 219 unsigned int mask, val, mode, id; 224 220 225 221 if (drvdata->mode == DW_PCIE_EP_TYPE) ··· 227 223 else 228 224 mode = PCI_EXP_TYPE_ROOT_PORT; 229 225 230 - id = imx6_pcie->controller_id; 226 + id = imx_pcie->controller_id; 227 + 228 + /* If mode_mask is 0, then generic PHY driver is used to set the mode */ 229 + if (!drvdata->mode_mask[0]) 230 + return; 231 231 232 232 /* If mode_mask[id] is zero, means each controller have its individual gpr */ 233 233 if (!drvdata->mode_mask[id]) ··· 240 232 mask = drvdata->mode_mask[id]; 241 233 val = mode << (ffs(mask) - 1); 242 234 243 - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); 235 + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); 244 236 } 245 237 246 - static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) 238 + static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, bool exp_val) 247 239 { 248 - struct dw_pcie *pci = imx6_pcie->pci; 240 + struct dw_pcie *pci = imx_pcie->pci; 249 241 bool val; 250 242 u32 max_iterations = 10; 251 243 u32 wait_counter = 0; ··· 264 256 return -ETIMEDOUT; 265 257 } 266 258 267 - static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 259 + static int pcie_phy_wait_ack(struct imx_pcie *imx_pcie, int addr) 268 260 { 269 - struct dw_pcie *pci = imx6_pcie->pci; 261 + struct dw_pcie *pci = imx_pcie->pci; 270 262 u32 val; 271 263 int ret; 272 264 ··· 276 268 val |= PCIE_PHY_CTRL_CAP_ADR; 277 269 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 278 270 279 - ret = pcie_phy_poll_ack(imx6_pcie, true); 271 + ret = pcie_phy_poll_ack(imx_pcie, true); 280 272 if (ret) 281 273 return ret; 282 274 283 275 val = PCIE_PHY_CTRL_DATA(addr); 284 276 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 285 277 286 - return pcie_phy_poll_ack(imx6_pcie, false); 278 + return pcie_phy_poll_ack(imx_pcie, false); 287 279 } 288 280 289 281 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 290 - static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) 282 + static int pcie_phy_read(struct imx_pcie *imx_pcie, int addr, u16 *data) 291 283 { 292 - struct dw_pcie *pci = imx6_pcie->pci; 284 + struct dw_pcie *pci = imx_pcie->pci; 293 285 u32 phy_ctl; 294 286 int ret; 295 287 296 - ret = pcie_phy_wait_ack(imx6_pcie, addr); 288 + ret = pcie_phy_wait_ack(imx_pcie, addr); 297 289 if (ret) 298 290 return ret; 299 291 ··· 301 293 phy_ctl = PCIE_PHY_CTRL_RD; 302 294 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 303 295 304 - ret = pcie_phy_poll_ack(imx6_pcie, true); 296 + ret = pcie_phy_poll_ack(imx_pcie, true); 305 297 if (ret) 306 298 return ret; 307 299 ··· 310 302 /* deassert Read signal */ 311 303 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 312 304 313 - return pcie_phy_poll_ack(imx6_pcie, false); 305 + return pcie_phy_poll_ack(imx_pcie, false); 314 306 } 315 307 316 - static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) 308 + static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data) 317 309 { 318 - struct dw_pcie *pci = imx6_pcie->pci; 310 + struct dw_pcie *pci = imx_pcie->pci; 319 311 u32 var; 320 312 int ret; 321 313 322 314 /* write addr */ 323 315 /* cap addr */ 324 - ret = pcie_phy_wait_ack(imx6_pcie, addr); 316 + ret = pcie_phy_wait_ack(imx_pcie, addr); 325 317 if (ret) 326 318 return ret; 327 319 ··· 332 324 var |= PCIE_PHY_CTRL_CAP_DAT; 333 325 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 334 326 335 - ret = pcie_phy_poll_ack(imx6_pcie, true); 327 + ret = pcie_phy_poll_ack(imx_pcie, true); 336 328 if (ret) 337 329 return ret; 338 330 ··· 341 333 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 342 334 343 335 /* wait for ack de-assertion */ 344 - ret = pcie_phy_poll_ack(imx6_pcie, false); 336 + ret = pcie_phy_poll_ack(imx_pcie, false); 345 337 if (ret) 346 338 return ret; 347 339 ··· 350 342 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 351 343 352 344 /* wait for ack */ 353 - ret = pcie_phy_poll_ack(imx6_pcie, true); 345 + ret = pcie_phy_poll_ack(imx_pcie, true); 354 346 if (ret) 355 347 return ret; 356 348 ··· 359 351 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 360 352 361 353 /* wait for ack de-assertion */ 362 - ret = pcie_phy_poll_ack(imx6_pcie, false); 354 + ret = pcie_phy_poll_ack(imx_pcie, false); 363 355 if (ret) 364 356 return ret; 365 357 ··· 368 360 return 0; 369 361 } 370 362 371 - static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie) 363 + static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie) 372 364 { 373 365 /* TODO: Currently this code assumes external oscillator is being used */ 374 - regmap_update_bits(imx6_pcie->iomuxc_gpr, 375 - imx6_pcie_grp_offset(imx6_pcie), 366 + regmap_update_bits(imx_pcie->iomuxc_gpr, 367 + imx_pcie_grp_offset(imx_pcie), 376 368 IMX8MQ_GPR_PCIE_REF_USE_PAD, 377 369 IMX8MQ_GPR_PCIE_REF_USE_PAD); 378 370 /* 379 371 * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is 380 372 * supplied by 3.3V, the VREG_BYPASS should be cleared to zero. 381 373 */ 382 - if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000) 383 - regmap_update_bits(imx6_pcie->iomuxc_gpr, 384 - imx6_pcie_grp_offset(imx6_pcie), 374 + if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000) 375 + regmap_update_bits(imx_pcie->iomuxc_gpr, 376 + imx_pcie_grp_offset(imx_pcie), 385 377 IMX8MQ_GPR_PCIE_VREG_BYPASS, 386 378 0); 387 379 388 380 return 0; 389 381 } 390 382 391 - static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie) 383 + static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie) 392 384 { 393 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 385 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 394 386 395 387 return 0; 396 388 } 397 389 398 - static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 390 + static int imx_pcie_init_phy(struct imx_pcie *imx_pcie) 399 391 { 400 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 392 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, 401 393 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 402 394 403 395 /* configure constant input signal to the pcie ctrl and phy */ 404 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 396 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, 405 397 IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 406 398 407 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 399 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, 408 400 IMX6Q_GPR8_TX_DEEMPH_GEN1, 409 - imx6_pcie->tx_deemph_gen1 << 0); 410 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 401 + imx_pcie->tx_deemph_gen1 << 0); 402 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, 411 403 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 412 - imx6_pcie->tx_deemph_gen2_3p5db << 6); 413 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 404 + imx_pcie->tx_deemph_gen2_3p5db << 6); 405 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, 414 406 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 415 - imx6_pcie->tx_deemph_gen2_6db << 12); 416 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 407 + imx_pcie->tx_deemph_gen2_6db << 12); 408 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, 417 409 IMX6Q_GPR8_TX_SWING_FULL, 418 - imx6_pcie->tx_swing_full << 18); 419 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 410 + imx_pcie->tx_swing_full << 18); 411 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, 420 412 IMX6Q_GPR8_TX_SWING_LOW, 421 - imx6_pcie->tx_swing_low << 25); 413 + imx_pcie->tx_swing_low << 25); 422 414 return 0; 423 415 } 424 416 425 - static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie) 417 + static int imx6sx_pcie_init_phy(struct imx_pcie *imx_pcie) 426 418 { 427 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 419 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, 428 420 IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); 429 421 430 - return imx6_pcie_init_phy(imx6_pcie); 422 + return imx_pcie_init_phy(imx_pcie); 431 423 } 432 424 433 - static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) 425 + static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie) 434 426 { 435 427 u32 val; 436 - struct device *dev = imx6_pcie->pci->dev; 428 + struct device *dev = imx_pcie->pci->dev; 437 429 438 - if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, 430 + if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr, 439 431 IOMUXC_GPR22, val, 440 432 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, 441 433 PHY_PLL_LOCK_WAIT_USLEEP_MAX, ··· 443 435 dev_err(dev, "PCIe PLL lock timeout\n"); 444 436 } 445 437 446 - static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 438 + static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie) 447 439 { 448 440 unsigned long phy_rate = 0; 449 441 int mult, div; 450 442 u16 val; 451 443 int i; 452 444 453 - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 445 + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) 454 446 return 0; 455 447 456 - for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) 457 - if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0) 458 - phy_rate = clk_get_rate(imx6_pcie->clks[i].clk); 448 + for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++) 449 + if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0) 450 + phy_rate = clk_get_rate(imx_pcie->clks[i].clk); 459 451 460 452 switch (phy_rate) { 461 453 case 125000000: ··· 473 465 div = 1; 474 466 break; 475 467 default: 476 - dev_err(imx6_pcie->pci->dev, 468 + dev_err(imx_pcie->pci->dev, 477 469 "Unsupported PHY reference clock rate %lu\n", phy_rate); 478 470 return -EINVAL; 479 471 } 480 472 481 - pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 473 + pcie_phy_read(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 482 474 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << 483 475 PCIE_PHY_MPLL_MULTIPLIER_SHIFT); 484 476 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; 485 477 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; 486 - pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 478 + pcie_phy_write(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 487 479 488 - pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); 480 + pcie_phy_read(imx_pcie, PCIE_PHY_ATEOVRD, &val); 489 481 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << 490 482 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); 491 483 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; 492 484 val |= PCIE_PHY_ATEOVRD_EN; 493 - pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); 485 + pcie_phy_write(imx_pcie, PCIE_PHY_ATEOVRD, val); 494 486 495 487 return 0; 496 488 } 497 489 498 - static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) 490 + static void imx_pcie_reset_phy(struct imx_pcie *imx_pcie) 499 491 { 500 492 u16 tmp; 501 493 502 - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 494 + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) 503 495 return; 504 496 505 - pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 497 + pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp); 506 498 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 507 499 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 508 - pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 500 + pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp); 509 501 510 502 usleep_range(2000, 3000); 511 503 512 - pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 504 + pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp); 513 505 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | 514 506 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 515 - pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 507 + pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp); 516 508 } 517 509 518 510 #ifdef CONFIG_ARM ··· 551 543 } 552 544 #endif 553 545 554 - static int imx6_pcie_attach_pd(struct device *dev) 546 + static int imx_pcie_attach_pd(struct device *dev) 555 547 { 556 - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 548 + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); 557 549 struct device_link *link; 558 550 559 551 /* Do nothing when in a single power domain */ 560 552 if (dev->pm_domain) 561 553 return 0; 562 554 563 - imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 564 - if (IS_ERR(imx6_pcie->pd_pcie)) 565 - return PTR_ERR(imx6_pcie->pd_pcie); 555 + imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 556 + if (IS_ERR(imx_pcie->pd_pcie)) 557 + return PTR_ERR(imx_pcie->pd_pcie); 566 558 /* Do nothing when power domain missing */ 567 - if (!imx6_pcie->pd_pcie) 559 + if (!imx_pcie->pd_pcie) 568 560 return 0; 569 - link = device_link_add(dev, imx6_pcie->pd_pcie, 561 + link = device_link_add(dev, imx_pcie->pd_pcie, 570 562 DL_FLAG_STATELESS | 571 563 DL_FLAG_PM_RUNTIME | 572 564 DL_FLAG_RPM_ACTIVE); ··· 575 567 return -EINVAL; 576 568 } 577 569 578 - imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 579 - if (IS_ERR(imx6_pcie->pd_pcie_phy)) 580 - return PTR_ERR(imx6_pcie->pd_pcie_phy); 570 + imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 571 + if (IS_ERR(imx_pcie->pd_pcie_phy)) 572 + return PTR_ERR(imx_pcie->pd_pcie_phy); 581 573 582 - link = device_link_add(dev, imx6_pcie->pd_pcie_phy, 574 + link = device_link_add(dev, imx_pcie->pd_pcie_phy, 583 575 DL_FLAG_STATELESS | 584 576 DL_FLAG_PM_RUNTIME | 585 577 DL_FLAG_RPM_ACTIVE); ··· 591 583 return 0; 592 584 } 593 585 594 - static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 586 + static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) 595 587 { 596 - unsigned int offset; 597 - int ret = 0; 588 + if (enable) 589 + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, 590 + IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 598 591 599 - switch (imx6_pcie->drvdata->variant) { 600 - case IMX6SX: 601 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 602 - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); 603 - break; 604 - case IMX6QP: 605 - case IMX6Q: 592 + return 0; 593 + } 594 + 595 + static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) 596 + { 597 + if (enable) { 606 598 /* power up core phy and enable ref clock */ 607 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 608 - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 599 + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); 609 600 /* 610 601 * the async reset input need ref clock to sync internally, 611 602 * when the ref clock comes after reset, internal synced ··· 612 605 * add one ~10us delay here. 613 606 */ 614 607 usleep_range(10, 100); 615 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 616 - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 617 - break; 618 - case IMX7D: 619 - case IMX95: 620 - case IMX95_EP: 621 - break; 622 - case IMX8MM: 623 - case IMX8MM_EP: 624 - case IMX8MQ: 625 - case IMX8MQ_EP: 626 - case IMX8MP: 627 - case IMX8MP_EP: 628 - offset = imx6_pcie_grp_offset(imx6_pcie); 629 - /* 630 - * Set the over ride low and enabled 631 - * make sure that REF_CLK is turned on. 632 - */ 633 - regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 634 - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 635 - 0); 636 - regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 637 - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, 638 - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); 639 - break; 608 + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); 609 + } else { 610 + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); 611 + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); 640 612 } 641 613 642 - return ret; 614 + return 0; 643 615 } 644 616 645 - static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) 617 + static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) 646 618 { 647 - switch (imx6_pcie->drvdata->variant) { 648 - case IMX6QP: 649 - case IMX6Q: 650 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 651 - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); 652 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 653 - IMX6Q_GPR1_PCIE_TEST_PD, 654 - IMX6Q_GPR1_PCIE_TEST_PD); 655 - break; 656 - case IMX7D: 657 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 658 - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 659 - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 660 - break; 661 - default: 662 - break; 619 + int offset = imx_pcie_grp_offset(imx_pcie); 620 + 621 + if (enable) { 622 + regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); 623 + regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); 663 624 } 625 + 626 + return 0; 664 627 } 665 628 666 - static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) 629 + static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) 667 630 { 668 - struct dw_pcie *pci = imx6_pcie->pci; 631 + if (!enable) 632 + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, 633 + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 634 + return 0; 635 + } 636 + 637 + static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) 638 + { 639 + struct dw_pcie *pci = imx_pcie->pci; 669 640 struct device *dev = pci->dev; 670 641 int ret; 671 642 672 - ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 643 + ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); 673 644 if (ret) 674 645 return ret; 675 646 676 - ret = imx6_pcie_enable_ref_clk(imx6_pcie); 677 - if (ret) { 678 - dev_err(dev, "unable to enable pcie ref clock\n"); 679 - goto err_ref_clk; 647 + if (imx_pcie->drvdata->enable_ref_clk) { 648 + ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true); 649 + if (ret) { 650 + dev_err(dev, "Failed to enable PCIe REFCLK\n"); 651 + goto err_ref_clk; 652 + } 680 653 } 681 654 682 655 /* allow the clocks to stabilize */ ··· 664 677 return 0; 665 678 666 679 err_ref_clk: 667 - clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 680 + clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); 668 681 669 682 return ret; 670 683 } 671 684 672 - static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 685 + static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) 673 686 { 674 - imx6_pcie_disable_ref_clk(imx6_pcie); 675 - clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 687 + if (imx_pcie->drvdata->enable_ref_clk) 688 + imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); 689 + clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); 676 690 } 677 691 678 - static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 692 + static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) 679 693 { 680 - reset_control_assert(imx6_pcie->pciephy_reset); 681 - reset_control_assert(imx6_pcie->apps_reset); 694 + if (assert) 695 + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, 696 + IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 682 697 683 - switch (imx6_pcie->drvdata->variant) { 684 - case IMX6SX: 685 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 686 - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 687 - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 688 - /* Force PCIe PHY reset */ 689 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 690 - IMX6SX_GPR5_PCIE_BTNRST_RESET, 691 - IMX6SX_GPR5_PCIE_BTNRST_RESET); 692 - break; 693 - case IMX6QP: 694 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 695 - IMX6Q_GPR1_PCIE_SW_RST, 696 - IMX6Q_GPR1_PCIE_SW_RST); 697 - break; 698 - case IMX6Q: 699 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 700 - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); 701 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 702 - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); 703 - break; 704 - default: 705 - break; 706 - } 707 - 708 - /* Some boards don't have PCIe reset GPIO. */ 709 - gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 1); 698 + /* Force PCIe PHY reset */ 699 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, 700 + assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0); 701 + return 0; 710 702 } 711 703 712 - static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 704 + static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) 713 705 { 714 - struct dw_pcie *pci = imx6_pcie->pci; 706 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, 707 + assert ? IMX6Q_GPR1_PCIE_SW_RST : 0); 708 + if (!assert) 709 + usleep_range(200, 500); 710 + 711 + return 0; 712 + } 713 + 714 + static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) 715 + { 716 + if (!assert) 717 + return 0; 718 + 719 + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); 720 + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); 721 + 722 + return 0; 723 + } 724 + 725 + static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) 726 + { 727 + struct dw_pcie *pci = imx_pcie->pci; 715 728 struct device *dev = pci->dev; 716 729 717 - reset_control_deassert(imx6_pcie->pciephy_reset); 730 + if (assert) 731 + return 0; 718 732 719 - switch (imx6_pcie->drvdata->variant) { 720 - case IMX7D: 721 - /* Workaround for ERR010728, failure of PCI-e PLL VCO to 722 - * oscillate, especially when cold. This turns off "Duty-cycle 723 - * Corrector" and other mysterious undocumented things. 724 - */ 725 - if (likely(imx6_pcie->phy_base)) { 726 - /* De-assert DCC_FB_EN */ 727 - writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, 728 - imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); 729 - /* Assert RX_EQS and RX_EQS_SEL */ 730 - writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL 731 - | PCIE_PHY_CMN_REG24_RX_EQ, 732 - imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); 733 - /* Assert ATT_MODE */ 734 - writel(PCIE_PHY_CMN_REG26_ATT_MODE, 735 - imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); 736 - } else { 737 - dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); 738 - } 733 + /* 734 + * Workaround for ERR010728 (IMX7DS_2N09P, Rev. 1.1, 4/2023): 735 + * 736 + * PCIe: PLL may fail to lock under corner conditions. 737 + * 738 + * Initial VCO oscillation may fail under corner conditions such as 739 + * cold temperature which will cause the PCIe PLL fail to lock in the 740 + * initialization phase. 741 + * 742 + * The Duty-cycle Corrector calibration must be disabled. 743 + * 744 + * 1. De-assert the G_RST signal by clearing 745 + * SRC_PCIEPHY_RCR[PCIEPHY_G_RST]. 746 + * 2. De-assert DCC_FB_EN by writing data “0x29” to the register 747 + * address 0x306d0014 (PCIE_PHY_CMN_REG4). 748 + * 3. Assert RX_EQS, RX_EQ_SEL by writing data “0x48” to the register 749 + * address 0x306d0090 (PCIE_PHY_CMN_REG24). 750 + * 4. Assert ATT_MODE by writing data “0xbc” to the register 751 + * address 0x306d0098 (PCIE_PHY_CMN_REG26). 752 + * 5. De-assert the CMN_RST signal by clearing register bit 753 + * SRC_PCIEPHY_RCR[PCIEPHY_BTN] 754 + */ 739 755 740 - imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 741 - break; 742 - case IMX6SX: 743 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 744 - IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); 745 - break; 746 - case IMX6QP: 747 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 748 - IMX6Q_GPR1_PCIE_SW_RST, 0); 749 - 750 - usleep_range(200, 500); 751 - break; 752 - default: 753 - break; 756 + if (likely(imx_pcie->phy_base)) { 757 + /* De-assert DCC_FB_EN */ 758 + writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4); 759 + /* Assert RX_EQS and RX_EQS_SEL */ 760 + writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ, 761 + imx_pcie->phy_base + PCIE_PHY_CMN_REG24); 762 + /* Assert ATT_MODE */ 763 + writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26); 764 + } else { 765 + dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); 754 766 } 767 + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); 768 + return 0; 769 + } 770 + 771 + static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) 772 + { 773 + reset_control_assert(imx_pcie->pciephy_reset); 774 + reset_control_assert(imx_pcie->apps_reset); 775 + 776 + if (imx_pcie->drvdata->core_reset) 777 + imx_pcie->drvdata->core_reset(imx_pcie, true); 755 778 756 779 /* Some boards don't have PCIe reset GPIO. */ 757 - if (imx6_pcie->reset_gpiod) { 780 + gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1); 781 + } 782 + 783 + static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) 784 + { 785 + reset_control_deassert(imx_pcie->pciephy_reset); 786 + 787 + if (imx_pcie->drvdata->core_reset) 788 + imx_pcie->drvdata->core_reset(imx_pcie, false); 789 + 790 + /* Some boards don't have PCIe reset GPIO. */ 791 + if (imx_pcie->reset_gpiod) { 758 792 msleep(100); 759 - gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 0); 793 + gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0); 760 794 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ 761 795 msleep(100); 762 796 } ··· 785 777 return 0; 786 778 } 787 779 788 - static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 780 + static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie) 789 781 { 790 - struct dw_pcie *pci = imx6_pcie->pci; 782 + struct dw_pcie *pci = imx_pcie->pci; 791 783 struct device *dev = pci->dev; 792 784 u32 tmp; 793 785 unsigned int retries; ··· 804 796 return -ETIMEDOUT; 805 797 } 806 798 807 - static void imx6_pcie_ltssm_enable(struct device *dev) 799 + static void imx_pcie_ltssm_enable(struct device *dev) 808 800 { 809 - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 810 - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 801 + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); 802 + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; 803 + u8 offset = dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP); 804 + u32 tmp; 811 805 806 + tmp = dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP); 807 + phy_set_speed(imx_pcie->phy, FIELD_GET(PCI_EXP_LNKCAP_SLS, tmp)); 812 808 if (drvdata->ltssm_mask) 813 - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, 809 + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, 814 810 drvdata->ltssm_mask); 815 811 816 - reset_control_deassert(imx6_pcie->apps_reset); 812 + reset_control_deassert(imx_pcie->apps_reset); 817 813 } 818 814 819 - static void imx6_pcie_ltssm_disable(struct device *dev) 815 + static void imx_pcie_ltssm_disable(struct device *dev) 820 816 { 821 - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 822 - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 817 + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); 818 + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; 823 819 820 + phy_set_speed(imx_pcie->phy, 0); 824 821 if (drvdata->ltssm_mask) 825 - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, 822 + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, 826 823 drvdata->ltssm_mask, 0); 827 824 828 - reset_control_assert(imx6_pcie->apps_reset); 825 + reset_control_assert(imx_pcie->apps_reset); 829 826 } 830 827 831 - static int imx6_pcie_start_link(struct dw_pcie *pci) 828 + static int imx_pcie_start_link(struct dw_pcie *pci) 832 829 { 833 - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 830 + struct imx_pcie *imx_pcie = to_imx_pcie(pci); 834 831 struct device *dev = pci->dev; 835 832 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 836 833 u32 tmp; ··· 854 841 dw_pcie_dbi_ro_wr_dis(pci); 855 842 856 843 /* Start LTSSM. */ 857 - imx6_pcie_ltssm_enable(dev); 844 + imx_pcie_ltssm_enable(dev); 858 845 859 846 ret = dw_pcie_wait_for_link(pci); 860 847 if (ret) 861 848 goto err_reset_phy; 862 849 863 - if (pci->link_gen > 1) { 850 + if (pci->max_link_speed > 1) { 864 851 /* Allow faster modes after the link is up */ 865 852 dw_pcie_dbi_ro_wr_en(pci); 866 853 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 867 854 tmp &= ~PCI_EXP_LNKCAP_SLS; 868 - tmp |= pci->link_gen; 855 + tmp |= pci->max_link_speed; 869 856 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 870 857 871 858 /* ··· 877 864 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 878 865 dw_pcie_dbi_ro_wr_dis(pci); 879 866 880 - if (imx6_pcie->drvdata->flags & 881 - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { 867 + if (imx_pcie->drvdata->flags & 868 + IMX_PCIE_FLAG_IMX_SPEED_CHANGE) { 882 869 /* 883 870 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 884 871 * from i.MX6 family when no link speed transition ··· 888 875 * failure. 889 876 */ 890 877 891 - ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 878 + ret = imx_pcie_wait_for_speed_change(imx_pcie); 892 879 if (ret) { 893 880 dev_err(dev, "Failed to bring link up!\n"); 894 881 goto err_reset_phy; ··· 903 890 dev_info(dev, "Link: Only Gen1 is enabled\n"); 904 891 } 905 892 906 - imx6_pcie->link_is_up = true; 893 + imx_pcie->link_is_up = true; 907 894 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 908 895 dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); 909 896 return 0; 910 897 911 898 err_reset_phy: 912 - imx6_pcie->link_is_up = false; 899 + imx_pcie->link_is_up = false; 913 900 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 914 901 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), 915 902 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); 916 - imx6_pcie_reset_phy(imx6_pcie); 903 + imx_pcie_reset_phy(imx_pcie); 917 904 return 0; 918 905 } 919 906 920 - static void imx6_pcie_stop_link(struct dw_pcie *pci) 907 + static void imx_pcie_stop_link(struct dw_pcie *pci) 921 908 { 922 909 struct device *dev = pci->dev; 923 910 924 911 /* Turn off PCIe LTSSM */ 925 - imx6_pcie_ltssm_disable(dev); 912 + imx_pcie_ltssm_disable(dev); 926 913 } 927 914 928 - static int imx6_pcie_host_init(struct dw_pcie_rp *pp) 915 + static int imx_pcie_host_init(struct dw_pcie_rp *pp) 929 916 { 930 917 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 931 918 struct device *dev = pci->dev; 932 - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 919 + struct imx_pcie *imx_pcie = to_imx_pcie(pci); 933 920 int ret; 934 921 935 - if (imx6_pcie->vpcie) { 936 - ret = regulator_enable(imx6_pcie->vpcie); 922 + if (imx_pcie->vpcie) { 923 + ret = regulator_enable(imx_pcie->vpcie); 937 924 if (ret) { 938 925 dev_err(dev, "failed to enable vpcie regulator: %d\n", 939 926 ret); ··· 941 928 } 942 929 } 943 930 944 - imx6_pcie_assert_core_reset(imx6_pcie); 931 + imx_pcie_assert_core_reset(imx_pcie); 945 932 946 - if (imx6_pcie->drvdata->init_phy) 947 - imx6_pcie->drvdata->init_phy(imx6_pcie); 933 + if (imx_pcie->drvdata->init_phy) 934 + imx_pcie->drvdata->init_phy(imx_pcie); 948 935 949 - imx6_pcie_configure_type(imx6_pcie); 936 + imx_pcie_configure_type(imx_pcie); 950 937 951 - ret = imx6_pcie_clk_enable(imx6_pcie); 938 + ret = imx_pcie_clk_enable(imx_pcie); 952 939 if (ret) { 953 940 dev_err(dev, "unable to enable pcie clocks: %d\n", ret); 954 941 goto err_reg_disable; 955 942 } 956 943 957 - if (imx6_pcie->phy) { 958 - ret = phy_init(imx6_pcie->phy); 944 + if (imx_pcie->phy) { 945 + ret = phy_init(imx_pcie->phy); 959 946 if (ret) { 960 947 dev_err(dev, "pcie PHY power up failed\n"); 961 948 goto err_clk_disable; 962 949 } 963 - } 964 950 965 - if (imx6_pcie->phy) { 966 - ret = phy_power_on(imx6_pcie->phy); 951 + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); 952 + if (ret) { 953 + dev_err(dev, "unable to set PCIe PHY mode\n"); 954 + goto err_phy_exit; 955 + } 956 + 957 + ret = phy_power_on(imx_pcie->phy); 967 958 if (ret) { 968 959 dev_err(dev, "waiting for PHY ready timeout!\n"); 969 - goto err_phy_off; 960 + goto err_phy_exit; 970 961 } 971 962 } 972 963 973 - ret = imx6_pcie_deassert_core_reset(imx6_pcie); 964 + ret = imx_pcie_deassert_core_reset(imx_pcie); 974 965 if (ret < 0) { 975 966 dev_err(dev, "pcie deassert core reset failed: %d\n", ret); 976 967 goto err_phy_off; 977 968 } 978 969 979 - imx6_setup_phy_mpll(imx6_pcie); 970 + imx_setup_phy_mpll(imx_pcie); 980 971 981 972 return 0; 982 973 983 974 err_phy_off: 984 - if (imx6_pcie->phy) 985 - phy_exit(imx6_pcie->phy); 975 + phy_power_off(imx_pcie->phy); 976 + err_phy_exit: 977 + phy_exit(imx_pcie->phy); 986 978 err_clk_disable: 987 - imx6_pcie_clk_disable(imx6_pcie); 979 + imx_pcie_clk_disable(imx_pcie); 988 980 err_reg_disable: 989 - if (imx6_pcie->vpcie) 990 - regulator_disable(imx6_pcie->vpcie); 981 + if (imx_pcie->vpcie) 982 + regulator_disable(imx_pcie->vpcie); 991 983 return ret; 992 984 } 993 985 994 - static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) 986 + static void imx_pcie_host_exit(struct dw_pcie_rp *pp) 995 987 { 996 988 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 997 - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 989 + struct imx_pcie *imx_pcie = to_imx_pcie(pci); 998 990 999 - if (imx6_pcie->phy) { 1000 - if (phy_power_off(imx6_pcie->phy)) 991 + if (imx_pcie->phy) { 992 + if (phy_power_off(imx_pcie->phy)) 1001 993 dev_err(pci->dev, "unable to power off PHY\n"); 1002 - phy_exit(imx6_pcie->phy); 994 + phy_exit(imx_pcie->phy); 1003 995 } 1004 - imx6_pcie_clk_disable(imx6_pcie); 996 + imx_pcie_clk_disable(imx_pcie); 1005 997 1006 - if (imx6_pcie->vpcie) 1007 - regulator_disable(imx6_pcie->vpcie); 998 + if (imx_pcie->vpcie) 999 + regulator_disable(imx_pcie->vpcie); 1008 1000 } 1009 1001 1010 - static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 1011 - .init = imx6_pcie_host_init, 1012 - .deinit = imx6_pcie_host_exit, 1002 + static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) 1003 + { 1004 + struct imx_pcie *imx_pcie = to_imx_pcie(pcie); 1005 + struct dw_pcie_rp *pp = &pcie->pp; 1006 + struct resource_entry *entry; 1007 + 1008 + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) 1009 + return cpu_addr; 1010 + 1011 + entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); 1012 + if (!entry) 1013 + return cpu_addr; 1014 + 1015 + return cpu_addr - entry->offset; 1016 + } 1017 + 1018 + static const struct dw_pcie_host_ops imx_pcie_host_ops = { 1019 + .init = imx_pcie_host_init, 1020 + .deinit = imx_pcie_host_exit, 1013 1021 }; 1014 1022 1015 1023 static const struct dw_pcie_ops dw_pcie_ops = { 1016 - .start_link = imx6_pcie_start_link, 1017 - .stop_link = imx6_pcie_stop_link, 1024 + .start_link = imx_pcie_start_link, 1025 + .stop_link = imx_pcie_stop_link, 1026 + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup, 1018 1027 }; 1019 1028 1020 - static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) 1029 + static void imx_pcie_ep_init(struct dw_pcie_ep *ep) 1021 1030 { 1022 1031 enum pci_barno bar; 1023 1032 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); ··· 1048 1013 dw_pcie_ep_reset_bar(pci, bar); 1049 1014 } 1050 1015 1051 - static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1016 + static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1052 1017 unsigned int type, u16 interrupt_num) 1053 1018 { 1054 1019 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); ··· 1095 1060 }; 1096 1061 1097 1062 static const struct pci_epc_features* 1098 - imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) 1063 + imx_pcie_ep_get_features(struct dw_pcie_ep *ep) 1099 1064 { 1100 1065 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1101 - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1066 + struct imx_pcie *imx_pcie = to_imx_pcie(pci); 1102 1067 1103 - return imx6_pcie->drvdata->epc_features; 1068 + return imx_pcie->drvdata->epc_features; 1104 1069 } 1105 1070 1106 1071 static const struct dw_pcie_ep_ops pcie_ep_ops = { 1107 - .init = imx6_pcie_ep_init, 1108 - .raise_irq = imx6_pcie_ep_raise_irq, 1109 - .get_features = imx6_pcie_ep_get_features, 1072 + .init = imx_pcie_ep_init, 1073 + .raise_irq = imx_pcie_ep_raise_irq, 1074 + .get_features = imx_pcie_ep_get_features, 1110 1075 }; 1111 1076 1112 - static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, 1077 + static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, 1113 1078 struct platform_device *pdev) 1114 1079 { 1115 1080 int ret; 1116 1081 unsigned int pcie_dbi2_offset; 1117 1082 struct dw_pcie_ep *ep; 1118 - struct dw_pcie *pci = imx6_pcie->pci; 1083 + struct dw_pcie *pci = imx_pcie->pci; 1119 1084 struct dw_pcie_rp *pp = &pci->pp; 1120 1085 struct device *dev = pci->dev; 1121 1086 1122 - imx6_pcie_host_init(pp); 1087 + imx_pcie_host_init(pp); 1123 1088 ep = &pci->ep; 1124 1089 ep->ops = &pcie_ep_ops; 1125 1090 1126 - switch (imx6_pcie->drvdata->variant) { 1091 + switch (imx_pcie->drvdata->variant) { 1127 1092 case IMX8MQ_EP: 1128 1093 case IMX8MM_EP: 1129 1094 case IMX8MP_EP: ··· 1145 1110 if (device_property_match_string(dev, "reg-names", "dbi2") >= 0) 1146 1111 pci->dbi_base2 = NULL; 1147 1112 1148 - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) 1113 + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_SUPPORT_64BIT)) 1149 1114 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1115 + 1116 + ep->page_size = imx_pcie->drvdata->epc_features->align; 1150 1117 1151 1118 ret = dw_pcie_ep_init(ep); 1152 1119 if (ret) { ··· 1166 1129 pci_epc_init_notify(ep->epc); 1167 1130 1168 1131 /* Start LTSSM. */ 1169 - imx6_pcie_ltssm_enable(dev); 1132 + imx_pcie_ltssm_enable(dev); 1170 1133 1171 1134 return 0; 1172 1135 } 1173 1136 1174 - static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) 1137 + static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie) 1175 1138 { 1176 - struct device *dev = imx6_pcie->pci->dev; 1139 + struct device *dev = imx_pcie->pci->dev; 1177 1140 1178 1141 /* Some variants have a turnoff reset in DT */ 1179 - if (imx6_pcie->turnoff_reset) { 1180 - reset_control_assert(imx6_pcie->turnoff_reset); 1181 - reset_control_deassert(imx6_pcie->turnoff_reset); 1142 + if (imx_pcie->turnoff_reset) { 1143 + reset_control_assert(imx_pcie->turnoff_reset); 1144 + reset_control_deassert(imx_pcie->turnoff_reset); 1182 1145 goto pm_turnoff_sleep; 1183 1146 } 1184 1147 1185 1148 /* Others poke directly at IOMUXC registers */ 1186 - switch (imx6_pcie->drvdata->variant) { 1149 + switch (imx_pcie->drvdata->variant) { 1187 1150 case IMX6SX: 1188 1151 case IMX6QP: 1189 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1152 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, 1190 1153 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 1191 1154 IMX6SX_GPR12_PCIE_PM_TURN_OFF); 1192 - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1155 + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, 1193 1156 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); 1194 1157 break; 1195 1158 default: ··· 1208 1171 usleep_range(1000, 10000); 1209 1172 } 1210 1173 1211 - static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save) 1174 + static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save) 1212 1175 { 1213 1176 u8 offset; 1214 1177 u16 val; 1215 - struct dw_pcie *pci = imx6_pcie->pci; 1178 + struct dw_pcie *pci = imx_pcie->pci; 1216 1179 1217 1180 if (pci_msi_enabled()) { 1218 1181 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 1219 1182 if (save) { 1220 1183 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 1221 - imx6_pcie->msi_ctrl = val; 1184 + imx_pcie->msi_ctrl = val; 1222 1185 } else { 1223 1186 dw_pcie_dbi_ro_wr_en(pci); 1224 - val = imx6_pcie->msi_ctrl; 1187 + val = imx_pcie->msi_ctrl; 1225 1188 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 1226 1189 dw_pcie_dbi_ro_wr_dis(pci); 1227 1190 } 1228 1191 } 1229 1192 } 1230 1193 1231 - static int imx6_pcie_suspend_noirq(struct device *dev) 1194 + static int imx_pcie_suspend_noirq(struct device *dev) 1232 1195 { 1233 - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1234 - struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1196 + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); 1197 + struct dw_pcie_rp *pp = &imx_pcie->pci->pp; 1235 1198 1236 - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1199 + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) 1237 1200 return 0; 1238 1201 1239 - imx6_pcie_msi_save_restore(imx6_pcie, true); 1240 - imx6_pcie_pm_turnoff(imx6_pcie); 1241 - imx6_pcie_stop_link(imx6_pcie->pci); 1242 - imx6_pcie_host_exit(pp); 1202 + imx_pcie_msi_save_restore(imx_pcie, true); 1203 + imx_pcie_pm_turnoff(imx_pcie); 1204 + imx_pcie_stop_link(imx_pcie->pci); 1205 + imx_pcie_host_exit(pp); 1243 1206 1244 1207 return 0; 1245 1208 } 1246 1209 1247 - static int imx6_pcie_resume_noirq(struct device *dev) 1210 + static int imx_pcie_resume_noirq(struct device *dev) 1248 1211 { 1249 1212 int ret; 1250 - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1251 - struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1213 + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); 1214 + struct dw_pcie_rp *pp = &imx_pcie->pci->pp; 1252 1215 1253 - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1216 + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) 1254 1217 return 0; 1255 1218 1256 - ret = imx6_pcie_host_init(pp); 1219 + ret = imx_pcie_host_init(pp); 1257 1220 if (ret) 1258 1221 return ret; 1259 - imx6_pcie_msi_save_restore(imx6_pcie, false); 1222 + imx_pcie_msi_save_restore(imx_pcie, false); 1260 1223 dw_pcie_setup_rc(pp); 1261 1224 1262 - if (imx6_pcie->link_is_up) 1263 - imx6_pcie_start_link(imx6_pcie->pci); 1225 + if (imx_pcie->link_is_up) 1226 + imx_pcie_start_link(imx_pcie->pci); 1264 1227 1265 1228 return 0; 1266 1229 } 1267 1230 1268 - static const struct dev_pm_ops imx6_pcie_pm_ops = { 1269 - NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, 1270 - imx6_pcie_resume_noirq) 1231 + static const struct dev_pm_ops imx_pcie_pm_ops = { 1232 + NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_pcie_suspend_noirq, 1233 + imx_pcie_resume_noirq) 1271 1234 }; 1272 1235 1273 - static int imx6_pcie_probe(struct platform_device *pdev) 1236 + static int imx_pcie_probe(struct platform_device *pdev) 1274 1237 { 1275 1238 struct device *dev = &pdev->dev; 1276 1239 struct dw_pcie *pci; 1277 - struct imx6_pcie *imx6_pcie; 1240 + struct imx_pcie *imx_pcie; 1278 1241 struct device_node *np; 1279 1242 struct resource *dbi_base; 1280 1243 struct device_node *node = dev->of_node; ··· 1282 1245 u16 val; 1283 1246 int i; 1284 1247 1285 - imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); 1286 - if (!imx6_pcie) 1248 + imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL); 1249 + if (!imx_pcie) 1287 1250 return -ENOMEM; 1288 1251 1289 1252 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); ··· 1292 1255 1293 1256 pci->dev = dev; 1294 1257 pci->ops = &dw_pcie_ops; 1295 - pci->pp.ops = &imx6_pcie_host_ops; 1258 + pci->pp.ops = &imx_pcie_host_ops; 1296 1259 1297 - imx6_pcie->pci = pci; 1298 - imx6_pcie->drvdata = of_device_get_match_data(dev); 1260 + imx_pcie->pci = pci; 1261 + imx_pcie->drvdata = of_device_get_match_data(dev); 1299 1262 1300 1263 /* Find the PHY if one is defined, only imx7d uses it */ 1301 1264 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); ··· 1307 1270 dev_err(dev, "Unable to map PCIe PHY\n"); 1308 1271 return ret; 1309 1272 } 1310 - imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); 1311 - if (IS_ERR(imx6_pcie->phy_base)) 1312 - return PTR_ERR(imx6_pcie->phy_base); 1273 + imx_pcie->phy_base = devm_ioremap_resource(dev, &res); 1274 + if (IS_ERR(imx_pcie->phy_base)) 1275 + return PTR_ERR(imx_pcie->phy_base); 1313 1276 } 1314 1277 1315 1278 pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); ··· 1317 1280 return PTR_ERR(pci->dbi_base); 1318 1281 1319 1282 /* Fetch GPIOs */ 1320 - imx6_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1321 - if (IS_ERR(imx6_pcie->reset_gpiod)) 1322 - return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod), 1283 + imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1284 + if (IS_ERR(imx_pcie->reset_gpiod)) 1285 + return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod), 1323 1286 "unable to get reset gpio\n"); 1324 - gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset"); 1287 + gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset"); 1325 1288 1326 - if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS) 1289 + if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS) 1327 1290 return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n"); 1328 1291 1329 - for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) 1330 - imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i]; 1292 + for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++) 1293 + imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i]; 1331 1294 1332 1295 /* Fetch clocks */ 1333 - ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 1296 + ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks); 1334 1297 if (ret) 1335 1298 return ret; 1336 1299 1337 - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) { 1338 - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); 1339 - if (IS_ERR(imx6_pcie->phy)) 1340 - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), 1300 + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) { 1301 + imx_pcie->phy = devm_phy_get(dev, "pcie-phy"); 1302 + if (IS_ERR(imx_pcie->phy)) 1303 + return dev_err_probe(dev, PTR_ERR(imx_pcie->phy), 1341 1304 "failed to get pcie phy\n"); 1342 1305 } 1343 1306 1344 - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { 1345 - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); 1346 - if (IS_ERR(imx6_pcie->apps_reset)) 1347 - return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), 1307 + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_APP_RESET)) { 1308 + imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); 1309 + if (IS_ERR(imx_pcie->apps_reset)) 1310 + return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset), 1348 1311 "failed to get pcie apps reset control\n"); 1349 1312 } 1350 1313 1351 - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { 1352 - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); 1353 - if (IS_ERR(imx6_pcie->pciephy_reset)) 1354 - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), 1314 + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHY_RESET)) { 1315 + imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); 1316 + if (IS_ERR(imx_pcie->pciephy_reset)) 1317 + return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset), 1355 1318 "Failed to get PCIEPHY reset control\n"); 1356 1319 } 1357 1320 1358 - switch (imx6_pcie->drvdata->variant) { 1321 + switch (imx_pcie->drvdata->variant) { 1359 1322 case IMX8MQ: 1360 1323 case IMX8MQ_EP: 1361 1324 case IMX7D: 1362 1325 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) 1363 - imx6_pcie->controller_id = 1; 1326 + imx_pcie->controller_id = 1; 1364 1327 break; 1365 1328 default: 1366 1329 break; 1367 1330 } 1368 1331 1369 1332 /* Grab turnoff reset */ 1370 - imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1371 - if (IS_ERR(imx6_pcie->turnoff_reset)) { 1333 + imx_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1334 + if (IS_ERR(imx_pcie->turnoff_reset)) { 1372 1335 dev_err(dev, "Failed to get TURNOFF reset control\n"); 1373 - return PTR_ERR(imx6_pcie->turnoff_reset); 1336 + return PTR_ERR(imx_pcie->turnoff_reset); 1374 1337 } 1375 1338 1376 - if (imx6_pcie->drvdata->gpr) { 1339 + if (imx_pcie->drvdata->gpr) { 1377 1340 /* Grab GPR config register range */ 1378 - imx6_pcie->iomuxc_gpr = 1379 - syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); 1380 - if (IS_ERR(imx6_pcie->iomuxc_gpr)) 1381 - return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), 1341 + imx_pcie->iomuxc_gpr = 1342 + syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr); 1343 + if (IS_ERR(imx_pcie->iomuxc_gpr)) 1344 + return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), 1382 1345 "unable to find iomuxc registers\n"); 1383 1346 } 1384 1347 1385 - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) { 1348 + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_SERDES)) { 1386 1349 void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app"); 1387 1350 1388 1351 if (IS_ERR(off)) ··· 1395 1358 .reg_stride = 4, 1396 1359 }; 1397 1360 1398 - imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, &regmap_config); 1399 - if (IS_ERR(imx6_pcie->iomuxc_gpr)) 1400 - return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), 1361 + imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, &regmap_config); 1362 + if (IS_ERR(imx_pcie->iomuxc_gpr)) 1363 + return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), 1401 1364 "unable to find iomuxc registers\n"); 1402 1365 } 1403 1366 1404 1367 /* Grab PCIe PHY Tx Settings */ 1405 1368 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", 1406 - &imx6_pcie->tx_deemph_gen1)) 1407 - imx6_pcie->tx_deemph_gen1 = 0; 1369 + &imx_pcie->tx_deemph_gen1)) 1370 + imx_pcie->tx_deemph_gen1 = 0; 1408 1371 1409 1372 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", 1410 - &imx6_pcie->tx_deemph_gen2_3p5db)) 1411 - imx6_pcie->tx_deemph_gen2_3p5db = 0; 1373 + &imx_pcie->tx_deemph_gen2_3p5db)) 1374 + imx_pcie->tx_deemph_gen2_3p5db = 0; 1412 1375 1413 1376 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", 1414 - &imx6_pcie->tx_deemph_gen2_6db)) 1415 - imx6_pcie->tx_deemph_gen2_6db = 20; 1377 + &imx_pcie->tx_deemph_gen2_6db)) 1378 + imx_pcie->tx_deemph_gen2_6db = 20; 1416 1379 1417 1380 if (of_property_read_u32(node, "fsl,tx-swing-full", 1418 - &imx6_pcie->tx_swing_full)) 1419 - imx6_pcie->tx_swing_full = 127; 1381 + &imx_pcie->tx_swing_full)) 1382 + imx_pcie->tx_swing_full = 127; 1420 1383 1421 1384 if (of_property_read_u32(node, "fsl,tx-swing-low", 1422 - &imx6_pcie->tx_swing_low)) 1423 - imx6_pcie->tx_swing_low = 127; 1385 + &imx_pcie->tx_swing_low)) 1386 + imx_pcie->tx_swing_low = 127; 1424 1387 1425 1388 /* Limit link speed */ 1426 - pci->link_gen = 1; 1427 - of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); 1389 + pci->max_link_speed = 1; 1390 + of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed); 1428 1391 1429 - imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 1430 - if (IS_ERR(imx6_pcie->vpcie)) { 1431 - if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) 1432 - return PTR_ERR(imx6_pcie->vpcie); 1433 - imx6_pcie->vpcie = NULL; 1392 + imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 1393 + if (IS_ERR(imx_pcie->vpcie)) { 1394 + if (PTR_ERR(imx_pcie->vpcie) != -ENODEV) 1395 + return PTR_ERR(imx_pcie->vpcie); 1396 + imx_pcie->vpcie = NULL; 1434 1397 } 1435 1398 1436 - imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); 1437 - if (IS_ERR(imx6_pcie->vph)) { 1438 - if (PTR_ERR(imx6_pcie->vph) != -ENODEV) 1439 - return PTR_ERR(imx6_pcie->vph); 1440 - imx6_pcie->vph = NULL; 1399 + imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); 1400 + if (IS_ERR(imx_pcie->vph)) { 1401 + if (PTR_ERR(imx_pcie->vph) != -ENODEV) 1402 + return PTR_ERR(imx_pcie->vph); 1403 + imx_pcie->vph = NULL; 1441 1404 } 1442 1405 1443 - platform_set_drvdata(pdev, imx6_pcie); 1406 + platform_set_drvdata(pdev, imx_pcie); 1444 1407 1445 - ret = imx6_pcie_attach_pd(dev); 1408 + ret = imx_pcie_attach_pd(dev); 1446 1409 if (ret) 1447 1410 return ret; 1448 1411 1449 - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { 1450 - ret = imx6_add_pcie_ep(imx6_pcie, pdev); 1412 + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { 1413 + ret = imx_add_pcie_ep(imx_pcie, pdev); 1451 1414 if (ret < 0) 1452 1415 return ret; 1453 1416 } else { ··· 1467 1430 return 0; 1468 1431 } 1469 1432 1470 - static void imx6_pcie_shutdown(struct platform_device *pdev) 1433 + static void imx_pcie_shutdown(struct platform_device *pdev) 1471 1434 { 1472 - struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); 1435 + struct imx_pcie *imx_pcie = platform_get_drvdata(pdev); 1473 1436 1474 1437 /* bring down link, so bootloader gets clean state in case of reboot */ 1475 - imx6_pcie_assert_core_reset(imx6_pcie); 1438 + imx_pcie_assert_core_reset(imx_pcie); 1476 1439 } 1477 1440 1478 1441 static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"}; 1479 1442 static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; 1480 1443 static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; 1481 1444 static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; 1445 + static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"}; 1482 1446 1483 - static const struct imx6_pcie_drvdata drvdata[] = { 1447 + static const struct imx_pcie_drvdata drvdata[] = { 1484 1448 [IMX6Q] = { 1485 1449 .variant = IMX6Q, 1486 - .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1487 - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1450 + .flags = IMX_PCIE_FLAG_IMX_PHY | 1451 + IMX_PCIE_FLAG_IMX_SPEED_CHANGE, 1488 1452 .dbi_length = 0x200, 1489 1453 .gpr = "fsl,imx6q-iomuxc-gpr", 1490 1454 .clk_names = imx6q_clks, ··· 1494 1456 .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1495 1457 .mode_off[0] = IOMUXC_GPR12, 1496 1458 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1497 - .init_phy = imx6_pcie_init_phy, 1459 + .init_phy = imx_pcie_init_phy, 1460 + .enable_ref_clk = imx6q_pcie_enable_ref_clk, 1461 + .core_reset = imx6q_pcie_core_reset, 1498 1462 }, 1499 1463 [IMX6SX] = { 1500 1464 .variant = IMX6SX, 1501 - .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1502 - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1503 - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1465 + .flags = IMX_PCIE_FLAG_IMX_PHY | 1466 + IMX_PCIE_FLAG_IMX_SPEED_CHANGE | 1467 + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, 1504 1468 .gpr = "fsl,imx6q-iomuxc-gpr", 1505 1469 .clk_names = imx6sx_clks, 1506 1470 .clks_cnt = ARRAY_SIZE(imx6sx_clks), ··· 1511 1471 .mode_off[0] = IOMUXC_GPR12, 1512 1472 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1513 1473 .init_phy = imx6sx_pcie_init_phy, 1474 + .enable_ref_clk = imx6sx_pcie_enable_ref_clk, 1475 + .core_reset = imx6sx_pcie_core_reset, 1514 1476 }, 1515 1477 [IMX6QP] = { 1516 1478 .variant = IMX6QP, 1517 - .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1518 - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1519 - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1479 + .flags = IMX_PCIE_FLAG_IMX_PHY | 1480 + IMX_PCIE_FLAG_IMX_SPEED_CHANGE | 1481 + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, 1520 1482 .dbi_length = 0x200, 1521 1483 .gpr = "fsl,imx6q-iomuxc-gpr", 1522 1484 .clk_names = imx6q_clks, ··· 1527 1485 .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1528 1486 .mode_off[0] = IOMUXC_GPR12, 1529 1487 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1530 - .init_phy = imx6_pcie_init_phy, 1488 + .init_phy = imx_pcie_init_phy, 1489 + .enable_ref_clk = imx6q_pcie_enable_ref_clk, 1490 + .core_reset = imx6qp_pcie_core_reset, 1531 1491 }, 1532 1492 [IMX7D] = { 1533 1493 .variant = IMX7D, 1534 - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 1535 - IMX6_PCIE_FLAG_HAS_APP_RESET | 1536 - IMX6_PCIE_FLAG_HAS_PHY_RESET, 1494 + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | 1495 + IMX_PCIE_FLAG_HAS_APP_RESET | 1496 + IMX_PCIE_FLAG_HAS_PHY_RESET, 1537 1497 .gpr = "fsl,imx7d-iomuxc-gpr", 1538 1498 .clk_names = imx6q_clks, 1539 1499 .clks_cnt = ARRAY_SIZE(imx6q_clks), 1540 1500 .mode_off[0] = IOMUXC_GPR12, 1541 1501 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1542 1502 .init_phy = imx7d_pcie_init_phy, 1503 + .enable_ref_clk = imx7d_pcie_enable_ref_clk, 1504 + .core_reset = imx7d_pcie_core_reset, 1543 1505 }, 1544 1506 [IMX8MQ] = { 1545 1507 .variant = IMX8MQ, 1546 - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | 1547 - IMX6_PCIE_FLAG_HAS_PHY_RESET, 1508 + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | 1509 + IMX_PCIE_FLAG_HAS_PHY_RESET, 1548 1510 .gpr = "fsl,imx8mq-iomuxc-gpr", 1549 1511 .clk_names = imx8mq_clks, 1550 1512 .clks_cnt = ARRAY_SIZE(imx8mq_clks), ··· 1557 1511 .mode_off[1] = IOMUXC_GPR12, 1558 1512 .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 1559 1513 .init_phy = imx8mq_pcie_init_phy, 1514 + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, 1560 1515 }, 1561 1516 [IMX8MM] = { 1562 1517 .variant = IMX8MM, 1563 - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 1564 - IMX6_PCIE_FLAG_HAS_PHYDRV | 1565 - IMX6_PCIE_FLAG_HAS_APP_RESET, 1518 + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | 1519 + IMX_PCIE_FLAG_HAS_PHYDRV | 1520 + IMX_PCIE_FLAG_HAS_APP_RESET, 1566 1521 .gpr = "fsl,imx8mm-iomuxc-gpr", 1567 1522 .clk_names = imx8mm_clks, 1568 1523 .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1569 1524 .mode_off[0] = IOMUXC_GPR12, 1570 1525 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1526 + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, 1571 1527 }, 1572 1528 [IMX8MP] = { 1573 1529 .variant = IMX8MP, 1574 - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 1575 - IMX6_PCIE_FLAG_HAS_PHYDRV | 1576 - IMX6_PCIE_FLAG_HAS_APP_RESET, 1530 + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | 1531 + IMX_PCIE_FLAG_HAS_PHYDRV | 1532 + IMX_PCIE_FLAG_HAS_APP_RESET, 1577 1533 .gpr = "fsl,imx8mp-iomuxc-gpr", 1578 1534 .clk_names = imx8mm_clks, 1579 1535 .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1580 1536 .mode_off[0] = IOMUXC_GPR12, 1581 1537 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1538 + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, 1539 + }, 1540 + [IMX8Q] = { 1541 + .variant = IMX8Q, 1542 + .flags = IMX_PCIE_FLAG_HAS_PHYDRV | 1543 + IMX_PCIE_FLAG_CPU_ADDR_FIXUP, 1544 + .clk_names = imx8q_clks, 1545 + .clks_cnt = ARRAY_SIZE(imx8q_clks), 1582 1546 }, 1583 1547 [IMX95] = { 1584 1548 .variant = IMX95, 1585 - .flags = IMX6_PCIE_FLAG_HAS_SERDES, 1549 + .flags = IMX_PCIE_FLAG_HAS_SERDES, 1586 1550 .clk_names = imx8mq_clks, 1587 1551 .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1588 1552 .ltssm_off = IMX95_PE0_GEN_CTRL_3, ··· 1603 1547 }, 1604 1548 [IMX8MQ_EP] = { 1605 1549 .variant = IMX8MQ_EP, 1606 - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | 1607 - IMX6_PCIE_FLAG_HAS_PHY_RESET, 1550 + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | 1551 + IMX_PCIE_FLAG_HAS_PHY_RESET, 1608 1552 .mode = DW_PCIE_EP_TYPE, 1609 1553 .gpr = "fsl,imx8mq-iomuxc-gpr", 1610 1554 .clk_names = imx8mq_clks, ··· 1615 1559 .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 1616 1560 .epc_features = &imx8m_pcie_epc_features, 1617 1561 .init_phy = imx8mq_pcie_init_phy, 1562 + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, 1618 1563 }, 1619 1564 [IMX8MM_EP] = { 1620 1565 .variant = IMX8MM_EP, 1621 - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, 1566 + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | 1567 + IMX_PCIE_FLAG_HAS_PHYDRV, 1622 1568 .mode = DW_PCIE_EP_TYPE, 1623 1569 .gpr = "fsl,imx8mm-iomuxc-gpr", 1624 1570 .clk_names = imx8mm_clks, ··· 1628 1570 .mode_off[0] = IOMUXC_GPR12, 1629 1571 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1630 1572 .epc_features = &imx8m_pcie_epc_features, 1573 + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, 1631 1574 }, 1632 1575 [IMX8MP_EP] = { 1633 1576 .variant = IMX8MP_EP, 1634 - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, 1577 + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | 1578 + IMX_PCIE_FLAG_HAS_PHYDRV, 1635 1579 .mode = DW_PCIE_EP_TYPE, 1636 1580 .gpr = "fsl,imx8mp-iomuxc-gpr", 1637 1581 .clk_names = imx8mm_clks, ··· 1641 1581 .mode_off[0] = IOMUXC_GPR12, 1642 1582 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1643 1583 .epc_features = &imx8m_pcie_epc_features, 1584 + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, 1644 1585 }, 1645 1586 [IMX95_EP] = { 1646 1587 .variant = IMX95_EP, 1647 - .flags = IMX6_PCIE_FLAG_HAS_SERDES | 1648 - IMX6_PCIE_FLAG_SUPPORT_64BIT, 1588 + .flags = IMX_PCIE_FLAG_HAS_SERDES | 1589 + IMX_PCIE_FLAG_SUPPORT_64BIT, 1649 1590 .clk_names = imx8mq_clks, 1650 1591 .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1651 1592 .ltssm_off = IMX95_PE0_GEN_CTRL_3, ··· 1659 1598 }, 1660 1599 }; 1661 1600 1662 - static const struct of_device_id imx6_pcie_of_match[] = { 1601 + static const struct of_device_id imx_pcie_of_match[] = { 1663 1602 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, 1664 1603 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, 1665 1604 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, ··· 1667 1606 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, 1668 1607 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, 1669 1608 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, 1609 + { .compatible = "fsl,imx8q-pcie", .data = &drvdata[IMX8Q], }, 1670 1610 { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], }, 1671 1611 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, 1672 1612 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, ··· 1676 1614 {}, 1677 1615 }; 1678 1616 1679 - static struct platform_driver imx6_pcie_driver = { 1617 + static struct platform_driver imx_pcie_driver = { 1680 1618 .driver = { 1681 1619 .name = "imx6q-pcie", 1682 - .of_match_table = imx6_pcie_of_match, 1620 + .of_match_table = imx_pcie_of_match, 1683 1621 .suppress_bind_attrs = true, 1684 - .pm = &imx6_pcie_pm_ops, 1622 + .pm = &imx_pcie_pm_ops, 1685 1623 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1686 1624 }, 1687 - .probe = imx6_pcie_probe, 1688 - .shutdown = imx6_pcie_shutdown, 1625 + .probe = imx_pcie_probe, 1626 + .shutdown = imx_pcie_shutdown, 1689 1627 }; 1690 1628 1691 - static void imx6_pcie_quirk(struct pci_dev *dev) 1629 + static void imx_pcie_quirk(struct pci_dev *dev) 1692 1630 { 1693 1631 struct pci_bus *bus = dev->bus; 1694 1632 struct dw_pcie_rp *pp = bus->sysdata; ··· 1698 1636 return; 1699 1637 1700 1638 /* Make sure we only quirk devices associated with this driver */ 1701 - if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) 1639 + if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver) 1702 1640 return; 1703 1641 1704 1642 if (pci_is_root_bus(bus)) { 1705 1643 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1706 - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1644 + struct imx_pcie *imx_pcie = to_imx_pcie(pci); 1707 1645 1708 1646 /* 1709 1647 * Limit config length to avoid the kernel reading beyond 1710 1648 * the register set and causing an abort on i.MX 6Quad 1711 1649 */ 1712 - if (imx6_pcie->drvdata->dbi_length) { 1713 - dev->cfg_size = imx6_pcie->drvdata->dbi_length; 1650 + if (imx_pcie->drvdata->dbi_length) { 1651 + dev->cfg_size = imx_pcie->drvdata->dbi_length; 1714 1652 dev_info(&dev->dev, "Limiting cfg_size to %d\n", 1715 1653 dev->cfg_size); 1716 1654 } 1717 1655 } 1718 1656 } 1719 1657 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, 1720 - PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); 1658 + PCI_CLASS_BRIDGE_PCI, 8, imx_pcie_quirk); 1721 1659 1722 - static int __init imx6_pcie_init(void) 1660 + static int __init imx_pcie_init(void) 1723 1661 { 1724 1662 #ifdef CONFIG_ARM 1725 1663 struct device_node *np; 1726 1664 1727 - np = of_find_matching_node(NULL, imx6_pcie_of_match); 1665 + np = of_find_matching_node(NULL, imx_pcie_of_match); 1728 1666 if (!np) 1729 1667 return -ENODEV; 1730 1668 of_node_put(np); ··· 1740 1678 "external abort on non-linefetch"); 1741 1679 #endif 1742 1680 1743 - return platform_driver_register(&imx6_pcie_driver); 1681 + return platform_driver_register(&imx_pcie_driver); 1744 1682 } 1745 - device_initcall(imx6_pcie_init); 1683 + device_initcall(imx_pcie_init);
+1 -8
drivers/pci/controller/dwc/pci-keystone.c
··· 189 189 (int)data->hwirq, msg->address_hi, msg->address_lo); 190 190 } 191 191 192 - static int ks_pcie_msi_set_affinity(struct irq_data *irq_data, 193 - const struct cpumask *mask, bool force) 194 - { 195 - return -EINVAL; 196 - } 197 - 198 192 static void ks_pcie_msi_mask(struct irq_data *data) 199 193 { 200 194 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); ··· 241 247 .name = "KEYSTONE-PCI-MSI", 242 248 .irq_ack = ks_pcie_msi_irq_ack, 243 249 .irq_compose_msi_msg = ks_pcie_compose_msi_msg, 244 - .irq_set_affinity = ks_pcie_msi_set_affinity, 245 250 .irq_mask = ks_pcie_msi_mask, 246 251 .irq_unmask = ks_pcie_msi_unmask, 247 252 }; ··· 570 577 */ 571 578 if (pci_match_id(am6_pci_devids, bridge)) { 572 579 bridge_dev = pci_get_host_bridge_device(dev); 573 - if (!bridge_dev && !bridge_dev->parent) 580 + if (!bridge_dev || !bridge_dev->parent) 574 581 return; 575 582 576 583 ks_pcie = dev_get_drvdata(bridge_dev->parent);
+3 -9
drivers/pci/controller/dwc/pcie-designware-host.c
··· 48 48 }; 49 49 50 50 static struct msi_domain_info dw_pcie_msi_domain_info = { 51 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 52 - MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), 51 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 52 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX | 53 + MSI_FLAG_MULTI_PCI_MSI, 53 54 .chip = &dw_pcie_msi_irq_chip, 54 55 }; 55 56 ··· 117 116 (int)d->hwirq, msg->address_hi, msg->address_lo); 118 117 } 119 118 120 - static int dw_pci_msi_set_affinity(struct irq_data *d, 121 - const struct cpumask *mask, bool force) 122 - { 123 - return -EINVAL; 124 - } 125 - 126 119 static void dw_pci_bottom_mask(struct irq_data *d) 127 120 { 128 121 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); ··· 172 177 .name = "DWPCI-MSI", 173 178 .irq_ack = dw_pci_bottom_ack, 174 179 .irq_compose_msi_msg = dw_pci_setup_msi_msg, 175 - .irq_set_affinity = dw_pci_msi_set_affinity, 176 180 .irq_mask = dw_pci_bottom_mask, 177 181 .irq_unmask = dw_pci_bottom_unmask, 178 182 };
+18 -6
drivers/pci/controller/dwc/pcie-designware.c
··· 112 112 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); 113 113 if (IS_ERR(pci->dbi_base)) 114 114 return PTR_ERR(pci->dbi_base); 115 + pci->dbi_phys_addr = res->start; 115 116 } 116 117 117 118 /* DBI2 is mainly useful for the endpoint controller */ ··· 135 134 pci->atu_base = devm_ioremap_resource(pci->dev, res); 136 135 if (IS_ERR(pci->atu_base)) 137 136 return PTR_ERR(pci->atu_base); 137 + pci->atu_phys_addr = res->start; 138 138 } else { 139 139 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 140 140 } ··· 168 166 return ret; 169 167 } 170 168 171 - if (pci->link_gen < 1) 172 - pci->link_gen = of_pci_get_max_link_speed(np); 169 + if (pci->max_link_speed < 1) 170 + pci->max_link_speed = of_pci_get_max_link_speed(np); 173 171 174 172 of_property_read_u32(np, "num-lanes", &pci->num_lanes); 175 173 ··· 689 687 } 690 688 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); 691 689 692 - static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) 690 + static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) 693 691 { 694 692 u32 cap, ctrl2, link_speed; 695 693 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 696 694 697 695 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 696 + 697 + /* 698 + * Even if the platform doesn't want to limit the maximum link speed, 699 + * just cache the hardware default value so that the vendor drivers can 700 + * use it to do any link specific configuration. 701 + */ 702 + if (pci->max_link_speed < 1) { 703 + pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 704 + return; 705 + } 706 + 698 707 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); 699 708 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 700 709 701 - switch (pcie_link_speed[link_gen]) { 710 + switch (pcie_link_speed[pci->max_link_speed]) { 702 711 case PCIE_SPEED_2_5GT: 703 712 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT; 704 713 break; ··· 1071 1058 { 1072 1059 u32 val; 1073 1060 1074 - if (pci->link_gen > 0) 1075 - dw_pcie_link_set_max_speed(pci, pci->link_gen); 1061 + dw_pcie_link_set_max_speed(pci); 1076 1062 1077 1063 /* Configure Gen1 N_FTS */ 1078 1064 if (pci->n_fts[0]) {
+34 -1
drivers/pci/controller/dwc/pcie-designware.h
··· 125 125 #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) 126 126 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 127 127 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) 128 + #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT 0x1 129 + 130 + #define GEN3_EQ_CONTROL_OFF 0x8A8 131 + #define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0) 132 + #define GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE BIT(4) 133 + #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC GENMASK(23, 8) 134 + #define GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL BIT(24) 135 + 136 + #define GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x8AC 137 + #define GEN3_EQ_FMDC_T_MIN_PHASE23 GENMASK(4, 0) 138 + #define GEN3_EQ_FMDC_N_EVALS GENMASK(9, 5) 139 + #define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA GENMASK(13, 10) 140 + #define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA GENMASK(17, 14) 128 141 129 142 #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 130 143 #define PORT_MLTI_UPCFG_SUPPORT BIT(7) ··· 210 197 211 198 #define PCIE_PL_CHK_REG_ERR_ADDR 0xB28 212 199 200 + /* 201 + * 16.0 GT/s (Gen 4) lane margining register definitions 202 + */ 203 + #define GEN4_LANE_MARGINING_1_OFF 0xB80 204 + #define MARGINING_MAX_VOLTAGE_OFFSET GENMASK(29, 24) 205 + #define MARGINING_NUM_VOLTAGE_STEPS GENMASK(22, 16) 206 + #define MARGINING_MAX_TIMING_OFFSET GENMASK(13, 8) 207 + #define MARGINING_NUM_TIMING_STEPS GENMASK(5, 0) 208 + 209 + #define GEN4_LANE_MARGINING_2_OFF 0xB84 210 + #define MARGINING_IND_ERROR_SAMPLER BIT(28) 211 + #define MARGINING_SAMPLE_REPORTING_METHOD BIT(27) 212 + #define MARGINING_IND_LEFT_RIGHT_TIMING BIT(26) 213 + #define MARGINING_IND_UP_DOWN_VOLTAGE BIT(25) 214 + #define MARGINING_VOLTAGE_SUPPORTED BIT(24) 215 + #define MARGINING_MAXLANES GENMASK(20, 16) 216 + #define MARGINING_SAMPLE_RATE_TIMING GENMASK(13, 8) 217 + #define MARGINING_SAMPLE_RATE_VOLTAGE GENMASK(5, 0) 213 218 /* 214 219 * iATU Unroll-specific register definitions 215 220 * From 4.80 core version the address translation will be made by unroll ··· 438 407 struct dw_pcie { 439 408 struct device *dev; 440 409 void __iomem *dbi_base; 410 + resource_size_t dbi_phys_addr; 441 411 void __iomem *dbi_base2; 442 412 void __iomem *atu_base; 413 + resource_size_t atu_phys_addr; 443 414 size_t atu_size; 444 415 u32 num_ib_windows; 445 416 u32 num_ob_windows; ··· 454 421 u32 type; 455 422 unsigned long caps; 456 423 int num_lanes; 457 - int link_gen; 424 + int max_link_speed; 458 425 u8 n_fts[2]; 459 426 struct dw_edma_chip edma; 460 427 struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS];
+2 -2
drivers/pci/controller/dwc/pcie-intel-gw.c
··· 132 132 133 133 static void intel_pcie_init_n_fts(struct dw_pcie *pci) 134 134 { 135 - switch (pci->link_gen) { 135 + switch (pci->max_link_speed) { 136 136 case 3: 137 137 pci->n_fts[1] = PORT_AFR_N_FTS_GEN3; 138 138 break; ··· 252 252 int ret; 253 253 struct dw_pcie *pci = &pcie->pci; 254 254 255 - if (pci->link_gen < 3) 255 + if (pci->max_link_speed < 3) 256 256 return 0; 257 257 258 258 /* Send PME_TURN_OFF message */
+2 -2
drivers/pci/controller/dwc/pcie-kirin.c
··· 420 420 "unable to get a valid reset gpio\n"); 421 421 } 422 422 423 - pcie->num_slots++; 424 - if (pcie->num_slots > MAX_PCI_SLOTS) { 423 + if (pcie->num_slots + 1 >= MAX_PCI_SLOTS) { 425 424 dev_err(dev, "Too many PCI slots!\n"); 426 425 return -EINVAL; 427 426 } 427 + pcie->num_slots++; 428 428 429 429 ret = of_pci_get_devfn(child); 430 430 if (ret < 0) {
+78
drivers/pci/controller/dwc/pcie-qcom-common.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #include <linux/pci.h> 7 + 8 + #include "pcie-designware.h" 9 + #include "pcie-qcom-common.h" 10 + 11 + void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) 12 + { 13 + u32 reg; 14 + 15 + /* 16 + * GEN3_RELATED_OFF register is repurposed to apply equalization 17 + * settings at various data transmission rates through registers namely 18 + * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF 19 + * determines the data rate for which these equalization settings are 20 + * applied. 21 + */ 22 + reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 23 + reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 24 + reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 25 + reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 26 + GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT); 27 + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); 28 + 29 + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); 30 + reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | 31 + GEN3_EQ_FMDC_N_EVALS | 32 + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | 33 + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); 34 + reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | 35 + FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | 36 + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | 37 + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); 38 + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); 39 + 40 + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 41 + reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | 42 + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | 43 + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | 44 + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); 45 + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); 46 + } 47 + EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization); 48 + 49 + void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci) 50 + { 51 + u32 reg; 52 + 53 + reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF); 54 + reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET | 55 + MARGINING_NUM_VOLTAGE_STEPS | 56 + MARGINING_MAX_TIMING_OFFSET | 57 + MARGINING_NUM_TIMING_STEPS); 58 + reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) | 59 + FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) | 60 + FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) | 61 + FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10); 62 + dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg); 63 + 64 + reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF); 65 + reg |= MARGINING_IND_ERROR_SAMPLER | 66 + MARGINING_SAMPLE_REPORTING_METHOD | 67 + MARGINING_IND_LEFT_RIGHT_TIMING | 68 + MARGINING_VOLTAGE_SUPPORTED; 69 + reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE | 70 + MARGINING_MAXLANES | 71 + MARGINING_SAMPLE_RATE_TIMING | 72 + MARGINING_SAMPLE_RATE_VOLTAGE); 73 + reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) | 74 + FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) | 75 + FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f); 76 + dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg); 77 + } 78 + EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining);
+14
drivers/pci/controller/dwc/pcie-qcom-common.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef _PCIE_QCOM_COMMON_H 7 + #define _PCIE_QCOM_COMMON_H 8 + 9 + struct dw_pcie; 10 + 11 + void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci); 12 + void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci); 13 + 14 + #endif
+26 -15
drivers/pci/controller/dwc/pcie-qcom-ep.c
··· 25 25 26 26 #include "../../pci.h" 27 27 #include "pcie-designware.h" 28 + #include "pcie-qcom-common.h" 28 29 29 30 /* PARF registers */ 30 31 #define PARF_SYS_CTRL 0x00 ··· 499 498 goto err_disable_resources; 500 499 } 501 500 501 + if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { 502 + qcom_pcie_common_set_16gt_equalization(pci); 503 + qcom_pcie_common_set_16gt_lane_margining(pci); 504 + } 505 + 502 506 /* 503 507 * The physical address of the MMIO region which is exposed as the BAR 504 508 * should be written to MHI BASE registers. ··· 665 659 struct dw_pcie *pci = &pcie_ep->pci; 666 660 struct device *dev = pci->dev; 667 661 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); 668 - u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); 669 662 u32 dstate, val; 670 663 671 664 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); 672 - status &= mask; 673 665 674 666 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { 675 667 dev_dbg(dev, "Received Linkdown event\n"); ··· 697 693 dw_pcie_ep_linkup(&pci->ep); 698 694 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; 699 695 } else { 700 - dev_err(dev, "Received unknown event: %d\n", status); 696 + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", 697 + status); 701 698 } 702 699 703 700 return IRQ_HANDLED; ··· 729 724 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, 730 725 struct qcom_pcie_ep *pcie_ep) 731 726 { 727 + struct device *dev = pcie_ep->pci.dev; 728 + char *name; 732 729 int ret; 730 + 731 + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d", 732 + pcie_ep->pci.ep.epc->domain_nr); 733 + if (!name) 734 + return -ENOMEM; 733 735 734 736 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); 735 737 if (pcie_ep->global_irq < 0) ··· 745 733 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, 746 734 qcom_pcie_ep_global_irq_thread, 747 735 IRQF_ONESHOT, 748 - "global_irq", pcie_ep); 736 + name, pcie_ep); 749 737 if (ret) { 750 738 dev_err(&pdev->dev, "Failed to request Global IRQ\n"); 751 739 return ret; 752 740 } 741 + 742 + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d", 743 + pcie_ep->pci.ep.epc->domain_nr); 744 + if (!name) 745 + return -ENOMEM; 753 746 754 747 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); 755 748 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); 756 749 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, 757 750 qcom_pcie_ep_perst_irq_thread, 758 751 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 759 - "perst_irq", pcie_ep); 752 + name, pcie_ep); 760 753 if (ret) { 761 754 dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); 762 755 disable_irq(pcie_ep->global_irq); ··· 875 858 if (ret) 876 859 return ret; 877 860 878 - ret = qcom_pcie_enable_resources(pcie_ep); 879 - if (ret) { 880 - dev_err(dev, "Failed to enable resources: %d\n", ret); 881 - return ret; 882 - } 883 - 884 861 ret = dw_pcie_ep_init(&pcie_ep->pci.ep); 885 862 if (ret) { 886 863 dev_err(dev, "Failed to initialize endpoint: %d\n", ret); 887 - goto err_disable_resources; 864 + return ret; 888 865 } 889 866 890 867 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep); 891 868 if (ret) 892 - goto err_disable_resources; 869 + goto err_ep_deinit; 893 870 894 871 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 895 872 if (!name) { ··· 900 889 disable_irq(pcie_ep->global_irq); 901 890 disable_irq(pcie_ep->perst_irq); 902 891 903 - err_disable_resources: 904 - qcom_pcie_disable_resources(pcie_ep); 892 + err_ep_deinit: 893 + dw_pcie_ep_deinit(&pcie_ep->pci.ep); 905 894 906 895 return ret; 907 896 }
+117 -16
drivers/pci/controller/dwc/pcie-qcom.c
··· 35 35 36 36 #include "../../pci.h" 37 37 #include "pcie-designware.h" 38 + #include "pcie-qcom-common.h" 38 39 39 40 /* PARF registers */ 40 41 #define PARF_SYS_CTRL 0x00 ··· 46 45 #define PARF_PHY_REFCLK 0x4c 47 46 #define PARF_CONFIG_BITS 0x50 48 47 #define PARF_DBI_BASE_ADDR 0x168 48 + #define PARF_SLV_ADDR_SPACE_SIZE 0x16c 49 49 #define PARF_MHI_CLOCK_RESET_CTRL 0x174 50 50 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 51 51 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 52 52 #define PARF_Q2A_FLUSH 0x1ac 53 53 #define PARF_LTSSM 0x1b0 54 + #define PARF_INT_ALL_STATUS 0x224 55 + #define PARF_INT_ALL_CLEAR 0x228 56 + #define PARF_INT_ALL_MASK 0x22c 54 57 #define PARF_SID_OFFSET 0x234 55 58 #define PARF_BDF_TRANSLATE_CFG 0x24c 56 - #define PARF_SLV_ADDR_SPACE_SIZE 0x358 59 + #define PARF_DBI_BASE_ADDR_V2 0x350 60 + #define PARF_DBI_BASE_ADDR_V2_HI 0x354 61 + #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 62 + #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c 57 63 #define PARF_NO_SNOOP_OVERIDE 0x3d4 64 + #define PARF_ATU_BASE_ADDR 0x634 65 + #define PARF_ATU_BASE_ADDR_HI 0x638 58 66 #define PARF_DEVICE_TYPE 0x1000 59 67 #define PARF_BDF_TO_SID_TABLE_N 0x2000 60 68 #define PARF_BDF_TO_SID_CFG 0x2c00 ··· 118 108 #define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) 119 109 120 110 /* PARF_SLV_ADDR_SPACE_SIZE register value */ 121 - #define SLV_ADDR_SPACE_SZ 0x10000000 111 + #define SLV_ADDR_SPACE_SZ 0x80000000 122 112 123 113 /* PARF_MHI_CLOCK_RESET_CTRL register fields */ 124 114 #define AHB_CLK_EN BIT(0) ··· 130 120 131 121 /* PARF_LTSSM register fields */ 132 122 #define LTSSM_EN BIT(8) 123 + 124 + /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 125 + #define PARF_INT_ALL_LINK_UP BIT(13) 133 126 134 127 /* PARF_NO_SNOOP_OVERIDE register fields */ 135 128 #define WR_NO_SNOOP_OVERIDE_EN BIT(1) ··· 297 284 { 298 285 struct qcom_pcie *pcie = to_qcom_pcie(pci); 299 286 287 + if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { 288 + qcom_pcie_common_set_16gt_equalization(pci); 289 + qcom_pcie_common_set_16gt_lane_margining(pci); 290 + } 291 + 300 292 /* Enable Link Training state machine */ 301 293 if (pcie->cfg->ops->ltssm_enable) 302 294 pcie->cfg->ops->ltssm_enable(pcie); ··· 341 323 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); 342 324 343 325 dw_pcie_dbi_ro_wr_dis(pci); 326 + } 327 + 328 + static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie) 329 + { 330 + struct dw_pcie *pci = pcie->pci; 331 + 332 + if (pci->dbi_phys_addr) { 333 + /* 334 + * PARF_DBI_BASE_ADDR register is in CPU domain and require to 335 + * be programmed with CPU physical address. 336 + */ 337 + writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + 338 + PARF_DBI_BASE_ADDR); 339 + writel(SLV_ADDR_SPACE_SZ, pcie->parf + 340 + PARF_SLV_ADDR_SPACE_SIZE); 341 + } 342 + } 343 + 344 + static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie) 345 + { 346 + struct dw_pcie *pci = pcie->pci; 347 + 348 + if (pci->dbi_phys_addr) { 349 + /* 350 + * PARF_DBI_BASE_ADDR_V2 and PARF_ATU_BASE_ADDR registers are 351 + * in CPU domain and require to be programmed with CPU 352 + * physical addresses. 353 + */ 354 + writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + 355 + PARF_DBI_BASE_ADDR_V2); 356 + writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + 357 + PARF_DBI_BASE_ADDR_V2_HI); 358 + 359 + if (pci->atu_phys_addr) { 360 + writel(lower_32_bits(pci->atu_phys_addr), pcie->parf + 361 + PARF_ATU_BASE_ADDR); 362 + writel(upper_32_bits(pci->atu_phys_addr), pcie->parf + 363 + PARF_ATU_BASE_ADDR_HI); 364 + } 365 + 366 + writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2); 367 + writel(SLV_ADDR_SPACE_SZ, pcie->parf + 368 + PARF_SLV_ADDR_SPACE_SIZE_V2_HI); 369 + } 344 370 } 345 371 346 372 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) ··· 603 541 604 542 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) 605 543 { 606 - /* change DBI base address */ 607 - writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 544 + qcom_pcie_configure_dbi_base(pcie); 608 545 609 546 if (IS_ENABLED(CONFIG_PCI_MSI)) { 610 547 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); ··· 690 629 val &= ~PHY_TEST_PWR_DOWN; 691 630 writel(val, pcie->parf + PARF_PHY_CTRL); 692 631 693 - /* change DBI base address */ 694 - writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 632 + qcom_pcie_configure_dbi_base(pcie); 695 633 696 634 /* MAC PHY_POWERDOWN MUX DISABLE */ 697 635 val = readl(pcie->parf + PARF_SYS_CTRL); ··· 872 812 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 873 813 u32 val; 874 814 875 - writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); 876 - 877 815 val = readl(pcie->parf + PARF_PHY_CTRL); 878 816 val &= ~PHY_TEST_PWR_DOWN; 879 817 writel(val, pcie->parf + PARF_PHY_CTRL); 880 818 881 - writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 819 + qcom_pcie_configure_dbi_atu_base(pcie); 882 820 883 821 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS 884 822 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | ··· 972 914 val &= ~PHY_TEST_PWR_DOWN; 973 915 writel(val, pcie->parf + PARF_PHY_CTRL); 974 916 975 - /* change DBI base address */ 976 - writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 917 + qcom_pcie_configure_dbi_atu_base(pcie); 977 918 978 919 /* MAC PHY_POWERDOWN MUX DISABLE */ 979 920 val = readl(pcie->parf + PARF_SYS_CTRL); ··· 1181 1124 u32 val; 1182 1125 int i; 1183 1126 1184 - writel(SLV_ADDR_SPACE_SZ, 1185 - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); 1186 - 1187 1127 val = readl(pcie->parf + PARF_PHY_CTRL); 1188 1128 val &= ~PHY_TEST_PWR_DOWN; 1189 1129 writel(val, pcie->parf + PARF_PHY_CTRL); 1190 1130 1191 - writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 1131 + qcom_pcie_configure_dbi_atu_base(pcie); 1192 1132 1193 1133 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); 1194 1134 writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, ··· 1543 1489 qcom_pcie_link_transition_count); 1544 1490 } 1545 1491 1492 + static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) 1493 + { 1494 + struct qcom_pcie *pcie = data; 1495 + struct dw_pcie_rp *pp = &pcie->pci->pp; 1496 + struct device *dev = pcie->pci->dev; 1497 + u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); 1498 + 1499 + writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); 1500 + 1501 + if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { 1502 + dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); 1503 + /* Rescan the bus to enumerate endpoint devices */ 1504 + pci_lock_rescan_remove(); 1505 + pci_rescan_bus(pp->bridge->bus); 1506 + pci_unlock_rescan_remove(); 1507 + } else { 1508 + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", 1509 + status); 1510 + } 1511 + 1512 + return IRQ_HANDLED; 1513 + } 1514 + 1546 1515 static int qcom_pcie_probe(struct platform_device *pdev) 1547 1516 { 1548 1517 const struct qcom_pcie_cfg *pcie_cfg; ··· 1576 1499 struct dw_pcie_rp *pp; 1577 1500 struct resource *res; 1578 1501 struct dw_pcie *pci; 1579 - int ret; 1502 + int ret, irq; 1503 + char *name; 1580 1504 1581 1505 pcie_cfg = of_device_get_match_data(dev); 1582 1506 if (!pcie_cfg || !pcie_cfg->ops) { ··· 1698 1620 goto err_phy_exit; 1699 1621 } 1700 1622 1623 + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d", 1624 + pci_domain_nr(pp->bridge->bus)); 1625 + if (!name) { 1626 + ret = -ENOMEM; 1627 + goto err_host_deinit; 1628 + } 1629 + 1630 + irq = platform_get_irq_byname_optional(pdev, "global"); 1631 + if (irq > 0) { 1632 + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1633 + qcom_pcie_global_irq_thread, 1634 + IRQF_ONESHOT, name, pcie); 1635 + if (ret) { 1636 + dev_err_probe(&pdev->dev, ret, 1637 + "Failed to request Global IRQ\n"); 1638 + goto err_host_deinit; 1639 + } 1640 + 1641 + writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); 1642 + } 1643 + 1701 1644 qcom_pcie_icc_opp_update(pcie); 1702 1645 1703 1646 if (pcie->mhi) ··· 1726 1627 1727 1628 return 0; 1728 1629 1630 + err_host_deinit: 1631 + dw_pcie_host_deinit(pp); 1729 1632 err_phy_exit: 1730 1633 phy_exit(pcie->phy); 1731 1634 err_pm_runtime_put:
+9 -4
drivers/pci/controller/dwc/pcie-rcar-gen4.c
··· 141 141 } 142 142 143 143 /* 144 - * Require direct speed change with retrying here if the link_gen is 145 - * PCIe Gen2 or higher. 144 + * Require direct speed change with retrying here if the max_link_speed 145 + * is PCIe Gen2 or higher. 146 146 */ 147 - changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1; 147 + changes = min_not_zero(dw->max_link_speed, RCAR_MAX_LINK_SPEED) - 1; 148 148 149 149 /* 150 150 * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained. ··· 606 606 static int rcar_gen4_pcie_download_phy_firmware(struct rcar_gen4_pcie *rcar) 607 607 { 608 608 /* The check_addr values are magical numbers in the datasheet */ 609 - const u32 check_addr[] = { 0x00101018, 0x00101118, 0x00101021, 0x00101121}; 609 + static const u32 check_addr[] = { 610 + 0x00101018, 611 + 0x00101118, 612 + 0x00101021, 613 + 0x00101121, 614 + }; 610 615 struct dw_pcie *dw = &rcar->dw; 611 616 const struct firmware *fw; 612 617 unsigned int i, timeout;
+1 -1
drivers/pci/controller/dwc/pcie-spear13xx.c
··· 233 233 } 234 234 235 235 if (of_property_read_bool(np, "st,pcie-is-gen1")) 236 - pci->link_gen = 1; 236 + pci->max_link_speed = 1; 237 237 238 238 platform_set_drvdata(pdev, spear13xx_pcie); 239 239
+16 -21
drivers/pci/controller/dwc/pcie-tegra194.c
··· 177 177 #define N_FTS_VAL 52 178 178 #define FTS_VAL 52 179 179 180 - #define GEN3_EQ_CONTROL_OFF 0x8a8 181 - #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT 8 182 - #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8) 183 - #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) 184 - 185 180 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0 186 - #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3 187 - #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0) 188 - #define AMBA_ERROR_RESPONSE_CRS_OKAY 0 189 - #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1 190 - #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2 181 + #define AMBA_ERROR_RESPONSE_RRS_SHIFT 3 182 + #define AMBA_ERROR_RESPONSE_RRS_MASK GENMASK(1, 0) 183 + #define AMBA_ERROR_RESPONSE_RRS_OKAY 0 184 + #define AMBA_ERROR_RESPONSE_RRS_OKAY_FFFFFFFF 1 185 + #define AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 2 191 186 192 187 #define MSIX_ADDR_MATCH_LOW_OFF 0x940 193 188 #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0) ··· 856 861 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 857 862 858 863 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 859 - val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; 860 - val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); 861 - val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; 864 + val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC; 865 + val |= FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, 0x3ff); 866 + val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE; 862 867 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); 863 868 864 869 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); ··· 867 872 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 868 873 869 874 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 870 - val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; 871 - val |= (pcie->of_data->gen4_preset_vec << 872 - GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); 873 - val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; 875 + val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC; 876 + val |= FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, 877 + pcie->of_data->gen4_preset_vec); 878 + val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE; 874 879 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); 875 880 876 881 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); ··· 902 907 903 908 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 904 909 905 - /* Enable as 0xFFFF0001 response for CRS */ 910 + /* Enable as 0xFFFF0001 response for RRS */ 906 911 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); 907 - val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT); 908 - val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 << 909 - AMBA_ERROR_RESPONSE_CRS_SHIFT); 912 + val &= ~(AMBA_ERROR_RESPONSE_RRS_MASK << AMBA_ERROR_RESPONSE_RRS_SHIFT); 913 + val |= (AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 << 914 + AMBA_ERROR_RESPONSE_RRS_SHIFT); 910 915 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); 911 916 912 917 /* Clear Slot Clock Configuration bit if SRNS configuration */
+2 -9
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
··· 360 360 }; 361 361 362 362 static struct msi_domain_info mobiveil_msi_domain_info = { 363 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 364 - MSI_FLAG_PCI_MSIX), 363 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 364 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX, 365 365 .chip = &mobiveil_msi_irq_chip, 366 366 }; 367 367 ··· 378 378 (int)data->hwirq, msg->address_hi, msg->address_lo); 379 379 } 380 380 381 - static int mobiveil_msi_set_affinity(struct irq_data *irq_data, 382 - const struct cpumask *mask, bool force) 383 - { 384 - return -EINVAL; 385 - } 386 - 387 381 static struct irq_chip mobiveil_msi_bottom_irq_chip = { 388 382 .name = "Mobiveil MSI", 389 383 .irq_compose_msi_msg = mobiveil_compose_msi_msg, 390 - .irq_set_affinity = mobiveil_msi_set_affinity, 391 384 }; 392 385 393 386 static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
+34 -40
drivers/pci/controller/pci-aardvark.c
··· 50 50 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) 51 51 #define PIO_COMPLETION_STATUS_OK 0 52 52 #define PIO_COMPLETION_STATUS_UR 1 53 - #define PIO_COMPLETION_STATUS_CRS 2 53 + #define PIO_COMPLETION_STATUS_RRS 2 54 54 #define PIO_COMPLETION_STATUS_CA 4 55 55 #define PIO_NON_POSTED_REQ BIT(10) 56 56 #define PIO_ERR_STATUS BIT(11) ··· 262 262 263 263 #define MSI_IRQ_NUM 32 264 264 265 - #define CFG_RD_CRS_VAL 0xffff0001 265 + #define CFG_RD_RRS_VAL 0xffff0001 266 266 267 267 struct advk_pcie { 268 268 struct platform_device *pdev; ··· 649 649 advk_pcie_train_link(pcie); 650 650 } 651 651 652 - static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) 652 + static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_rrs, u32 *val) 653 653 { 654 654 struct device *dev = &pcie->pdev->dev; 655 655 u32 reg; ··· 669 669 * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only 670 670 * means a PIO write error, and for PIO read it is successful with 671 671 * a read value of 0xFFFFFFFF. 672 - * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7) 672 + * 3) value Config Request Retry Status(RRS) of COMPLETION_STATUS(bit9:7) 673 673 * only means a PIO write error, and for PIO read it is successful 674 674 * with a read value of 0xFFFF0001. 675 675 * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means ··· 694 694 strcomp_status = "UR"; 695 695 ret = -EOPNOTSUPP; 696 696 break; 697 - case PIO_COMPLETION_STATUS_CRS: 698 - if (allow_crs && val) { 699 - /* PCIe r4.0, sec 2.3.2, says: 700 - * If CRS Software Visibility is enabled: 697 + case PIO_COMPLETION_STATUS_RRS: 698 + if (allow_rrs && val) { 699 + /* PCIe r6.0, sec 2.3.2, says: 700 + * If Configuration RRS Software Visibility is enabled: 701 701 * For a Configuration Read Request that includes both 702 702 * bytes of the Vendor ID field of a device Function's 703 703 * Configuration Space Header, the Root Complex must ··· 706 706 * all '1's for any additional bytes included in the 707 707 * request. 708 708 * 709 - * So CRS in this case is not an error status. 709 + * So RRS in this case is not an error status. 710 710 */ 711 - *val = CFG_RD_CRS_VAL; 711 + *val = CFG_RD_RRS_VAL; 712 712 strcomp_status = NULL; 713 713 ret = 0; 714 714 break; 715 715 } 716 - /* PCIe r4.0, sec 2.3.2, says: 717 - * If CRS Software Visibility is not enabled, the Root Complex 716 + /* PCIe r6.0, sec 2.3.2, says: 717 + * If RRS Software Visibility is not enabled, the Root Complex 718 718 * must re-issue the Configuration Request as a new Request. 719 - * If CRS Software Visibility is enabled: For a Configuration 719 + * If RRS Software Visibility is enabled: For a Configuration 720 720 * Write Request or for any other Configuration Read Request, 721 721 * the Root Complex must re-issue the Configuration Request as 722 722 * a new Request. 723 723 * A Root Complex implementation may choose to limit the number 724 - * of Configuration Request/CRS Completion Status loops before 724 + * of Configuration Request/RRS Completion Status loops before 725 725 * determining that something is wrong with the target of the 726 726 * Request and taking appropriate action, e.g., complete the 727 727 * Request to the host as a failed transaction. ··· 729 729 * So return -EAGAIN and caller (pci-aardvark.c driver) will 730 730 * re-issue request again up to the PIO_RETRY_CNT retries. 731 731 */ 732 - strcomp_status = "CRS"; 732 + strcomp_status = "RRS"; 733 733 ret = -EAGAIN; 734 734 break; 735 735 case PIO_COMPLETION_STATUS_CA: ··· 920 920 921 921 case PCI_EXP_RTCTL: { 922 922 u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); 923 - /* Only emulation of PMEIE and CRSSVE bits is provided */ 924 - rootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_CRSSVE; 923 + /* Only emulation of PMEIE and RRS_SVE bits is provided */ 924 + rootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_RRS_SVE; 925 925 bridge->pcie_conf.rootctl = cpu_to_le16(rootctl); 926 926 break; 927 927 } ··· 1075 1075 bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); 1076 1076 1077 1077 /* Indicates supports for Completion Retry Status */ 1078 - bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); 1078 + bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_RRS_SV); 1079 1079 1080 1080 bridge->subsystem_vendor_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) & 0xffff; 1081 1081 bridge->subsystem_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) >> 16; ··· 1141 1141 { 1142 1142 struct advk_pcie *pcie = bus->sysdata; 1143 1143 int retry_count; 1144 - bool allow_crs; 1144 + bool allow_rrs; 1145 1145 u32 reg; 1146 1146 int ret; 1147 1147 ··· 1153 1153 size, val); 1154 1154 1155 1155 /* 1156 - * Completion Retry Status is possible to return only when reading all 1157 - * 4 bytes from PCI_VENDOR_ID and PCI_DEVICE_ID registers at once and 1158 - * CRSSVE flag on Root Bridge is enabled. 1156 + * Configuration Request Retry Status (RRS) is possible to return 1157 + * only when reading both bytes from PCI_VENDOR_ID at once and 1158 + * RRS_SVE flag on Root Port is enabled. 1159 1159 */ 1160 - allow_crs = (where == PCI_VENDOR_ID) && (size == 4) && 1160 + allow_rrs = (where == PCI_VENDOR_ID) && (size >= 2) && 1161 1161 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & 1162 - PCI_EXP_RTCTL_CRSSVE); 1162 + PCI_EXP_RTCTL_RRS_SVE); 1163 1163 1164 1164 if (advk_pcie_pio_is_running(pcie)) 1165 - goto try_crs; 1165 + goto try_rrs; 1166 1166 1167 1167 /* Program the control register */ 1168 1168 reg = advk_readl(pcie, PIO_CTRL); ··· 1189 1189 1190 1190 ret = advk_pcie_wait_pio(pcie); 1191 1191 if (ret < 0) 1192 - goto try_crs; 1192 + goto try_rrs; 1193 1193 1194 1194 retry_count += ret; 1195 1195 1196 1196 /* Check PIO status and get the read result */ 1197 - ret = advk_pcie_check_pio_status(pcie, allow_crs, val); 1197 + ret = advk_pcie_check_pio_status(pcie, allow_rrs, val); 1198 1198 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); 1199 1199 1200 1200 if (ret < 0) ··· 1207 1207 1208 1208 return PCIBIOS_SUCCESSFUL; 1209 1209 1210 - try_crs: 1210 + try_rrs: 1211 1211 /* 1212 - * If it is possible, return Completion Retry Status so that caller 1213 - * tries to issue the request again instead of failing. 1212 + * If it is possible, return Configuration Request Retry Status so 1213 + * that caller tries to issue the request again instead of failing. 1214 1214 */ 1215 - if (allow_crs) { 1216 - *val = CFG_RD_CRS_VAL; 1215 + if (allow_rrs) { 1216 + *val = CFG_RD_RRS_VAL; 1217 1217 return PCIBIOS_SUCCESSFUL; 1218 1218 } 1219 1219 ··· 1304 1304 msg->data = data->hwirq; 1305 1305 } 1306 1306 1307 - static int advk_msi_set_affinity(struct irq_data *irq_data, 1308 - const struct cpumask *mask, bool force) 1309 - { 1310 - return -EINVAL; 1311 - } 1312 - 1313 1307 static void advk_msi_irq_mask(struct irq_data *d) 1314 1308 { 1315 1309 struct advk_pcie *pcie = d->domain->host_data; ··· 1347 1353 static struct irq_chip advk_msi_bottom_irq_chip = { 1348 1354 .name = "MSI", 1349 1355 .irq_compose_msi_msg = advk_msi_irq_compose_msi_msg, 1350 - .irq_set_affinity = advk_msi_set_affinity, 1351 1356 .irq_mask = advk_msi_irq_mask, 1352 1357 .irq_unmask = advk_msi_irq_unmask, 1353 1358 }; ··· 1444 1451 1445 1452 static struct msi_domain_info advk_msi_domain_info = { 1446 1453 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 1447 - MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, 1454 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI | 1455 + MSI_FLAG_PCI_MSIX, 1448 1456 .chip = &advk_msi_irq_chip, 1449 1457 }; 1450 1458
+2 -8
drivers/pci/controller/pci-tegra.c
··· 1629 1629 spin_unlock_irqrestore(&msi->mask_lock, flags); 1630 1630 } 1631 1631 1632 - static int tegra_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force) 1633 - { 1634 - return -EINVAL; 1635 - } 1636 - 1637 1632 static void tegra_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 1638 1633 { 1639 1634 struct tegra_msi *msi = irq_data_get_irq_chip_data(data); ··· 1643 1648 .irq_ack = tegra_msi_irq_ack, 1644 1649 .irq_mask = tegra_msi_irq_mask, 1645 1650 .irq_unmask = tegra_msi_irq_unmask, 1646 - .irq_set_affinity = tegra_msi_set_affinity, 1647 1651 .irq_compose_msi_msg = tegra_compose_msi_msg, 1648 1652 }; 1649 1653 ··· 1691 1697 }; 1692 1698 1693 1699 static struct msi_domain_info tegra_msi_info = { 1694 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 1695 - MSI_FLAG_PCI_MSIX), 1700 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 1701 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX, 1696 1702 .chip = &tegra_msi_top_chip, 1697 1703 }; 1698 1704
+3 -3
drivers/pci/controller/pci-xgene.c
··· 171 171 172 172 /* 173 173 * The v1 controller has a bug in its Configuration Request Retry 174 - * Status (CRS) logic: when CRS Software Visibility is enabled and 174 + * Status (RRS) logic: when RRS Software Visibility is enabled and 175 175 * we read the Vendor and Device ID of a non-existent device, the 176 176 * controller fabricates return data of 0xFFFF0001 ("device exists 177 177 * but is not ready") instead of 0xFFFFFFFF (PCI_ERROR_RESPONSE) 178 178 * ("device does not exist"). This causes the PCI core to retry 179 179 * the read until it times out. Avoid this by not claiming to 180 - * support CRS SV. 180 + * support RRS SV. 181 181 */ 182 182 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && 183 183 ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL)) 184 - *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); 184 + *val &= ~(PCI_EXP_RTCAP_RRS_SV << 16); 185 185 186 186 if (size <= 2) 187 187 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
+2 -9
drivers/pci/controller/pcie-altera-msi.c
··· 81 81 }; 82 82 83 83 static struct msi_domain_info altera_msi_domain_info = { 84 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 85 - MSI_FLAG_PCI_MSIX), 84 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 85 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX, 86 86 .chip = &altera_msi_irq_chip, 87 87 }; 88 88 ··· 99 99 (int)data->hwirq, msg->address_hi, msg->address_lo); 100 100 } 101 101 102 - static int altera_msi_set_affinity(struct irq_data *irq_data, 103 - const struct cpumask *mask, bool force) 104 - { 105 - return -EINVAL; 106 - } 107 - 108 102 static struct irq_chip altera_msi_bottom_irq_chip = { 109 103 .name = "Altera MSI", 110 104 .irq_compose_msi_msg = altera_compose_msi_msg, 111 - .irq_set_affinity = altera_msi_set_affinity, 112 105 }; 113 106 114 107 static int altera_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+1 -2
drivers/pci/controller/pcie-altera.c
··· 55 55 #define TLP_READ_TAG 0x1d 56 56 #define TLP_WRITE_TAG 0x10 57 57 #define RP_DEVFN 0 58 - #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) 59 58 #define TLP_CFG_DW0(pcie, cfg) \ 60 59 (((cfg) << 24) | \ 61 60 TLP_PAYLOAD_SIZE) 62 61 #define TLP_CFG_DW1(pcie, tag, be) \ 63 - (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be)) 62 + (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be)) 64 63 #define TLP_CFG_DW2(bus, devfn, offset) \ 65 64 (((bus) << 24) | ((devfn) << 16) | (offset)) 66 65 #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
+420 -182
drivers/pci/controller/pcie-brcmstb.c
··· 75 75 #define PCIE_MEM_WIN0_HI(win) \ 76 76 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8) 77 77 78 + /* 79 + * NOTE: You may see the term "BAR" in a number of register names used by 80 + * this driver. The term is an artifact of when the HW core was an 81 + * endpoint device (EP). Now it is a root complex (RC) and anywhere a 82 + * register has the term "BAR" it is related to an inbound window. 83 + */ 84 + 85 + #define PCIE_BRCM_MAX_INBOUND_WINS 16 78 86 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c 79 87 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f 80 88 81 - #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 82 - #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f 83 - #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 89 + #define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4 84 90 85 - #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c 86 - #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f 87 91 88 92 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044 89 93 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048 ··· 126 122 #define PCIE_MEM_WIN0_LIMIT_HI(win) \ 127 123 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) 128 124 129 - #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 130 125 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 131 126 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000 132 127 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 ··· 134 131 (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ 135 132 PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) 136 133 137 - #define PCIE_INTR2_CPU_BASE 0x4300 134 + #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac 135 + #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK BIT(0) 136 + #define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP 0x410c 137 + 138 138 #define PCIE_MSI_INTR2_BASE 0x4500 139 - /* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */ 139 + 140 + /* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */ 140 141 #define MSI_INT_STATUS 0x0 141 142 #define MSI_INT_CLR 0x8 142 143 #define MSI_INT_MASK_SET 0x10 ··· 191 184 #define SSC_STATUS_PLL_LOCK_MASK 0x800 192 185 #define PCIE_BRCM_MAX_MEMC 3 193 186 194 - #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) 195 - #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) 196 - #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) 187 + #define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX]) 188 + #define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA]) 189 + #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1]) 190 + #define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG]) 191 + #define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE]) 197 192 198 193 /* Rescal registers */ 199 194 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700 ··· 214 205 RGR1_SW_INIT_1, 215 206 EXT_CFG_INDEX, 216 207 EXT_CFG_DATA, 208 + PCIE_HARD_DEBUG, 209 + PCIE_INTR2_CPU_BASE, 217 210 }; 218 211 219 - enum { 220 - RGR1_SW_INIT_1_INIT_MASK, 221 - RGR1_SW_INIT_1_INIT_SHIFT, 222 - }; 223 - 224 - enum pcie_type { 212 + enum pcie_soc_base { 225 213 GENERIC, 226 - BCM7425, 227 - BCM7435, 214 + BCM2711, 228 215 BCM4908, 229 216 BCM7278, 230 - BCM2711, 217 + BCM7425, 218 + BCM7435, 219 + BCM7712, 220 + }; 221 + 222 + struct inbound_win { 223 + u64 size; 224 + u64 pci_offset; 225 + u64 cpu_addr; 231 226 }; 232 227 233 228 struct pcie_cfg_data { 234 229 const int *offsets; 235 - const enum pcie_type type; 236 - void (*perst_set)(struct brcm_pcie *pcie, u32 val); 237 - void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); 230 + const enum pcie_soc_base soc_base; 231 + const bool has_phy; 232 + u8 num_inbound_wins; 233 + int (*perst_set)(struct brcm_pcie *pcie, u32 val); 234 + int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); 238 235 }; 239 236 240 237 struct subdev_regulators { ··· 277 262 u64 msi_target_addr; 278 263 struct brcm_msi *msi; 279 264 const int *reg_offsets; 280 - enum pcie_type type; 265 + enum pcie_soc_base soc_base; 281 266 struct reset_control *rescal; 282 267 struct reset_control *perst_reset; 268 + struct reset_control *bridge_reset; 269 + struct reset_control *swinit_reset; 283 270 int num_memc; 284 271 u64 memc_size[PCIE_BRCM_MAX_MEMC]; 285 272 u32 hw_rev; 286 - void (*perst_set)(struct brcm_pcie *pcie, u32 val); 287 - void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); 273 + int (*perst_set)(struct brcm_pcie *pcie, u32 val); 274 + int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); 288 275 struct subdev_regulators *sr; 289 276 bool ep_wakeup_capable; 277 + bool has_phy; 278 + u8 num_inbound_wins; 290 279 }; 291 280 292 281 static inline bool is_bmips(const struct brcm_pcie *pcie) 293 282 { 294 - return pcie->type == BCM7435 || pcie->type == BCM7425; 283 + return pcie->soc_base == BCM7435 || pcie->soc_base == BCM7425; 295 284 } 296 285 297 286 /* ··· 413 394 } 414 395 415 396 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, 416 - unsigned int win, u64 cpu_addr, 397 + u8 win, u64 cpu_addr, 417 398 u64 pcie_addr, u64 size) 418 399 { 419 400 u32 cpu_addr_mb_high, limit_addr_mb_high; ··· 464 445 }; 465 446 466 447 static struct msi_domain_info brcm_msi_domain_info = { 467 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 468 - MSI_FLAG_MULTI_PCI_MSI), 448 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 449 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI, 469 450 .chip = &brcm_msi_irq_chip, 470 451 }; 471 452 ··· 503 484 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; 504 485 } 505 486 506 - static int brcm_msi_set_affinity(struct irq_data *irq_data, 507 - const struct cpumask *mask, bool force) 508 - { 509 - return -EINVAL; 510 - } 511 - 512 487 static void brcm_msi_ack_irq(struct irq_data *data) 513 488 { 514 489 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); ··· 515 502 static struct irq_chip brcm_msi_bottom_irq_chip = { 516 503 .name = "BRCM STB MSI", 517 504 .irq_compose_msi_msg = brcm_msi_compose_msi_msg, 518 - .irq_set_affinity = brcm_msi_set_affinity, 519 505 .irq_ack = brcm_msi_ack_irq, 520 506 }; 521 507 ··· 661 649 BUILD_BUG_ON(BRCM_INT_PCI_MSI_LEGACY_NR > BRCM_INT_PCI_MSI_NR); 662 650 663 651 if (msi->legacy) { 664 - msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE; 652 + msi->intr_base = msi->base + INTR2_CPU_BASE(pcie); 665 653 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; 666 654 msi->legacy_shift = 24; 667 655 } else { ··· 742 730 return base + DATA_ADDR(pcie); 743 731 } 744 732 745 - static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) 733 + static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) 746 734 { 747 - u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; 735 + u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; 748 736 u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; 737 + int ret = 0; 738 + 739 + if (pcie->bridge_reset) { 740 + if (val) 741 + ret = reset_control_assert(pcie->bridge_reset); 742 + else 743 + ret = reset_control_deassert(pcie->bridge_reset); 744 + 745 + if (ret) 746 + dev_err(pcie->dev, "failed to %s 'bridge' reset, err=%d\n", 747 + val ? "assert" : "deassert", ret); 748 + 749 + return ret; 750 + } 749 751 750 752 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 751 753 tmp = (tmp & ~mask) | ((val << shift) & mask); 752 754 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 755 + 756 + return ret; 753 757 } 754 758 755 - static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) 759 + static int brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) 756 760 { 757 761 u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK; 758 762 u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT; ··· 776 748 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 777 749 tmp = (tmp & ~mask) | ((val << shift) & mask); 778 750 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 751 + 752 + return 0; 779 753 } 780 754 781 - static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) 755 + static int brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) 782 756 { 757 + int ret; 758 + 783 759 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) 784 - return; 760 + return -EINVAL; 785 761 786 762 if (val) 787 - reset_control_assert(pcie->perst_reset); 763 + ret = reset_control_assert(pcie->perst_reset); 788 764 else 789 - reset_control_deassert(pcie->perst_reset); 765 + ret = reset_control_deassert(pcie->perst_reset); 766 + 767 + if (ret) 768 + dev_err(pcie->dev, "failed to %s 'perst' reset, err=%d\n", 769 + val ? "assert" : "deassert", ret); 770 + return ret; 790 771 } 791 772 792 - static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) 773 + static int brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) 793 774 { 794 775 u32 tmp; 795 776 ··· 806 769 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); 807 770 u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK); 808 771 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); 772 + 773 + return 0; 809 774 } 810 775 811 - static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) 776 + static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) 812 777 { 813 778 u32 tmp; 814 779 815 780 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 816 781 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); 817 782 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); 783 + 784 + return 0; 818 785 } 819 786 820 - static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, 821 - u64 *rc_bar2_size, 822 - u64 *rc_bar2_offset) 787 + static void add_inbound_win(struct inbound_win *b, u8 *count, u64 size, 788 + u64 cpu_addr, u64 pci_offset) 789 + { 790 + b->size = size; 791 + b->cpu_addr = cpu_addr; 792 + b->pci_offset = pci_offset; 793 + (*count)++; 794 + } 795 + 796 + static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, 797 + struct inbound_win inbound_wins[]) 823 798 { 824 799 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 800 + u64 pci_offset, cpu_addr, size = 0, tot_size = 0; 825 801 struct resource_entry *entry; 826 802 struct device *dev = pcie->dev; 827 803 u64 lowest_pcie_addr = ~(u64)0; 828 804 int ret, i = 0; 829 - u64 size = 0; 805 + u8 n = 0; 806 + 807 + /* 808 + * The HW registers (and PCIe) use order-1 numbering for BARs. As such, 809 + * we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1]. 810 + */ 811 + struct inbound_win *b_begin = &inbound_wins[1]; 812 + struct inbound_win *b = b_begin; 813 + 814 + /* 815 + * STB chips beside 7712 disable the first inbound window default. 816 + * Rather being mapped to system memory it is mapped to the 817 + * internal registers of the SoC. This feature is deprecated, has 818 + * security considerations, and is not implemented in our modern 819 + * SoCs. 820 + */ 821 + if (pcie->soc_base != BCM7712) 822 + add_inbound_win(b++, &n, 0, 0, 0); 830 823 831 824 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 832 - u64 pcie_beg = entry->res->start - entry->offset; 825 + u64 pcie_start = entry->res->start - entry->offset; 826 + u64 cpu_start = entry->res->start; 833 827 834 - size += entry->res->end - entry->res->start + 1; 835 - if (pcie_beg < lowest_pcie_addr) 836 - lowest_pcie_addr = pcie_beg; 828 + size = resource_size(entry->res); 829 + tot_size += size; 830 + if (pcie_start < lowest_pcie_addr) 831 + lowest_pcie_addr = pcie_start; 832 + /* 833 + * 7712 and newer chips may have many BARs, with each 834 + * offering a non-overlapping viewport to system memory. 835 + * That being said, each BARs size must still be a power of 836 + * two. 837 + */ 838 + if (pcie->soc_base == BCM7712) 839 + add_inbound_win(b++, &n, size, cpu_start, pcie_start); 840 + 841 + if (n > pcie->num_inbound_wins) 842 + break; 837 843 } 838 844 839 845 if (lowest_pcie_addr == ~(u64)0) { ··· 884 804 return -EINVAL; 885 805 } 886 806 807 + /* 808 + * 7712 and newer chips do not have an internal memory mapping system 809 + * that enables multiple memory controllers. As such, it can return 810 + * now w/o doing special configuration. 811 + */ 812 + if (pcie->soc_base == BCM7712) 813 + return n; 814 + 887 815 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, 888 816 PCIE_BRCM_MAX_MEMC); 889 - 890 817 if (ret <= 0) { 891 818 /* Make an educated guess */ 892 819 pcie->num_memc = 1; 893 - pcie->memc_size[0] = 1ULL << fls64(size - 1); 820 + pcie->memc_size[0] = 1ULL << fls64(tot_size - 1); 894 821 } else { 895 822 pcie->num_memc = ret; 896 823 } ··· 906 819 for (i = 0, size = 0; i < pcie->num_memc; i++) 907 820 size += pcie->memc_size[i]; 908 821 909 - /* System memory starts at this address in PCIe-space */ 910 - *rc_bar2_offset = lowest_pcie_addr; 911 - /* The sum of all memc views must also be a power of 2 */ 912 - *rc_bar2_size = 1ULL << fls64(size - 1); 822 + /* Our HW mandates that the window size must be a power of 2 */ 823 + size = 1ULL << fls64(size - 1); 824 + 825 + /* 826 + * For STB chips, the BAR2 cpu_addr is hardwired to the start 827 + * of system memory, so we set it to 0. 828 + */ 829 + cpu_addr = 0; 830 + pci_offset = lowest_pcie_addr; 913 831 914 832 /* 915 833 * We validate the inbound memory view even though we should trust ··· 949 857 * outbound memory @ 3GB). So instead it will start at the 1x 950 858 * multiple of its size 951 859 */ 952 - if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || 953 - (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) { 954 - dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n", 955 - *rc_bar2_size, *rc_bar2_offset); 860 + if (!size || (pci_offset & (size - 1)) || 861 + (pci_offset < SZ_4G && pci_offset > SZ_2G)) { 862 + dev_err(dev, "Invalid inbound_win2_offset/size: size 0x%llx, off 0x%llx\n", 863 + size, pci_offset); 956 864 return -EINVAL; 957 865 } 958 866 959 - return 0; 867 + /* Enable inbound window 2, the main inbound window for STB chips */ 868 + add_inbound_win(b++, &n, size, cpu_addr, pci_offset); 869 + 870 + /* 871 + * Disable inbound window 3. On some chips presents the same 872 + * window as #2 but the data appears in a settable endianness. 873 + */ 874 + add_inbound_win(b++, &n, 0, 0, 0); 875 + 876 + return n; 877 + } 878 + 879 + static u32 brcm_bar_reg_offset(int bar) 880 + { 881 + if (bar <= 3) 882 + return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); 883 + else 884 + return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); 885 + } 886 + 887 + static u32 brcm_ubus_reg_offset(int bar) 888 + { 889 + if (bar <= 3) 890 + return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); 891 + else 892 + return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 4); 893 + } 894 + 895 + static void set_inbound_win_registers(struct brcm_pcie *pcie, 896 + const struct inbound_win *inbound_wins, 897 + u8 num_inbound_wins) 898 + { 899 + void __iomem *base = pcie->base; 900 + int i; 901 + 902 + for (i = 1; i <= num_inbound_wins; i++) { 903 + u64 pci_offset = inbound_wins[i].pci_offset; 904 + u64 cpu_addr = inbound_wins[i].cpu_addr; 905 + u64 size = inbound_wins[i].size; 906 + u32 reg_offset = brcm_bar_reg_offset(i); 907 + u32 tmp = lower_32_bits(pci_offset); 908 + 909 + u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(size), 910 + PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK); 911 + 912 + /* Write low */ 913 + writel_relaxed(tmp, base + reg_offset); 914 + /* Write high */ 915 + writel_relaxed(upper_32_bits(pci_offset), base + reg_offset + 4); 916 + 917 + /* 918 + * Most STB chips: 919 + * Do nothing. 920 + * 7712: 921 + * All of their BARs need to be set. 922 + */ 923 + if (pcie->soc_base == BCM7712) { 924 + /* BUS remap register settings */ 925 + reg_offset = brcm_ubus_reg_offset(i); 926 + tmp = lower_32_bits(cpu_addr) & ~0xfff; 927 + tmp |= PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK; 928 + writel_relaxed(tmp, base + reg_offset); 929 + tmp = upper_32_bits(cpu_addr); 930 + writel_relaxed(tmp, base + reg_offset + 4); 931 + } 932 + } 960 933 } 961 934 962 935 static int brcm_pcie_setup(struct brcm_pcie *pcie) 963 936 { 964 - u64 rc_bar2_offset, rc_bar2_size; 937 + struct inbound_win inbound_wins[PCIE_BRCM_MAX_INBOUND_WINS]; 965 938 void __iomem *base = pcie->base; 966 939 struct pci_host_bridge *bridge; 967 940 struct resource_entry *entry; 968 941 u32 tmp, burst, aspm_support; 969 - int num_out_wins = 0; 970 - int ret, memc; 942 + u8 num_out_wins = 0; 943 + int num_inbound_wins = 0; 944 + int memc, ret; 971 945 972 946 /* Reset the bridge */ 973 - pcie->bridge_sw_init_set(pcie, 1); 947 + ret = pcie->bridge_sw_init_set(pcie, 1); 948 + if (ret) 949 + return ret; 974 950 975 951 /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ 976 - if (pcie->type == BCM2711) 977 - pcie->perst_set(pcie, 1); 952 + if (pcie->soc_base == BCM2711) { 953 + ret = pcie->perst_set(pcie, 1); 954 + if (ret) { 955 + pcie->bridge_sw_init_set(pcie, 0); 956 + return ret; 957 + } 958 + } 978 959 979 960 usleep_range(100, 200); 980 961 981 962 /* Take the bridge out of reset */ 982 - pcie->bridge_sw_init_set(pcie, 0); 963 + ret = pcie->bridge_sw_init_set(pcie, 0); 964 + if (ret) 965 + return ret; 983 966 984 - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 967 + tmp = readl(base + HARD_DEBUG(pcie)); 985 968 if (is_bmips(pcie)) 986 969 tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; 987 970 else 988 971 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; 989 - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 972 + writel(tmp, base + HARD_DEBUG(pcie)); 990 973 /* Wait for SerDes to be stable */ 991 974 usleep_range(100, 200); 992 975 ··· 1072 905 */ 1073 906 if (is_bmips(pcie)) 1074 907 burst = 0x1; /* 256 bytes */ 1075 - else if (pcie->type == BCM2711) 908 + else if (pcie->soc_base == BCM2711) 1076 909 burst = 0x0; /* 128 bytes */ 1077 - else if (pcie->type == BCM7278) 910 + else if (pcie->soc_base == BCM7278) 1078 911 burst = 0x3; /* 512 bytes */ 1079 912 else 1080 913 burst = 0x2; /* 512 bytes */ ··· 1091 924 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK); 1092 925 writel(tmp, base + PCIE_MISC_MISC_CTRL); 1093 926 1094 - ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, 1095 - &rc_bar2_offset); 1096 - if (ret) 1097 - return ret; 927 + num_inbound_wins = brcm_pcie_get_inbound_wins(pcie, inbound_wins); 928 + if (num_inbound_wins < 0) 929 + return num_inbound_wins; 1098 930 1099 - tmp = lower_32_bits(rc_bar2_offset); 1100 - u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), 1101 - PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK); 1102 - writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); 1103 - writel(upper_32_bits(rc_bar2_offset), 1104 - base + PCIE_MISC_RC_BAR2_CONFIG_HI); 931 + set_inbound_win_registers(pcie, inbound_wins, num_inbound_wins); 932 + 933 + if (!brcm_pcie_rc_mode(pcie)) { 934 + dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); 935 + return -EINVAL; 936 + } 1105 937 1106 938 tmp = readl(base + PCIE_MISC_MISC_CTRL); 1107 939 for (memc = 0; memc < pcie->num_memc; memc++) { ··· 1122 956 * 4GB or when the inbound area is smaller than 4GB (taking into 1123 957 * account the rounding-up we're forced to perform). 1124 958 */ 1125 - if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G) 959 + if (inbound_wins[2].pci_offset >= SZ_4G || 960 + (inbound_wins[2].size + inbound_wins[2].pci_offset) < SZ_4G) 1126 961 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; 1127 962 else 1128 963 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; 1129 964 1130 - if (!brcm_pcie_rc_mode(pcie)) { 1131 - dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); 1132 - return -EINVAL; 1133 - } 1134 - 1135 - /* disable the PCIe->GISB memory window (RC_BAR1) */ 1136 - tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO); 1137 - tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK; 1138 - writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO); 1139 - 1140 - /* disable the PCIe->SCB memory window (RC_BAR3) */ 1141 - tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO); 1142 - tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK; 1143 - writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO); 1144 965 1145 966 /* Don't advertise L0s capability if 'aspm-no-l0s' */ 1146 967 aspm_support = PCIE_LINK_STATE_L1; ··· 1178 1025 num_out_wins++; 1179 1026 } 1180 1027 1181 - /* PCIe->SCB endian mode for BAR */ 1028 + /* PCIe->SCB endian mode for inbound window */ 1182 1029 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); 1183 1030 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, 1184 1031 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); ··· 1198 1045 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; 1199 1046 u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ 1200 1047 1048 + /* 7712 does not have this (RGR1) timer */ 1049 + if (pcie->soc_base == BCM7712) 1050 + return; 1051 + 1201 1052 /* Each unit in timeout register is 1/216,000,000 seconds */ 1202 1053 writel(216 * timeout_us, pcie->base + REG_OFFSET); 1203 1054 } ··· 1220 1063 } 1221 1064 1222 1065 /* Start out assuming safe mode (both mode bits cleared) */ 1223 - clkreq_cntl = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1066 + clkreq_cntl = readl(pcie->base + HARD_DEBUG(pcie)); 1224 1067 clkreq_cntl &= ~PCIE_CLKREQ_MASK; 1225 1068 1226 1069 if (strcmp(mode, "no-l1ss") == 0) { ··· 1263 1106 dev_err(pcie->dev, err_msg); 1264 1107 mode = "safe"; 1265 1108 } 1266 - writel(clkreq_cntl, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1109 + writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie)); 1267 1110 1268 1111 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); 1269 1112 } ··· 1277 1120 int ret, i; 1278 1121 1279 1122 /* Unassert the fundamental reset */ 1280 - pcie->perst_set(pcie, 0); 1123 + ret = pcie->perst_set(pcie, 0); 1124 + if (ret) 1125 + return ret; 1281 1126 1282 1127 /* 1283 1128 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification ··· 1463 1304 1464 1305 static inline int brcm_phy_start(struct brcm_pcie *pcie) 1465 1306 { 1466 - return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; 1307 + return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0; 1467 1308 } 1468 1309 1469 1310 static inline int brcm_phy_stop(struct brcm_pcie *pcie) 1470 1311 { 1471 - return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; 1312 + return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; 1472 1313 } 1473 1314 1474 - static void brcm_pcie_turn_off(struct brcm_pcie *pcie) 1315 + static int brcm_pcie_turn_off(struct brcm_pcie *pcie) 1475 1316 { 1476 1317 void __iomem *base = pcie->base; 1477 - int tmp; 1318 + int tmp, ret; 1478 1319 1479 1320 if (brcm_pcie_link_up(pcie)) 1480 1321 brcm_pcie_enter_l23(pcie); 1481 1322 /* Assert fundamental reset */ 1482 - pcie->perst_set(pcie, 1); 1323 + ret = pcie->perst_set(pcie, 1); 1324 + if (ret) 1325 + return ret; 1483 1326 1484 1327 /* Deassert request for L23 in case it was asserted */ 1485 1328 tmp = readl(base + PCIE_MISC_PCIE_CTRL); ··· 1489 1328 writel(tmp, base + PCIE_MISC_PCIE_CTRL); 1490 1329 1491 1330 /* Turn off SerDes */ 1492 - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1331 + tmp = readl(base + HARD_DEBUG(pcie)); 1493 1332 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); 1494 - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1333 + writel(tmp, base + HARD_DEBUG(pcie)); 1495 1334 1496 1335 /* Shutdown PCIe bridge */ 1497 - pcie->bridge_sw_init_set(pcie, 1); 1336 + ret = pcie->bridge_sw_init_set(pcie, 1); 1337 + 1338 + return ret; 1498 1339 } 1499 1340 1500 1341 static int pci_dev_may_wakeup(struct pci_dev *dev, void *data) ··· 1514 1351 { 1515 1352 struct brcm_pcie *pcie = dev_get_drvdata(dev); 1516 1353 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1517 - int ret; 1354 + int ret, rret; 1518 1355 1519 - brcm_pcie_turn_off(pcie); 1356 + ret = brcm_pcie_turn_off(pcie); 1357 + if (ret) 1358 + return ret; 1359 + 1520 1360 /* 1521 1361 * If brcm_phy_stop() returns an error, just dev_err(). If we 1522 1362 * return the error it will cause the suspend to fail and this is a ··· 1548 1382 pcie->sr->supplies); 1549 1383 if (ret) { 1550 1384 dev_err(dev, "Could not turn off regulators\n"); 1551 - reset_control_reset(pcie->rescal); 1385 + rret = reset_control_reset(pcie->rescal); 1386 + if (rret) 1387 + dev_err(dev, "failed to reset 'rascal' controller ret=%d\n", 1388 + rret); 1552 1389 return ret; 1553 1390 } 1554 1391 } ··· 1566 1397 struct brcm_pcie *pcie = dev_get_drvdata(dev); 1567 1398 void __iomem *base; 1568 1399 u32 tmp; 1569 - int ret; 1400 + int ret, rret; 1570 1401 1571 1402 base = pcie->base; 1572 1403 ret = clk_prepare_enable(pcie->clk); ··· 1585 1416 pcie->bridge_sw_init_set(pcie, 0); 1586 1417 1587 1418 /* SERDES_IDDQ = 0 */ 1588 - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1419 + tmp = readl(base + HARD_DEBUG(pcie)); 1589 1420 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); 1590 - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 1421 + writel(tmp, base + HARD_DEBUG(pcie)); 1591 1422 1592 1423 /* wait for serdes to be stable */ 1593 1424 udelay(100); ··· 1628 1459 if (pcie->sr) 1629 1460 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); 1630 1461 err_reset: 1631 - reset_control_rearm(pcie->rescal); 1462 + rret = reset_control_rearm(pcie->rescal); 1463 + if (rret) 1464 + dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=%d\n", rret); 1632 1465 err_disable_clk: 1633 1466 clk_disable_unprepare(pcie->clk); 1634 1467 return ret; ··· 1658 1487 } 1659 1488 1660 1489 static const int pcie_offsets[] = { 1661 - [RGR1_SW_INIT_1] = 0x9210, 1662 - [EXT_CFG_INDEX] = 0x9000, 1663 - [EXT_CFG_DATA] = 0x9004, 1490 + [RGR1_SW_INIT_1] = 0x9210, 1491 + [EXT_CFG_INDEX] = 0x9000, 1492 + [EXT_CFG_DATA] = 0x9004, 1493 + [PCIE_HARD_DEBUG] = 0x4204, 1494 + [PCIE_INTR2_CPU_BASE] = 0x4300, 1664 1495 }; 1665 1496 1666 - static const int pcie_offsets_bmips_7425[] = { 1667 - [RGR1_SW_INIT_1] = 0x8010, 1668 - [EXT_CFG_INDEX] = 0x8300, 1669 - [EXT_CFG_DATA] = 0x8304, 1497 + static const int pcie_offsets_bcm7278[] = { 1498 + [RGR1_SW_INIT_1] = 0xc010, 1499 + [EXT_CFG_INDEX] = 0x9000, 1500 + [EXT_CFG_DATA] = 0x9004, 1501 + [PCIE_HARD_DEBUG] = 0x4204, 1502 + [PCIE_INTR2_CPU_BASE] = 0x4300, 1503 + }; 1504 + 1505 + static const int pcie_offsets_bcm7425[] = { 1506 + [RGR1_SW_INIT_1] = 0x8010, 1507 + [EXT_CFG_INDEX] = 0x8300, 1508 + [EXT_CFG_DATA] = 0x8304, 1509 + [PCIE_HARD_DEBUG] = 0x4204, 1510 + [PCIE_INTR2_CPU_BASE] = 0x4300, 1511 + }; 1512 + 1513 + static const int pcie_offsets_bcm7712[] = { 1514 + [EXT_CFG_INDEX] = 0x9000, 1515 + [EXT_CFG_DATA] = 0x9004, 1516 + [PCIE_HARD_DEBUG] = 0x4304, 1517 + [PCIE_INTR2_CPU_BASE] = 0x4400, 1670 1518 }; 1671 1519 1672 1520 static const struct pcie_cfg_data generic_cfg = { 1673 1521 .offsets = pcie_offsets, 1674 - .type = GENERIC, 1522 + .soc_base = GENERIC, 1675 1523 .perst_set = brcm_pcie_perst_set_generic, 1676 1524 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 1677 - }; 1678 - 1679 - static const struct pcie_cfg_data bcm7425_cfg = { 1680 - .offsets = pcie_offsets_bmips_7425, 1681 - .type = BCM7425, 1682 - .perst_set = brcm_pcie_perst_set_generic, 1683 - .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 1684 - }; 1685 - 1686 - static const struct pcie_cfg_data bcm7435_cfg = { 1687 - .offsets = pcie_offsets, 1688 - .type = BCM7435, 1689 - .perst_set = brcm_pcie_perst_set_generic, 1690 - .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 1691 - }; 1692 - 1693 - static const struct pcie_cfg_data bcm4908_cfg = { 1694 - .offsets = pcie_offsets, 1695 - .type = BCM4908, 1696 - .perst_set = brcm_pcie_perst_set_4908, 1697 - .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 1698 - }; 1699 - 1700 - static const int pcie_offset_bcm7278[] = { 1701 - [RGR1_SW_INIT_1] = 0xc010, 1702 - [EXT_CFG_INDEX] = 0x9000, 1703 - [EXT_CFG_DATA] = 0x9004, 1704 - }; 1705 - 1706 - static const struct pcie_cfg_data bcm7278_cfg = { 1707 - .offsets = pcie_offset_bcm7278, 1708 - .type = BCM7278, 1709 - .perst_set = brcm_pcie_perst_set_7278, 1710 - .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, 1525 + .num_inbound_wins = 3, 1711 1526 }; 1712 1527 1713 1528 static const struct pcie_cfg_data bcm2711_cfg = { 1714 1529 .offsets = pcie_offsets, 1715 - .type = BCM2711, 1530 + .soc_base = BCM2711, 1716 1531 .perst_set = brcm_pcie_perst_set_generic, 1717 1532 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 1533 + .num_inbound_wins = 3, 1534 + }; 1535 + 1536 + static const struct pcie_cfg_data bcm4908_cfg = { 1537 + .offsets = pcie_offsets, 1538 + .soc_base = BCM4908, 1539 + .perst_set = brcm_pcie_perst_set_4908, 1540 + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 1541 + .num_inbound_wins = 3, 1542 + }; 1543 + 1544 + static const struct pcie_cfg_data bcm7278_cfg = { 1545 + .offsets = pcie_offsets_bcm7278, 1546 + .soc_base = BCM7278, 1547 + .perst_set = brcm_pcie_perst_set_7278, 1548 + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, 1549 + .num_inbound_wins = 3, 1550 + }; 1551 + 1552 + static const struct pcie_cfg_data bcm7425_cfg = { 1553 + .offsets = pcie_offsets_bcm7425, 1554 + .soc_base = BCM7425, 1555 + .perst_set = brcm_pcie_perst_set_generic, 1556 + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 1557 + .num_inbound_wins = 3, 1558 + }; 1559 + 1560 + static const struct pcie_cfg_data bcm7435_cfg = { 1561 + .offsets = pcie_offsets, 1562 + .soc_base = BCM7435, 1563 + .perst_set = brcm_pcie_perst_set_generic, 1564 + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 1565 + .num_inbound_wins = 3, 1566 + }; 1567 + 1568 + static const struct pcie_cfg_data bcm7216_cfg = { 1569 + .offsets = pcie_offsets_bcm7278, 1570 + .soc_base = BCM7278, 1571 + .perst_set = brcm_pcie_perst_set_7278, 1572 + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, 1573 + .has_phy = true, 1574 + .num_inbound_wins = 3, 1575 + }; 1576 + 1577 + static const struct pcie_cfg_data bcm7712_cfg = { 1578 + .offsets = pcie_offsets_bcm7712, 1579 + .perst_set = brcm_pcie_perst_set_7278, 1580 + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, 1581 + .soc_base = BCM7712, 1582 + .num_inbound_wins = 10, 1718 1583 }; 1719 1584 1720 1585 static const struct of_device_id brcm_pcie_match[] = { 1721 1586 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg }, 1722 1587 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, 1723 1588 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, 1589 + { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg }, 1724 1590 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, 1725 - { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg }, 1726 - { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, 1727 - { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg }, 1728 1591 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg }, 1592 + { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg }, 1593 + { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, 1594 + { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg }, 1729 1595 {}, 1730 1596 }; 1731 1597 ··· 1804 1596 pcie->dev = &pdev->dev; 1805 1597 pcie->np = np; 1806 1598 pcie->reg_offsets = data->offsets; 1807 - pcie->type = data->type; 1599 + pcie->soc_base = data->soc_base; 1808 1600 pcie->perst_set = data->perst_set; 1809 1601 pcie->bridge_sw_init_set = data->bridge_sw_init_set; 1602 + pcie->has_phy = data->has_phy; 1603 + pcie->num_inbound_wins = data->num_inbound_wins; 1810 1604 1811 1605 pcie->base = devm_platform_ioremap_resource(pdev, 0); 1812 1606 if (IS_ERR(pcie->base)) ··· 1823 1613 1824 1614 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); 1825 1615 1826 - ret = clk_prepare_enable(pcie->clk); 1827 - if (ret) { 1828 - dev_err(&pdev->dev, "could not enable clock\n"); 1829 - return ret; 1830 - } 1831 1616 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); 1832 - if (IS_ERR(pcie->rescal)) { 1833 - clk_disable_unprepare(pcie->clk); 1617 + if (IS_ERR(pcie->rescal)) 1834 1618 return PTR_ERR(pcie->rescal); 1835 - } 1619 + 1836 1620 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); 1837 - if (IS_ERR(pcie->perst_reset)) { 1838 - clk_disable_unprepare(pcie->clk); 1621 + if (IS_ERR(pcie->perst_reset)) 1839 1622 return PTR_ERR(pcie->perst_reset); 1623 + 1624 + pcie->bridge_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge"); 1625 + if (IS_ERR(pcie->bridge_reset)) 1626 + return PTR_ERR(pcie->bridge_reset); 1627 + 1628 + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); 1629 + if (IS_ERR(pcie->swinit_reset)) 1630 + return PTR_ERR(pcie->swinit_reset); 1631 + 1632 + ret = clk_prepare_enable(pcie->clk); 1633 + if (ret) 1634 + return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); 1635 + 1636 + pcie->bridge_sw_init_set(pcie, 0); 1637 + 1638 + if (pcie->swinit_reset) { 1639 + ret = reset_control_assert(pcie->swinit_reset); 1640 + if (ret) { 1641 + clk_disable_unprepare(pcie->clk); 1642 + return dev_err_probe(&pdev->dev, ret, 1643 + "could not assert reset 'swinit'\n"); 1644 + } 1645 + 1646 + /* HW team recommends 1us for proper sync and propagation of reset */ 1647 + udelay(1); 1648 + 1649 + ret = reset_control_deassert(pcie->swinit_reset); 1650 + if (ret) { 1651 + clk_disable_unprepare(pcie->clk); 1652 + return dev_err_probe(&pdev->dev, ret, 1653 + "could not de-assert reset 'swinit'\n"); 1654 + } 1840 1655 } 1841 1656 1842 1657 ret = reset_control_reset(pcie->rescal); 1843 - if (ret) 1844 - dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); 1658 + if (ret) { 1659 + clk_disable_unprepare(pcie->clk); 1660 + return dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n"); 1661 + } 1845 1662 1846 1663 ret = brcm_phy_start(pcie); 1847 1664 if (ret) { ··· 1882 1645 goto fail; 1883 1646 1884 1647 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); 1885 - if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { 1648 + if (pcie->soc_base == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { 1886 1649 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); 1887 1650 ret = -ENODEV; 1888 1651 goto fail; ··· 1897 1660 } 1898 1661 } 1899 1662 1900 - bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; 1663 + bridge->ops = pcie->soc_base == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; 1901 1664 bridge->sysdata = pcie; 1902 1665 1903 1666 platform_set_drvdata(pdev, pcie); ··· 1915 1678 1916 1679 fail: 1917 1680 __brcm_pcie_remove(pcie); 1681 + 1918 1682 return ret; 1919 1683 } 1920 1684
+9 -9
drivers/pci/controller/pcie-iproc.c
··· 54 54 55 55 #define CFG_RD_SUCCESS 0 56 56 #define CFG_RD_UR 1 57 - #define CFG_RD_CRS 2 57 + #define CFG_RD_RRS 2 58 58 #define CFG_RD_CA 3 59 59 #define CFG_RETRY_STATUS 0xffff0001 60 60 #define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milliseconds */ ··· 485 485 u32 status; 486 486 487 487 /* 488 - * As per PCIe spec r3.1, sec 2.3.2, CRS Software Visibility only 488 + * As per PCIe r6.0, sec 2.3.2, Config RRS Software Visibility only 489 489 * affects config reads of the Vendor ID. For config writes or any 490 490 * other config reads, the Root may automatically reissue the 491 491 * configuration request again as a new request. 492 492 * 493 493 * For config reads, this hardware returns CFG_RETRY_STATUS data 494 - * when it receives a CRS completion, regardless of the address of 495 - * the read or the CRS Software Visibility Enable bit. As a 494 + * when it receives a RRS completion, regardless of the address of 495 + * the read or the RRS Software Visibility Enable bit. As a 496 496 * partial workaround for this, we retry in software any read that 497 497 * returns CFG_RETRY_STATUS. 498 498 * 499 499 * Note that a non-Vendor ID config register may have a value of 500 500 * CFG_RETRY_STATUS. If we read that, we can't distinguish it from 501 - * a CRS completion, so we will incorrectly retry the read and 501 + * a RRS completion, so we will incorrectly retry the read and 502 502 * eventually return the wrong data (0xffffffff). 503 503 */ 504 504 data = readl(cfg_data_p); 505 505 while (data == CFG_RETRY_STATUS && timeout--) { 506 506 /* 507 - * CRS state is set in CFG_RD status register 507 + * RRS state is set in CFG_RD status register 508 508 * This will handle the case where CFG_RETRY_STATUS is 509 509 * valid config data. 510 510 */ 511 511 status = iproc_pcie_read_reg(pcie, IPROC_PCIE_CFG_RD_STATUS); 512 - if (status != CFG_RD_CRS) 512 + if (status != CFG_RD_RRS) 513 513 return data; 514 514 515 515 udelay(1); ··· 556 556 break; 557 557 558 558 case IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL: 559 - /* Don't advertise CRS SV support */ 560 - *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); 559 + /* Don't advertise RRS SV support */ 560 + *val &= ~(PCI_EXP_RTCAP_RRS_SV << 16); 561 561 break; 562 562 563 563 default:
+168 -25
drivers/pci/controller/pcie-mediatek-gen3.c
··· 6 6 * Author: Jianjun Wang <jianjun.wang@mediatek.com> 7 7 */ 8 8 9 + #include <linux/bitfield.h> 9 10 #include <linux/clk.h> 11 + #include <linux/clk-provider.h> 10 12 #include <linux/delay.h> 11 13 #include <linux/iopoll.h> 12 14 #include <linux/irq.h> ··· 17 15 #include <linux/kernel.h> 18 16 #include <linux/module.h> 19 17 #include <linux/msi.h> 18 + #include <linux/of_device.h> 19 + #include <linux/of_pci.h> 20 20 #include <linux/pci.h> 21 21 #include <linux/phy/phy.h> 22 22 #include <linux/platform_device.h> ··· 32 28 #define PCIE_PCI_IDS_1 0x9c 33 29 #define PCI_CLASS(class) (class << 8) 34 30 #define PCIE_RC_MODE BIT(0) 31 + 32 + #define PCIE_EQ_PRESET_01_REG 0x100 33 + #define PCIE_VAL_LN0_DOWNSTREAM GENMASK(6, 0) 34 + #define PCIE_VAL_LN0_UPSTREAM GENMASK(14, 8) 35 + #define PCIE_VAL_LN1_DOWNSTREAM GENMASK(22, 16) 36 + #define PCIE_VAL_LN1_UPSTREAM GENMASK(30, 24) 35 37 36 38 #define PCIE_CFGNUM_REG 0x140 37 39 #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) ··· 78 68 #define PCIE_MSI_SET_ENABLE_REG 0x190 79 69 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) 80 70 71 + #define PCIE_PIPE4_PIE8_REG 0x338 72 + #define PCIE_K_FINETUNE_MAX GENMASK(5, 0) 73 + #define PCIE_K_FINETUNE_ERR GENMASK(7, 6) 74 + #define PCIE_K_PRESET_TO_USE GENMASK(18, 8) 75 + #define PCIE_K_PHYPARAM_QUERY BIT(19) 76 + #define PCIE_K_QUERY_TIMEOUT BIT(20) 77 + #define PCIE_K_PRESET_TO_USE_16G GENMASK(31, 21) 78 + 81 79 #define PCIE_MSI_SET_BASE_REG 0xc00 82 80 #define PCIE_MSI_SET_OFFSET 0x10 83 81 #define PCIE_MSI_SET_STATUS_OFFSET 0x04 ··· 118 100 #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) 119 101 #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) 120 102 103 + #define MAX_NUM_PHY_RESETS 3 104 + 105 + /* Time in ms needed to complete PCIe reset on EN7581 SoC */ 106 + #define PCIE_EN7581_RESET_TIME_MS 100 107 + 108 + struct mtk_gen3_pcie; 109 + 110 + /** 111 + * struct mtk_gen3_pcie_pdata - differentiate between host generations 112 + * @power_up: pcie power_up callback 113 + * @phy_resets: phy reset lines SoC data. 114 + */ 115 + struct mtk_gen3_pcie_pdata { 116 + int (*power_up)(struct mtk_gen3_pcie *pcie); 117 + struct { 118 + const char *id[MAX_NUM_PHY_RESETS]; 119 + int num_resets; 120 + } phy_resets; 121 + }; 122 + 121 123 /** 122 124 * struct mtk_msi_set - MSI information for each set 123 125 * @base: IO mapped register base ··· 156 118 * @base: IO mapped register base 157 119 * @reg_base: physical register base 158 120 * @mac_reset: MAC reset control 159 - * @phy_reset: PHY reset control 121 + * @phy_resets: PHY reset controllers 160 122 * @phy: PHY controller block 161 123 * @clks: PCIe clocks 162 124 * @num_clks: PCIe clocks count for this port ··· 169 131 * @msi_sets: MSI sets information 170 132 * @lock: lock protecting IRQ bit map 171 133 * @msi_irq_in_use: bit map for assigned MSI IRQ 134 + * @soc: pointer to SoC-dependent operations 172 135 */ 173 136 struct mtk_gen3_pcie { 174 137 struct device *dev; 175 138 void __iomem *base; 176 139 phys_addr_t reg_base; 177 140 struct reset_control *mac_reset; 178 - struct reset_control *phy_reset; 141 + struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RESETS]; 179 142 struct phy *phy; 180 143 struct clk_bulk_data *clks; 181 144 int num_clks; ··· 190 151 struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM]; 191 152 struct mutex lock; 192 153 DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM); 154 + 155 + const struct mtk_gen3_pcie_pdata *soc; 193 156 }; 194 157 195 158 /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */ ··· 465 424 return 0; 466 425 } 467 426 468 - static int mtk_pcie_set_affinity(struct irq_data *data, 469 - const struct cpumask *mask, bool force) 470 - { 471 - return -EINVAL; 472 - } 473 - 474 427 static void mtk_pcie_msi_irq_mask(struct irq_data *data) 475 428 { 476 429 pci_msi_mask_irq(data); ··· 485 450 }; 486 451 487 452 static struct msi_domain_info mtk_msi_domain_info = { 488 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 489 - MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), 453 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 454 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX | 455 + MSI_FLAG_MULTI_PCI_MSI, 490 456 .chip = &mtk_msi_irq_chip, 491 457 }; 492 458 ··· 553 517 .irq_mask = mtk_msi_bottom_irq_mask, 554 518 .irq_unmask = mtk_msi_bottom_irq_unmask, 555 519 .irq_compose_msi_msg = mtk_compose_msi_msg, 556 - .irq_set_affinity = mtk_pcie_set_affinity, 557 520 .name = "MSI", 558 521 }; 559 522 ··· 653 618 .irq_mask = mtk_intx_mask, 654 619 .irq_unmask = mtk_intx_unmask, 655 620 .irq_eoi = mtk_intx_eoi, 656 - .irq_set_affinity = mtk_pcie_set_affinity, 657 621 .name = "INTx", 658 622 }; 659 623 ··· 809 775 810 776 static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) 811 777 { 778 + int i, ret, num_resets = pcie->soc->phy_resets.num_resets; 812 779 struct device *dev = pcie->dev; 813 780 struct platform_device *pdev = to_platform_device(dev); 814 781 struct resource *regs; 815 - int ret; 816 782 817 783 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); 818 784 if (!regs) ··· 825 791 826 792 pcie->reg_base = regs->start; 827 793 828 - pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy"); 829 - if (IS_ERR(pcie->phy_reset)) { 830 - ret = PTR_ERR(pcie->phy_reset); 831 - if (ret != -EPROBE_DEFER) 832 - dev_err(dev, "failed to get PHY reset\n"); 794 + for (i = 0; i < num_resets; i++) 795 + pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i]; 833 796 797 + ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets); 798 + if (ret) { 799 + dev_err(dev, "failed to get PHY bulk reset\n"); 834 800 return ret; 835 801 } 836 802 ··· 861 827 return 0; 862 828 } 863 829 830 + static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) 831 + { 832 + struct device *dev = pcie->dev; 833 + int err; 834 + u32 val; 835 + 836 + /* 837 + * Wait for the time needed to complete the bulk assert in 838 + * mtk_pcie_setup for EN7581 SoC. 839 + */ 840 + mdelay(PCIE_EN7581_RESET_TIME_MS); 841 + 842 + err = phy_init(pcie->phy); 843 + if (err) { 844 + dev_err(dev, "failed to initialize PHY\n"); 845 + return err; 846 + } 847 + 848 + err = phy_power_on(pcie->phy); 849 + if (err) { 850 + dev_err(dev, "failed to power on PHY\n"); 851 + goto err_phy_on; 852 + } 853 + 854 + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); 855 + if (err) { 856 + dev_err(dev, "failed to deassert PHYs\n"); 857 + goto err_phy_deassert; 858 + } 859 + 860 + /* 861 + * Wait for the time needed to complete the bulk de-assert above. 862 + * This time is specific for EN7581 SoC. 863 + */ 864 + mdelay(PCIE_EN7581_RESET_TIME_MS); 865 + 866 + pm_runtime_enable(dev); 867 + pm_runtime_get_sync(dev); 868 + 869 + err = clk_bulk_prepare(pcie->num_clks, pcie->clks); 870 + if (err) { 871 + dev_err(dev, "failed to prepare clock\n"); 872 + goto err_clk_prepare; 873 + } 874 + 875 + val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | 876 + FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | 877 + FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | 878 + FIELD_PREP(PCIE_VAL_LN1_UPSTREAM, 0x41); 879 + writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG); 880 + 881 + val = PCIE_K_PHYPARAM_QUERY | PCIE_K_QUERY_TIMEOUT | 882 + FIELD_PREP(PCIE_K_PRESET_TO_USE_16G, 0x80) | 883 + FIELD_PREP(PCIE_K_PRESET_TO_USE, 0x2) | 884 + FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); 885 + writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); 886 + 887 + err = clk_bulk_enable(pcie->num_clks, pcie->clks); 888 + if (err) { 889 + dev_err(dev, "failed to prepare clock\n"); 890 + goto err_clk_enable; 891 + } 892 + 893 + return 0; 894 + 895 + err_clk_enable: 896 + clk_bulk_unprepare(pcie->num_clks, pcie->clks); 897 + err_clk_prepare: 898 + pm_runtime_put_sync(dev); 899 + pm_runtime_disable(dev); 900 + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); 901 + err_phy_deassert: 902 + phy_power_off(pcie->phy); 903 + err_phy_on: 904 + phy_exit(pcie->phy); 905 + 906 + return err; 907 + } 908 + 864 909 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) 865 910 { 866 911 struct device *dev = pcie->dev; 867 912 int err; 868 913 869 914 /* PHY power on and enable pipe clock */ 870 - reset_control_deassert(pcie->phy_reset); 915 + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); 916 + if (err) { 917 + dev_err(dev, "failed to deassert PHYs\n"); 918 + return err; 919 + } 871 920 872 921 err = phy_init(pcie->phy); 873 922 if (err) { ··· 986 869 err_phy_on: 987 870 phy_exit(pcie->phy); 988 871 err_phy_init: 989 - reset_control_assert(pcie->phy_reset); 872 + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); 990 873 991 874 return err; 992 875 } ··· 1001 884 1002 885 phy_power_off(pcie->phy); 1003 886 phy_exit(pcie->phy); 1004 - reset_control_assert(pcie->phy_reset); 887 + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); 1005 888 } 1006 889 1007 890 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) ··· 1013 896 return err; 1014 897 1015 898 /* 899 + * Deassert the line in order to avoid unbalance in deassert_count 900 + * counter since the bulk is shared. 901 + */ 902 + reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); 903 + /* 1016 904 * The controller may have been left out of reset by the bootloader 1017 905 * so make sure that we get a clean start by asserting resets here. 1018 906 */ 1019 - reset_control_assert(pcie->phy_reset); 907 + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); 908 + 1020 909 reset_control_assert(pcie->mac_reset); 1021 910 usleep_range(10, 20); 1022 911 1023 912 /* Don't touch the hardware registers before power up */ 1024 - err = mtk_pcie_power_up(pcie); 913 + err = pcie->soc->power_up(pcie); 1025 914 if (err) 1026 915 return err; 1027 916 ··· 1062 939 pcie = pci_host_bridge_priv(host); 1063 940 1064 941 pcie->dev = dev; 942 + pcie->soc = device_get_match_data(dev); 1065 943 platform_set_drvdata(pdev, pcie); 1066 944 1067 945 err = mtk_pcie_setup(pcie); ··· 1178 1054 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); 1179 1055 int err; 1180 1056 1181 - err = mtk_pcie_power_up(pcie); 1057 + err = pcie->soc->power_up(pcie); 1182 1058 if (err) 1183 1059 return err; 1184 1060 ··· 1198 1074 mtk_pcie_resume_noirq) 1199 1075 }; 1200 1076 1077 + static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = { 1078 + .power_up = mtk_pcie_power_up, 1079 + .phy_resets = { 1080 + .id[0] = "phy", 1081 + .num_resets = 1, 1082 + }, 1083 + }; 1084 + 1085 + static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = { 1086 + .power_up = mtk_pcie_en7581_power_up, 1087 + .phy_resets = { 1088 + .id[0] = "phy-lane0", 1089 + .id[1] = "phy-lane1", 1090 + .id[2] = "phy-lane2", 1091 + .num_resets = 3, 1092 + }, 1093 + }; 1094 + 1201 1095 static const struct of_device_id mtk_pcie_of_match[] = { 1202 - { .compatible = "mediatek,mt8192-pcie" }, 1096 + { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 }, 1097 + { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 }, 1203 1098 {}, 1204 1099 }; 1205 1100 MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
+2 -10
drivers/pci/controller/pcie-mediatek.c
··· 211 211 * @base: IO mapped register base 212 212 * @cfg: IO mapped register map for PCIe config 213 213 * @free_ck: free-run reference clock 214 - * @mem: non-prefetchable memory resource 215 214 * @ports: pointer to PCIe port information 216 215 * @soc: pointer to SoC-dependent operations 217 216 */ ··· 406 407 (int)data->hwirq, msg->address_hi, msg->address_lo); 407 408 } 408 409 409 - static int mtk_msi_set_affinity(struct irq_data *irq_data, 410 - const struct cpumask *mask, bool force) 411 - { 412 - return -EINVAL; 413 - } 414 - 415 410 static void mtk_msi_ack_irq(struct irq_data *data) 416 411 { 417 412 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); ··· 417 424 static struct irq_chip mtk_msi_bottom_irq_chip = { 418 425 .name = "MTK MSI", 419 426 .irq_compose_msi_msg = mtk_compose_msi_msg, 420 - .irq_set_affinity = mtk_msi_set_affinity, 421 427 .irq_ack = mtk_msi_ack_irq, 422 428 }; 423 429 ··· 478 486 }; 479 487 480 488 static struct msi_domain_info mtk_msi_domain_info = { 481 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 482 - MSI_FLAG_PCI_MSIX), 489 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 490 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX, 483 491 .chip = &mtk_msi_irq_chip, 484 492 }; 485 493
+2 -8
drivers/pci/controller/pcie-rcar-host.c
··· 658 658 spin_unlock_irqrestore(&msi->mask_lock, flags); 659 659 } 660 660 661 - static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force) 662 - { 663 - return -EINVAL; 664 - } 665 - 666 661 static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 667 662 { 668 663 struct rcar_msi *msi = irq_data_get_irq_chip_data(data); ··· 673 678 .irq_ack = rcar_msi_irq_ack, 674 679 .irq_mask = rcar_msi_irq_mask, 675 680 .irq_unmask = rcar_msi_irq_unmask, 676 - .irq_set_affinity = rcar_msi_set_affinity, 677 681 .irq_compose_msi_msg = rcar_compose_msi_msg, 678 682 }; 679 683 ··· 719 725 }; 720 726 721 727 static struct msi_domain_info rcar_msi_info = { 722 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 723 - MSI_FLAG_MULTI_PCI_MSI), 728 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 729 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI, 724 730 .chip = &rcar_msi_top_chip, 725 731 }; 726 732
+54 -10
drivers/pci/controller/pcie-xilinx-dma-pl.c
··· 71 71 72 72 /* Phy Status/Control Register definitions */ 73 73 #define XILINX_PCIE_DMA_REG_PSCR_LNKUP BIT(11) 74 + #define QDMA_BRIDGE_BASE_OFF 0xcd8 74 75 75 76 /* Number of MSI IRQs */ 76 77 #define XILINX_NUM_MSI_IRQS 64 78 + 79 + enum xilinx_pl_dma_version { 80 + XDMA, 81 + QDMA, 82 + }; 83 + 84 + /** 85 + * struct xilinx_pl_dma_variant - PL DMA PCIe variant information 86 + * @version: DMA version 87 + */ 88 + struct xilinx_pl_dma_variant { 89 + enum xilinx_pl_dma_version version; 90 + }; 77 91 78 92 struct xilinx_msi { 79 93 struct irq_domain *msi_domain; ··· 102 88 * struct pl_dma_pcie - PCIe port information 103 89 * @dev: Device pointer 104 90 * @reg_base: IO Mapped Register Base 91 + * @cfg_base: IO Mapped Configuration Base 105 92 * @irq: Interrupt number 106 93 * @cfg: Holds mappings of config space window 107 94 * @phys_reg_base: Physical address of reg base ··· 112 97 * @msi: MSI information 113 98 * @intx_irq: INTx error interrupt number 114 99 * @lock: Lock protecting shared register access 100 + * @variant: PL DMA PCIe version check pointer 115 101 */ 116 102 struct pl_dma_pcie { 117 103 struct device *dev; 118 104 void __iomem *reg_base; 105 + void __iomem *cfg_base; 119 106 int irq; 120 107 struct pci_config_window *cfg; 121 108 phys_addr_t phys_reg_base; ··· 127 110 struct xilinx_msi msi; 128 111 int intx_irq; 129 112 raw_spinlock_t lock; 113 + const struct xilinx_pl_dma_variant *variant; 130 114 }; 131 115 132 116 static inline u32 pcie_read(struct pl_dma_pcie *port, u32 reg) 133 117 { 118 + if (port->variant->version == QDMA) 119 + return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); 120 + 134 121 return readl(port->reg_base + reg); 135 122 } 136 123 137 124 static inline void pcie_write(struct pl_dma_pcie *port, u32 val, u32 reg) 138 125 { 139 - writel(val, port->reg_base + reg); 126 + if (port->variant->version == QDMA) 127 + writel(val, port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); 128 + else 129 + writel(val, port->reg_base + reg); 140 130 } 141 131 142 132 static inline bool xilinx_pl_dma_pcie_link_up(struct pl_dma_pcie *port) ··· 196 172 197 173 if (!xilinx_pl_dma_pcie_valid_device(bus, devfn)) 198 174 return NULL; 175 + 176 + if (port->variant->version == QDMA) 177 + return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 199 178 200 179 return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 201 180 } ··· 382 355 }; 383 356 384 357 static struct msi_domain_info xilinx_msi_domain_info = { 385 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 386 - MSI_FLAG_MULTI_PCI_MSI), 358 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 359 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI, 387 360 .chip = &xilinx_msi_irq_chip, 388 361 }; 389 362 ··· 397 370 msg->data = data->hwirq; 398 371 } 399 372 400 - static int xilinx_msi_set_affinity(struct irq_data *irq_data, 401 - const struct cpumask *mask, bool force) 402 - { 403 - return -EINVAL; 404 - } 405 - 406 373 static struct irq_chip xilinx_irq_chip = { 407 374 .name = "pl_dma:MSI", 408 375 .irq_compose_msi_msg = xilinx_compose_msi_msg, 409 - .irq_set_affinity = xilinx_msi_set_affinity, 410 376 }; 411 377 412 378 static int xilinx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, ··· 751 731 752 732 port->reg_base = port->cfg->win; 753 733 734 + if (port->variant->version == QDMA) { 735 + port->cfg_base = port->cfg->win; 736 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); 737 + port->reg_base = devm_ioremap_resource(dev, res); 738 + if (IS_ERR(port->reg_base)) 739 + return PTR_ERR(port->reg_base); 740 + port->phys_reg_base = res->start; 741 + } 742 + 754 743 err = xilinx_request_msi_irq(port); 755 744 if (err) { 756 745 pci_ecam_free(port->cfg); ··· 788 759 bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); 789 760 if (!bus) 790 761 return -ENODEV; 762 + 763 + port->variant = of_device_get_match_data(dev); 791 764 792 765 err = xilinx_pl_dma_pcie_parse_dt(port, bus->res); 793 766 if (err) { ··· 822 791 return err; 823 792 } 824 793 794 + static const struct xilinx_pl_dma_variant xdma_host = { 795 + .version = XDMA, 796 + }; 797 + 798 + static const struct xilinx_pl_dma_variant qdma_host = { 799 + .version = QDMA, 800 + }; 801 + 825 802 static const struct of_device_id xilinx_pl_dma_pcie_of_match[] = { 826 803 { 827 804 .compatible = "xlnx,xdma-host-3.00", 805 + .data = &xdma_host, 806 + }, 807 + { 808 + .compatible = "xlnx,qdma-host-3.00", 809 + .data = &qdma_host, 828 810 }, 829 811 {} 830 812 };
+118 -32
drivers/pci/controller/pcie-xilinx-nwl.c
··· 19 19 #include <linux/of_platform.h> 20 20 #include <linux/pci.h> 21 21 #include <linux/pci-ecam.h> 22 + #include <linux/phy/phy.h> 22 23 #include <linux/platform_device.h> 23 24 #include <linux/irqchip/chained_irq.h> 24 25 ··· 81 80 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) 82 81 #define MSGF_MISC_SR_FATAL_DEV BIT(23) 83 82 #define MSGF_MISC_SR_LINK_DOWN BIT(24) 84 - #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) 85 - #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) 83 + #define MSGF_MISC_SR_LINK_AUTO_BWIDTH BIT(25) 84 + #define MSGF_MISC_SR_LINK_BWIDTH BIT(26) 86 85 87 86 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \ 88 87 MSGF_MISC_SR_RXMSG_OVER | \ ··· 97 96 MSGF_MISC_SR_NON_FATAL_DEV | \ 98 97 MSGF_MISC_SR_FATAL_DEV | \ 99 98 MSGF_MISC_SR_LINK_DOWN | \ 100 - MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \ 101 - MSGF_MSIC_SR_LINK_BWIDTH) 99 + MSGF_MISC_SR_LINK_AUTO_BWIDTH | \ 100 + MSGF_MISC_SR_LINK_BWIDTH) 102 101 103 102 /* Legacy interrupt status mask bits */ 104 103 #define MSGF_LEG_SR_INTA BIT(0) ··· 158 157 void __iomem *breg_base; 159 158 void __iomem *pcireg_base; 160 159 void __iomem *ecam_base; 160 + struct phy *phy[4]; 161 161 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */ 162 162 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */ 163 163 phys_addr_t phys_ecam_base; /* Physical Configuration Base */ ··· 269 267 return IRQ_NONE; 270 268 271 269 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER) 272 - dev_err(dev, "Received Message FIFO Overflow\n"); 270 + dev_err_ratelimited(dev, "Received Message FIFO Overflow\n"); 273 271 274 272 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR) 275 - dev_err(dev, "Slave error\n"); 273 + dev_err_ratelimited(dev, "Slave error\n"); 276 274 277 275 if (misc_stat & MSGF_MISC_SR_MASTER_ERR) 278 - dev_err(dev, "Master error\n"); 276 + dev_err_ratelimited(dev, "Master error\n"); 279 277 280 278 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR) 281 - dev_err(dev, "In Misc Ingress address translation error\n"); 279 + dev_err_ratelimited(dev, "In Misc Ingress address translation error\n"); 282 280 283 281 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR) 284 - dev_err(dev, "In Misc Egress address translation error\n"); 282 + dev_err_ratelimited(dev, "In Misc Egress address translation error\n"); 285 283 286 284 if (misc_stat & MSGF_MISC_SR_FATAL_AER) 287 - dev_err(dev, "Fatal Error in AER Capability\n"); 285 + dev_err_ratelimited(dev, "Fatal Error in AER Capability\n"); 288 286 289 287 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER) 290 - dev_err(dev, "Non-Fatal Error in AER Capability\n"); 288 + dev_err_ratelimited(dev, "Non-Fatal Error in AER Capability\n"); 291 289 292 290 if (misc_stat & MSGF_MISC_SR_CORR_AER) 293 - dev_err(dev, "Correctable Error in AER Capability\n"); 291 + dev_err_ratelimited(dev, "Correctable Error in AER Capability\n"); 294 292 295 293 if (misc_stat & MSGF_MISC_SR_UR_DETECT) 296 - dev_err(dev, "Unsupported request Detected\n"); 294 + dev_err_ratelimited(dev, "Unsupported request Detected\n"); 297 295 298 296 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV) 299 - dev_err(dev, "Non-Fatal Error Detected\n"); 297 + dev_err_ratelimited(dev, "Non-Fatal Error Detected\n"); 300 298 301 299 if (misc_stat & MSGF_MISC_SR_FATAL_DEV) 302 - dev_err(dev, "Fatal Error Detected\n"); 300 + dev_err_ratelimited(dev, "Fatal Error Detected\n"); 303 301 304 - if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH) 302 + if (misc_stat & MSGF_MISC_SR_LINK_AUTO_BWIDTH) 305 303 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n"); 306 304 307 - if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH) 305 + if (misc_stat & MSGF_MISC_SR_LINK_BWIDTH) 308 306 dev_info(dev, "Link Bandwidth Management Status bit set\n"); 309 307 310 308 /* Clear misc interrupt status */ ··· 373 371 u32 mask; 374 372 u32 val; 375 373 376 - mask = 1 << (data->hwirq - 1); 374 + mask = 1 << data->hwirq; 377 375 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); 378 376 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); 379 377 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); ··· 387 385 u32 mask; 388 386 u32 val; 389 387 390 - mask = 1 << (data->hwirq - 1); 388 + mask = 1 << data->hwirq; 391 389 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); 392 390 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); 393 391 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); ··· 427 425 }; 428 426 429 427 static struct msi_domain_info nwl_msi_domain_info = { 430 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 431 - MSI_FLAG_MULTI_PCI_MSI), 428 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 429 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI, 432 430 .chip = &nwl_msi_irq_chip, 433 431 }; 434 432 #endif ··· 443 441 msg->data = data->hwirq; 444 442 } 445 443 446 - static int nwl_msi_set_affinity(struct irq_data *irq_data, 447 - const struct cpumask *mask, bool force) 448 - { 449 - return -EINVAL; 450 - } 451 - 452 444 static struct irq_chip nwl_irq_chip = { 453 445 .name = "Xilinx MSI", 454 446 .irq_compose_msi_msg = nwl_compose_msi_msg, 455 - .irq_set_affinity = nwl_msi_set_affinity, 456 447 }; 457 448 458 449 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, ··· 514 519 } 515 520 #endif 516 521 return 0; 522 + } 523 + 524 + static void nwl_pcie_phy_power_off(struct nwl_pcie *pcie, int i) 525 + { 526 + int err = phy_power_off(pcie->phy[i]); 527 + 528 + if (err) 529 + dev_err(pcie->dev, "could not power off phy %d (err=%d)\n", i, 530 + err); 531 + } 532 + 533 + static void nwl_pcie_phy_exit(struct nwl_pcie *pcie, int i) 534 + { 535 + int err = phy_exit(pcie->phy[i]); 536 + 537 + if (err) 538 + dev_err(pcie->dev, "could not exit phy %d (err=%d)\n", i, err); 539 + } 540 + 541 + static int nwl_pcie_phy_enable(struct nwl_pcie *pcie) 542 + { 543 + int i, ret; 544 + 545 + for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { 546 + ret = phy_init(pcie->phy[i]); 547 + if (ret) 548 + goto err; 549 + 550 + ret = phy_power_on(pcie->phy[i]); 551 + if (ret) { 552 + nwl_pcie_phy_exit(pcie, i); 553 + goto err; 554 + } 555 + } 556 + 557 + return 0; 558 + 559 + err: 560 + while (i--) { 561 + nwl_pcie_phy_power_off(pcie, i); 562 + nwl_pcie_phy_exit(pcie, i); 563 + } 564 + 565 + return ret; 566 + } 567 + 568 + static void nwl_pcie_phy_disable(struct nwl_pcie *pcie) 569 + { 570 + int i; 571 + 572 + for (i = ARRAY_SIZE(pcie->phy); i--;) { 573 + nwl_pcie_phy_power_off(pcie, i); 574 + nwl_pcie_phy_exit(pcie, i); 575 + } 517 576 } 518 577 519 578 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) ··· 781 732 { 782 733 struct device *dev = pcie->dev; 783 734 struct resource *res; 735 + int i; 784 736 785 737 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); 786 738 pcie->breg_base = devm_ioremap_resource(dev, res); ··· 809 759 irq_set_chained_handler_and_data(pcie->irq_intx, 810 760 nwl_pcie_leg_handler, pcie); 811 761 762 + 763 + for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { 764 + pcie->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i); 765 + if (PTR_ERR(pcie->phy[i]) == -ENODEV) { 766 + pcie->phy[i] = NULL; 767 + break; 768 + } 769 + 770 + if (IS_ERR(pcie->phy[i])) 771 + return PTR_ERR(pcie->phy[i]); 772 + } 773 + 812 774 return 0; 813 775 } 814 776 ··· 841 779 return -ENODEV; 842 780 843 781 pcie = pci_host_bridge_priv(bridge); 782 + platform_set_drvdata(pdev, pcie); 844 783 845 784 pcie->dev = dev; 846 785 ··· 861 798 return err; 862 799 } 863 800 801 + err = nwl_pcie_phy_enable(pcie); 802 + if (err) { 803 + dev_err(dev, "could not enable PHYs\n"); 804 + goto err_clk; 805 + } 806 + 864 807 err = nwl_pcie_bridge_init(pcie); 865 808 if (err) { 866 809 dev_err(dev, "HW Initialization failed\n"); 867 - return err; 810 + goto err_phy; 868 811 } 869 812 870 813 err = nwl_pcie_init_irq_domain(pcie); 871 814 if (err) { 872 815 dev_err(dev, "Failed creating IRQ Domain\n"); 873 - return err; 816 + goto err_phy; 874 817 } 875 818 876 819 bridge->sysdata = pcie; ··· 886 817 err = nwl_pcie_enable_msi(pcie); 887 818 if (err < 0) { 888 819 dev_err(dev, "failed to enable MSI support: %d\n", err); 889 - return err; 820 + goto err_phy; 890 821 } 891 822 } 892 823 893 - return pci_host_probe(bridge); 824 + err = pci_host_probe(bridge); 825 + if (!err) 826 + return 0; 827 + 828 + err_phy: 829 + nwl_pcie_phy_disable(pcie); 830 + err_clk: 831 + clk_disable_unprepare(pcie->clk); 832 + return err; 833 + } 834 + 835 + static void nwl_pcie_remove(struct platform_device *pdev) 836 + { 837 + struct nwl_pcie *pcie = platform_get_drvdata(pdev); 838 + 839 + nwl_pcie_phy_disable(pcie); 840 + clk_disable_unprepare(pcie->clk); 894 841 } 895 842 896 843 static struct platform_driver nwl_pcie_driver = { ··· 916 831 .of_match_table = nwl_pcie_of_match, 917 832 }, 918 833 .probe = nwl_pcie_probe, 834 + .remove_new = nwl_pcie_remove, 919 835 }; 920 836 builtin_platform_driver(nwl_pcie_driver);
+2 -7
drivers/pci/controller/pcie-xilinx.c
··· 208 208 .irq_ack = xilinx_msi_top_irq_ack, 209 209 }; 210 210 211 - static int xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force) 212 - { 213 - return -EINVAL; 214 - } 215 - 216 211 static void xilinx_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 217 212 { 218 213 struct xilinx_pcie *pcie = irq_data_get_irq_chip_data(data); ··· 220 225 221 226 static struct irq_chip xilinx_msi_bottom_chip = { 222 227 .name = "Xilinx MSI", 223 - .irq_set_affinity = xilinx_msi_set_affinity, 224 228 .irq_compose_msi_msg = xilinx_compose_msi_msg, 225 229 }; 226 230 ··· 265 271 }; 266 272 267 273 static struct msi_domain_info xilinx_msi_info = { 268 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), 274 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 275 + MSI_FLAG_NO_AFFINITY, 269 276 .chip = &xilinx_msi_top_chip, 270 277 }; 271 278
+2 -9
drivers/pci/controller/plda/pcie-plda-host.c
··· 76 76 (int)data->hwirq, msg->address_hi, msg->address_lo); 77 77 } 78 78 79 - static int plda_msi_set_affinity(struct irq_data *irq_data, 80 - const struct cpumask *mask, bool force) 81 - { 82 - return -EINVAL; 83 - } 84 - 85 79 static struct irq_chip plda_msi_bottom_irq_chip = { 86 80 .name = "PLDA MSI", 87 81 .irq_ack = plda_msi_bottom_irq_ack, 88 82 .irq_compose_msi_msg = plda_compose_msi_msg, 89 - .irq_set_affinity = plda_msi_set_affinity, 90 83 }; 91 84 92 85 static int plda_irq_msi_domain_alloc(struct irq_domain *domain, ··· 139 146 }; 140 147 141 148 static struct msi_domain_info plda_msi_domain_info = { 142 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 143 - MSI_FLAG_PCI_MSIX), 149 + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 150 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX, 144 151 .chip = &plda_msi_irq_chip, 145 152 }; 146 153
+3 -14
drivers/pci/controller/vmd.c
··· 204 204 raw_spin_unlock_irqrestore(&list_lock, flags); 205 205 } 206 206 207 - /* 208 - * XXX: Stubbed until we develop acceptable way to not create conflicts with 209 - * other devices sharing the same vector. 210 - */ 211 - static int vmd_irq_set_affinity(struct irq_data *data, 212 - const struct cpumask *dest, bool force) 213 - { 214 - return -EINVAL; 215 - } 216 - 217 207 static struct irq_chip vmd_msi_controller = { 218 208 .name = "VMD-MSI", 219 209 .irq_enable = vmd_irq_enable, 220 210 .irq_disable = vmd_irq_disable, 221 211 .irq_compose_msi_msg = vmd_compose_msi_msg, 222 - .irq_set_affinity = vmd_irq_set_affinity, 223 212 }; 224 213 225 214 static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info, ··· 315 326 316 327 static struct msi_domain_info vmd_msi_domain_info = { 317 328 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 318 - MSI_FLAG_PCI_MSIX, 329 + MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX, 319 330 .ops = &vmd_msi_domain_ops, 320 331 .chip = &vmd_msi_controller, 321 332 }; ··· 1042 1053 1043 1054 static void vmd_shutdown(struct pci_dev *dev) 1044 1055 { 1045 - struct vmd_dev *vmd = pci_get_drvdata(dev); 1056 + struct vmd_dev *vmd = pci_get_drvdata(dev); 1046 1057 1047 - vmd_remove_irq_domain(vmd); 1058 + vmd_remove_irq_domain(vmd); 1048 1059 } 1049 1060 1050 1061 #ifdef CONFIG_PM_SLEEP
+7 -2
drivers/pci/devres.c
··· 730 730 * Mapping and region will get automatically released on driver detach. If 731 731 * desired, release manually only with pcim_iounmap_region(). 732 732 */ 733 - static void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar, 733 + void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar, 734 734 const char *name) 735 735 { 736 736 int ret; ··· 763 763 764 764 return IOMEM_ERR_PTR(ret); 765 765 } 766 + EXPORT_SYMBOL(pcim_iomap_region); 766 767 767 768 /** 768 769 * pcim_iounmap_region - Unmap and release a PCI BAR ··· 786 785 } 787 786 788 787 /** 789 - * pcim_iomap_regions - Request and iomap PCI BARs 788 + * pcim_iomap_regions - Request and iomap PCI BARs (DEPRECATED) 790 789 * @pdev: PCI device to map IO resources for 791 790 * @mask: Mask of BARs to request and iomap 792 791 * @name: Name associated with the requests ··· 794 793 * Returns: 0 on success, negative error code on failure. 795 794 * 796 795 * Request and iomap regions specified by @mask. 796 + * 797 + * This function is DEPRECATED. Do not use it in new code. 798 + * Use pcim_iomap_region() instead. 797 799 */ 798 800 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name) 799 801 { ··· 869 865 { 870 866 return _pcim_request_region(pdev, bar, name, 0); 871 867 } 868 + EXPORT_SYMBOL(pcim_request_region); 872 869 873 870 /** 874 871 * pcim_request_region_exclusive - Request a PCI BAR exclusively
+14
drivers/pci/endpoint/pci-epc-core.c
··· 838 838 { 839 839 pci_ep_cfs_remove_epc_group(epc->group); 840 840 device_unregister(&epc->dev); 841 + 842 + #ifdef CONFIG_PCI_DOMAINS_GENERIC 843 + pci_bus_release_domain_nr(&epc->dev, epc->domain_nr); 844 + #endif 841 845 } 842 846 EXPORT_SYMBOL_GPL(pci_epc_destroy); 843 847 ··· 903 899 epc->dev.parent = dev; 904 900 epc->dev.release = pci_epc_release; 905 901 epc->ops = ops; 902 + 903 + #ifdef CONFIG_PCI_DOMAINS_GENERIC 904 + epc->domain_nr = pci_bus_find_domain_nr(NULL, dev); 905 + #else 906 + /* 907 + * TODO: If the architecture doesn't support generic PCI 908 + * domains, then a custom implementation has to be used. 909 + */ 910 + WARN_ONCE(1, "This architecture doesn't support generic PCI domains\n"); 911 + #endif 906 912 907 913 ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); 908 914 if (ret)
-5
drivers/pci/hotplug/TODO
··· 51 51 52 52 shpchp: 53 53 54 - * There is only a single implementation of struct hpc_ops. Can the struct be 55 - removed and its functions invoked directly? This has already been done in 56 - pciehp with commit 82a9e79ef132 ("PCI: pciehp: remove hpc_ops"). Clarify 57 - if there was a specific reason not to apply the same change to shpchp. 58 - 59 54 * The hardirq handler shpc_isr() queues events on a workqueue. It can be 60 55 simplified by converting it to threaded IRQ handling. Use pciehp as a 61 56 template.
+1 -1
drivers/pci/hotplug/cpqphp_core.c
··· 328 328 } else { 329 329 /* Did not get a match on the target PCI device. Check 330 330 * if the current IRQ table entry is a PCI-to-PCI 331 - * bridge device. If so, and it's secondary bus 331 + * bridge device. If so, and its secondary bus 332 332 * matches the bus number for the target device, I need 333 333 * to save the bridge's slot number. If I can not find 334 334 * an entry for the target device, I will have to
+2 -2
drivers/pci/hotplug/cpqphp_pci.c
··· 138 138 139 139 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &vendID) == -1) 140 140 return -1; 141 - if (vendID == 0xffffffff) 141 + if (PCI_POSSIBLE_ERROR(vendID)) 142 142 return -1; 143 143 return pci_bus_read_config_dword(bus, devfn, offset, value); 144 144 } ··· 253 253 *dev_num = tdevice; 254 254 ctrl->pci_bus->number = tbus; 255 255 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work); 256 - if (!nobridge || (work == 0xffffffff)) 256 + if (!nobridge || PCI_POSSIBLE_ERROR(work)) 257 257 return 0; 258 258 259 259 dbg("bus_num %d devfn %d\n", *bus_num, *dev_num);
+1 -1
drivers/pci/hotplug/s390_pci_hpc.c
··· 112 112 113 113 static int get_adapter_status(struct hotplug_slot *hotplug_slot, u8 *value) 114 114 { 115 - /* if the slot exits it always contains a function */ 115 + /* if the slot exists it always contains a function */ 116 116 *value = 1; 117 117 return 0; 118 118 }
+17 -21
drivers/pci/hotplug/shpchp.h
··· 72 72 u8 latch_save; 73 73 u8 pwr_save; 74 74 struct controller *ctrl; 75 - const struct hpc_ops *hpc_ops; 76 75 struct hotplug_slot hotplug_slot; 77 76 struct list_head slot_list; 78 77 struct delayed_work work; /* work for button event */ ··· 93 94 int slot_num_inc; /* 1 or -1 */ 94 95 struct pci_dev *pci_dev; 95 96 struct list_head slot_list; 96 - const struct hpc_ops *hpc_ops; 97 97 wait_queue_head_t queue; /* sleep & wake process */ 98 98 u8 slot_device_offset; 99 99 u32 pcix_misc2_reg; /* for amd pogo errata */ ··· 298 300 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); 299 301 } 300 302 301 - struct hpc_ops { 302 - int (*power_on_slot)(struct slot *slot); 303 - int (*slot_enable)(struct slot *slot); 304 - int (*slot_disable)(struct slot *slot); 305 - int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed); 306 - int (*get_power_status)(struct slot *slot, u8 *status); 307 - int (*get_attention_status)(struct slot *slot, u8 *status); 308 - int (*set_attention_status)(struct slot *slot, u8 status); 309 - int (*get_latch_status)(struct slot *slot, u8 *status); 310 - int (*get_adapter_status)(struct slot *slot, u8 *status); 311 - int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed); 312 - int (*get_prog_int)(struct slot *slot, u8 *prog_int); 313 - int (*query_power_fault)(struct slot *slot); 314 - void (*green_led_on)(struct slot *slot); 315 - void (*green_led_off)(struct slot *slot); 316 - void (*green_led_blink)(struct slot *slot); 317 - void (*release_ctlr)(struct controller *ctrl); 318 - int (*check_cmd_status)(struct controller *ctrl); 319 - }; 303 + int shpchp_power_on_slot(struct slot *slot); 304 + int shpchp_slot_enable(struct slot *slot); 305 + int shpchp_slot_disable(struct slot *slot); 306 + int shpchp_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed speed); 307 + int shpchp_get_power_status(struct slot *slot, u8 *status); 308 + int shpchp_get_attention_status(struct slot *slot, u8 *status); 309 + int shpchp_set_attention_status(struct slot *slot, u8 status); 310 + int shpchp_get_latch_status(struct slot *slot, u8 *status); 311 + int shpchp_get_adapter_status(struct slot *slot, u8 *status); 312 + int shpchp_get_adapter_speed(struct slot *slot, enum pci_bus_speed *speed); 313 + int shpchp_get_prog_int(struct slot *slot, u8 *prog_int); 314 + int shpchp_query_power_fault(struct slot *slot); 315 + void shpchp_green_led_on(struct slot *slot); 316 + void shpchp_green_led_off(struct slot *slot); 317 + void shpchp_green_led_blink(struct slot *slot); 318 + void shpchp_release_ctlr(struct controller *ctrl); 319 + int shpchp_check_cmd_status(struct controller *ctrl); 320 320 321 321 #endif /* _SHPCHP_H */
+7 -8
drivers/pci/hotplug/shpchp_core.c
··· 81 81 slot->ctrl = ctrl; 82 82 slot->bus = ctrl->pci_dev->subordinate->number; 83 83 slot->device = ctrl->slot_device_offset + i; 84 - slot->hpc_ops = ctrl->hpc_ops; 85 84 slot->number = ctrl->first_slot + (ctrl->slot_num_inc * i); 86 85 87 86 slot->wq = alloc_workqueue("shpchp-%d", 0, 0, slot->number); ··· 149 150 __func__, slot_name(slot)); 150 151 151 152 slot->attention_save = status; 152 - slot->hpc_ops->set_attention_status(slot, status); 153 + shpchp_set_attention_status(slot, status); 153 154 154 155 return 0; 155 156 } ··· 182 183 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 183 184 __func__, slot_name(slot)); 184 185 185 - retval = slot->hpc_ops->get_power_status(slot, value); 186 + retval = shpchp_get_power_status(slot, value); 186 187 if (retval < 0) 187 188 *value = slot->pwr_save; 188 189 ··· 197 198 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 198 199 __func__, slot_name(slot)); 199 200 200 - retval = slot->hpc_ops->get_attention_status(slot, value); 201 + retval = shpchp_get_attention_status(slot, value); 201 202 if (retval < 0) 202 203 *value = slot->attention_save; 203 204 ··· 212 213 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 213 214 __func__, slot_name(slot)); 214 215 215 - retval = slot->hpc_ops->get_latch_status(slot, value); 216 + retval = shpchp_get_latch_status(slot, value); 216 217 if (retval < 0) 217 218 *value = slot->latch_save; 218 219 ··· 227 228 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 228 229 __func__, slot_name(slot)); 229 230 230 - retval = slot->hpc_ops->get_adapter_status(slot, value); 231 + retval = shpchp_get_adapter_status(slot, value); 231 232 if (retval < 0) 232 233 *value = slot->presence_save; 233 234 ··· 292 293 err_cleanup_slots: 293 294 cleanup_slots(ctrl); 294 295 err_out_release_ctlr: 295 - ctrl->hpc_ops->release_ctlr(ctrl); 296 + shpchp_release_ctlr(ctrl); 296 297 err_out_free_ctrl: 297 298 kfree(ctrl); 298 299 err_out_none: ··· 305 306 306 307 dev->shpc_managed = 0; 307 308 shpchp_remove_ctrl_files(ctrl); 308 - ctrl->hpc_ops->release_ctlr(ctrl); 309 + shpchp_release_ctlr(ctrl); 309 310 kfree(ctrl); 310 311 } 311 312
+39 -40
drivers/pci/hotplug/shpchp_ctrl.c
··· 51 51 ctrl_dbg(ctrl, "Attention button interrupt received\n"); 52 52 53 53 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 54 - p_slot->hpc_ops->get_adapter_status(p_slot, &(p_slot->presence_save)); 54 + shpchp_get_adapter_status(p_slot, &p_slot->presence_save); 55 55 56 56 /* 57 57 * Button pressed - See if need to TAKE ACTION!!! ··· 75 75 ctrl_dbg(ctrl, "Switch interrupt received\n"); 76 76 77 77 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 78 - p_slot->hpc_ops->get_adapter_status(p_slot, &(p_slot->presence_save)); 79 - p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 78 + shpchp_get_adapter_status(p_slot, &p_slot->presence_save); 79 + shpchp_get_latch_status(p_slot, &getstatus); 80 80 ctrl_dbg(ctrl, "Card present %x Power status %x\n", 81 81 p_slot->presence_save, p_slot->pwr_save); 82 82 ··· 116 116 /* 117 117 * Save the presence state 118 118 */ 119 - p_slot->hpc_ops->get_adapter_status(p_slot, &(p_slot->presence_save)); 119 + shpchp_get_adapter_status(p_slot, &p_slot->presence_save); 120 120 if (p_slot->presence_save) { 121 121 /* 122 122 * Card Present ··· 148 148 149 149 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 150 150 151 - if (!(p_slot->hpc_ops->query_power_fault(p_slot))) { 151 + if (!(shpchp_query_power_fault(p_slot))) { 152 152 /* 153 153 * Power fault Cleared 154 154 */ ··· 181 181 int rc = 0; 182 182 183 183 ctrl_dbg(ctrl, "Change speed to %d\n", speed); 184 - rc = p_slot->hpc_ops->set_bus_speed_mode(p_slot, speed); 184 + rc = shpchp_set_bus_speed_mode(p_slot, speed); 185 185 if (rc) { 186 186 ctrl_err(ctrl, "%s: Issue of set bus speed mode command failed\n", 187 187 __func__); ··· 241 241 __func__, p_slot->device, ctrl->slot_device_offset, hp_slot); 242 242 243 243 /* Power on slot without connecting to bus */ 244 - rc = p_slot->hpc_ops->power_on_slot(p_slot); 244 + rc = shpchp_power_on_slot(p_slot); 245 245 if (rc) { 246 246 ctrl_err(ctrl, "Failed to power on slot\n"); 247 247 return -1; 248 248 } 249 249 250 250 if ((ctrl->pci_dev->vendor == 0x8086) && (ctrl->pci_dev->device == 0x0332)) { 251 - rc = p_slot->hpc_ops->set_bus_speed_mode(p_slot, PCI_SPEED_33MHz); 251 + rc = shpchp_set_bus_speed_mode(p_slot, PCI_SPEED_33MHz); 252 252 if (rc) { 253 253 ctrl_err(ctrl, "%s: Issue of set bus speed mode command failed\n", 254 254 __func__); ··· 256 256 } 257 257 258 258 /* turn on board, blink green LED, turn off Amber LED */ 259 - rc = p_slot->hpc_ops->slot_enable(p_slot); 259 + rc = shpchp_slot_enable(p_slot); 260 260 if (rc) { 261 261 ctrl_err(ctrl, "Issue of Slot Enable command failed\n"); 262 262 return rc; 263 263 } 264 264 } 265 265 266 - rc = p_slot->hpc_ops->get_adapter_speed(p_slot, &asp); 266 + rc = shpchp_get_adapter_speed(p_slot, &asp); 267 267 if (rc) { 268 268 ctrl_err(ctrl, "Can't get adapter speed or bus mode mismatch\n"); 269 269 return WRONG_BUS_FREQUENCY; ··· 285 285 return rc; 286 286 287 287 /* turn on board, blink green LED, turn off Amber LED */ 288 - rc = p_slot->hpc_ops->slot_enable(p_slot); 288 + rc = shpchp_slot_enable(p_slot); 289 289 if (rc) { 290 290 ctrl_err(ctrl, "Issue of Slot Enable command failed\n"); 291 291 return rc; ··· 313 313 p_slot->is_a_board = 0x01; 314 314 p_slot->pwr_save = 1; 315 315 316 - p_slot->hpc_ops->green_led_on(p_slot); 316 + shpchp_green_led_on(p_slot); 317 317 318 318 return 0; 319 319 320 320 err_exit: 321 321 /* turn off slot, turn on Amber LED, turn off Green LED */ 322 - rc = p_slot->hpc_ops->slot_disable(p_slot); 322 + rc = shpchp_slot_disable(p_slot); 323 323 if (rc) { 324 324 ctrl_err(ctrl, "%s: Issue of Slot Disable command failed\n", 325 325 __func__); ··· 352 352 p_slot->status = 0x01; 353 353 354 354 /* turn off slot, turn on Amber LED, turn off Green LED */ 355 - rc = p_slot->hpc_ops->slot_disable(p_slot); 355 + rc = shpchp_slot_disable(p_slot); 356 356 if (rc) { 357 357 ctrl_err(ctrl, "%s: Issue of Slot Disable command failed\n", 358 358 __func__); 359 359 return rc; 360 360 } 361 361 362 - rc = p_slot->hpc_ops->set_attention_status(p_slot, 0); 362 + rc = shpchp_set_attention_status(p_slot, 0); 363 363 if (rc) { 364 364 ctrl_err(ctrl, "Issue of Set Attention command failed\n"); 365 365 return rc; ··· 401 401 case POWERON_STATE: 402 402 mutex_unlock(&p_slot->lock); 403 403 if (shpchp_enable_slot(p_slot)) 404 - p_slot->hpc_ops->green_led_off(p_slot); 404 + shpchp_green_led_off(p_slot); 405 405 mutex_lock(&p_slot->lock); 406 406 p_slot->state = STATIC_STATE; 407 407 break; ··· 446 446 447 447 static void update_slot_info(struct slot *slot) 448 448 { 449 - slot->hpc_ops->get_power_status(slot, &slot->pwr_save); 450 - slot->hpc_ops->get_attention_status(slot, &slot->attention_save); 451 - slot->hpc_ops->get_latch_status(slot, &slot->latch_save); 452 - slot->hpc_ops->get_adapter_status(slot, &slot->presence_save); 449 + shpchp_get_power_status(slot, &slot->pwr_save); 450 + shpchp_get_attention_status(slot, &slot->attention_save); 451 + shpchp_get_latch_status(slot, &slot->latch_save); 452 + shpchp_get_adapter_status(slot, &slot->presence_save); 453 453 } 454 454 455 455 /* ··· 462 462 463 463 switch (p_slot->state) { 464 464 case STATIC_STATE: 465 - p_slot->hpc_ops->get_power_status(p_slot, &getstatus); 465 + shpchp_get_power_status(p_slot, &getstatus); 466 466 if (getstatus) { 467 467 p_slot->state = BLINKINGOFF_STATE; 468 468 ctrl_info(ctrl, "PCI slot #%s - powering off due to button press\n", ··· 473 473 slot_name(p_slot)); 474 474 } 475 475 /* blink green LED and turn off amber */ 476 - p_slot->hpc_ops->green_led_blink(p_slot); 477 - p_slot->hpc_ops->set_attention_status(p_slot, 0); 476 + shpchp_green_led_blink(p_slot); 477 + shpchp_set_attention_status(p_slot, 0); 478 478 479 479 queue_delayed_work(p_slot->wq, &p_slot->work, 5*HZ); 480 480 break; ··· 489 489 slot_name(p_slot)); 490 490 cancel_delayed_work(&p_slot->work); 491 491 if (p_slot->state == BLINKINGOFF_STATE) 492 - p_slot->hpc_ops->green_led_on(p_slot); 492 + shpchp_green_led_on(p_slot); 493 493 else 494 - p_slot->hpc_ops->green_led_off(p_slot); 495 - p_slot->hpc_ops->set_attention_status(p_slot, 0); 494 + shpchp_green_led_off(p_slot); 495 + shpchp_set_attention_status(p_slot, 0); 496 496 ctrl_info(ctrl, "PCI slot #%s - action canceled due to button press\n", 497 497 slot_name(p_slot)); 498 498 p_slot->state = STATIC_STATE; ··· 526 526 break; 527 527 case INT_POWER_FAULT: 528 528 ctrl_dbg(p_slot->ctrl, "%s: Power fault\n", __func__); 529 - p_slot->hpc_ops->set_attention_status(p_slot, 1); 530 - p_slot->hpc_ops->green_led_off(p_slot); 529 + shpchp_set_attention_status(p_slot, 1); 530 + shpchp_green_led_off(p_slot); 531 531 break; 532 532 default: 533 533 update_slot_info(p_slot); ··· 547 547 548 548 /* Check to see if (latch closed, card present, power off) */ 549 549 mutex_lock(&p_slot->ctrl->crit_sect); 550 - rc = p_slot->hpc_ops->get_adapter_status(p_slot, &getstatus); 550 + rc = shpchp_get_adapter_status(p_slot, &getstatus); 551 551 if (rc || !getstatus) { 552 552 ctrl_info(ctrl, "No adapter on slot(%s)\n", slot_name(p_slot)); 553 553 goto out; 554 554 } 555 - rc = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 555 + rc = shpchp_get_latch_status(p_slot, &getstatus); 556 556 if (rc || getstatus) { 557 557 ctrl_info(ctrl, "Latch open on slot(%s)\n", slot_name(p_slot)); 558 558 goto out; 559 559 } 560 - rc = p_slot->hpc_ops->get_power_status(p_slot, &getstatus); 560 + rc = shpchp_get_power_status(p_slot, &getstatus); 561 561 if (rc || getstatus) { 562 562 ctrl_info(ctrl, "Already enabled on slot(%s)\n", 563 563 slot_name(p_slot)); ··· 567 567 p_slot->is_a_board = 1; 568 568 569 569 /* We have to save the presence info for these slots */ 570 - p_slot->hpc_ops->get_adapter_status(p_slot, &(p_slot->presence_save)); 571 - p_slot->hpc_ops->get_power_status(p_slot, &(p_slot->pwr_save)); 570 + shpchp_get_adapter_status(p_slot, &p_slot->presence_save); 571 + shpchp_get_power_status(p_slot, &p_slot->pwr_save); 572 572 ctrl_dbg(ctrl, "%s: p_slot->pwr_save %x\n", __func__, p_slot->pwr_save); 573 - p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 573 + shpchp_get_latch_status(p_slot, &getstatus); 574 574 575 575 if ((p_slot->ctrl->pci_dev->vendor == PCI_VENDOR_ID_AMD && 576 576 p_slot->ctrl->pci_dev->device == PCI_DEVICE_ID_AMD_POGO_7458) ··· 584 584 retval = board_added(p_slot); 585 585 586 586 if (retval) { 587 - p_slot->hpc_ops->get_adapter_status(p_slot, 588 - &(p_slot->presence_save)); 589 - p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 587 + shpchp_get_adapter_status(p_slot, &p_slot->presence_save); 588 + shpchp_get_latch_status(p_slot, &getstatus); 590 589 } 591 590 592 591 update_slot_info(p_slot); ··· 607 608 /* Check to see if (latch closed, card present, power on) */ 608 609 mutex_lock(&p_slot->ctrl->crit_sect); 609 610 610 - rc = p_slot->hpc_ops->get_adapter_status(p_slot, &getstatus); 611 + rc = shpchp_get_adapter_status(p_slot, &getstatus); 611 612 if (rc || !getstatus) { 612 613 ctrl_info(ctrl, "No adapter on slot(%s)\n", slot_name(p_slot)); 613 614 goto out; 614 615 } 615 - rc = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 616 + rc = shpchp_get_latch_status(p_slot, &getstatus); 616 617 if (rc || getstatus) { 617 618 ctrl_info(ctrl, "Latch open on slot(%s)\n", slot_name(p_slot)); 618 619 goto out; 619 620 } 620 - rc = p_slot->hpc_ops->get_power_status(p_slot, &getstatus); 621 + rc = shpchp_get_power_status(p_slot, &getstatus); 621 622 if (rc || !getstatus) { 622 623 ctrl_info(ctrl, "Already disabled on slot(%s)\n", 623 624 slot_name(p_slot));
+19 -44
drivers/pci/hotplug/shpchp_hpc.c
··· 167 167 168 168 static irqreturn_t shpc_isr(int irq, void *dev_id); 169 169 static void start_int_poll_timer(struct controller *ctrl, int sec); 170 - static int hpc_check_cmd_status(struct controller *ctrl); 171 170 172 171 static inline u8 shpc_readb(struct controller *ctrl, int reg) 173 172 { ··· 316 317 if (retval) 317 318 goto out; 318 319 319 - cmd_status = hpc_check_cmd_status(slot->ctrl); 320 + cmd_status = shpchp_check_cmd_status(slot->ctrl); 320 321 if (cmd_status) { 321 322 ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n", 322 323 cmd, cmd_status); ··· 327 328 return retval; 328 329 } 329 330 330 - static int hpc_check_cmd_status(struct controller *ctrl) 331 + int shpchp_check_cmd_status(struct controller *ctrl) 331 332 { 332 333 int retval = 0; 333 334 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; ··· 356 357 } 357 358 358 359 359 - static int hpc_get_attention_status(struct slot *slot, u8 *status) 360 + int shpchp_get_attention_status(struct slot *slot, u8 *status) 360 361 { 361 362 struct controller *ctrl = slot->ctrl; 362 363 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); ··· 380 381 return 0; 381 382 } 382 383 383 - static int hpc_get_power_status(struct slot *slot, u8 *status) 384 + int shpchp_get_power_status(struct slot *slot, u8 *status) 384 385 { 385 386 struct controller *ctrl = slot->ctrl; 386 387 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); ··· 405 406 } 406 407 407 408 408 - static int hpc_get_latch_status(struct slot *slot, u8 *status) 409 + int shpchp_get_latch_status(struct slot *slot, u8 *status) 409 410 { 410 411 struct controller *ctrl = slot->ctrl; 411 412 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); ··· 415 416 return 0; 416 417 } 417 418 418 - static int hpc_get_adapter_status(struct slot *slot, u8 *status) 419 + int shpchp_get_adapter_status(struct slot *slot, u8 *status) 419 420 { 420 421 struct controller *ctrl = slot->ctrl; 421 422 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); ··· 426 427 return 0; 427 428 } 428 429 429 - static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 430 + int shpchp_get_prog_int(struct slot *slot, u8 *prog_int) 430 431 { 431 432 struct controller *ctrl = slot->ctrl; 432 433 ··· 435 436 return 0; 436 437 } 437 438 438 - static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 439 + int shpchp_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 439 440 { 440 441 int retval = 0; 441 442 struct controller *ctrl = slot->ctrl; ··· 443 444 u8 m66_cap = !!(slot_reg & MHZ66_CAP); 444 445 u8 pi, pcix_cap; 445 446 446 - retval = hpc_get_prog_int(slot, &pi); 447 + retval = shpchp_get_prog_int(slot, &pi); 447 448 if (retval) 448 449 return retval; 449 450 ··· 488 489 return retval; 489 490 } 490 491 491 - static int hpc_query_power_fault(struct slot *slot) 492 + int shpchp_query_power_fault(struct slot *slot) 492 493 { 493 494 struct controller *ctrl = slot->ctrl; 494 495 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); ··· 497 498 return !(slot_reg & POWER_FAULT); 498 499 } 499 500 500 - static int hpc_set_attention_status(struct slot *slot, u8 value) 501 + int shpchp_set_attention_status(struct slot *slot, u8 value) 501 502 { 502 503 u8 slot_cmd = 0; 503 504 ··· 519 520 } 520 521 521 522 522 - static void hpc_set_green_led_on(struct slot *slot) 523 + void shpchp_green_led_on(struct slot *slot) 523 524 { 524 525 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); 525 526 } 526 527 527 - static void hpc_set_green_led_off(struct slot *slot) 528 + void shpchp_green_led_off(struct slot *slot) 528 529 { 529 530 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); 530 531 } 531 532 532 - static void hpc_set_green_led_blink(struct slot *slot) 533 + void shpchp_green_led_blink(struct slot *slot) 533 534 { 534 535 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); 535 536 } 536 537 537 - static void hpc_release_ctlr(struct controller *ctrl) 538 + void shpchp_release_ctlr(struct controller *ctrl) 538 539 { 539 540 int i; 540 541 u32 slot_reg, serr_int; ··· 574 575 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 575 576 } 576 577 577 - static int hpc_power_on_slot(struct slot *slot) 578 + int shpchp_power_on_slot(struct slot *slot) 578 579 { 579 580 int retval; 580 581 ··· 585 586 return retval; 586 587 } 587 588 588 - static int hpc_slot_enable(struct slot *slot) 589 + int shpchp_slot_enable(struct slot *slot) 589 590 { 590 591 int retval; 591 592 ··· 598 599 return retval; 599 600 } 600 601 601 - static int hpc_slot_disable(struct slot *slot) 602 + int shpchp_slot_disable(struct slot *slot) 602 603 { 603 604 int retval; 604 605 ··· 680 681 } 681 682 682 683 683 - static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value) 684 + int shpchp_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value) 684 685 { 685 686 int retval; 686 687 struct controller *ctrl = slot->ctrl; ··· 870 871 return retval; 871 872 } 872 873 873 - static const struct hpc_ops shpchp_hpc_ops = { 874 - .power_on_slot = hpc_power_on_slot, 875 - .slot_enable = hpc_slot_enable, 876 - .slot_disable = hpc_slot_disable, 877 - .set_bus_speed_mode = hpc_set_bus_speed_mode, 878 - .set_attention_status = hpc_set_attention_status, 879 - .get_power_status = hpc_get_power_status, 880 - .get_attention_status = hpc_get_attention_status, 881 - .get_latch_status = hpc_get_latch_status, 882 - .get_adapter_status = hpc_get_adapter_status, 883 - 884 - .get_adapter_speed = hpc_get_adapter_speed, 885 - .get_prog_int = hpc_get_prog_int, 886 - 887 - .query_power_fault = hpc_query_power_fault, 888 - .green_led_on = hpc_set_green_led_on, 889 - .green_led_off = hpc_set_green_led_off, 890 - .green_led_blink = hpc_set_green_led_blink, 891 - 892 - .release_ctlr = hpc_release_ctlr, 893 - }; 894 - 895 874 int shpc_init(struct controller *ctrl, struct pci_dev *pdev) 896 875 { 897 876 int rc = -1, num_slots = 0; ··· 954 977 955 978 /* Setup wait queue */ 956 979 init_waitqueue_head(&ctrl->queue); 957 - 958 - ctrl->hpc_ops = &shpchp_hpc_ops; 959 980 960 981 /* Return PCI Controller Info */ 961 982 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
+1 -1
drivers/pci/iomap.c
··· 156 156 * the different IOMAP ranges. 157 157 * 158 158 * But if the architecture does not use the generic iomap code, and if 159 - * it has _not_ defined it's own private pci_iounmap function, we define 159 + * it has _not_ defined its own private pci_iounmap function, we define 160 160 * it here. 161 161 * 162 162 * NOTE! This default implementation assumes that if the architecture
+595
drivers/pci/npem.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * PCIe Enclosure management driver created for LED interfaces based on 4 + * indications. It says *what indications* blink but does not specify *how* 5 + * they blink - it is hardware defined. 6 + * 7 + * The driver name refers to Native PCIe Enclosure Management. It is 8 + * first indication oriented standard with specification. 9 + * 10 + * Native PCIe Enclosure Management (NPEM) 11 + * PCIe Base Specification r6.1 sec 6.28, 7.9.19 12 + * 13 + * _DSM Definitions for PCIe SSD Status LED 14 + * PCI Firmware Specification, r3.3 sec 4.7 15 + * 16 + * Two backends are supported to manipulate indications: Direct NPEM register 17 + * access (npem_ops) and indirect access through the ACPI _DSM (dsm_ops). 18 + * _DSM is used if supported, else NPEM. 19 + * 20 + * Copyright (c) 2021-2022 Dell Inc. 21 + * Copyright (c) 2023-2024 Intel Corporation 22 + * Mariusz Tkaczyk <mariusz.tkaczyk@linux.intel.com> 23 + */ 24 + 25 + #include <linux/acpi.h> 26 + #include <linux/bitops.h> 27 + #include <linux/errno.h> 28 + #include <linux/iopoll.h> 29 + #include <linux/leds.h> 30 + #include <linux/mutex.h> 31 + #include <linux/pci.h> 32 + #include <linux/pci_regs.h> 33 + #include <linux/types.h> 34 + #include <linux/uleds.h> 35 + 36 + #include "pci.h" 37 + 38 + struct indication { 39 + u32 bit; 40 + const char *name; 41 + }; 42 + 43 + static const struct indication npem_indications[] = { 44 + {PCI_NPEM_IND_OK, "enclosure:ok"}, 45 + {PCI_NPEM_IND_LOCATE, "enclosure:locate"}, 46 + {PCI_NPEM_IND_FAIL, "enclosure:fail"}, 47 + {PCI_NPEM_IND_REBUILD, "enclosure:rebuild"}, 48 + {PCI_NPEM_IND_PFA, "enclosure:pfa"}, 49 + {PCI_NPEM_IND_HOTSPARE, "enclosure:hotspare"}, 50 + {PCI_NPEM_IND_ICA, "enclosure:ica"}, 51 + {PCI_NPEM_IND_IFA, "enclosure:ifa"}, 52 + {PCI_NPEM_IND_IDT, "enclosure:idt"}, 53 + {PCI_NPEM_IND_DISABLED, "enclosure:disabled"}, 54 + {PCI_NPEM_IND_SPEC_0, "enclosure:specific_0"}, 55 + {PCI_NPEM_IND_SPEC_1, "enclosure:specific_1"}, 56 + {PCI_NPEM_IND_SPEC_2, "enclosure:specific_2"}, 57 + {PCI_NPEM_IND_SPEC_3, "enclosure:specific_3"}, 58 + {PCI_NPEM_IND_SPEC_4, "enclosure:specific_4"}, 59 + {PCI_NPEM_IND_SPEC_5, "enclosure:specific_5"}, 60 + {PCI_NPEM_IND_SPEC_6, "enclosure:specific_6"}, 61 + {PCI_NPEM_IND_SPEC_7, "enclosure:specific_7"}, 62 + {0, NULL} 63 + }; 64 + 65 + /* _DSM PCIe SSD LED States correspond to NPEM register values */ 66 + static const struct indication dsm_indications[] = { 67 + {PCI_NPEM_IND_OK, "enclosure:ok"}, 68 + {PCI_NPEM_IND_LOCATE, "enclosure:locate"}, 69 + {PCI_NPEM_IND_FAIL, "enclosure:fail"}, 70 + {PCI_NPEM_IND_REBUILD, "enclosure:rebuild"}, 71 + {PCI_NPEM_IND_PFA, "enclosure:pfa"}, 72 + {PCI_NPEM_IND_HOTSPARE, "enclosure:hotspare"}, 73 + {PCI_NPEM_IND_ICA, "enclosure:ica"}, 74 + {PCI_NPEM_IND_IFA, "enclosure:ifa"}, 75 + {PCI_NPEM_IND_IDT, "enclosure:idt"}, 76 + {PCI_NPEM_IND_DISABLED, "enclosure:disabled"}, 77 + {0, NULL} 78 + }; 79 + 80 + #define for_each_indication(ind, inds) \ 81 + for (ind = inds; ind->bit; ind++) 82 + 83 + /* 84 + * The driver has internal list of supported indications. Ideally, the driver 85 + * should not touch bits that are not defined and for which LED devices are 86 + * not exposed but in reality, it needs to turn them off. 87 + * 88 + * Otherwise, there will be no possibility to turn off indications turned on by 89 + * other utilities or turned on by default and it leads to bad user experience. 90 + * 91 + * Additionally, it excludes NPEM commands like RESET or ENABLE. 92 + */ 93 + static u32 reg_to_indications(u32 caps, const struct indication *inds) 94 + { 95 + const struct indication *ind; 96 + u32 supported_indications = 0; 97 + 98 + for_each_indication(ind, inds) 99 + supported_indications |= ind->bit; 100 + 101 + return caps & supported_indications; 102 + } 103 + 104 + /** 105 + * struct npem_led - LED details 106 + * @indication: indication details 107 + * @npem: NPEM device 108 + * @name: LED name 109 + * @led: LED device 110 + */ 111 + struct npem_led { 112 + const struct indication *indication; 113 + struct npem *npem; 114 + char name[LED_MAX_NAME_SIZE]; 115 + struct led_classdev led; 116 + }; 117 + 118 + /** 119 + * struct npem_ops - backend specific callbacks 120 + * @get_active_indications: get active indications 121 + * npem: NPEM device 122 + * inds: response buffer 123 + * @set_active_indications: set new indications 124 + * npem: npem device 125 + * inds: bit mask to set 126 + * @inds: supported indications array, set of indications is backend specific 127 + * @name: backend name 128 + */ 129 + struct npem_ops { 130 + int (*get_active_indications)(struct npem *npem, u32 *inds); 131 + int (*set_active_indications)(struct npem *npem, u32 inds); 132 + const struct indication *inds; 133 + const char *name; 134 + }; 135 + 136 + /** 137 + * struct npem - NPEM device properties 138 + * @dev: PCI device this driver is attached to 139 + * @ops: backend specific callbacks 140 + * @lock: serializes concurrent access to NPEM device by multiple LED devices 141 + * @pos: cached offset of NPEM Capability Register in Configuration Space; 142 + * only used if NPEM registers are accessed directly and not through _DSM 143 + * @supported_indications: cached bit mask of supported indications; 144 + * non-indication and reserved bits in the NPEM Capability Register are 145 + * cleared in this bit mask 146 + * @active_indications: cached bit mask of active indications; 147 + * non-indication and reserved bits in the NPEM Control Register are 148 + * cleared in this bit mask 149 + * @active_inds_initialized: whether @active_indications has been initialized; 150 + * On Dell platforms, it is required that IPMI drivers are loaded before 151 + * the GET_STATE_DSM method is invoked: They use an IPMI OpRegion to 152 + * get/set the active LEDs. By initializing @active_indications lazily 153 + * (on first access to an LED), IPMI drivers are given a chance to load. 154 + * If they are not loaded in time, users will see various errors on LED 155 + * access in dmesg. Once they are loaded, the errors go away and LED 156 + * access becomes possible. 157 + * @led_cnt: size of @leds array 158 + * @leds: array containing LED class devices of all supported LEDs 159 + */ 160 + struct npem { 161 + struct pci_dev *dev; 162 + const struct npem_ops *ops; 163 + struct mutex lock; 164 + u16 pos; 165 + u32 supported_indications; 166 + u32 active_indications; 167 + unsigned int active_inds_initialized:1; 168 + int led_cnt; 169 + struct npem_led leds[]; 170 + }; 171 + 172 + static int npem_read_reg(struct npem *npem, u16 reg, u32 *val) 173 + { 174 + int ret = pci_read_config_dword(npem->dev, npem->pos + reg, val); 175 + 176 + return pcibios_err_to_errno(ret); 177 + } 178 + 179 + static int npem_write_ctrl(struct npem *npem, u32 reg) 180 + { 181 + int pos = npem->pos + PCI_NPEM_CTRL; 182 + int ret = pci_write_config_dword(npem->dev, pos, reg); 183 + 184 + return pcibios_err_to_errno(ret); 185 + } 186 + 187 + static int npem_get_active_indications(struct npem *npem, u32 *inds) 188 + { 189 + u32 ctrl; 190 + int ret; 191 + 192 + ret = npem_read_reg(npem, PCI_NPEM_CTRL, &ctrl); 193 + if (ret) 194 + return ret; 195 + 196 + /* If PCI_NPEM_CTRL_ENABLE is not set then no indication should blink */ 197 + if (!(ctrl & PCI_NPEM_CTRL_ENABLE)) { 198 + *inds = 0; 199 + return 0; 200 + } 201 + 202 + *inds = ctrl & npem->supported_indications; 203 + 204 + return 0; 205 + } 206 + 207 + static int npem_set_active_indications(struct npem *npem, u32 inds) 208 + { 209 + int ctrl, ret, ret_val; 210 + u32 cc_status; 211 + 212 + lockdep_assert_held(&npem->lock); 213 + 214 + /* This bit is always required */ 215 + ctrl = inds | PCI_NPEM_CTRL_ENABLE; 216 + 217 + ret = npem_write_ctrl(npem, ctrl); 218 + if (ret) 219 + return ret; 220 + 221 + /* 222 + * For the case where a NPEM command has not completed immediately, 223 + * it is recommended that software not continuously "spin" on polling 224 + * the status register, but rather poll under interrupt at a reduced 225 + * rate; for example at 10 ms intervals. 226 + * 227 + * PCIe r6.1 sec 6.28 "Implementation Note: Software Polling of NPEM 228 + * Command Completed" 229 + */ 230 + ret = read_poll_timeout(npem_read_reg, ret_val, 231 + ret_val || (cc_status & PCI_NPEM_STATUS_CC), 232 + 10 * USEC_PER_MSEC, USEC_PER_SEC, false, npem, 233 + PCI_NPEM_STATUS, &cc_status); 234 + if (ret) 235 + return ret; 236 + if (ret_val) 237 + return ret_val; 238 + 239 + /* 240 + * All writes to control register, including writes that do not change 241 + * the register value, are NPEM commands and should eventually result 242 + * in a command completion indication in the NPEM Status Register. 243 + * 244 + * PCIe Base Specification r6.1 sec 7.9.19.3 245 + * 246 + * Register may not be updated, or other conflicting bits may be 247 + * cleared. Spec is not strict here. Read NPEM Control register after 248 + * write to keep cache in-sync. 249 + */ 250 + return npem_get_active_indications(npem, &npem->active_indications); 251 + } 252 + 253 + static const struct npem_ops npem_ops = { 254 + .get_active_indications = npem_get_active_indications, 255 + .set_active_indications = npem_set_active_indications, 256 + .name = "Native PCIe Enclosure Management", 257 + .inds = npem_indications, 258 + }; 259 + 260 + #define DSM_GUID GUID_INIT(0x5d524d9d, 0xfff9, 0x4d4b, 0x8c, 0xb7, 0x74, 0x7e,\ 261 + 0xd5, 0x1e, 0x19, 0x4d) 262 + #define GET_SUPPORTED_STATES_DSM 1 263 + #define GET_STATE_DSM 2 264 + #define SET_STATE_DSM 3 265 + 266 + static const guid_t dsm_guid = DSM_GUID; 267 + 268 + static bool npem_has_dsm(struct pci_dev *pdev) 269 + { 270 + acpi_handle handle; 271 + 272 + handle = ACPI_HANDLE(&pdev->dev); 273 + if (!handle) 274 + return false; 275 + 276 + return acpi_check_dsm(handle, &dsm_guid, 0x1, 277 + BIT(GET_SUPPORTED_STATES_DSM) | 278 + BIT(GET_STATE_DSM) | BIT(SET_STATE_DSM)); 279 + } 280 + 281 + struct dsm_output { 282 + u16 status; 283 + u8 function_specific_err; 284 + u8 vendor_specific_err; 285 + u32 state; 286 + }; 287 + 288 + /** 289 + * dsm_evaluate() - send DSM PCIe SSD Status LED command 290 + * @pdev: PCI device 291 + * @dsm_func: DSM LED Function 292 + * @output: buffer to copy DSM Response 293 + * @value_to_set: value for SET_STATE_DSM function 294 + * 295 + * To not bother caller with ACPI context, the returned _DSM Output Buffer is 296 + * copied. 297 + */ 298 + static int dsm_evaluate(struct pci_dev *pdev, u64 dsm_func, 299 + struct dsm_output *output, u32 value_to_set) 300 + { 301 + acpi_handle handle = ACPI_HANDLE(&pdev->dev); 302 + union acpi_object *out_obj, arg3[2]; 303 + union acpi_object *arg3_p = NULL; 304 + 305 + if (dsm_func == SET_STATE_DSM) { 306 + arg3[0].type = ACPI_TYPE_PACKAGE; 307 + arg3[0].package.count = 1; 308 + arg3[0].package.elements = &arg3[1]; 309 + 310 + arg3[1].type = ACPI_TYPE_BUFFER; 311 + arg3[1].buffer.length = 4; 312 + arg3[1].buffer.pointer = (u8 *)&value_to_set; 313 + 314 + arg3_p = arg3; 315 + } 316 + 317 + out_obj = acpi_evaluate_dsm_typed(handle, &dsm_guid, 0x1, dsm_func, 318 + arg3_p, ACPI_TYPE_BUFFER); 319 + if (!out_obj) 320 + return -EIO; 321 + 322 + if (out_obj->buffer.length < sizeof(struct dsm_output)) { 323 + ACPI_FREE(out_obj); 324 + return -EIO; 325 + } 326 + 327 + memcpy(output, out_obj->buffer.pointer, sizeof(struct dsm_output)); 328 + 329 + ACPI_FREE(out_obj); 330 + return 0; 331 + } 332 + 333 + static int dsm_get(struct pci_dev *pdev, u64 dsm_func, u32 *buf) 334 + { 335 + struct dsm_output output; 336 + int ret = dsm_evaluate(pdev, dsm_func, &output, 0); 337 + 338 + if (ret) 339 + return ret; 340 + 341 + if (output.status != 0) 342 + return -EIO; 343 + 344 + *buf = output.state; 345 + return 0; 346 + } 347 + 348 + static int dsm_get_active_indications(struct npem *npem, u32 *buf) 349 + { 350 + int ret = dsm_get(npem->dev, GET_STATE_DSM, buf); 351 + 352 + /* Filter out not supported indications in response */ 353 + *buf &= npem->supported_indications; 354 + return ret; 355 + } 356 + 357 + static int dsm_set_active_indications(struct npem *npem, u32 value) 358 + { 359 + struct dsm_output output; 360 + int ret = dsm_evaluate(npem->dev, SET_STATE_DSM, &output, value); 361 + 362 + if (ret) 363 + return ret; 364 + 365 + switch (output.status) { 366 + case 4: 367 + /* 368 + * Not all bits are set. If this bit is set, the platform 369 + * disregarded some or all of the request state changes. OSPM 370 + * should check the resulting PCIe SSD Status LED States to see 371 + * what, if anything, has changed. 372 + * 373 + * PCI Firmware Specification, r3.3 Table 4-19. 374 + */ 375 + if (output.function_specific_err != 1) 376 + return -EIO; 377 + fallthrough; 378 + case 0: 379 + break; 380 + default: 381 + return -EIO; 382 + } 383 + 384 + npem->active_indications = output.state; 385 + 386 + return 0; 387 + } 388 + 389 + static const struct npem_ops dsm_ops = { 390 + .get_active_indications = dsm_get_active_indications, 391 + .set_active_indications = dsm_set_active_indications, 392 + .name = "_DSM PCIe SSD Status LED Management", 393 + .inds = dsm_indications, 394 + }; 395 + 396 + static int npem_initialize_active_indications(struct npem *npem) 397 + { 398 + int ret; 399 + 400 + lockdep_assert_held(&npem->lock); 401 + 402 + if (npem->active_inds_initialized) 403 + return 0; 404 + 405 + ret = npem->ops->get_active_indications(npem, 406 + &npem->active_indications); 407 + if (ret) 408 + return ret; 409 + 410 + npem->active_inds_initialized = true; 411 + return 0; 412 + } 413 + 414 + /* 415 + * The status of each indicator is cached on first brightness_ get/set time 416 + * and updated at write time. brightness_get() is only responsible for 417 + * reflecting the last written/cached value. 418 + */ 419 + static enum led_brightness brightness_get(struct led_classdev *led) 420 + { 421 + struct npem_led *nled = container_of(led, struct npem_led, led); 422 + struct npem *npem = nled->npem; 423 + int ret, val = 0; 424 + 425 + ret = mutex_lock_interruptible(&npem->lock); 426 + if (ret) 427 + return ret; 428 + 429 + ret = npem_initialize_active_indications(npem); 430 + if (ret) 431 + goto out; 432 + 433 + if (npem->active_indications & nled->indication->bit) 434 + val = 1; 435 + 436 + out: 437 + mutex_unlock(&npem->lock); 438 + return val; 439 + } 440 + 441 + static int brightness_set(struct led_classdev *led, 442 + enum led_brightness brightness) 443 + { 444 + struct npem_led *nled = container_of(led, struct npem_led, led); 445 + struct npem *npem = nled->npem; 446 + u32 indications; 447 + int ret; 448 + 449 + ret = mutex_lock_interruptible(&npem->lock); 450 + if (ret) 451 + return ret; 452 + 453 + ret = npem_initialize_active_indications(npem); 454 + if (ret) 455 + goto out; 456 + 457 + if (brightness == 0) 458 + indications = npem->active_indications & ~(nled->indication->bit); 459 + else 460 + indications = npem->active_indications | nled->indication->bit; 461 + 462 + ret = npem->ops->set_active_indications(npem, indications); 463 + 464 + out: 465 + mutex_unlock(&npem->lock); 466 + return ret; 467 + } 468 + 469 + static void npem_free(struct npem *npem) 470 + { 471 + struct npem_led *nled; 472 + int cnt; 473 + 474 + if (!npem) 475 + return; 476 + 477 + for (cnt = 0; cnt < npem->led_cnt; cnt++) { 478 + nled = &npem->leds[cnt]; 479 + 480 + if (nled->name[0]) 481 + led_classdev_unregister(&nled->led); 482 + } 483 + 484 + mutex_destroy(&npem->lock); 485 + kfree(npem); 486 + } 487 + 488 + static int pci_npem_set_led_classdev(struct npem *npem, struct npem_led *nled) 489 + { 490 + struct led_classdev *led = &nled->led; 491 + struct led_init_data init_data = {}; 492 + char *name = nled->name; 493 + int ret; 494 + 495 + init_data.devicename = pci_name(npem->dev); 496 + init_data.default_label = nled->indication->name; 497 + 498 + ret = led_compose_name(&npem->dev->dev, &init_data, name); 499 + if (ret) 500 + return ret; 501 + 502 + led->name = name; 503 + led->brightness_set_blocking = brightness_set; 504 + led->brightness_get = brightness_get; 505 + led->max_brightness = 1; 506 + led->default_trigger = "none"; 507 + led->flags = 0; 508 + 509 + ret = led_classdev_register(&npem->dev->dev, led); 510 + if (ret) 511 + /* Clear the name to indicate that it is not registered. */ 512 + name[0] = 0; 513 + return ret; 514 + } 515 + 516 + static int pci_npem_init(struct pci_dev *dev, const struct npem_ops *ops, 517 + int pos, u32 caps) 518 + { 519 + u32 supported = reg_to_indications(caps, ops->inds); 520 + int supported_cnt = hweight32(supported); 521 + const struct indication *indication; 522 + struct npem_led *nled; 523 + struct npem *npem; 524 + int led_idx = 0; 525 + int ret; 526 + 527 + npem = kzalloc(struct_size(npem, leds, supported_cnt), GFP_KERNEL); 528 + if (!npem) 529 + return -ENOMEM; 530 + 531 + npem->supported_indications = supported; 532 + npem->led_cnt = supported_cnt; 533 + npem->pos = pos; 534 + npem->dev = dev; 535 + npem->ops = ops; 536 + 537 + mutex_init(&npem->lock); 538 + 539 + for_each_indication(indication, npem_indications) { 540 + if (!(npem->supported_indications & indication->bit)) 541 + continue; 542 + 543 + nled = &npem->leds[led_idx++]; 544 + nled->indication = indication; 545 + nled->npem = npem; 546 + 547 + ret = pci_npem_set_led_classdev(npem, nled); 548 + if (ret) { 549 + npem_free(npem); 550 + return ret; 551 + } 552 + } 553 + 554 + dev->npem = npem; 555 + return 0; 556 + } 557 + 558 + void pci_npem_remove(struct pci_dev *dev) 559 + { 560 + npem_free(dev->npem); 561 + } 562 + 563 + void pci_npem_create(struct pci_dev *dev) 564 + { 565 + const struct npem_ops *ops = &npem_ops; 566 + int pos = 0, ret; 567 + u32 cap; 568 + 569 + if (npem_has_dsm(dev)) { 570 + /* 571 + * OS should use the DSM for LED control if it is available 572 + * PCI Firmware Spec r3.3 sec 4.7. 573 + */ 574 + ret = dsm_get(dev, GET_SUPPORTED_STATES_DSM, &cap); 575 + if (ret) 576 + return; 577 + 578 + ops = &dsm_ops; 579 + } else { 580 + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_NPEM); 581 + if (pos == 0) 582 + return; 583 + 584 + if (pci_read_config_dword(dev, pos + PCI_NPEM_CAP, &cap) != 0 || 585 + (cap & PCI_NPEM_CAP_CAPABLE) == 0) 586 + return; 587 + } 588 + 589 + pci_info(dev, "Configuring %s\n", ops->name); 590 + 591 + ret = pci_npem_init(dev, ops, pos, cap); 592 + if (ret) 593 + pci_err(dev, "Failed to register %s, err: %d\n", ops->name, 594 + ret); 595 + }
+2 -2
drivers/pci/pci-bridge-emul.c
··· 257 257 */ 258 258 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 259 259 PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE | 260 - PCI_EXP_RTCTL_CRSSVE), 261 - .ro = PCI_EXP_RTCAP_CRSVIS << 16, 260 + PCI_EXP_RTCTL_RRS_SVE), 261 + .ro = PCI_EXP_RTCAP_RRS_SV << 16, 262 262 }, 263 263 264 264 [PCI_EXP_RTSTA / 4] = {
+1 -1
drivers/pci/pci-driver.c
··· 1670 1670 iommu_device_unuse_default_domain(dev); 1671 1671 } 1672 1672 1673 - struct bus_type pci_bus_type = { 1673 + const struct bus_type pci_bus_type = { 1674 1674 .name = "pci", 1675 1675 .match = pci_bus_match, 1676 1676 .uevent = pci_uevent,
+5
drivers/pci/pci-sysfs.c
··· 31 31 #include <linux/aperture.h> 32 32 #include "pci.h" 33 33 34 + #ifndef ARCH_PCI_DEV_GROUPS 35 + #define ARCH_PCI_DEV_GROUPS 36 + #endif 37 + 34 38 static int sysfs_initialized; /* = 0 */ 35 39 36 40 /* show configuration fields */ ··· 1628 1624 &pci_dev_acpi_attr_group, 1629 1625 #endif 1630 1626 &pci_dev_resource_resize_group, 1627 + ARCH_PCI_DEV_GROUPS 1631 1628 NULL, 1632 1629 }; 1633 1630
+51 -24
drivers/pci/pci.c
··· 1283 1283 { 1284 1284 int delay = 1; 1285 1285 bool retrain = false; 1286 - struct pci_dev *bridge; 1286 + struct pci_dev *root, *bridge; 1287 + 1288 + root = pcie_find_root_port(dev); 1287 1289 1288 1290 if (pci_is_pcie(dev)) { 1289 1291 bridge = pci_upstream_bridge(dev); ··· 1294 1292 } 1295 1293 1296 1294 /* 1297 - * After reset, the device should not silently discard config 1298 - * requests, but it may still indicate that it needs more time by 1299 - * responding to them with CRS completions. The Root Port will 1300 - * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete 1301 - * the read (except when CRS SV is enabled and the read was for the 1302 - * Vendor ID; in that case it synthesizes 0x0001 data). 1295 + * The caller has already waited long enough after a reset that the 1296 + * device should respond to config requests, but it may respond 1297 + * with Request Retry Status (RRS) if it needs more time to 1298 + * initialize. 1303 1299 * 1304 - * Wait for the device to return a non-CRS completion. Read the 1305 - * Command register instead of Vendor ID so we don't have to 1306 - * contend with the CRS SV value. 1300 + * If the device is below a Root Port with Configuration RRS 1301 + * Software Visibility enabled, reading the Vendor ID returns a 1302 + * special data value if the device responded with RRS. Read the 1303 + * Vendor ID until we get non-RRS status. 1304 + * 1305 + * If there's no Root Port or Configuration RRS Software Visibility 1306 + * is not enabled, the device may still respond with RRS, but 1307 + * hardware may retry the config request. If no retries receive 1308 + * Successful Completion, hardware generally synthesizes ~0 1309 + * (PCI_ERROR_RESPONSE) data to complete the read. Reading Vendor 1310 + * ID for VFs and non-existent devices also returns ~0, so read the 1311 + * Command register until it returns something other than ~0. 1307 1312 */ 1308 1313 for (;;) { 1309 1314 u32 id; ··· 1320 1311 return -ENOTTY; 1321 1312 } 1322 1313 1323 - pci_read_config_dword(dev, PCI_COMMAND, &id); 1324 - if (!PCI_POSSIBLE_ERROR(id)) 1325 - break; 1314 + if (root && root->config_rrs_sv) { 1315 + pci_read_config_dword(dev, PCI_VENDOR_ID, &id); 1316 + if (!pci_bus_rrs_vendor_id(id)) 1317 + break; 1318 + } else { 1319 + pci_read_config_dword(dev, PCI_COMMAND, &id); 1320 + if (!PCI_POSSIBLE_ERROR(id)) 1321 + break; 1322 + } 1326 1323 1327 1324 if (delay > timeout) { 1328 1325 pci_warn(dev, "not ready %dms after %s; giving up\n", ··· 1339 1324 if (delay > PCI_RESET_WAIT) { 1340 1325 if (retrain) { 1341 1326 retrain = false; 1342 - if (pcie_failed_link_retrain(bridge)) { 1327 + if (pcie_failed_link_retrain(bridge) == 0) { 1343 1328 delay = 1; 1344 1329 continue; 1345 1330 } ··· 4733 4718 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_RL); 4734 4719 } 4735 4720 4736 - return pcie_wait_for_link_status(pdev, use_lt, !use_lt); 4721 + rc = pcie_wait_for_link_status(pdev, use_lt, !use_lt); 4722 + 4723 + /* 4724 + * Clear LBMS after a manual retrain so that the bit can be used 4725 + * to track link speed or width changes made by hardware itself 4726 + * in attempt to correct unreliable link operation. 4727 + */ 4728 + pcie_capability_write_word(pdev, PCI_EXP_LNKSTA, PCI_EXP_LNKSTA_LBMS); 4729 + return rc; 4737 4730 } 4738 4731 4739 4732 /** ··· 5695 5672 5696 5673 list_for_each_entry(dev, &bus->devices, bus_list) { 5697 5674 pci_dev_restore(dev); 5698 - if (dev->subordinate) 5675 + if (dev->subordinate) { 5676 + pci_bridge_wait_for_secondary_bus(dev, "bus reset"); 5699 5677 pci_bus_restore_locked(dev->subordinate); 5678 + } 5700 5679 } 5701 5680 } 5702 5681 ··· 5732 5707 if (!dev->slot || dev->slot != slot) 5733 5708 continue; 5734 5709 pci_dev_restore(dev); 5735 - if (dev->subordinate) 5710 + if (dev->subordinate) { 5711 + pci_bridge_wait_for_secondary_bus(dev, "slot reset"); 5736 5712 pci_bus_restore_locked(dev->subordinate); 5713 + } 5737 5714 } 5738 5715 } 5739 5716 ··· 6829 6802 return ida_alloc(&pci_domain_nr_dynamic_ida, GFP_KERNEL); 6830 6803 } 6831 6804 6832 - static void of_pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent) 6805 + static void of_pci_bus_release_domain_nr(struct device *parent, int domain_nr) 6833 6806 { 6834 - if (bus->domain_nr < 0) 6807 + if (domain_nr < 0) 6835 6808 return; 6836 6809 6837 6810 /* Release domain from IDA where it was allocated. */ 6838 - if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr) 6839 - ida_free(&pci_domain_nr_static_ida, bus->domain_nr); 6811 + if (of_get_pci_domain_nr(parent->of_node) == domain_nr) 6812 + ida_free(&pci_domain_nr_static_ida, domain_nr); 6840 6813 else 6841 - ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr); 6814 + ida_free(&pci_domain_nr_dynamic_ida, domain_nr); 6842 6815 } 6843 6816 6844 6817 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) ··· 6847 6820 acpi_pci_bus_find_domain_nr(bus); 6848 6821 } 6849 6822 6850 - void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent) 6823 + void pci_bus_release_domain_nr(struct device *parent, int domain_nr) 6851 6824 { 6852 6825 if (!acpi_disabled) 6853 6826 return; 6854 - of_pci_bus_release_domain_nr(bus, parent); 6827 + of_pci_bus_release_domain_nr(parent, domain_nr); 6855 6828 } 6856 6829 #endif 6857 6830
+35 -11
drivers/pci/pci.h
··· 13 13 14 14 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 15 15 16 - /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */ 16 + /* 17 + * Power stable to PERST# inactive. 18 + * 19 + * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 20 + * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 21 + * "T_PVPERL". 22 + */ 17 23 #define PCIE_T_PVPERL_MS 100 24 + 25 + /* 26 + * REFCLK stable before PERST# inactive. 27 + * 28 + * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 29 + * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 30 + * "T_PERST-CLK". 31 + */ 32 + #define PCIE_T_PERST_CLK_US 100 18 33 19 34 /* 20 35 * End of conventional reset (PERST# de-asserted) to first configuration ··· 139 124 void pcie_clear_root_pme_status(struct pci_dev *dev); 140 125 bool pci_check_pme_status(struct pci_dev *dev); 141 126 void pci_pme_wakeup_bus(struct pci_bus *bus); 142 - int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 143 127 void pci_pme_restore(struct pci_dev *dev); 144 128 bool pci_dev_need_resume(struct pci_dev *dev); 145 129 void pci_dev_adjust_pme(struct pci_dev *dev); ··· 152 138 bool pci_bridge_d3_possible(struct pci_dev *dev); 153 139 void pci_bridge_d3_update(struct pci_dev *dev); 154 140 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 141 + 142 + static inline bool pci_bus_rrs_vendor_id(u32 l) 143 + { 144 + return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 145 + } 155 146 156 147 static inline void pci_wakeup_event(struct pci_dev *dev) 157 148 { ··· 188 169 } 189 170 190 171 void pci_vpd_init(struct pci_dev *dev); 191 - void pci_vpd_release(struct pci_dev *dev); 192 172 extern const struct attribute_group pci_dev_vpd_attr_group; 193 173 194 174 /* PCI Virtual Channel */ ··· 308 290 309 291 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 310 292 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 311 - int crs_timeout); 293 + int rrs_timeout); 312 294 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 313 - int crs_timeout); 314 - int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 295 + int rrs_timeout); 296 + int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout); 315 297 316 298 int pci_setup_device(struct pci_dev *dev); 317 299 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, ··· 414 396 static inline void pci_doe_init(struct pci_dev *pdev) { } 415 397 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 416 398 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 399 + #endif 400 + 401 + #ifdef CONFIG_PCI_NPEM 402 + void pci_npem_create(struct pci_dev *dev); 403 + void pci_npem_remove(struct pci_dev *dev); 404 + #else 405 + static inline void pci_npem_create(struct pci_dev *dev) { } 406 + static inline void pci_npem_remove(struct pci_dev *dev) { } 417 407 #endif 418 408 419 409 /** ··· 632 606 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 633 607 int pci_dev_specific_enable_acs(struct pci_dev *dev); 634 608 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 635 - bool pcie_failed_link_retrain(struct pci_dev *dev); 609 + int pcie_failed_link_retrain(struct pci_dev *dev); 636 610 #else 637 611 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 638 612 u16 acs_flags) ··· 647 621 { 648 622 return -ENOTTY; 649 623 } 650 - static inline bool pcie_failed_link_retrain(struct pci_dev *dev) 624 + static inline int pcie_failed_link_retrain(struct pci_dev *dev) 651 625 { 652 - return false; 626 + return -ENOTTY; 653 627 } 654 628 #endif 655 629 ··· 913 887 #endif 914 888 915 889 int pcim_intx(struct pci_dev *dev, int enable); 916 - 917 - int pcim_request_region(struct pci_dev *pdev, int bar, const char *name); 918 890 int pcim_request_region_exclusive(struct pci_dev *pdev, int bar, 919 891 const char *name); 920 892 void pcim_release_region(struct pci_dev *pdev, int bar);
+2 -2
drivers/pci/pcie/aer_inject.c
··· 430 430 else 431 431 rperr->root_status |= PCI_ERR_ROOT_COR_RCV; 432 432 rperr->source_id &= 0xffff0000; 433 - rperr->source_id |= (einj->bus << 8) | devfn; 433 + rperr->source_id |= PCI_DEVID(einj->bus, devfn); 434 434 } 435 435 if (einj->uncor_status) { 436 436 if (rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV) ··· 443 443 rperr->root_status |= PCI_ERR_ROOT_NONFATAL_RCV; 444 444 rperr->root_status |= PCI_ERR_ROOT_UNCOR_RCV; 445 445 rperr->source_id &= 0x0000ffff; 446 - rperr->source_id |= ((einj->bus << 8) | devfn) << 16; 446 + rperr->source_id |= PCI_DEVID(einj->bus, devfn) << 16; 447 447 } 448 448 spin_unlock_irqrestore(&inject_lock, flags); 449 449
+18 -19
drivers/pci/probe.c
··· 1061 1061 1062 1062 free: 1063 1063 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1064 - pci_bus_release_domain_nr(bus, parent); 1064 + pci_bus_release_domain_nr(parent, bus->domain_nr); 1065 1065 #endif 1066 1066 kfree(bus); 1067 1067 return err; ··· 1203 1203 } 1204 1204 EXPORT_SYMBOL(pci_add_new_bus); 1205 1205 1206 - static void pci_enable_crs(struct pci_dev *pdev) 1206 + static void pci_enable_rrs_sv(struct pci_dev *pdev) 1207 1207 { 1208 1208 u16 root_cap = 0; 1209 1209 1210 - /* Enable CRS Software Visibility if supported */ 1210 + /* Enable Configuration RRS Software Visibility if supported */ 1211 1211 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1212 - if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1212 + if (root_cap & PCI_EXP_RTCAP_RRS_SV) { 1213 1213 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1214 - PCI_EXP_RTCTL_CRSSVE); 1214 + PCI_EXP_RTCTL_RRS_SVE); 1215 + pdev->config_rrs_sv = 1; 1216 + } 1215 1217 } 1216 1218 1217 1219 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, ··· 1328 1326 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1329 1327 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1330 1328 1331 - pci_enable_crs(dev); 1329 + pci_enable_rrs_sv(dev); 1332 1330 1333 1331 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1334 1332 !is_cardbus && !broken) { ··· 2345 2343 } 2346 2344 EXPORT_SYMBOL(pci_alloc_dev); 2347 2345 2348 - static bool pci_bus_crs_vendor_id(u32 l) 2349 - { 2350 - return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 2351 - } 2352 - 2353 - static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2346 + static bool pci_bus_wait_rrs(struct pci_bus *bus, int devfn, u32 *l, 2354 2347 int timeout) 2355 2348 { 2356 2349 int delay = 1; 2357 2350 2358 - if (!pci_bus_crs_vendor_id(*l)) 2359 - return true; /* not a CRS completion */ 2351 + if (!pci_bus_rrs_vendor_id(*l)) 2352 + return true; /* not a Configuration RRS completion */ 2360 2353 2361 2354 if (!timeout) 2362 - return false; /* CRS, but caller doesn't want to wait */ 2355 + return false; /* RRS, but caller doesn't want to wait */ 2363 2356 2364 2357 /* 2365 2358 * We got the reserved Vendor ID that indicates a completion with 2366 - * Configuration Request Retry Status (CRS). Retry until we get a 2359 + * Configuration Request Retry Status (RRS). Retry until we get a 2367 2360 * valid Vendor ID or we time out. 2368 2361 */ 2369 - while (pci_bus_crs_vendor_id(*l)) { 2362 + while (pci_bus_rrs_vendor_id(*l)) { 2370 2363 if (delay > timeout) { 2371 2364 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2372 2365 pci_domain_nr(bus), bus->number, ··· 2400 2403 *l == 0x0000ffff || *l == 0xffff0000) 2401 2404 return false; 2402 2405 2403 - if (pci_bus_crs_vendor_id(*l)) 2404 - return pci_bus_wait_crs(bus, devfn, l, timeout); 2406 + if (pci_bus_rrs_vendor_id(*l)) 2407 + return pci_bus_wait_rrs(bus, devfn, l, timeout); 2405 2408 2406 2409 return true; 2407 2410 } ··· 2590 2593 dev->match_driver = false; 2591 2594 ret = device_add(&dev->dev); 2592 2595 WARN_ON(ret < 0); 2596 + 2597 + pci_npem_create(dev); 2593 2598 } 2594 2599 2595 2600 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
+5
drivers/pci/pwrctl/pci-pwrctl-pwrseq.c
··· 67 67 .data = "wlan", 68 68 }, 69 69 { 70 + /* ATH11K in WCN6855 package. */ 71 + .compatible = "pci17cb,1103", 72 + .data = "wlan", 73 + }, 74 + { 70 75 /* ATH12K in WCN7850 package. */ 71 76 .compatible = "pci17cb,1107", 72 77 .data = "wlan",
+30 -9
drivers/pci/quirks.c
··· 66 66 * apply this erratum workaround to any downstream ports as long as they 67 67 * support Link Active reporting and have the Link Control 2 register. 68 68 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 69 - * request a retrain and wait 200ms for the data link to go up. 69 + * request a retrain and check the result. 70 70 * 71 71 * If this turns out successful and we know by the Vendor:Device ID it is 72 72 * safe to do so, then lift the restriction, letting the devices negotiate ··· 74 74 * firmware may have already arranged and lift it with ports that already 75 75 * report their data link being up. 76 76 * 77 - * Return TRUE if the link has been successfully retrained, otherwise FALSE. 77 + * Otherwise revert the speed to the original setting and request a retrain 78 + * again to remove any residual state, ignoring the result as it's supposed 79 + * to fail anyway. 80 + * 81 + * Return 0 if the link has been successfully retrained. Return an error 82 + * if retraining was not needed or we attempted a retrain and it failed. 78 83 */ 79 - bool pcie_failed_link_retrain(struct pci_dev *dev) 84 + int pcie_failed_link_retrain(struct pci_dev *dev) 80 85 { 81 86 static const struct pci_device_id ids[] = { 82 87 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ 83 88 {} 84 89 }; 85 90 u16 lnksta, lnkctl2; 91 + int ret = -ENOTTY; 86 92 87 93 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 88 94 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 89 - return false; 95 + return ret; 90 96 91 97 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 92 98 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 93 99 if ((lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) == 94 100 PCI_EXP_LNKSTA_LBMS) { 101 + u16 oldlnkctl2 = lnkctl2; 102 + 95 103 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 96 104 97 105 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 98 106 lnkctl2 |= PCI_EXP_LNKCTL2_TLS_2_5GT; 99 107 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); 100 108 101 - if (pcie_retrain_link(dev, false)) { 109 + ret = pcie_retrain_link(dev, false); 110 + if (ret) { 102 111 pci_info(dev, "retraining failed\n"); 103 - return false; 112 + pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, 113 + oldlnkctl2); 114 + pcie_retrain_link(dev, true); 115 + return ret; 104 116 } 105 117 106 118 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); ··· 129 117 lnkctl2 |= lnkcap & PCI_EXP_LNKCAP_SLS; 130 118 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); 131 119 132 - if (pcie_retrain_link(dev, false)) { 120 + ret = pcie_retrain_link(dev, false); 121 + if (ret) { 133 122 pci_info(dev, "retraining failed\n"); 134 - return false; 123 + return ret; 135 124 } 136 125 } 137 126 138 - return true; 127 + return ret; 139 128 } 140 129 141 130 static ktime_t fixup_debug_start(struct pci_dev *dev, ··· 3621 3608 quirk_broken_intx_masking); 3622 3609 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3623 3610 quirk_broken_intx_masking); 3611 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2, 3612 + quirk_broken_intx_masking); 3624 3613 3625 3614 /* 3626 3615 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) ··· 4260 4245 */ 4261 4246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4262 4247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4248 + 4249 + /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */ 4250 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias); 4251 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias); 4263 4252 4264 4253 static void quirk_dma_func1_alias(struct pci_dev *dev) 4265 4254 { ··· 5089 5070 /* QCOM QDF2xxx root ports */ 5090 5071 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5091 5072 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5073 + /* QCOM SA8775P root port */ 5074 + { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, 5092 5075 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5093 5076 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5094 5077 /* Intel PCH root ports */
+3 -1
drivers/pci/remove.c
··· 50 50 if (!dev->dev.kobj.parent) 51 51 return; 52 52 53 + pci_npem_remove(dev); 54 + 53 55 device_del(&dev->dev); 54 56 55 57 down_write(&pci_bus_sem); ··· 181 179 #ifdef CONFIG_PCI_DOMAINS_GENERIC 182 180 /* Release domain_nr if it was dynamically allocated */ 183 181 if (host_bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 184 - pci_bus_release_domain_nr(bus, host_bridge->dev.parent); 182 + pci_bus_release_domain_nr(host_bridge->dev.parent, bus->domain_nr); 185 183 #endif 186 184 187 185 pci_remove_bus(bus);
+1 -1
include/linux/bcma/bcma_driver_pci.h
··· 203 203 #define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840 204 204 205 205 /* PCIE Root Capability Register bits (Host mode only) */ 206 - #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001 206 + #define BCMA_CORE_PCI_RC_RRS_VISIBILITY 0x0001 207 207 208 208 struct bcma_drv_pci; 209 209 struct bcma_bus;
+2
include/linux/msi.h
··· 554 554 MSI_FLAG_MSIX_CONTIGUOUS = (1 << 19), 555 555 /* PCI/MSI-X vectors can be dynamically allocated/freed post MSI-X enable */ 556 556 MSI_FLAG_PCI_MSIX_ALLOC_DYN = (1 << 20), 557 + /* PCI MSIs cannot be steered separately to CPU cores */ 558 + MSI_FLAG_NO_AFFINITY = (1 << 21), 557 559 }; 558 560 559 561 /**
+3
include/linux/pci-epc.h
··· 128 128 * @group: configfs group representing the PCI EPC device 129 129 * @lock: mutex to protect pci_epc ops 130 130 * @function_num_map: bitmap to manage physical function number 131 + * @domain_nr: PCI domain number of the endpoint controller 131 132 * @init_complete: flag to indicate whether the EPC initialization is complete 132 133 * or not 133 134 */ ··· 146 145 /* mutex to protect against concurrent access of EP controller */ 147 146 struct mutex lock; 148 147 unsigned long function_num_map; 148 + int domain_nr; 149 149 bool init_complete; 150 150 }; 151 151 152 152 /** 153 + * enum pci_epc_bar_type - configurability of endpoint BAR 153 154 * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC. 154 155 * @BAR_FIXED: The BAR mask is fixed by the hardware. 155 156 * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
+9 -2
include/linux/pci.h
··· 371 371 can be generated */ 372 372 unsigned int pme_poll:1; /* Poll device's PME status bit */ 373 373 unsigned int pinned:1; /* Whether this dev is pinned */ 374 + unsigned int config_rrs_sv:1; /* Config RRS software visibility */ 374 375 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 375 376 unsigned int d1_support:1; /* Low power state D1 is supported */ 376 377 unsigned int d2_support:1; /* Low power state D2 is supported */ ··· 517 516 #endif 518 517 #ifdef CONFIG_PCI_DOE 519 518 struct xarray doe_mbs; /* Data Object Exchange mailboxes */ 519 + #endif 520 + #ifdef CONFIG_PCI_NPEM 521 + struct npem *npem; /* Native PCIe Enclosure Management */ 520 522 #endif 521 523 u16 acs_cap; /* ACS Capability offset */ 522 524 phys_addr_t rom; /* Physical address if not from BAR */ ··· 1102 1098 1103 1099 extern enum pcie_bus_config_types pcie_bus_config; 1104 1100 1105 - extern struct bus_type pci_bus_type; 1101 + extern const struct bus_type pci_bus_type; 1106 1102 1107 1103 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1108 1104 * code, or PCI core code. */ ··· 1888 1884 { return 0; } 1889 1885 #endif 1890 1886 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1891 - void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent); 1887 + void pci_bus_release_domain_nr(struct device *parent, int domain_nr); 1892 1888 #endif 1893 1889 1894 1890 /* Some architectures require additional setup to direct VGA traffic */ ··· 2294 2290 #endif 2295 2291 2296 2292 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2293 + void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar, 2294 + const char *name); 2297 2295 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2298 2296 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2297 + int pcim_request_region(struct pci_dev *pdev, int bar, const char *name); 2299 2298 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2300 2299 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2301 2300 const char *name);
+2
include/linux/pci_ids.h
··· 2662 2662 #define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 2663 2663 #define PCI_DEVICE_ID_DCI_PCCOM2 0x0004 2664 2664 2665 + #define PCI_VENDOR_ID_GLENFLY 0x6766 2666 + 2665 2667 #define PCI_VENDOR_ID_INTEL 0x8086 2666 2668 #define PCI_DEVICE_ID_INTEL_EESSC 0x0008 2667 2669 #define PCI_DEVICE_ID_INTEL_HDA_CML_LP 0x02c8
+39 -2
include/uapi/linux/pci_regs.h
··· 634 634 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */ 635 635 #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ 636 636 #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ 637 - #define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ 637 + #define PCI_EXP_RTCTL_RRS_SVE 0x0010 /* Config RRS Software Visibility Enable */ 638 + #define PCI_EXP_RTCTL_CRSSVE PCI_EXP_RTCTL_RRS_SVE /* compatibility */ 638 639 #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ 639 - #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ 640 + #define PCI_EXP_RTCAP_RRS_SV 0x0001 /* Config RRS Software Visibility */ 641 + #define PCI_EXP_RTCAP_CRSVIS PCI_EXP_RTCAP_RRS_SV /* compatibility */ 640 642 #define PCI_EXP_RTSTA 0x20 /* Root Status */ 641 643 #define PCI_EXP_RTSTA_PME_RQ_ID 0x0000ffff /* PME Requester ID */ 642 644 #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ ··· 742 740 #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ 743 741 #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ 744 742 #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ 743 + #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ 745 744 #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ 746 745 #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ 747 746 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE ··· 1123 1120 #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F 1124 1121 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 1125 1122 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 1123 + 1124 + /* Native PCIe Enclosure Management */ 1125 + #define PCI_NPEM_CAP 0x04 /* NPEM capability register */ 1126 + #define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */ 1127 + 1128 + #define PCI_NPEM_CTRL 0x08 /* NPEM control register */ 1129 + #define PCI_NPEM_CTRL_ENABLE 0x00000001 /* NPEM Enable */ 1130 + 1131 + /* 1132 + * Native PCIe Enclosure Management indication bits and Reset command bit 1133 + * are corresponding for capability and control registers. 1134 + */ 1135 + #define PCI_NPEM_CMD_RESET 0x00000002 /* Reset Command */ 1136 + #define PCI_NPEM_IND_OK 0x00000004 /* OK */ 1137 + #define PCI_NPEM_IND_LOCATE 0x00000008 /* Locate */ 1138 + #define PCI_NPEM_IND_FAIL 0x00000010 /* Fail */ 1139 + #define PCI_NPEM_IND_REBUILD 0x00000020 /* Rebuild */ 1140 + #define PCI_NPEM_IND_PFA 0x00000040 /* Predicted Failure Analysis */ 1141 + #define PCI_NPEM_IND_HOTSPARE 0x00000080 /* Hot Spare */ 1142 + #define PCI_NPEM_IND_ICA 0x00000100 /* In Critical Array */ 1143 + #define PCI_NPEM_IND_IFA 0x00000200 /* In Failed Array */ 1144 + #define PCI_NPEM_IND_IDT 0x00000400 /* Device Type */ 1145 + #define PCI_NPEM_IND_DISABLED 0x00000800 /* Disabled */ 1146 + #define PCI_NPEM_IND_SPEC_0 0x01000000 1147 + #define PCI_NPEM_IND_SPEC_1 0x02000000 1148 + #define PCI_NPEM_IND_SPEC_2 0x04000000 1149 + #define PCI_NPEM_IND_SPEC_3 0x08000000 1150 + #define PCI_NPEM_IND_SPEC_4 0x10000000 1151 + #define PCI_NPEM_IND_SPEC_5 0x20000000 1152 + #define PCI_NPEM_IND_SPEC_6 0x40000000 1153 + #define PCI_NPEM_IND_SPEC_7 0x80000000 1154 + 1155 + #define PCI_NPEM_STATUS 0x0c /* NPEM status register */ 1156 + #define PCI_NPEM_STATUS_CC 0x00000001 /* Command Completed */ 1126 1157 1127 1158 /* Data Object Exchange */ 1128 1159 #define PCI_DOE_CAP 0x04 /* DOE Capabilities Register */
+1 -1
kernel/irq/msi.c
··· 832 832 struct irq_chip *chip = info->chip; 833 833 834 834 BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask); 835 - if (!chip->irq_set_affinity) 835 + if (!chip->irq_set_affinity && !(info->flags & MSI_FLAG_NO_AFFINITY)) 836 836 chip->irq_set_affinity = msi_domain_set_affinity; 837 837 } 838 838
+1 -1
sound/pci/hda/hda_intel.c
··· 2688 2688 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2689 2689 AZX_DCAPS_PM_RUNTIME }, 2690 2690 /* GLENFLY */ 2691 - { PCI_DEVICE(0x6766, PCI_ANY_ID), 2691 + { PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID), 2692 2692 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2693 2693 .class_mask = 0xffffff, 2694 2694 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
+1 -1
tools/pci/Makefile
··· 42 42 clean: 43 43 rm -f $(ALL_PROGRAMS) 44 44 rm -rf $(OUTPUT)include/ 45 - find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete 45 + find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.cmd' -delete -o -name '\.*.d' -delete 46 46 47 47 install: $(ALL_PROGRAMS) 48 48 install -d -m 755 $(DESTDIR)$(bindir); \
-2
tools/pci/pcitest.c
··· 16 16 17 17 #include <linux/pcitest.h> 18 18 19 - #define BILLION 1E9 20 - 21 19 static char *result[] = { "NOT OKAY", "OKAY" }; 22 20 static char *irq[] = { "LEGACY", "MSI", "MSI-X" }; 23 21