tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2021-06-04-1' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Two big regression reverts in here, one for fbdev and one i915.
Otherwise it's mostly amdgpu display fixes, and tegra fixes.

fb:
- revert broken fb_defio patch

amdgpu:
- Display fixes
- FRU EEPROM error handling fix
- RAS fix
- PSP fix
- Releasing pinned BO fix

i915:
- Revert conversion to io_mapping_map_user() which lead to BUG_ON()
- Fix check for error valued returns in a selftest

tegra:
- SOR power domain race condition fix
- build warning fix
- runtime pm ref leak fix
- modifier fix"

* tag 'drm-fixes-2021-06-04-1' of git://anongit.freedesktop.org/drm/drm:
amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomic
drm/amdgpu: make sure we unpin the UVD BO
drm/amd/amdgpu:save psp ring wptr to avoid attack
drm/amd/display: Fix potential memory leak in DMUB hw_init
drm/amdgpu: Don't query CE and UE errors
drm/amd/display: Fix overlay validation by considering cursors
drm/amdgpu: refine amdgpu_fru_get_product_info
drm/amdgpu: add judgement for dc support
drm/amd/display: Fix GPU scaling regression by FS video support
drm/amd/display: Allow bandwidth validation for 0 streams.
Revert "i915: use io_mapping_map_user"
drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest()
Revert "fb_defio: Remove custom address_space_operations"
drm/tegra: Correct DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT
drm/tegra: sor: Fix AUX device reference leak
drm/tegra: Get ref for DP AUX channel, not its ddc adapter
drm/tegra: Fix shift overflow in tegra_shared_plane_atomic_update
drm/tegra: sor: Fully initialize SOR before registration
gpu: host1x: Split up client initalization and registration
drm/tegra: sor: Do not leak runtime PM reference

Linus Torvalds 3a3c5ab3 f88cd3fb

+240 -99
-16
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
··· 337 337 { 338 338 struct amdgpu_ctx *ctx; 339 339 struct amdgpu_ctx_mgr *mgr; 340 - unsigned long ras_counter; 341 340 342 341 if (!fpriv) 343 342 return -EINVAL; ··· 360 361 361 362 if (atomic_read(&ctx->guilty)) 362 363 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; 363 - 364 - /*query ue count*/ 365 - ras_counter = amdgpu_ras_query_error_count(adev, false); 366 - /*ras counter is monotonic increasing*/ 367 - if (ras_counter != ctx->ras_counter_ue) { 368 - out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; 369 - ctx->ras_counter_ue = ras_counter; 370 - } 371 - 372 - /*query ce count*/ 373 - ras_counter = amdgpu_ras_query_error_count(adev, true); 374 - if (ras_counter != ctx->ras_counter_ce) { 375 - out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; 376 - ctx->ras_counter_ce = ras_counter; 377 - } 378 364 379 365 mutex_unlock(&mgr->lock); 380 366 return 0;
+3 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 3118 3118 */ 3119 3119 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) 3120 3120 { 3121 - if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display) 3121 + if (amdgpu_sriov_vf(adev) || 3122 + adev->enable_virtual_display || 3123 + (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)) 3122 3124 return false; 3123 3125 3124 3126 return amdgpu_device_asic_has_dc_support(adev->asic_type);
+23 -19
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
··· 101 101 int amdgpu_fru_get_product_info(struct amdgpu_device *adev) 102 102 { 103 103 unsigned char buff[34]; 104 - int addrptr = 0, size = 0; 104 + int addrptr, size; 105 + int len; 105 106 106 107 if (!is_fru_eeprom_supported(adev)) 107 108 return 0; ··· 110 109 /* If algo exists, it means that the i2c_adapter's initialized */ 111 110 if (!adev->pm.smu_i2c.algo) { 112 111 DRM_WARN("Cannot access FRU, EEPROM accessor not initialized"); 113 - return 0; 112 + return -ENODEV; 114 113 } 115 114 116 115 /* There's a lot of repetition here. This is due to the FRU having ··· 129 128 size = amdgpu_fru_read_eeprom(adev, addrptr, buff); 130 129 if (size < 1) { 131 130 DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", size); 132 - return size; 131 + return -EINVAL; 133 132 } 134 133 135 134 /* Increment the addrptr by the size of the field, and 1 due to the ··· 139 138 size = amdgpu_fru_read_eeprom(adev, addrptr, buff); 140 139 if (size < 1) { 141 140 DRM_ERROR("Failed to read FRU product name, ret:%d", size); 142 - return size; 141 + return -EINVAL; 143 142 } 144 143 144 + len = size; 145 145 /* Product name should only be 32 characters. Any more, 146 146 * and something could be wrong. Cap it at 32 to be safe 147 147 */ 148 - if (size > 32) { 148 + if (len >= sizeof(adev->product_name)) { 149 149 DRM_WARN("FRU Product Number is larger than 32 characters. This is likely a mistake"); 150 - size = 32; 150 + len = sizeof(adev->product_name) - 1; 151 151 } 152 152 /* Start at 2 due to buff using fields 0 and 1 for the address */ 153 - memcpy(adev->product_name, &buff[2], size); 154 - adev->product_name[size] = '\0'; 153 + memcpy(adev->product_name, &buff[2], len); 154 + adev->product_name[len] = '\0'; 155 155 156 156 addrptr += size + 1; 157 157 size = amdgpu_fru_read_eeprom(adev, addrptr, buff); 158 158 if (size < 1) { 159 159 DRM_ERROR("Failed to read FRU product number, ret:%d", size); 160 - return size; 160 + return -EINVAL; 161 161 } 162 162 163 + len = size; 163 164 /* Product number should only be 16 characters. Any more, 164 165 * and something could be wrong. Cap it at 16 to be safe 165 166 */ 166 - if (size > 16) { 167 + if (len >= sizeof(adev->product_number)) { 167 168 DRM_WARN("FRU Product Number is larger than 16 characters. This is likely a mistake"); 168 - size = 16; 169 + len = sizeof(adev->product_number) - 1; 169 170 } 170 - memcpy(adev->product_number, &buff[2], size); 171 - adev->product_number[size] = '\0'; 171 + memcpy(adev->product_number, &buff[2], len); 172 + adev->product_number[len] = '\0'; 172 173 173 174 addrptr += size + 1; 174 175 size = amdgpu_fru_read_eeprom(adev, addrptr, buff); 175 176 176 177 if (size < 1) { 177 178 DRM_ERROR("Failed to read FRU product version, ret:%d", size); 178 - return size; 179 + return -EINVAL; 179 180 } 180 181 181 182 addrptr += size + 1; ··· 185 182 186 183 if (size < 1) { 187 184 DRM_ERROR("Failed to read FRU serial number, ret:%d", size); 188 - return size; 185 + return -EINVAL; 189 186 } 190 187 188 + len = size; 191 189 /* Serial number should only be 16 characters. Any more, 192 190 * and something could be wrong. Cap it at 16 to be safe 193 191 */ 194 - if (size > 16) { 192 + if (len >= sizeof(adev->serial)) { 195 193 DRM_WARN("FRU Serial Number is larger than 16 characters. This is likely a mistake"); 196 - size = 16; 194 + len = sizeof(adev->serial) - 1; 197 195 } 198 - memcpy(adev->serial, &buff[2], size); 199 - adev->serial[size] = '\0'; 196 + memcpy(adev->serial, &buff[2], len); 197 + adev->serial[len] = '\0'; 200 198 201 199 return 0; 202 200 }
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
··· 76 76 uint64_t ring_mem_mc_addr; 77 77 void *ring_mem_handle; 78 78 uint32_t ring_size; 79 + uint32_t ring_wptr; 79 80 }; 80 81 81 82 /* More registers may will be supported */
+2 -1
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
··· 720 720 struct amdgpu_device *adev = psp->adev; 721 721 722 722 if (amdgpu_sriov_vf(adev)) 723 - data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 723 + data = psp->km_ring.ring_wptr; 724 724 else 725 725 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 726 726 ··· 734 734 if (amdgpu_sriov_vf(adev)) { 735 735 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 736 736 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 737 + psp->km_ring.ring_wptr = value; 737 738 } else 738 739 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 739 740 }
+2 -1
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
··· 379 379 struct amdgpu_device *adev = psp->adev; 380 380 381 381 if (amdgpu_sriov_vf(adev)) 382 - data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 382 + data = psp->km_ring.ring_wptr; 383 383 else 384 384 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 385 385 return data; ··· 394 394 /* send interrupt to PSP for SRIOV ring write pointer update */ 395 395 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 396 396 GFX_CTRL_CMD_ID_CONSUME_CMD); 397 + psp->km_ring.ring_wptr = value; 397 398 } else 398 399 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 399 400 }
+1
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
··· 357 357 358 358 error: 359 359 dma_fence_put(fence); 360 + amdgpu_bo_unpin(bo); 360 361 amdgpu_bo_unreserve(bo); 361 362 amdgpu_bo_unref(&bo); 362 363 return r;
+19 -11
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 925 925 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 926 926 } 927 927 928 - adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 928 + if (!adev->dm.dc->ctx->dmub_srv) 929 + adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 929 930 if (!adev->dm.dc->ctx->dmub_srv) { 930 931 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 931 932 return -ENOMEM; ··· 1954 1953 s3_handle_mst(adev_to_drm(adev), true); 1955 1954 1956 1955 amdgpu_dm_irq_suspend(adev); 1957 - 1958 1956 1959 1957 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1960 1958 ··· 5500 5500 struct drm_display_mode saved_mode; 5501 5501 struct drm_display_mode *freesync_mode = NULL; 5502 5502 bool native_mode_found = false; 5503 - bool recalculate_timing = dm_state ? (dm_state->scaling != RMX_OFF) : false; 5503 + bool recalculate_timing = false; 5504 + bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 5504 5505 int mode_refresh; 5505 5506 int preferred_refresh = 0; 5506 5507 #if defined(CONFIG_DRM_AMD_DC_DCN) ··· 5564 5563 */ 5565 5564 DRM_DEBUG_DRIVER("No preferred mode found\n"); 5566 5565 } else { 5567 - recalculate_timing |= amdgpu_freesync_vid_mode && 5566 + recalculate_timing = amdgpu_freesync_vid_mode && 5568 5567 is_freesync_video_mode(&mode, aconnector); 5569 5568 if (recalculate_timing) { 5570 5569 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); ··· 5572 5571 mode = *freesync_mode; 5573 5572 } else { 5574 5573 decide_crtc_timing_for_drm_display_mode( 5575 - &mode, preferred_mode, 5576 - dm_state ? (dm_state->scaling != RMX_OFF) : false); 5577 - } 5574 + &mode, preferred_mode, scale); 5578 5575 5579 - preferred_refresh = drm_mode_vrefresh(preferred_mode); 5576 + preferred_refresh = drm_mode_vrefresh(preferred_mode); 5577 + } 5580 5578 } 5581 5579 5582 5580 if (recalculate_timing) ··· 5587 5587 * If scaling is enabled and refresh rate didn't change 5588 5588 * we copy the vic and polarities of the old timings 5589 5589 */ 5590 - if (!recalculate_timing || mode_refresh != preferred_refresh) 5590 + if (!scale || mode_refresh != preferred_refresh) 5591 5591 fill_stream_properties_from_drm_display_mode( 5592 5592 stream, &mode, &aconnector->base, con_state, NULL, 5593 5593 requested_bpc); ··· 9854 9854 9855 9855 if (cursor_scale_w != primary_scale_w || 9856 9856 cursor_scale_h != primary_scale_h) { 9857 - DRM_DEBUG_ATOMIC("Cursor plane scaling doesn't match primary plane\n"); 9857 + drm_dbg_atomic(crtc->dev, "Cursor plane scaling doesn't match primary plane\n"); 9858 9858 return -EINVAL; 9859 9859 } 9860 9860 ··· 9891 9891 int i; 9892 9892 struct drm_plane *plane; 9893 9893 struct drm_plane_state *old_plane_state, *new_plane_state; 9894 - struct drm_plane_state *primary_state, *overlay_state = NULL; 9894 + struct drm_plane_state *primary_state, *cursor_state, *overlay_state = NULL; 9895 9895 9896 9896 /* Check if primary plane is contained inside overlay */ 9897 9897 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { ··· 9919 9919 9920 9920 /* check if primary plane is enabled */ 9921 9921 if (!primary_state->crtc) 9922 + return 0; 9923 + 9924 + /* check if cursor plane is enabled */ 9925 + cursor_state = drm_atomic_get_plane_state(state, overlay_state->crtc->cursor); 9926 + if (IS_ERR(cursor_state)) 9927 + return PTR_ERR(cursor_state); 9928 + 9929 + if (drm_atomic_plane_disabling(plane->state, cursor_state)) 9922 9930 return 0; 9923 9931 9924 9932 /* Perform the bounds check to ensure the overlay plane covers the primary */
+1 -1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
··· 3236 3236 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 3237 3237 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 3238 3238 3239 - if (voltage_supported && dummy_pstate_supported) { 3239 + if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) { 3240 3240 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 3241 3241 goto restore_dml_state; 3242 3242 }
-1
drivers/gpu/drm/i915/Kconfig
··· 20 20 select INPUT if ACPI 21 21 select ACPI_VIDEO if ACPI 22 22 select ACPI_BUTTON if ACPI 23 - select IO_MAPPING 24 23 select SYNC_FILE 25 24 select IOSF_MBI 26 25 select CRC32
+5 -4
drivers/gpu/drm/i915/gem/i915_gem_mman.c
··· 367 367 goto err_unpin; 368 368 369 369 /* Finally, remap it using the new GTT offset */ 370 - ret = io_mapping_map_user(&ggtt->iomap, area, area->vm_start + 371 - (vma->ggtt_view.partial.offset << PAGE_SHIFT), 372 - (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT, 373 - min_t(u64, vma->size, area->vm_end - area->vm_start)); 370 + ret = remap_io_mapping(area, 371 + area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT), 372 + (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT, 373 + min_t(u64, vma->size, area->vm_end - area->vm_start), 374 + &ggtt->iomap); 374 375 if (ret) 375 376 goto err_fence; 376 377
+3
drivers/gpu/drm/i915/i915_drv.h
··· 1905 1905 struct drm_file *file); 1906 1906 1907 1907 /* i915_mm.c */ 1908 + int remap_io_mapping(struct vm_area_struct *vma, 1909 + unsigned long addr, unsigned long pfn, unsigned long size, 1910 + struct io_mapping *iomap); 1908 1911 int remap_io_sg(struct vm_area_struct *vma, 1909 1912 unsigned long addr, unsigned long size, 1910 1913 struct scatterlist *sgl, resource_size_t iobase);
+44
drivers/gpu/drm/i915/i915_mm.c
··· 37 37 resource_size_t iobase; 38 38 }; 39 39 40 + static int remap_pfn(pte_t *pte, unsigned long addr, void *data) 41 + { 42 + struct remap_pfn *r = data; 43 + 44 + /* Special PTE are not associated with any struct page */ 45 + set_pte_at(r->mm, addr, pte, pte_mkspecial(pfn_pte(r->pfn, r->prot))); 46 + r->pfn++; 47 + 48 + return 0; 49 + } 50 + 40 51 #define use_dma(io) ((io) != -1) 41 52 42 53 static inline unsigned long sgt_pfn(const struct remap_pfn *r) ··· 77 66 return 0; 78 67 } 79 68 69 + /** 70 + * remap_io_mapping - remap an IO mapping to userspace 71 + * @vma: user vma to map to 72 + * @addr: target user address to start at 73 + * @pfn: physical address of kernel memory 74 + * @size: size of map area 75 + * @iomap: the source io_mapping 76 + * 77 + * Note: this is only safe if the mm semaphore is held when called. 78 + */ 79 + int remap_io_mapping(struct vm_area_struct *vma, 80 + unsigned long addr, unsigned long pfn, unsigned long size, 81 + struct io_mapping *iomap) 82 + { 83 + struct remap_pfn r; 84 + int err; 85 + 80 86 #define EXPECTED_FLAGS (VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP) 87 + GEM_BUG_ON((vma->vm_flags & EXPECTED_FLAGS) != EXPECTED_FLAGS); 88 + 89 + /* We rely on prevalidation of the io-mapping to skip track_pfn(). */ 90 + r.mm = vma->vm_mm; 91 + r.pfn = pfn; 92 + r.prot = __pgprot((pgprot_val(iomap->prot) & _PAGE_CACHE_MASK) | 93 + (pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK)); 94 + 95 + err = apply_to_page_range(r.mm, addr, size, remap_pfn, &r); 96 + if (unlikely(err)) { 97 + zap_vma_ptes(vma, addr, (r.pfn - pfn) << PAGE_SHIFT); 98 + return err; 99 + } 100 + 101 + return 0; 102 + } 81 103 82 104 /** 83 105 * remap_io_sg - remap an IO mapping to userspace
+2 -2
drivers/gpu/drm/i915/selftests/i915_request.c
··· 1592 1592 1593 1593 for (n = 0; n < smoke[0].ncontexts; n++) { 1594 1594 smoke[0].contexts[n] = live_context(i915, file); 1595 - if (!smoke[0].contexts[n]) { 1596 - ret = -ENOMEM; 1595 + if (IS_ERR(smoke[0].contexts[n])) { 1596 + ret = PTR_ERR(smoke[0].contexts[n]); 1597 1597 goto out_contexts; 1598 1598 } 1599 1599 }
+1 -1
drivers/gpu/drm/tegra/drm.h
··· 25 25 #include "trace.h" 26 26 27 27 /* XXX move to include/uapi/drm/drm_fourcc.h? */ 28 - #define DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT BIT(22) 28 + #define DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT BIT_ULL(22) 29 29 30 30 struct reset_control; 31 31
+1 -1
drivers/gpu/drm/tegra/hub.c
··· 510 510 * dGPU sector layout. 511 511 */ 512 512 if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU) 513 - base |= BIT(39); 513 + base |= BIT_ULL(39); 514 514 #endif 515 515 516 516 tegra_plane_writel(p, tegra_plane_state->format, DC_WIN_COLOR_DEPTH);
+42 -28
drivers/gpu/drm/tegra/sor.c
··· 3125 3125 if (err < 0) { 3126 3126 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", 3127 3127 err); 3128 - return err; 3128 + goto rpm_put; 3129 3129 } 3130 3130 3131 3131 err = reset_control_assert(sor->rst); 3132 3132 if (err < 0) { 3133 3133 dev_err(sor->dev, "failed to assert SOR reset: %d\n", 3134 3134 err); 3135 - return err; 3135 + goto rpm_put; 3136 3136 } 3137 3137 } 3138 3138 3139 3139 err = clk_prepare_enable(sor->clk); 3140 3140 if (err < 0) { 3141 3141 dev_err(sor->dev, "failed to enable clock: %d\n", err); 3142 - return err; 3142 + goto rpm_put; 3143 3143 } 3144 3144 3145 3145 usleep_range(1000, 3000); ··· 3150 3150 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", 3151 3151 err); 3152 3152 clk_disable_unprepare(sor->clk); 3153 - return err; 3153 + goto rpm_put; 3154 3154 } 3155 3155 3156 3156 reset_control_release(sor->rst); ··· 3171 3171 } 3172 3172 3173 3173 return 0; 3174 + 3175 + rpm_put: 3176 + if (sor->rst) 3177 + pm_runtime_put(sor->dev); 3178 + 3179 + return err; 3174 3180 } 3175 3181 3176 3182 static int tegra_sor_exit(struct host1x_client *client) ··· 3745 3739 if (!sor->aux) 3746 3740 return -EPROBE_DEFER; 3747 3741 3748 - if (get_device(&sor->aux->ddc.dev)) { 3749 - if (try_module_get(sor->aux->ddc.owner)) 3750 - sor->output.ddc = &sor->aux->ddc; 3751 - else 3752 - put_device(&sor->aux->ddc.dev); 3753 - } 3742 + if (get_device(sor->aux->dev)) 3743 + sor->output.ddc = &sor->aux->ddc; 3754 3744 } 3755 3745 3756 3746 if (!sor->aux) { ··· 3774 3772 3775 3773 err = tegra_sor_parse_dt(sor); 3776 3774 if (err < 0) 3777 - return err; 3775 + goto put_aux; 3778 3776 3779 3777 err = tegra_output_probe(&sor->output); 3780 - if (err < 0) 3781 - return dev_err_probe(&pdev->dev, err, 3782 - "failed to probe output\n"); 3778 + if (err < 0) { 3779 + dev_err_probe(&pdev->dev, err, "failed to probe output\n"); 3780 + goto put_aux; 3781 + } 3783 3782 3784 3783 if (sor->ops && sor->ops->probe) { 3785 3784 err = sor->ops->probe(sor); ··· 3919 3916 platform_set_drvdata(pdev, sor); 3920 3917 pm_runtime_enable(&pdev->dev); 3921 3918 3922 - INIT_LIST_HEAD(&sor->client.list); 3919 + host1x_client_init(&sor->client); 3923 3920 sor->client.ops = &sor_client_ops; 3924 3921 sor->client.dev = &pdev->dev; 3925 - 3926 - err = host1x_client_register(&sor->client); 3927 - if (err < 0) { 3928 - dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3929 - err); 3930 - goto rpm_disable; 3931 - } 3932 3922 3933 3923 /* 3934 3924 * On Tegra210 and earlier, provide our own implementation for the ··· 3934 3938 sor->index); 3935 3939 if (!name) { 3936 3940 err = -ENOMEM; 3937 - goto unregister; 3941 + goto uninit; 3938 3942 } 3939 3943 3940 3944 err = host1x_client_resume(&sor->client); 3941 3945 if (err < 0) { 3942 3946 dev_err(sor->dev, "failed to resume: %d\n", err); 3943 - goto unregister; 3947 + goto uninit; 3944 3948 } 3945 3949 3946 3950 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); ··· 3951 3955 err = PTR_ERR(sor->clk_pad); 3952 3956 dev_err(sor->dev, "failed to register SOR pad clock: %d\n", 3953 3957 err); 3954 - goto unregister; 3958 + goto uninit; 3959 + } 3960 + 3961 + err = __host1x_client_register(&sor->client); 3962 + if (err < 0) { 3963 + dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3964 + err); 3965 + goto uninit; 3955 3966 } 3956 3967 3957 3968 return 0; 3958 3969 3959 - unregister: 3960 - host1x_client_unregister(&sor->client); 3961 - rpm_disable: 3970 + uninit: 3971 + host1x_client_exit(&sor->client); 3962 3972 pm_runtime_disable(&pdev->dev); 3963 3973 remove: 3974 + if (sor->aux) 3975 + sor->output.ddc = NULL; 3976 + 3964 3977 tegra_output_remove(&sor->output); 3978 + put_aux: 3979 + if (sor->aux) 3980 + put_device(sor->aux->dev); 3981 + 3965 3982 return err; 3966 3983 } 3967 3984 ··· 3991 3982 } 3992 3983 3993 3984 pm_runtime_disable(&pdev->dev); 3985 + 3986 + if (sor->aux) { 3987 + put_device(sor->aux->dev); 3988 + sor->output.ddc = NULL; 3989 + } 3994 3990 3995 3991 tegra_output_remove(&sor->output); 3996 3992
+24 -6
drivers/gpu/host1x/bus.c
··· 736 736 EXPORT_SYMBOL(host1x_driver_unregister); 737 737 738 738 /** 739 + * __host1x_client_init() - initialize a host1x client 740 + * @client: host1x client 741 + * @key: lock class key for the client-specific mutex 742 + */ 743 + void __host1x_client_init(struct host1x_client *client, struct lock_class_key *key) 744 + { 745 + INIT_LIST_HEAD(&client->list); 746 + __mutex_init(&client->lock, "host1x client lock", key); 747 + client->usecount = 0; 748 + } 749 + EXPORT_SYMBOL(__host1x_client_init); 750 + 751 + /** 752 + * host1x_client_exit() - uninitialize a host1x client 753 + * @client: host1x client 754 + */ 755 + void host1x_client_exit(struct host1x_client *client) 756 + { 757 + mutex_destroy(&client->lock); 758 + } 759 + EXPORT_SYMBOL(host1x_client_exit); 760 + 761 + /** 739 762 * __host1x_client_register() - register a host1x client 740 763 * @client: host1x client 741 764 * @key: lock class key for the client-specific mutex ··· 770 747 * device and call host1x_device_init(), which will in turn call each client's 771 748 * &host1x_client_ops.init implementation. 772 749 */ 773 - int __host1x_client_register(struct host1x_client *client, 774 - struct lock_class_key *key) 750 + int __host1x_client_register(struct host1x_client *client) 775 751 { 776 752 struct host1x *host1x; 777 753 int err; 778 - 779 - INIT_LIST_HEAD(&client->list); 780 - __mutex_init(&client->lock, "host1x client lock", key); 781 - client->usecount = 0; 782 754 783 755 mutex_lock(&devices_lock); 784 756
+35
drivers/video/fbdev/core/fb_defio.c
··· 52 52 return VM_FAULT_SIGBUS; 53 53 54 54 get_page(page); 55 + 56 + if (vmf->vma->vm_file) 57 + page->mapping = vmf->vma->vm_file->f_mapping; 58 + else 59 + printk(KERN_ERR "no mapping available\n"); 60 + 61 + BUG_ON(!page->mapping); 55 62 page->index = vmf->pgoff; 56 63 57 64 vmf->page = page; ··· 151 144 .page_mkwrite = fb_deferred_io_mkwrite, 152 145 }; 153 146 147 + static int fb_deferred_io_set_page_dirty(struct page *page) 148 + { 149 + if (!PageDirty(page)) 150 + SetPageDirty(page); 151 + return 0; 152 + } 153 + 154 + static const struct address_space_operations fb_deferred_io_aops = { 155 + .set_page_dirty = fb_deferred_io_set_page_dirty, 156 + }; 157 + 154 158 int fb_deferred_io_mmap(struct fb_info *info, struct vm_area_struct *vma) 155 159 { 156 160 vma->vm_ops = &fb_deferred_io_vm_ops; ··· 212 194 } 213 195 EXPORT_SYMBOL_GPL(fb_deferred_io_init); 214 196 197 + void fb_deferred_io_open(struct fb_info *info, 198 + struct inode *inode, 199 + struct file *file) 200 + { 201 + file->f_mapping->a_ops = &fb_deferred_io_aops; 202 + } 203 + EXPORT_SYMBOL_GPL(fb_deferred_io_open); 204 + 215 205 void fb_deferred_io_cleanup(struct fb_info *info) 216 206 { 217 207 struct fb_deferred_io *fbdefio = info->fbdefio; 208 + struct page *page; 209 + int i; 218 210 219 211 BUG_ON(!fbdefio); 220 212 cancel_delayed_work_sync(&info->deferred_work); 213 + 214 + /* clear out the mapping that we setup */ 215 + for (i = 0 ; i < info->fix.smem_len; i += PAGE_SIZE) { 216 + page = fb_deferred_io_page(info, i); 217 + page->mapping = NULL; 218 + } 219 + 221 220 mutex_destroy(&fbdefio->lock); 222 221 } 223 222 EXPORT_SYMBOL_GPL(fb_deferred_io_cleanup);
+4
drivers/video/fbdev/core/fbmem.c
··· 1415 1415 if (res) 1416 1416 module_put(info->fbops->owner); 1417 1417 } 1418 + #ifdef CONFIG_FB_DEFERRED_IO 1419 + if (info->fbdefio) 1420 + fb_deferred_io_open(info, inode, file); 1421 + #endif 1418 1422 out: 1419 1423 unlock_fb_info(info); 1420 1424 if (res)
+3
include/linux/fb.h
··· 659 659 /* drivers/video/fb_defio.c */ 660 660 int fb_deferred_io_mmap(struct fb_info *info, struct vm_area_struct *vma); 661 661 extern void fb_deferred_io_init(struct fb_info *info); 662 + extern void fb_deferred_io_open(struct fb_info *info, 663 + struct inode *inode, 664 + struct file *file); 662 665 extern void fb_deferred_io_cleanup(struct fb_info *info); 663 666 extern int fb_deferred_io_fsync(struct file *file, loff_t start, 664 667 loff_t end, int datasync);
+24 -6
include/linux/host1x.h
··· 332 332 int host1x_device_init(struct host1x_device *device); 333 333 int host1x_device_exit(struct host1x_device *device); 334 334 335 - int __host1x_client_register(struct host1x_client *client, 336 - struct lock_class_key *key); 337 - #define host1x_client_register(class) \ 338 - ({ \ 339 - static struct lock_class_key __key; \ 340 - __host1x_client_register(class, &__key); \ 335 + void __host1x_client_init(struct host1x_client *client, struct lock_class_key *key); 336 + void host1x_client_exit(struct host1x_client *client); 337 + 338 + #define host1x_client_init(client) \ 339 + ({ \ 340 + static struct lock_class_key __key; \ 341 + __host1x_client_init(client, &__key); \ 342 + }) 343 + 344 + int __host1x_client_register(struct host1x_client *client); 345 + 346 + /* 347 + * Note that this wrapper calls __host1x_client_init() for compatibility 348 + * with existing callers. Callers that want to separately initialize and 349 + * register a host1x client must first initialize using either of the 350 + * __host1x_client_init() or host1x_client_init() functions and then use 351 + * the low-level __host1x_client_register() function to avoid the client 352 + * getting reinitialized. 353 + */ 354 + #define host1x_client_register(client) \ 355 + ({ \ 356 + static struct lock_class_key __key; \ 357 + __host1x_client_init(client, &__key); \ 358 + __host1x_client_register(client); \ 341 359 }) 342 360 343 361 int host1x_client_unregister(struct host1x_client *client);