tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
"A couple of platforms have some last-minute fixes, in particular:

- riscv gets some fixes for noncoherent DMA on the renesas and thead
platforms and dts fix for SPI on the visionfive 2 board

- Qualcomm Snapdragon gets three dts fixes to address board specific
regressions on the pmic and gpio nodes

- Rockchip platforms get multiple dts fixes to address issues on the
recent rk3399 platform as well as the older rk3128 platform that
apparently regressed a while ago.

- TI OMAP gets some trivial code and dts fixes and a regression fix
for the omap1 ams-delta modem

- NXP i.MX firmware has one fix for a use-after-free but in its error
handling"

* tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM
riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT
riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT
riscv: dts: thead: set dma-noncoherent to soc bus
arm64: dts: rockchip: Fix i2s0 pin conflict on ROCK Pi 4 boards
arm64: dts: rockchip: Add i2s0-2ch-bus-bclk-off pins to RK3399
clk: ti: Fix missing omap5 mcbsp functional clock and aliases
clk: ti: Fix missing omap4 mcbsp functional clock and aliases
ARM: OMAP1: ams-delta: Fix MODEM initialization failure
soc: renesas: Make ARCH_R9A07G043 depend on required options
riscv: dts: starfive: visionfive 2: correct spi's ss pin
firmware/imx-dsp: Fix use_after_free in imx_dsp_setup_channels()
ARM: OMAP: timer32K: fix all kernel-doc warnings
ARM: omap2: fix a debug printk
ARM: dts: rockchip: Fix timer clocks for RK3128
ARM: dts: rockchip: Add missing quirk for RK3128's dma engine
ARM: dts: rockchip: Add missing arm timer interrupt for RK3128
ARM: dts: rockchip: Fix i2c0 register address for RK3128
arm64: dts: rockchip: set codec system-clock-fixed on px30-ringneck-haikou
arm64: dts: rockchip: use codec as clock master on px30-ringneck-haikou
...

Linus Torvalds 3a568e3a c17cda15

+127 -119
+3 -2
MAINTAINERS
··· 13846 13846 F: drivers/staging/media/meson/vdec/ 13847 13847 13848 13848 METHODE UDPU SUPPORT 13849 - M: Vladimir Vid <vladimir.vid@sartura.hr> 13849 + M: Robert Marko <robert.marko@sartura.hr> 13850 13850 S: Maintained 13851 - F: arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts 13851 + F: arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts 13852 + F: arch/arm64/boot/dts/marvell/armada-3720-uDPU.* 13852 13853 13853 13854 MHI BUS 13854 13855 M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+10 -8
arch/arm/boot/dts/rockchip/rk3128.dtsi
··· 64 64 compatible = "arm,armv7-timer"; 65 65 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 66 66 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 67 - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 67 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 68 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 68 69 arm,cpu-registers-not-fw-configured; 69 70 clock-frequency = <24000000>; 70 71 }; ··· 234 233 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 235 234 reg = <0x20044000 0x20>; 236 235 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 237 - clocks = <&cru PCLK_TIMER>, <&xin24m>; 236 + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 238 237 clock-names = "pclk", "timer"; 239 238 }; 240 239 ··· 242 241 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 243 242 reg = <0x20044020 0x20>; 244 243 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 245 - clocks = <&cru PCLK_TIMER>, <&xin24m>; 244 + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 246 245 clock-names = "pclk", "timer"; 247 246 }; 248 247 ··· 250 249 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 251 250 reg = <0x20044040 0x20>; 252 251 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 253 - clocks = <&cru PCLK_TIMER>, <&xin24m>; 252 + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 254 253 clock-names = "pclk", "timer"; 255 254 }; 256 255 ··· 258 257 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 259 258 reg = <0x20044060 0x20>; 260 259 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 261 - clocks = <&cru PCLK_TIMER>, <&xin24m>; 260 + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 262 261 clock-names = "pclk", "timer"; 263 262 }; 264 263 ··· 266 265 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 267 266 reg = <0x20044080 0x20>; 268 267 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 269 - clocks = <&cru PCLK_TIMER>, <&xin24m>; 268 + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 270 269 clock-names = "pclk", "timer"; 271 270 }; 272 271 ··· 274 273 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 275 274 reg = <0x200440a0 0x20>; 276 275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 277 - clocks = <&cru PCLK_TIMER>, <&xin24m>; 276 + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 278 277 clock-names = "pclk", "timer"; 279 278 }; 280 279 ··· 427 426 428 427 i2c0: i2c@20072000 { 429 428 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 430 - reg = <20072000 0x1000>; 429 + reg = <0x20072000 0x1000>; 431 430 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 432 431 clock-names = "i2c"; 433 432 clocks = <&cru PCLK_I2C0>; ··· 459 458 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 460 459 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 461 460 arm,pl330-broken-no-flushp; 461 + arm,pl330-periph-burst; 462 462 clocks = <&cru ACLK_DMAC>; 463 463 clock-names = "apb_pclk"; 464 464 #dma-cells = <1>;
+6
arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi
··· 109 109 reg = <0x0 0xff>, /* MPU private access */ 110 110 <0x49022000 0xff>; /* L3 Interconnect */ 111 111 reg-names = "mpu", "dma"; 112 + clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 24>; 113 + clock-names = "fck"; 112 114 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 113 115 interrupt-names = "common"; 114 116 ti,buffer-size = <128>; ··· 144 142 reg = <0x0 0xff>, /* MPU private access */ 145 143 <0x49024000 0xff>; /* L3 Interconnect */ 146 144 reg-names = "mpu", "dma"; 145 + clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 24>; 146 + clock-names = "fck"; 147 147 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 148 148 interrupt-names = "common"; 149 149 ti,buffer-size = <128>; ··· 179 175 reg = <0x0 0xff>, /* MPU private access */ 180 176 <0x49026000 0xff>; /* L3 Interconnect */ 181 177 reg-names = "mpu", "dma"; 178 + clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 24>; 179 + clock-names = "fck"; 182 180 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 183 181 interrupt-names = "common"; 184 182 ti,buffer-size = <128>;
+2
arch/arm/boot/dts/ti/omap/omap4-l4.dtsi
··· 2043 2043 compatible = "ti,omap4-mcbsp"; 2044 2044 reg = <0x0 0xff>; /* L4 Interconnect */ 2045 2045 reg-names = "mpu"; 2046 + clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 24>; 2047 + clock-names = "fck"; 2046 2048 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2047 2049 interrupt-names = "common"; 2048 2050 ti,buffer-size = <128>;
+6
arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi
··· 109 109 reg = <0x0 0xff>, /* MPU private access */ 110 110 <0x49022000 0xff>; /* L3 Interconnect */ 111 111 reg-names = "mpu", "dma"; 112 + clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 24>; 113 + clock-names = "fck"; 112 114 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 113 115 interrupt-names = "common"; 114 116 ti,buffer-size = <128>; ··· 144 142 reg = <0x0 0xff>, /* MPU private access */ 145 143 <0x49024000 0xff>; /* L3 Interconnect */ 146 144 reg-names = "mpu", "dma"; 145 + clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 24>; 146 + clock-names = "fck"; 147 147 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 148 148 interrupt-names = "common"; 149 149 ti,buffer-size = <128>; ··· 179 175 reg = <0x0 0xff>, /* MPU private access */ 180 176 <0x49026000 0xff>; /* L3 Interconnect */ 181 177 reg-names = "mpu", "dma"; 178 + clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 24>; 179 + clock-names = "fck"; 182 180 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 183 181 interrupt-names = "common"; 184 182 ti,buffer-size = <128>;
+16 -44
arch/arm/mach-omap1/board-ams-delta.c
··· 550 550 &ams_delta_nand_device, 551 551 &ams_delta_lcd_device, 552 552 &cx20442_codec_device, 553 + &modem_nreset_device, 553 554 }; 554 555 555 556 static struct gpiod_lookup_table *ams_delta_gpio_tables[] __initdata = { ··· 783 782 { }, 784 783 }; 785 784 785 + static int ams_delta_modem_pm_activate(struct device *dev) 786 + { 787 + modem_priv.regulator = regulator_get(dev, "RESET#"); 788 + if (IS_ERR(modem_priv.regulator)) 789 + return -EPROBE_DEFER; 790 + 791 + return 0; 792 + } 793 + 794 + static struct dev_pm_domain ams_delta_modem_pm_domain = { 795 + .activate = ams_delta_modem_pm_activate, 796 + }; 797 + 786 798 static struct platform_device ams_delta_modem_device = { 787 799 .name = "serial8250", 788 800 .id = PLAT8250_DEV_PLATFORM1, 789 801 .dev = { 790 802 .platform_data = ams_delta_modem_ports, 803 + .pm_domain = &ams_delta_modem_pm_domain, 791 804 }, 792 805 }; 793 - 794 - static int __init modem_nreset_init(void) 795 - { 796 - int err; 797 - 798 - err = platform_device_register(&modem_nreset_device); 799 - if (err) 800 - pr_err("Couldn't register the modem regulator device\n"); 801 - 802 - return err; 803 - } 804 - 805 806 806 807 /* 807 808 * This function expects MODEM IRQ number already assigned to the port. ··· 836 833 } 837 834 arch_initcall_sync(ams_delta_modem_init); 838 835 839 - static int __init late_init(void) 840 - { 841 - int err; 842 - 843 - err = modem_nreset_init(); 844 - if (err) 845 - return err; 846 - 847 - /* 848 - * Once the modem device is registered, the modem_nreset 849 - * regulator can be requested on behalf of that device. 850 - */ 851 - modem_priv.regulator = regulator_get(&ams_delta_modem_device.dev, 852 - "RESET#"); 853 - if (IS_ERR(modem_priv.regulator)) { 854 - err = PTR_ERR(modem_priv.regulator); 855 - goto unregister; 856 - } 857 - return 0; 858 - 859 - unregister: 860 - platform_device_unregister(&ams_delta_modem_device); 861 - return err; 862 - } 863 - 864 - static void __init ams_delta_init_late(void) 865 - { 866 - omap1_init_late(); 867 - late_init(); 868 - } 869 - 870 836 static void __init ams_delta_map_io(void) 871 837 { 872 838 omap1_map_io(); ··· 849 877 .init_early = omap1_init_early, 850 878 .init_irq = omap1_init_irq, 851 879 .init_machine = ams_delta_init, 852 - .init_late = ams_delta_init_late, 880 + .init_late = omap1_init_late, 853 881 .init_time = omap1_timer_init, 854 882 .restart = omap1_restart, 855 883 MACHINE_END
+7 -7
arch/arm/mach-omap1/timer32k.c
··· 176 176 return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; 177 177 } 178 178 179 + static struct timespec64 persistent_ts; 180 + static cycles_t cycles; 181 + static unsigned int persistent_mult, persistent_shift; 182 + 179 183 /** 180 184 * omap_read_persistent_clock64 - Return time from a persistent clock. 185 + * @ts: &struct timespec64 for the returned time 181 186 * 182 187 * Reads the time from a source which isn't disabled during PM, the 183 188 * 32k sync timer. Convert the cycles elapsed since last read into 184 189 * nsecs and adds to a monotonically increasing timespec64. 185 190 */ 186 - static struct timespec64 persistent_ts; 187 - static cycles_t cycles; 188 - static unsigned int persistent_mult, persistent_shift; 189 - 190 191 static void omap_read_persistent_clock64(struct timespec64 *ts) 191 192 { 192 193 unsigned long long nsecs; ··· 207 206 /** 208 207 * omap_init_clocksource_32k - setup and register counter 32k as a 209 208 * kernel clocksource 210 - * @pbase: base addr of counter_32k module 211 - * @size: size of counter_32k to map 209 + * @vbase: base addr of counter_32k module 212 210 * 213 - * Returns 0 upon success or negative error code upon failure. 211 + * Returns: %0 upon success or negative error code upon failure. 214 212 * 215 213 */ 216 214 static int __init omap_init_clocksource_32k(void __iomem *vbase)
+1 -1
arch/arm/mach-omap2/omap_hwmod.c
··· 2209 2209 return err; 2210 2210 2211 2211 pr_debug("omap_hwmod: %s %pOFn at %pR\n", 2212 - oh->name, np, &res); 2212 + oh->name, np, res); 2213 2213 2214 2214 if (oh && oh->mpu_rt_idx) { 2215 2215 omap_hwmod_fix_mpu_rt_idx(oh, np, res);
+15 -17
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
··· 62 62 stdout-path = "serial0:115200n8"; 63 63 }; 64 64 65 - clocks { 66 - divclk4: divclk4 { 67 - compatible = "fixed-clock"; 68 - #clock-cells = <0>; 69 - clock-frequency = <32768>; 70 - clock-output-names = "divclk4"; 65 + div1_mclk: divclk1 { 66 + compatible = "gpio-gate-clock"; 67 + pinctrl-0 = <&audio_mclk>; 68 + pinctrl-names = "default"; 69 + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; 70 + #clock-cells = <0>; 71 + enable-gpios = <&pm8994_gpios 15 0>; 72 + }; 71 73 72 - pinctrl-names = "default"; 73 - pinctrl-0 = <&divclk4_pin_a>; 74 - }; 74 + divclk4: divclk4 { 75 + compatible = "fixed-clock"; 76 + #clock-cells = <0>; 77 + clock-frequency = <32768>; 78 + clock-output-names = "divclk4"; 75 79 76 - div1_mclk: divclk1 { 77 - compatible = "gpio-gate-clock"; 78 - pinctrl-0 = <&audio_mclk>; 79 - pinctrl-names = "default"; 80 - clocks = <&rpmcc RPM_SMD_DIV_CLK1>; 81 - #clock-cells = <0>; 82 - enable-gpios = <&pm8994_gpios 15 0>; 83 - }; 80 + pinctrl-names = "default"; 81 + pinctrl-0 = <&divclk4_pin_a>; 84 82 }; 85 83 86 84 gpio-keys {
+15 -17
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
··· 11 11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 12 12 13 13 / { 14 - clocks { 15 - divclk1_cdc: divclk1 { 16 - compatible = "gpio-gate-clock"; 17 - clocks = <&rpmcc RPM_SMD_DIV_CLK1>; 18 - #clock-cells = <0>; 19 - enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>; 14 + divclk1_cdc: divclk1 { 15 + compatible = "gpio-gate-clock"; 16 + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; 17 + #clock-cells = <0>; 18 + enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>; 20 19 21 - pinctrl-names = "default"; 22 - pinctrl-0 = <&divclk1_default>; 23 - }; 20 + pinctrl-names = "default"; 21 + pinctrl-0 = <&divclk1_default>; 22 + }; 24 23 25 - divclk4: divclk4 { 26 - compatible = "fixed-clock"; 27 - #clock-cells = <0>; 28 - clock-frequency = <32768>; 29 - clock-output-names = "divclk4"; 24 + divclk4: divclk4 { 25 + compatible = "fixed-clock"; 26 + #clock-cells = <0>; 27 + clock-frequency = <32768>; 28 + clock-output-names = "divclk4"; 30 29 31 - pinctrl-names = "default"; 32 - pinctrl-0 = <&divclk4_pin_a>; 33 - }; 30 + pinctrl-names = "default"; 31 + pinctrl-0 = <&divclk4_pin_a>; 34 32 }; 35 33 36 34 gpio-keys {
+7 -9
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
··· 20 20 qcom,pmic-id = <0x20009 0x2000a 0x00 0x00>; 21 21 qcom,board-id = <31 0>; 22 22 23 - clocks { 24 - divclk2_haptics: divclk2 { 25 - compatible = "fixed-clock"; 26 - #clock-cells = <0>; 27 - clock-frequency = <32768>; 28 - clock-output-names = "divclk2"; 23 + divclk2_haptics: divclk2 { 24 + compatible = "fixed-clock"; 25 + #clock-cells = <0>; 26 + clock-frequency = <32768>; 27 + clock-output-names = "divclk2"; 29 28 30 - pinctrl-names = "default"; 31 - pinctrl-0 = <&divclk2_pin_a>; 32 - }; 29 + pinctrl-names = "default"; 30 + pinctrl-0 = <&divclk2_pin_a>; 33 31 }; 34 32 }; 35 33
+1 -1
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
··· 173 173 compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; 174 174 reg = <0x8800>; 175 175 gpio-controller; 176 - gpio-ranges = <&pmm8654au_2_gpios 0 0 12>; 176 + gpio-ranges = <&pmm8654au_1_gpios 0 0 12>; 177 177 #gpio-cells = <2>; 178 178 interrupt-controller; 179 179 #interrupt-cells = <2>;
+6 -4
arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
··· 68 68 simple-audio-card,format = "i2s"; 69 69 simple-audio-card,name = "Haikou,I2S-codec"; 70 70 simple-audio-card,mclk-fs = <512>; 71 + simple-audio-card,frame-master = <&sgtl5000_codec>; 72 + simple-audio-card,bitclock-master = <&sgtl5000_codec>; 71 73 72 - simple-audio-card,codec { 73 - clocks = <&sgtl5000_clk>; 74 + sgtl5000_codec: simple-audio-card,codec { 74 75 sound-dai = <&sgtl5000>; 76 + // Prevent the dai subsystem from overwriting the clock 77 + // frequency. We are using a fixed-frequency oscillator. 78 + system-clock-fixed; 75 79 }; 76 80 77 81 simple-audio-card,cpu { 78 - bitclock-master; 79 - frame-master; 80 82 sound-dai = <&i2s0_8ch>; 81 83 }; 82 84 };
+1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
··· 492 492 493 493 &i2s0 { 494 494 pinctrl-0 = <&i2s0_2ch_bus>; 495 + pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; 495 496 rockchip,capture-channels = <2>; 496 497 rockchip,playback-channels = <2>; 497 498 status = "okay";
+10
arch/arm64/boot/dts/rockchip/rk3399.dtsi
··· 2457 2457 <4 RK_PA0 1 &pcfg_pull_none>; 2458 2458 }; 2459 2459 2460 + i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off { 2461 + rockchip,pins = 2462 + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, 2463 + <3 RK_PD1 1 &pcfg_pull_none>, 2464 + <3 RK_PD2 1 &pcfg_pull_none>, 2465 + <3 RK_PD3 1 &pcfg_pull_none>, 2466 + <3 RK_PD7 1 &pcfg_pull_none>, 2467 + <4 RK_PA0 1 &pcfg_pull_none>; 2468 + }; 2469 + 2460 2470 i2s0_8ch_bus: i2s0-8ch-bus { 2461 2471 rockchip,pins = 2462 2472 <3 RK_PD0 1 &pcfg_pull_none>,
+1 -2
arch/riscv/Kconfig
··· 273 273 select ARCH_HAS_SYNC_DMA_FOR_CPU 274 274 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 275 275 select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB 276 - select DMA_DIRECT_REMAP if MMU 277 276 278 277 config RISCV_NONSTANDARD_CACHE_OPS 279 278 bool 280 - depends on RISCV_DMA_NONCOHERENT 281 279 help 282 280 This enables function pointer support for non-standard noncoherent 283 281 systems to handle cache management. ··· 548 550 depends on RISCV_ALTERNATIVE 549 551 default y 550 552 select RISCV_DMA_NONCOHERENT 553 + select DMA_DIRECT_REMAP 551 554 help 552 555 Adds support to dynamically detect the presence of the ZICBOM 553 556 extension (Cache Block Management Operations) and enable its
+1
arch/riscv/Kconfig.errata
··· 77 77 config ERRATA_THEAD_CMO 78 78 bool "Apply T-Head cache management errata" 79 79 depends on ERRATA_THEAD && MMU 80 + select DMA_DIRECT_REMAP 80 81 select RISCV_DMA_NONCOHERENT 81 82 default y 82 83 help
+1 -1
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
··· 431 431 }; 432 432 433 433 ss-pins { 434 - pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS, 434 + pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS, 435 435 GPOEN_ENABLE, 436 436 GPI_SYS_SPI0_FSS)>; 437 437 bias-disable;
+1
arch/riscv/boot/dts/thead/th1520.dtsi
··· 139 139 interrupt-parent = <&plic>; 140 140 #address-cells = <2>; 141 141 #size-cells = <2>; 142 + dma-noncoherent; 142 143 ranges; 143 144 144 145 plic: interrupt-controller@ffd8000000 {
+1 -1
drivers/cache/Kconfig
··· 3 3 4 4 config AX45MP_L2_CACHE 5 5 bool "Andes Technology AX45MP L2 Cache controller" 6 - depends on RISCV_DMA_NONCOHERENT 6 + depends on RISCV 7 7 select RISCV_NONSTANDARD_CACHE_OPS 8 8 help 9 9 Support for the L2 cache controller on Andes Technology AX45MP platforms.
+5
drivers/clk/ti/clk-44xx.c
··· 749 749 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"), 750 750 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"), 751 751 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"), 752 + DT_CLK("40122000.mcbsp", "prcm_fck", "abe-clkctrl:0028:26"), 753 + DT_CLK("40124000.mcbsp", "prcm_fck", "abe-clkctrl:0030:26"), 754 + DT_CLK("40126000.mcbsp", "prcm_fck", "abe-clkctrl:0038:26"), 752 755 DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"), 756 + DT_CLK("48096000.mcbsp", "prcm_fck", "l4-per-clkctrl:00c0:26"), 753 757 DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"), 754 758 DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"), 759 + DT_CLK(NULL, "pad_fck", "pad_clks_ck"), 755 760 DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"), 756 761 DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"), 757 762 DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
+4
drivers/clk/ti/clk-54xx.c
··· 565 565 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"), 566 566 DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"), 567 567 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"), 568 + DT_CLK("40122000.mcbsp", "prcm_fck", "abe-clkctrl:0028:26"), 568 569 DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"), 569 570 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"), 571 + DT_CLK("40124000.mcbsp", "prcm_fck", "abe-clkctrl:0030:26"), 570 572 DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"), 571 573 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"), 574 + DT_CLK("40126000.mcbsp", "prcm_fck", "abe-clkctrl:0038:26"), 572 575 DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"), 573 576 DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"), 574 577 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"), 575 578 DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"), 576 579 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"), 580 + DT_CLK(NULL, "pad_fck", "pad_clks_ck"), 577 581 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"), 578 582 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"), 579 583 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
+1 -1
drivers/firmware/imx/imx-dsp.c
··· 114 114 dsp_chan->idx = i % 2; 115 115 dsp_chan->ch = mbox_request_channel_byname(cl, chan_name); 116 116 if (IS_ERR(dsp_chan->ch)) { 117 - kfree(dsp_chan->name); 118 117 ret = PTR_ERR(dsp_chan->ch); 119 118 if (ret != -EPROBE_DEFER) 120 119 dev_err(dev, "Failed to request mbox chan %s ret %d\n", 121 120 chan_name, ret); 121 + kfree(dsp_chan->name); 122 122 goto out; 123 123 } 124 124
+6 -4
drivers/soc/renesas/Kconfig
··· 334 334 config ARCH_R9A07G043 335 335 bool "RISC-V Platform support for RZ/Five" 336 336 depends on NONPORTABLE 337 + depends on RISCV_ALTERNATIVE 338 + depends on !RISCV_ISA_ZICBOM 339 + depends on RISCV_SBI 337 340 select ARCH_RZG2L 338 - select AX45MP_L2_CACHE if RISCV_DMA_NONCOHERENT 341 + select AX45MP_L2_CACHE 339 342 select DMA_GLOBAL_POOL 340 - select ERRATA_ANDES if RISCV_SBI 341 - select ERRATA_ANDES_CMO if ERRATA_ANDES 342 - 343 + select ERRATA_ANDES 344 + select ERRATA_ANDES_CMO 343 345 help 344 346 This enables support for the Renesas RZ/Five SoC. 345 347