Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
RISC-V: KVM: Add timer functionality
The RISC-V hypervisor specification doesn't have any virtual timer
feature.
Due to this, the guest VCPU timer will be programmed via SBI calls.
The host will use a separate hrtimer event for each guest VCPU to
provide timer functionality. We inject a virtual timer interrupt to
the guest VCPU whenever the guest VCPU hrtimer event expires.
This patch adds guest VCPU timer implementation along with ONE_REG
interface to access VCPU timer state from user space.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
authored by
Atish Patra
and committed by
Anup Patel
3a9f66cb
9955371c
+334
-1
+7
arch/riscv/include/asm/kvm_host.h
+7
arch/riscv/include/asm/kvm_host.h
···
12
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#include <linux/types.h>
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#include <linux/kvm.h>
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#include <linux/kvm_types.h>
15
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#include <asm/kvm_vcpu_timer.h>
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#ifdef CONFIG_64BIT
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#define KVM_MAX_VCPUS (1U << 16)
···
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/* stage2 page table */
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pgd_t *pgd;
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phys_addr_t pgd_phys;
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/* Guest Timer */
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struct kvm_guest_timer timer;
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};
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struct kvm_mmio_decode {
···
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*/
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unsigned long irqs_pending;
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unsigned long irqs_pending_mask;
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/* VCPU Timer */
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struct kvm_vcpu_timer timer;
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/* MMIO instruction details */
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struct kvm_mmio_decode mmio_decode;
+44
arch/riscv/include/asm/kvm_vcpu_timer.h
+44
arch/riscv/include/asm/kvm_vcpu_timer.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Atish Patra <atish.patra@wdc.com>
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*/
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#ifndef __KVM_VCPU_RISCV_TIMER_H
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#define __KVM_VCPU_RISCV_TIMER_H
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#include <linux/hrtimer.h>
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struct kvm_guest_timer {
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/* Mult & Shift values to get nanoseconds from cycles */
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u32 nsec_mult;
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u32 nsec_shift;
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/* Time delta value */
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u64 time_delta;
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};
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struct kvm_vcpu_timer {
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/* Flag for whether init is done */
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bool init_done;
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/* Flag for whether timer event is configured */
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bool next_set;
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/* Next timer event cycles */
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u64 next_cycles;
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/* Underlying hrtimer instance */
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struct hrtimer hrt;
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};
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+
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int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles);
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int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg);
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int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg);
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int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu);
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int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu);
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int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu);
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void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu);
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int kvm_riscv_guest_timer_init(struct kvm *kvm);
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#endif
+17
arch/riscv/include/uapi/asm/kvm.h
+17
arch/riscv/include/uapi/asm/kvm.h
···
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unsigned long scounteren;
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};
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/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_timer {
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__u64 frequency;
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__u64 time;
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__u64 compare;
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__u64 state;
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};
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/* Possible states for kvm_riscv_timer */
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#define KVM_RISCV_TIMER_STATE_OFF 0
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#define KVM_RISCV_TIMER_STATE_ON 1
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#define KVM_REG_SIZE(id) \
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(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
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···
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#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_CSR_REG(name) \
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(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
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/* Timer registers are mapped as type 4 */
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#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_TIMER_REG(name) \
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(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
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#endif
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+1
arch/riscv/kvm/Makefile
+1
arch/riscv/kvm/Makefile
+14
arch/riscv/kvm/vcpu.c
+14
arch/riscv/kvm/vcpu.c
···
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memcpy(cntx, reset_cntx, sizeof(*cntx));
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kvm_riscv_vcpu_timer_reset(vcpu);
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WRITE_ONCE(vcpu->arch.irqs_pending, 0);
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WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0);
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}
···
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cntx->hstatus |= HSTATUS_SPVP;
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cntx->hstatus |= HSTATUS_SPV;
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/* Setup VCPU timer */
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kvm_riscv_vcpu_timer_init(vcpu);
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/* Reset VCPU */
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kvm_riscv_reset_vcpu(vcpu);
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···
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void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
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{
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/* Cleanup VCPU timer */
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kvm_riscv_vcpu_timer_deinit(vcpu);
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/* Flush the pages pre-allocated for Stage2 page table mappings */
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kvm_riscv_stage2_flush_cache(vcpu);
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}
···
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return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
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else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
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return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
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else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
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return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
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return -EINVAL;
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}
···
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return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
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else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
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return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
348
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else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
349
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return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
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return -EINVAL;
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}
···
590
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csr_write(CSR_VSATP, csr->vsatp);
591
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kvm_riscv_stage2_update_hgatp(vcpu);
581
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582
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kvm_riscv_vcpu_timer_restore(vcpu);
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vcpu->cpu = cpu;
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}
+225
arch/riscv/kvm/vcpu_timer.c
+225
arch/riscv/kvm/vcpu_timer.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
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/*
3
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
4
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*
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* Authors:
6
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* Atish Patra <atish.patra@wdc.com>
7
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*/
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/kvm_host.h>
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#include <linux/uaccess.h>
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#include <clocksource/timer-riscv.h>
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#include <asm/csr.h>
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#include <asm/delay.h>
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#include <asm/kvm_vcpu_timer.h>
17
+
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static u64 kvm_riscv_current_cycles(struct kvm_guest_timer *gt)
19
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{
20
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return get_cycles64() + gt->time_delta;
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}
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static u64 kvm_riscv_delta_cycles2ns(u64 cycles,
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struct kvm_guest_timer *gt,
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struct kvm_vcpu_timer *t)
26
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{
27
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unsigned long flags;
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u64 cycles_now, cycles_delta, delta_ns;
29
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30
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local_irq_save(flags);
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cycles_now = kvm_riscv_current_cycles(gt);
32
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if (cycles_now < cycles)
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cycles_delta = cycles - cycles_now;
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else
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cycles_delta = 0;
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delta_ns = (cycles_delta * gt->nsec_mult) >> gt->nsec_shift;
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local_irq_restore(flags);
38
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39
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return delta_ns;
40
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}
41
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static enum hrtimer_restart kvm_riscv_vcpu_hrtimer_expired(struct hrtimer *h)
43
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{
44
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u64 delta_ns;
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struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt);
46
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struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer);
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
48
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if (kvm_riscv_current_cycles(gt) < t->next_cycles) {
50
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delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t);
51
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hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns));
52
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return HRTIMER_RESTART;
53
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}
54
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55
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t->next_set = false;
56
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kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_TIMER);
57
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58
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return HRTIMER_NORESTART;
59
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}
60
+
61
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static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t)
62
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{
63
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if (!t->init_done || !t->next_set)
64
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return -EINVAL;
65
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66
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hrtimer_cancel(&t->hrt);
67
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t->next_set = false;
68
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69
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return 0;
70
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}
71
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int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
73
+
{
74
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
75
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
76
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u64 delta_ns;
77
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78
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if (!t->init_done)
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return -EINVAL;
80
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81
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kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_TIMER);
82
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83
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delta_ns = kvm_riscv_delta_cycles2ns(ncycles, gt, t);
84
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t->next_cycles = ncycles;
85
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hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL);
86
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t->next_set = true;
87
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88
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return 0;
89
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}
90
+
91
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int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu,
92
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const struct kvm_one_reg *reg)
93
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{
94
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
95
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
96
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u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
97
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
98
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_TIMER);
100
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u64 reg_val;
101
+
102
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if (KVM_REG_SIZE(reg->id) != sizeof(u64))
103
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return -EINVAL;
104
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if (reg_num >= sizeof(struct kvm_riscv_timer) / sizeof(u64))
105
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return -EINVAL;
106
+
107
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switch (reg_num) {
108
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case KVM_REG_RISCV_TIMER_REG(frequency):
109
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reg_val = riscv_timebase;
110
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break;
111
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case KVM_REG_RISCV_TIMER_REG(time):
112
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reg_val = kvm_riscv_current_cycles(gt);
113
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break;
114
+
case KVM_REG_RISCV_TIMER_REG(compare):
115
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reg_val = t->next_cycles;
116
+
break;
117
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case KVM_REG_RISCV_TIMER_REG(state):
118
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reg_val = (t->next_set) ? KVM_RISCV_TIMER_STATE_ON :
119
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KVM_RISCV_TIMER_STATE_OFF;
120
+
break;
121
+
default:
122
+
return -EINVAL;
123
+
};
124
+
125
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
126
+
return -EFAULT;
127
+
128
+
return 0;
129
+
}
130
+
131
+
int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu,
132
+
const struct kvm_one_reg *reg)
133
+
{
134
+
struct kvm_vcpu_timer *t = &vcpu->arch.timer;
135
+
struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
136
+
u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
137
+
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
138
+
KVM_REG_SIZE_MASK |
139
+
KVM_REG_RISCV_TIMER);
140
+
u64 reg_val;
141
+
int ret = 0;
142
+
143
+
if (KVM_REG_SIZE(reg->id) != sizeof(u64))
144
+
return -EINVAL;
145
+
if (reg_num >= sizeof(struct kvm_riscv_timer) / sizeof(u64))
146
+
return -EINVAL;
147
+
148
+
if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
149
+
return -EFAULT;
150
+
151
+
switch (reg_num) {
152
+
case KVM_REG_RISCV_TIMER_REG(frequency):
153
+
ret = -EOPNOTSUPP;
154
+
break;
155
+
case KVM_REG_RISCV_TIMER_REG(time):
156
+
gt->time_delta = reg_val - get_cycles64();
157
+
break;
158
+
case KVM_REG_RISCV_TIMER_REG(compare):
159
+
t->next_cycles = reg_val;
160
+
break;
161
+
case KVM_REG_RISCV_TIMER_REG(state):
162
+
if (reg_val == KVM_RISCV_TIMER_STATE_ON)
163
+
ret = kvm_riscv_vcpu_timer_next_event(vcpu, reg_val);
164
+
else
165
+
ret = kvm_riscv_vcpu_timer_cancel(t);
166
+
break;
167
+
default:
168
+
ret = -EINVAL;
169
+
break;
170
+
};
171
+
172
+
return ret;
173
+
}
174
+
175
+
int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu)
176
+
{
177
+
struct kvm_vcpu_timer *t = &vcpu->arch.timer;
178
+
179
+
if (t->init_done)
180
+
return -EINVAL;
181
+
182
+
hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
183
+
t->hrt.function = kvm_riscv_vcpu_hrtimer_expired;
184
+
t->init_done = true;
185
+
t->next_set = false;
186
+
187
+
return 0;
188
+
}
189
+
190
+
int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu)
191
+
{
192
+
int ret;
193
+
194
+
ret = kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
195
+
vcpu->arch.timer.init_done = false;
196
+
197
+
return ret;
198
+
}
199
+
200
+
int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu)
201
+
{
202
+
return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
203
+
}
204
+
205
+
void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
206
+
{
207
+
struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
208
+
209
+
#ifdef CONFIG_64BIT
210
+
csr_write(CSR_HTIMEDELTA, gt->time_delta);
211
+
#else
212
+
csr_write(CSR_HTIMEDELTA, (u32)(gt->time_delta));
213
+
csr_write(CSR_HTIMEDELTAH, (u32)(gt->time_delta >> 32));
214
+
#endif
215
+
}
216
+
217
+
int kvm_riscv_guest_timer_init(struct kvm *kvm)
218
+
{
219
+
struct kvm_guest_timer *gt = &kvm->arch.timer;
220
+
221
+
riscv_cs_get_mult_shift(>->nsec_mult, >->nsec_shift);
222
+
gt->time_delta = -get_cycles64();
223
+
224
+
return 0;
225
+
}
+1
-1
arch/riscv/kvm/vm.c
+1
-1
arch/riscv/kvm/vm.c
+9
drivers/clocksource/timer-riscv.c
+9
drivers/clocksource/timer-riscv.c
···
13
13
#include <linux/delay.h>
14
14
#include <linux/irq.h>
15
15
#include <linux/irqdomain.h>
16
+
#include <linux/module.h>
16
17
#include <linux/sched_clock.h>
17
18
#include <linux/io-64-nonatomic-lo-hi.h>
18
19
#include <linux/interrupt.h>
19
20
#include <linux/of_irq.h>
21
+
#include <clocksource/timer-riscv.h>
20
22
#include <asm/smp.h>
21
23
#include <asm/sbi.h>
22
24
#include <asm/timex.h>
···
80
78
disable_percpu_irq(riscv_clock_event_irq);
81
79
return 0;
82
80
}
81
+
82
+
void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
83
+
{
84
+
*mult = riscv_clocksource.mult;
85
+
*shift = riscv_clocksource.shift;
86
+
}
87
+
EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
83
88
84
89
/* called directly from the low-level interrupt handler */
85
90
static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
+16
include/clocksource/timer-riscv.h
+16
include/clocksource/timer-riscv.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (C) 2019 Western Digital Corporation or its affiliates.
4
+
*
5
+
* Authors:
6
+
* Atish Patra <atish.patra@wdc.com>
7
+
*/
8
+
9
+
#ifndef __TIMER_RISCV_H
10
+
#define __TIMER_RISCV_H
11
+
12
+
#include <linux/types.h>
13
+
14
+
extern void riscv_cs_get_mult_shift(u32 *mult, u32 *shift);
15
+
16
+
#endif