Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: cleanup all virtualization detection routine
we need to move virt detection much earlier because:
1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always
be at DE5 (dw) mmio offset from vega10, this way there is no
need to implement detect_hw_virt() routine in each nbio/chip file.
for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at
0x1503
2) we need to acknowledged we are SRIOV VF before we do IP discovery because
the IP discovery content will be updated by host everytime after it recieved
a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches
for this new handshake soon).
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Monk Liu
and committed by
Alex Deucher
3aa0115d
b89659b7
+48
-105
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
3055
3055
if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
3056
3056
adev->enable_mes = true;
3057
3057
3058
+
/* detect hw virtualization here */
3059
+
amdgpu_detect_virtualization(adev);
3060
+
3058
3061
if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) {
3059
3062
r = amdgpu_discovery_init(adev);
3060
3063
if (r) {
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
···
77
77
u32 *flags);
78
78
void (*ih_control)(struct amdgpu_device *adev);
79
79
void (*init_registers)(struct amdgpu_device *adev);
80
-
void (*detect_hw_virt)(struct amdgpu_device *adev);
81
80
void (*remap_hdp_registers)(struct amdgpu_device *adev);
82
81
void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
83
82
void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
+33
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+33
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
···
287
287
}
288
288
}
289
289
}
290
+
291
+
void amdgpu_detect_virtualization(struct amdgpu_device *adev)
292
+
{
293
+
uint32_t reg;
294
+
295
+
switch (adev->asic_type) {
296
+
case CHIP_TONGA:
297
+
case CHIP_FIJI:
298
+
reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
299
+
break;
300
+
case CHIP_VEGA10:
301
+
case CHIP_VEGA20:
302
+
case CHIP_NAVI10:
303
+
case CHIP_NAVI12:
304
+
case CHIP_ARCTURUS:
305
+
reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
306
+
break;
307
+
default: /* other chip doesn't support SRIOV */
308
+
reg = 0;
309
+
break;
310
+
}
311
+
312
+
if (reg & 1)
313
+
adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
314
+
315
+
if (reg & 0x80000000)
316
+
adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
317
+
318
+
if (!reg) {
319
+
if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
320
+
adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
321
+
}
322
+
}
+6
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+6
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
···
30
30
#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
31
31
#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
32
32
33
+
/* all asic after AI use this offset */
34
+
#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
35
+
/* tonga/fiji use this offset */
36
+
#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
37
+
33
38
struct amdgpu_mm_table {
34
39
struct amdgpu_bo *bo;
35
40
uint32_t *cpu_addr;
···
310
305
unsigned int key,
311
306
unsigned int chksum);
312
307
void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
308
+
void amdgpu_detect_virtualization(struct amdgpu_device *adev);
313
309
#endif
-8
drivers/gpu/drm/amd/amdgpu/cik.c
-8
drivers/gpu/drm/amd/amdgpu/cik.c
···
1811
1811
>> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1812
1812
}
1813
1813
1814
-
static void cik_detect_hw_virtualization(struct amdgpu_device *adev)
1815
-
{
1816
-
if (is_virtual_machine()) /* passthrough mode */
1817
-
adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
1818
-
}
1819
-
1820
1814
static void cik_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
1821
1815
{
1822
1816
if (!ring || !ring->funcs->emit_wreg) {
···
2173
2179
2174
2180
int cik_set_ip_blocks(struct amdgpu_device *adev)
2175
2181
{
2176
-
cik_detect_hw_virtualization(adev);
2177
-
2178
2182
switch (adev->asic_type) {
2179
2183
case CHIP_BONAIRE:
2180
2184
amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
-18
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
-18
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
···
290
290
.ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
291
291
};
292
292
293
-
static void nbio_v2_3_detect_hw_virt(struct amdgpu_device *adev)
294
-
{
295
-
uint32_t reg;
296
-
297
-
reg = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER);
298
-
if (reg & 1)
299
-
adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
300
-
301
-
if (reg & 0x80000000)
302
-
adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
303
-
304
-
if (!reg) {
305
-
if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
306
-
adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
307
-
}
308
-
}
309
-
310
293
static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
311
294
{
312
295
uint32_t def, data;
···
321
338
.get_clockgating_state = nbio_v2_3_get_clockgating_state,
322
339
.ih_control = nbio_v2_3_ih_control,
323
340
.init_registers = nbio_v2_3_init_registers,
324
-
.detect_hw_virt = nbio_v2_3_detect_hw_virt,
325
341
.remap_hdp_registers = nbio_v2_3_remap_hdp_registers,
326
342
};
-18
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
-18
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
···
241
241
.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
242
242
};
243
243
244
-
static void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
245
-
{
246
-
uint32_t reg;
247
-
248
-
reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER);
249
-
if (reg & 1)
250
-
adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
251
-
252
-
if (reg & 0x80000000)
253
-
adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
254
-
255
-
if (!reg) {
256
-
if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
257
-
adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
258
-
}
259
-
}
260
-
261
244
static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
262
245
{
263
246
uint32_t def, data;
···
277
294
.get_clockgating_state = nbio_v6_1_get_clockgating_state,
278
295
.ih_control = nbio_v6_1_ih_control,
279
296
.init_registers = nbio_v6_1_init_registers,
280
-
.detect_hw_virt = nbio_v6_1_detect_hw_virt,
281
297
};
-7
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
-7
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
···
280
280
.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
281
281
};
282
282
283
-
static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
284
-
{
285
-
if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
286
-
adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
287
-
}
288
-
289
283
static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
290
284
{
291
285
···
304
310
.get_clockgating_state = nbio_v7_0_get_clockgating_state,
305
311
.ih_control = nbio_v7_0_ih_control,
306
312
.init_registers = nbio_v7_0_init_registers,
307
-
.detect_hw_virt = nbio_v7_0_detect_hw_virt,
308
313
.remap_hdp_registers = nbio_v7_0_remap_hdp_registers,
309
314
};
-18
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
-18
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
···
292
292
.ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
293
293
};
294
294
295
-
static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
296
-
{
297
-
uint32_t reg;
298
-
299
-
reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);
300
-
if (reg & 1)
301
-
adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
302
-
303
-
if (reg & 0x80000000)
304
-
adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
305
-
306
-
if (!reg) {
307
-
if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
308
-
adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
309
-
}
310
-
}
311
-
312
295
static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
313
296
{
314
297
···
544
561
.get_clockgating_state = nbio_v7_4_get_clockgating_state,
545
562
.ih_control = nbio_v7_4_ih_control,
546
563
.init_registers = nbio_v7_4_init_registers,
547
-
.detect_hw_virt = nbio_v7_4_detect_hw_virt,
548
564
.remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
549
565
.handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
550
566
.handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
-2
drivers/gpu/drm/amd/amdgpu/nv.c
-2
drivers/gpu/drm/amd/amdgpu/nv.c
-8
drivers/gpu/drm/amd/amdgpu/si.c
-8
drivers/gpu/drm/amd/amdgpu/si.c
···
1249
1249
return 0;
1250
1250
}
1251
1251
1252
-
static void si_detect_hw_virtualization(struct amdgpu_device *adev)
1253
-
{
1254
-
if (is_virtual_machine()) /* passthrough mode */
1255
-
adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
1256
-
}
1257
-
1258
1252
static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
1259
1253
{
1260
1254
if (!ring || !ring->funcs->emit_wreg) {
···
2159
2165
2160
2166
int si_set_ip_blocks(struct amdgpu_device *adev)
2161
2167
{
2162
-
si_detect_hw_virtualization(adev);
2163
-
2164
2168
switch (adev->asic_type) {
2165
2169
case CHIP_VERDE:
2166
2170
case CHIP_TAHITI:
-1
drivers/gpu/drm/amd/amdgpu/soc15.c
-1
drivers/gpu/drm/amd/amdgpu/soc15.c
-24
drivers/gpu/drm/amd/amdgpu/vi.c
-24
drivers/gpu/drm/amd/amdgpu/vi.c
···
448
448
return true;
449
449
}
450
450
451
-
static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
452
-
{
453
-
uint32_t reg = 0;
454
-
455
-
if (adev->asic_type == CHIP_TONGA ||
456
-
adev->asic_type == CHIP_FIJI) {
457
-
reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
458
-
/* bit0: 0 means pf and 1 means vf */
459
-
if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
460
-
adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
461
-
/* bit31: 0 means disable IOV and 1 means enable */
462
-
if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
463
-
adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
464
-
}
465
-
466
-
if (reg == 0) {
467
-
if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */
468
-
adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
469
-
}
470
-
}
471
-
472
451
static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
473
452
{mmGRBM_STATUS},
474
453
{mmGRBM_STATUS2},
···
1709
1730
1710
1731
int vi_set_ip_blocks(struct amdgpu_device *adev)
1711
1732
{
1712
-
/* in early init stage, vbios code won't work */
1713
-
vi_detect_hw_virtualization(adev);
1714
-
1715
1733
if (amdgpu_sriov_vf(adev))
1716
1734
adev->virt.ops = &xgpu_vi_virt_ops;
1717
1735
+2
drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h
+2
drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h
···
1162
1162
#define mmRCC_CONFIG_MEMSIZE_BASE_IDX 0
1163
1163
#define mmRCC_CONFIG_RESERVED 0x0de4 // duplicate
1164
1164
#define mmRCC_CONFIG_RESERVED_BASE_IDX 0
1165
+
#ifndef mmRCC_IOV_FUNC_IDENTIFIER
1165
1166
#define mmRCC_IOV_FUNC_IDENTIFIER 0x0de5 // duplicate
1166
1167
#define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 0
1168
+
#endif
1167
1169
1168
1170
1169
1171
// addressBlock: syshub_mmreg_ind_syshubdec
+2
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h
+2
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h
···
4251
4251
#define mmRCC_CONFIG_MEMSIZE_BASE_IDX 2
4252
4252
#define mmRCC_CONFIG_RESERVED 0x00c4
4253
4253
#define mmRCC_CONFIG_RESERVED_BASE_IDX 2
4254
+
#ifndef mmRCC_IOV_FUNC_IDENTIFIER
4254
4255
#define mmRCC_IOV_FUNC_IDENTIFIER 0x00c5
4255
4256
#define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
4257
+
#endif
4256
4258
4257
4259
4258
4260
// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+2
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
+2
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
···
2687
2687
#define mmRCC_CONFIG_MEMSIZE_BASE_IDX 2
2688
2688
#define mmRCC_CONFIG_RESERVED 0x00c4
2689
2689
#define mmRCC_CONFIG_RESERVED_BASE_IDX 2
2690
+
#ifndef mmRCC_IOV_FUNC_IDENTIFIER
2690
2691
#define mmRCC_IOV_FUNC_IDENTIFIER 0x00c5
2691
2692
#define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
2693
+
#endif
2692
2694
2693
2695
2694
2696
// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1