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drm/i915/vga: Introduce intel_vga_{read,write}()

VGA register are rather special since they either get accessed
via the global IO addresses, or possibly through MMIO on
pre-g4x platforms. Wrap all VGA register accesses in
intel_vga_{read,write}() to make it obvious where they get
accessed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251208182637.334-13-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

+29 -9
+4 -2
drivers/gpu/drm/i915/display/intel_crt.c
··· 33 33 #include <drm/drm_edid.h> 34 34 #include <drm/drm_print.h> 35 35 #include <drm/drm_probe_helper.h> 36 + #include <video/vga.h> 36 37 37 38 #include "intel_connector.h" 38 39 #include "intel_crt.h" ··· 56 55 #include "intel_pch_display.h" 57 56 #include "intel_pch_refclk.h" 58 57 #include "intel_pfit.h" 58 + #include "intel_vga.h" 59 59 60 60 /* Here's the desired hotplug mode */ 61 61 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_ENABLE | \ ··· 738 736 * border color for Color info. 739 737 */ 740 738 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 741 - st00 = intel_de_read8(display, _VGA_MSR_WRITE); 739 + st00 = intel_vga_read(display, VGA_MIS_W, true); 742 740 status = ((st00 & (1 << 4)) != 0) ? 743 741 connector_status_connected : 744 742 connector_status_disconnected; ··· 786 784 do { 787 785 count++; 788 786 /* Read the ST00 VGA status register */ 789 - st00 = intel_de_read8(display, _VGA_MSR_WRITE); 787 + st00 = intel_vga_read(display, VGA_MIS_W, true); 790 788 if (st00 & (1 << 4)) 791 789 detect++; 792 790 } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
-2
drivers/gpu/drm/i915/display/intel_crt_regs.h
··· 45 45 #define ADPA_VSYNC_ACTIVE_HIGH REG_BIT(4) 46 46 #define ADPA_HSYNC_ACTIVE_HIGH REG_BIT(3) 47 47 48 - #define _VGA_MSR_WRITE _MMIO(0x3c2) 49 - 50 48 #endif /* __INTEL_CRT_REGS_H__ */
+22 -5
drivers/gpu/drm/i915/display/intel_vga.c
··· 140 140 vga_put(pdev, VGA_RSRC_LEGACY_IO); 141 141 } 142 142 143 + u8 intel_vga_read(struct intel_display *display, u16 reg, bool mmio) 144 + { 145 + if (mmio) 146 + return intel_de_read8(display, _MMIO(reg)); 147 + else 148 + return inb(reg); 149 + } 150 + 151 + static void intel_vga_write(struct intel_display *display, u16 reg, u8 val, bool mmio) 152 + { 153 + if (mmio) 154 + intel_de_write8(display, _MMIO(reg), val); 155 + else 156 + outb(val, reg); 157 + } 158 + 143 159 /* Disable the VGA plane that we never use */ 144 160 void intel_vga_disable(struct intel_display *display) 145 161 { ··· 209 193 210 194 drm_WARN_ON(display->drm, !intel_pci_has_vga_io_decode(pdev)); 211 195 212 - outb(0x01, VGA_SEQ_I); 213 - sr1 = inb(VGA_SEQ_D); 214 - outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D); 196 + intel_vga_write(display, VGA_SEQ_I, 0x01, false); 197 + sr1 = intel_vga_read(display, VGA_SEQ_D, false); 198 + sr1 |= VGA_SR01_SCREEN_OFF; 199 + intel_vga_write(display, VGA_SEQ_D, sr1, false); 215 200 216 - msr = inb(VGA_MIS_R); 201 + msr = intel_vga_read(display, VGA_MIS_R, false); 217 202 /* 218 203 * Always disable VGA memory decode for iGPU so that 219 204 * intel_vga_set_decode() doesn't need to access VGA registers. ··· 234 217 * RMbus NoClaim errors. 235 218 */ 236 219 msr &= ~VGA_MIS_COLOR; 237 - outb(msr, VGA_MIS_W); 220 + intel_vga_write(display, VGA_MIS_W, msr, false); 238 221 239 222 intel_vga_put(display, io_decode); 240 223
+3
drivers/gpu/drm/i915/display/intel_vga.h
··· 6 6 #ifndef __INTEL_VGA_H__ 7 7 #define __INTEL_VGA_H__ 8 8 9 + #include <linux/types.h> 10 + 9 11 struct intel_display; 10 12 13 + u8 intel_vga_read(struct intel_display *display, u16 reg, bool mmio); 11 14 void intel_vga_reset_io_mem(struct intel_display *display); 12 15 void intel_vga_disable(struct intel_display *display); 13 16 void intel_vga_register(struct intel_display *display);