Merge tag 'tty-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

-17

Documentation/devicetree/bindings/goldfish/tty.txt

··· 1 - Android Goldfish TTY 2 - 3 - Android goldfish tty device generated by android emulator. 4 - 5 - Required properties: 6 - 7 - - compatible : should contain "google,goldfish-tty" to match emulator 8 - - reg : <registers mapping> 9 - - interrupts : <interrupt mapping> 10 - 11 - Example: 12 - 13 - goldfish_tty@1f004000 { 14 - compatible = "google,goldfish-tty"; 15 - reg = <0x1f004000 0x1000>; 16 - interrupts = <0xc>; 17 - };

+1

Documentation/devicetree/bindings/serial/8250.yaml

··· 160 160 - enum: 161 161 - mrvl,mmp-uart 162 162 - spacemit,k1-uart 163 + - spacemit,k3-uart 163 164 - const: intel,xscale-uart 164 165 - items: 165 166 - enum:

+41

Documentation/devicetree/bindings/serial/google,goldfish-tty.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/serial/google,goldfish-tty.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Google Goldfish TTY 8 + 9 + maintainers: 10 + - Kuan-Wei Chiu <visitorckw@gmail.com> 11 + 12 + allOf: 13 + - $ref: /schemas/serial/serial.yaml# 14 + 15 + description: 16 + Android goldfish TTY device generated by Android emulator. 17 + 18 + properties: 19 + compatible: 20 + const: google,goldfish-tty 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + interrupts: 26 + maxItems: 1 27 + 28 + required: 29 + - compatible 30 + - reg 31 + - interrupts 32 + 33 + unevaluatedProperties: false 34 + 35 + examples: 36 + - | 37 + serial@1f004000 { 38 + compatible = "google,goldfish-tty"; 39 + reg = <0x1f004000 0x1000>; 40 + interrupts = <12>; 41 + };

+94 -11

Documentation/devicetree/bindings/serial/renesas,rsci.yaml

··· 10 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 12 12 13 - allOf: 14 - - $ref: serial.yaml# 15 - 16 13 properties: 17 14 compatible: 18 15 oneOf: 19 - - items: 20 - - const: renesas,r9a09g087-rsci # RZ/N2H 21 - - const: renesas,r9a09g077-rsci # RZ/T2H 16 + - enum: 17 + - renesas,r9a09g047-rsci # RZ/G3E 18 + - renesas,r9a09g077-rsci # RZ/T2H 22 19 23 20 - items: 21 + - enum: 22 + - renesas,r9a09g056-rsci # RZ/V2N 23 + - renesas,r9a09g057-rsci # RZ/V2H(P) 24 + - const: renesas,r9a09g047-rsci 25 + 26 + - items: 27 + - const: renesas,r9a09g087-rsci # RZ/N2H 24 28 - const: renesas,r9a09g077-rsci # RZ/T2H 25 29 26 30 reg: 27 31 maxItems: 1 28 32 29 33 interrupts: 34 + minItems: 4 30 35 items: 31 36 - description: Error interrupt 32 37 - description: Receive buffer full interrupt 33 38 - description: Transmit buffer empty interrupt 34 39 - description: Transmit end interrupt 40 + - description: Active edge detection interrupt 41 + - description: Break field detection interrupt 35 42 36 43 interrupt-names: 44 + minItems: 4 37 45 items: 38 46 - const: eri 39 47 - const: rxi 40 48 - const: txi 41 49 - const: tei 50 + - const: aed 51 + - const: bfd 42 52 43 53 clocks: 44 54 minItems: 2 45 - maxItems: 3 55 + maxItems: 6 46 56 47 57 clock-names: 48 - minItems: 2 58 + oneOf: 59 + - items: 60 + - const: operation 61 + - const: bus 62 + - const: sck # optional external clock input 63 + 64 + minItems: 2 65 + 66 + - items: 67 + - const: pclk 68 + - const: tclk 69 + - const: tclk_div4 70 + - const: tclk_div16 71 + - const: tclk_div64 72 + - const: sck # optional external clock input 73 + 74 + minItems: 5 75 + 76 + resets: 49 77 items: 50 - - const: operation 51 - - const: bus 52 - - const: sck # optional external clock input 78 + - description: Input for resetting the APB clock 79 + - description: Input for resetting TCLK 80 + 81 + reset-names: 82 + items: 83 + - const: presetn 84 + - const: tresetn 53 85 54 86 power-domains: 55 87 maxItems: 1 ··· 93 61 - clocks 94 62 - clock-names 95 63 - power-domains 64 + 65 + allOf: 66 + - $ref: serial.yaml# 67 + 68 + - if: 69 + properties: 70 + compatible: 71 + contains: 72 + const: renesas,r9a09g077-rsci 73 + then: 74 + properties: 75 + interrupts: 76 + maxItems: 4 77 + 78 + interrupt-names: 79 + maxItems: 4 80 + 81 + clocks: 82 + minItems: 2 83 + maxItems: 3 84 + 85 + clock-names: 86 + minItems: 2 87 + maxItems: 3 88 + 89 + resets: false 90 + 91 + - if: 92 + properties: 93 + compatible: 94 + contains: 95 + const: renesas,r9a09g047-rsci 96 + then: 97 + properties: 98 + interrupts: 99 + minItems: 6 100 + 101 + interrupt-names: 102 + minItems: 6 103 + 104 + clocks: 105 + minItems: 5 106 + maxItems: 6 107 + 108 + clock-names: 109 + minItems: 5 110 + maxItems: 6 111 + 112 + required: 113 + - resets 114 + - reset-names 96 115 97 116 unevaluatedProperties: false 98 117

+6 -10

Documentation/devicetree/bindings/serial/renesas,scif.yaml

··· 12 12 properties: 13 13 compatible: 14 14 oneOf: 15 + - enum: 16 + - renesas,scif-r7s9210 # RZ/A2 17 + - renesas,scif-r9a07g044 # RZ/G2{L,LC} 18 + - renesas,scif-r9a09g057 # RZ/V2H(P) 19 + 15 20 - items: 16 21 - enum: 17 22 - renesas,scif-r7s72100 # RZ/A1H 18 23 - const: renesas,scif # generic SCIF compatible UART 19 - 20 - - items: 21 - - enum: 22 - - renesas,scif-r7s9210 # RZ/A2 23 24 24 25 - items: 25 26 - enum: ··· 79 78 80 79 - items: 81 80 - enum: 82 - - renesas,scif-r9a07g044 # RZ/G2{L,LC} 83 - 84 - - items: 85 - - enum: 86 81 - renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five 87 82 - renesas,scif-r9a07g054 # RZ/V2L 88 83 - renesas,scif-r9a08g045 # RZ/G3S 84 + - renesas,scif-r9a08g046 # RZ/G3L 89 85 - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback 90 - 91 - - const: renesas,scif-r9a09g057 # RZ/V2H(P) 92 86 93 87 - items: 94 88 - enum:

+1 -25

Documentation/misc-devices/oxsemi-tornado.rst

··· 89 89 limitation imposed by ``serial8250_get_baud_rate`` standard baud rates 90 90 below 300bps become unavailable in the regular way, e.g. the rate of 91 91 200bps requires the baud base to be divided by 78125 and that is beyond 92 - the unsigned 16-bit range. The historic spd_cust feature can still be 93 - used by encoding the values for, the prescaler, the oversampling rate 94 - and the clock divisor (DLM/DLL) as follows to obtain such rates if so 95 - required: 96 - 97 - :: 98 - 99 - 31 29 28 20 19 16 15 0 100 - +-----+-----------------+-------+-------------------------------+ 101 - |0 0 0| CPR2:CPR | TCR | DLM:DLL | 102 - +-----+-----------------+-------+-------------------------------+ 103 - 104 - Use a value such encoded for the ``custom_divisor`` field along with the 105 - ASYNC_SPD_CUST flag set in the ``flags`` field in ``struct serial_struct`` 106 - passed with the TIOCSSERIAL ioctl(2), such as with the setserial(8) 107 - utility and its ``divisor`` and ``spd_cust`` parameters, and then select 108 - the baud rate of 38400bps. Note that the value of 0 in TCR sets the 109 - oversampling rate to 16 and prescaler values below 1 in CPR2/CPR are 110 - clamped by the driver to 1. 111 - 112 - For example the value of 0x1f4004e2 will set CPR2/CPR, TCR and DLM/DLL 113 - respectively to 0x1f4, 0x0 and 0x04e2, choosing the prescaler value, 114 - the oversampling rate and the clock divisor of 62.500, 16 and 1250 115 - respectively. These parameters will set the baud rate for the serial 116 - port to 62500000 / 62.500 / 1250 / 16 = 50bps. 92 + the unsigned 16-bit range. 117 93 118 94 Maciej W. Rozycki <macro@orcam.me.uk> 119 95

+8 -8

drivers/bluetooth/hci_aml.c

··· 677 677 .dequeue = aml_dequeue, 678 678 }; 679 679 680 - static void aml_device_driver_shutdown(struct device *dev) 681 - { 682 - struct aml_serdev *amldev = dev_get_drvdata(dev); 683 - 684 - aml_power_off(amldev); 685 - } 686 - 687 680 static int aml_serdev_probe(struct serdev_device *serdev) 688 681 { 689 682 struct aml_serdev *amldev; ··· 707 714 hci_uart_unregister_device(&amldev->serdev_hu); 708 715 } 709 716 717 + static void aml_serdev_shutdown(struct serdev_device *serdev) 718 + { 719 + struct aml_serdev *amldev = serdev_device_get_drvdata(serdev); 720 + 721 + aml_power_off(amldev); 722 + } 723 + 710 724 static const struct aml_device_data data_w155s2 = { 711 725 .iccm_offset = 256 * 1024, 712 726 }; ··· 732 732 static struct serdev_device_driver aml_serdev_driver = { 733 733 .probe = aml_serdev_probe, 734 734 .remove = aml_serdev_remove, 735 + .shutdown = aml_serdev_shutdown, 735 736 .driver = { 736 737 .name = "hci_uart_aml", 737 738 .of_match_table = aml_bluetooth_of_match, 738 - .shutdown = aml_device_driver_shutdown, 739 739 }, 740 740 }; 741 741

+2 -3

drivers/bluetooth/hci_qca.c

··· 2570 2570 hci_uart_unregister_device(&qcadev->serdev_hu); 2571 2571 } 2572 2572 2573 - static void qca_serdev_shutdown(struct device *dev) 2573 + static void qca_serdev_shutdown(struct serdev_device *serdev) 2574 2574 { 2575 2575 int ret; 2576 2576 int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS); 2577 - struct serdev_device *serdev = to_serdev_device(dev); 2578 2577 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev); 2579 2578 struct hci_uart *hu = &qcadev->serdev_hu; 2580 2579 struct hci_dev *hdev = hu->hdev; ··· 2795 2796 static struct serdev_device_driver qca_serdev_driver = { 2796 2797 .probe = qca_serdev_probe, 2797 2798 .remove = qca_serdev_remove, 2799 + .shutdown = qca_serdev_shutdown, 2798 2800 .driver = { 2799 2801 .name = "hci_uart_qca", 2800 2802 .of_match_table = of_match_ptr(qca_bluetooth_of_match), 2801 2803 .acpi_match_table = ACPI_PTR(qca_bluetooth_acpi_match), 2802 - .shutdown = qca_serdev_shutdown, 2803 2804 .pm = &qca_pm_ops, 2804 2805 #ifdef CONFIG_DEV_COREDUMP 2805 2806 .coredump = hciqca_coredump,

+3 -3

drivers/platform/surface/aggregator/core.c

··· 380 380 381 381 /* -- Power management. ----------------------------------------------------- */ 382 382 383 - static void ssam_serial_hub_shutdown(struct device *dev) 383 + static void ssam_serial_hub_shutdown(struct serdev_device *serdev) 384 384 { 385 - struct ssam_controller *c = dev_get_drvdata(dev); 385 + struct ssam_controller *c = dev_get_drvdata(&serdev->dev); 386 386 int status; 387 387 388 388 /* ··· 834 834 static struct serdev_device_driver ssam_serial_hub = { 835 835 .probe = ssam_serial_hub_probe, 836 836 .remove = ssam_serial_hub_remove, 837 + .shutdown = ssam_serial_hub_shutdown, 837 838 .driver = { 838 839 .name = "surface_serial_hub", 839 840 .acpi_match_table = ACPI_PTR(ssam_serial_hub_acpi_match), 840 841 .of_match_table = of_match_ptr(ssam_serial_hub_of_match), 841 842 .pm = &ssam_serial_hub_pm_ops, 842 - .shutdown = ssam_serial_hub_shutdown, 843 843 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 844 844 }, 845 845 };

+2 -3

drivers/tty/hvc/hvc_iucv.c

··· 9 9 * 10 10 * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com> 11 11 */ 12 - #define KMSG_COMPONENT "hvc_iucv" 13 - #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 12 + #define pr_fmt(fmt) "hvc_iucv: " fmt 14 13 15 14 #include <linux/types.h> 16 15 #include <linux/slab.h> ··· 1343 1344 } 1344 1345 } 1345 1346 1346 - hvc_iucv_buffer_cache = kmem_cache_create(KMSG_COMPONENT, 1347 + hvc_iucv_buffer_cache = kmem_cache_create("hvc_iucv", 1347 1348 sizeof(struct iucv_tty_buffer), 1348 1349 0, 0, NULL); 1349 1350 if (!hvc_iucv_buffer_cache) {

+2

drivers/tty/n_hdlc.c

··· 127 127 * @rx_buf_list: list of received frame buffers 128 128 * @tx_free_buf_list: list unused transmit frame buffers 129 129 * @rx_free_buf_list: list unused received frame buffers 130 + * @write_work: work struct for deferred frame transmission 131 + * @tty_for_write_work: pointer to tty instance used by the @write_work 130 132 */ 131 133 struct n_hdlc { 132 134 bool tbusy;

+21

drivers/tty/serdev/core.c

··· 414 414 sdrv->remove(to_serdev_device(dev)); 415 415 } 416 416 417 + static void serdev_drv_shutdown(struct device *dev) 418 + { 419 + const struct serdev_device_driver *sdrv = 420 + to_serdev_device_driver(dev->driver); 421 + 422 + if (dev->driver && sdrv->shutdown) 423 + sdrv->shutdown(to_serdev_device(dev)); 424 + } 425 + 417 426 static const struct bus_type serdev_bus_type = { 418 427 .name = "serial", 419 428 .match = serdev_device_match, 420 429 .probe = serdev_drv_probe, 421 430 .remove = serdev_drv_remove, 431 + .shutdown = serdev_drv_shutdown, 422 432 }; 423 433 424 434 /** ··· 824 814 } 825 815 EXPORT_SYMBOL_GPL(serdev_controller_remove); 826 816 817 + static void serdev_legacy_shutdown(struct serdev_device *serdev) 818 + { 819 + struct device *dev = &serdev->dev; 820 + struct device_driver *driver = dev->driver; 821 + 822 + driver->shutdown(dev); 823 + } 824 + 827 825 /** 828 826 * __serdev_device_driver_register() - Register client driver with serdev core 829 827 * @sdrv: client driver to be associated with client-device. ··· 847 829 848 830 /* force drivers to async probe so I/O is possible in probe */ 849 831 sdrv->driver.probe_type = PROBE_PREFER_ASYNCHRONOUS; 832 + 833 + if (!sdrv->shutdown && sdrv->driver.shutdown) 834 + sdrv->shutdown = serdev_legacy_shutdown; 850 835 851 836 return driver_register(&sdrv->driver); 852 837 }

+16 -7

drivers/tty/serial/8250/8250_dw.c

··· 643 643 if (err) 644 644 return err; 645 645 646 + err = pm_runtime_set_active(dev); 647 + if (err) 648 + return dev_err_probe(dev, err, "Failed to set the runtime suspend as active\n"); 649 + 646 650 data->uart_16550_compatible = device_property_read_bool(dev, "snps,uart-16550-compatible"); 647 651 648 652 data->pdata = device_get_match_data(p->dev); ··· 689 685 690 686 platform_set_drvdata(pdev, data); 691 687 692 - pm_runtime_set_active(dev); 693 688 pm_runtime_enable(dev); 694 689 695 690 return 0; ··· 744 741 745 742 static int dw8250_runtime_resume(struct device *dev) 746 743 { 744 + int ret; 747 745 struct dw8250_data *data = dev_get_drvdata(dev); 748 746 749 - clk_prepare_enable(data->pclk); 747 + ret = clk_prepare_enable(data->pclk); 748 + if (ret) 749 + return ret; 750 750 751 - clk_prepare_enable(data->clk); 751 + ret = clk_prepare_enable(data->clk); 752 + if (ret) { 753 + clk_disable_unprepare(data->pclk); 754 + return ret; 755 + } 752 756 753 757 return 0; 754 758 } 755 759 756 - static const struct dev_pm_ops dw8250_pm_ops = { 757 - SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 758 - RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 759 - }; 760 + static _DEFINE_DEV_PM_OPS(dw8250_pm_ops, dw8250_suspend, dw8250_resume, 761 + dw8250_runtime_suspend, dw8250_runtime_resume, 762 + NULL); 760 763 761 764 static const struct dw8250_platform_data dw8250_dw_apb = { 762 765 .usr_reg = DW_UART_USR,

+19 -8

drivers/tty/serial/8250/8250_keba.c

··· 6 6 */ 7 7 8 8 #include <linux/auxiliary_bus.h> 9 - #include <linux/device.h> 9 + #include <linux/bits.h> 10 + #include <linux/container_of.h> 11 + #include <linux/dev_printk.h> 12 + #include <linux/device/devres.h> 13 + #include <linux/err.h> 10 14 #include <linux/io.h> 11 15 #include <linux/misc/keba.h> 16 + #include <linux/mod_devicetable.h> 12 17 #include <linux/module.h> 18 + #include <linux/serial_core.h> 19 + #include <linux/spinlock.h> 20 + #include <linux/types.h> 13 21 14 22 #include "8250.h" 15 23 ··· 50 42 #define KUART_CAPABILITY_RS422 BIT(KUART_MODE_RS422) 51 43 #define KUART_CAPABILITY_RS232 BIT(KUART_MODE_RS232) 52 44 #define KUART_CAPABILITY_MASK GENMASK(3, 0) 45 + 46 + /* registers for Indexed Control Register access in enhanced mode */ 47 + #define KUART_EMODE_ICR_OFFSET UART_SCR 48 + #define KUART_EMODE_ICR_VALUE UART_LSR 53 49 54 50 /* Additional Control Register DTR line configuration */ 55 51 #define UART_ACR_DTRLC_MASK 0x18 ··· 102 90 u8 acr; 103 91 104 92 /* set index register to 0 to access ACR register */ 105 - serial_out(up, UART_SCR, UART_ACR); 93 + serial_out(up, KUART_EMODE_ICR_OFFSET, UART_ACR); 106 94 107 95 /* set value register to 0x10 writing DTR mode (1,0) */ 108 - acr = serial_in(up, UART_LSR); 96 + acr = serial_in(up, KUART_EMODE_ICR_VALUE); 109 97 acr &= ~UART_ACR_DTRLC_MASK; 110 98 acr |= dtrlc; 111 - serial_out(up, UART_LSR, acr); 99 + serial_out(up, KUART_EMODE_ICR_VALUE, acr); 112 100 } 113 101 114 102 static int kuart_rs485_config(struct uart_port *port, struct ktermios *termios, ··· 252 240 } 253 241 254 242 retval = serial8250_register_8250_port(&uart); 255 - if (retval < 0) { 256 - dev_err(&auxdev->dev, "UART registration failed!\n"); 257 - return retval; 258 - } 243 + if (retval < 0) 244 + return dev_err_probe(&auxdev->dev, retval, 245 + "UART registration failed!\n"); 259 246 kuart->line = retval; 260 247 261 248 return 0;

+4 -11

drivers/tty/serial/8250/8250_men_mcb.c

··· 28 28 #define MEN_UART3_MASK 0x04 29 29 #define MEN_UART4_MASK 0x08 30 30 31 - #define MEN_Z125_UARTS_AVAILABLE 0x01 32 - 33 31 #define MEN_Z025_MAX_UARTS 4 34 32 #define MEN_UART_MEM_SIZE 0x10 35 33 #define MEM_UART_REGISTER_SIZE 0x01 ··· 40 42 41 43 #define MEN_READ_REGISTER(addr) readb(addr) 42 44 43 - #define MAX_PORTS 4 44 - 45 45 struct serial_8250_men_mcb_data { 46 46 int num_ports; 47 - int line[MAX_PORTS]; 48 - unsigned int offset[MAX_PORTS]; 47 + int line[MEN_Z025_MAX_UARTS]; 48 + unsigned int offset[MEN_Z025_MAX_UARTS]; 49 49 }; 50 50 51 51 /* ··· 122 126 if (res < 0) 123 127 return res; 124 128 125 - for (i = 0; i < MAX_PORTS; i++) { 129 + for (i = 0; i < MEN_Z025_MAX_UARTS; i++) { 126 130 mask = 0x1 << i; 127 131 switch (uarts_available & mask) { 128 132 case MEN_UART1_MASK: ··· 146 150 } 147 151 } 148 152 149 - if (count <= 0 || count > MAX_PORTS) { 153 + if (count <= 0 || count > MEN_Z025_MAX_UARTS) { 150 154 dev_err(&mdev->dev, "unexpected number of ports: %u\n", 151 155 count); 152 156 return -ENODEV; ··· 264 268 MODULE_LICENSE("GPL v2"); 265 269 MODULE_DESCRIPTION("MEN 8250 UART driver"); 266 270 MODULE_AUTHOR("Michael Moese <michael.moese@men.de"); 267 - MODULE_ALIAS("mcb:16z125"); 268 - MODULE_ALIAS("mcb:16z025"); 269 - MODULE_ALIAS("mcb:16z057"); 270 271 MODULE_IMPORT_NS("MCB");

+24 -19

drivers/tty/serial/8250/8250_omap.c

··· 100 100 #define OMAP_UART_REV_52 0x0502 101 101 #define OMAP_UART_REV_63 0x0603 102 102 103 + /* Resume register */ 104 + #define UART_OMAP_RESUME 0x0B 105 + 103 106 /* Interrupt Enable Register 2 */ 104 107 #define UART_OMAP_IER2 0x1B 105 108 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) ··· 122 119 /* Timeout low and High */ 123 120 #define UART_OMAP_TO_L 0x26 124 121 #define UART_OMAP_TO_H 0x27 125 - 126 122 struct omap8250_priv { 127 123 void __iomem *membase; 128 124 int line; ··· 243 241 unsigned int div_13, div_16; 244 242 unsigned int abs_d13, abs_d16; 245 243 246 - /* 247 - * Old custom speed handling. 248 - */ 249 - if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 250 - priv->quot = port->custom_divisor & UART_DIV_MAX; 251 - /* 252 - * I assume that nobody is using this. But hey, if somebody 253 - * would like to specify the divisor _and_ the mode then the 254 - * driver is ready and waiting for it. 255 - */ 256 - if (port->custom_divisor & (1 << 16)) 257 - priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 258 - else 259 - priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 260 - return; 261 - } 262 244 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 263 245 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 264 246 ··· 915 929 goto out; 916 930 917 931 cookie = dma->rx_cookie; 918 - dma->rx_running = 0; 919 932 920 933 /* Re-enable RX FIFO interrupt now that transfer is complete */ 921 934 if (priv->habit & UART_HAS_RHR_IT_DIS) { ··· 948 963 goto out; 949 964 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 950 965 966 + dma->rx_running = 0; 951 967 p->port.icount.rx += ret; 952 968 p->port.icount.buf_overrun += count - ret; 953 969 out: ··· 1242 1256 return status; 1243 1257 } 1244 1258 1259 + static void am654_8250_handle_uart_errors(struct uart_8250_port *up, u8 iir, u16 status) 1260 + { 1261 + if (status & UART_LSR_OE) { 1262 + serial8250_clear_and_reinit_fifos(up); 1263 + serial_in(up, UART_LSR); 1264 + serial_in(up, UART_OMAP_RESUME); 1265 + } else { 1266 + if (status & (UART_LSR_FE | UART_LSR_PE | UART_LSR_BI)) 1267 + serial_in(up, UART_RX); 1268 + if (iir & UART_IIR_XOFF) 1269 + serial_in(up, UART_IIR); 1270 + } 1271 + } 1272 + 1245 1273 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1246 1274 u16 status) 1247 1275 { ··· 1266 1266 * Queue a new transfer if FIFO has data. 1267 1267 */ 1268 1268 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1269 - (up->ier & UART_IER_RDI)) { 1269 + (up->ier & UART_IER_RDI) && !(status & UART_LSR_OE)) { 1270 + am654_8250_handle_uart_errors(up, iir, status); 1270 1271 omap_8250_rx_dma(up); 1271 1272 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1272 1273 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { ··· 1283 1282 serial_out(up, UART_OMAP_EFR2, 0x0); 1284 1283 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1285 1284 serial_out(up, UART_IER, up->ier); 1285 + } else { 1286 + am654_8250_handle_uart_errors(up, iir, status); 1286 1287 } 1287 1288 } 1288 1289 ··· 1365 1362 1366 1363 if (!device_may_wakeup(dev)) 1367 1364 return 0; 1365 + 1366 + device_set_out_band_wakeup(dev); 1368 1367 1369 1368 return pinctrl_select_state(priv->pinctrl, priv->pinctrl_wakeup); 1370 1369 }

+37 -48

drivers/tty/serial/8250/8250_pci.c

··· 1205 1205 u8 tcr; 1206 1206 int i; 1207 1207 1208 - /* Old custom speed handling. */ 1209 - if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1210 - unsigned int cust_div = port->custom_divisor; 1208 + best_squot = quot_scale; 1209 + for (i = 0; i < ARRAY_SIZE(p); i++) { 1210 + unsigned int spre; 1211 + unsigned int srem; 1212 + u8 cp; 1213 + u8 tc; 1211 1214 1212 - quot = cust_div & UART_DIV_MAX; 1213 - tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1214 - cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1215 - if (cpr < OXSEMI_TORNADO_CPR_MIN) 1216 - cpr = OXSEMI_TORNADO_CPR_DEF; 1217 - } else { 1218 - best_squot = quot_scale; 1219 - for (i = 0; i < ARRAY_SIZE(p); i++) { 1220 - unsigned int spre; 1221 - unsigned int srem; 1222 - u8 cp; 1223 - u8 tc; 1215 + tc = p[i][0]; 1216 + cp = p[i][1]; 1217 + spre = tc * cp; 1224 1218 1225 - tc = p[i][0]; 1226 - cp = p[i][1]; 1227 - spre = tc * cp; 1219 + srem = sdiv % spre; 1220 + if (srem > spre / 2) 1221 + srem = spre - srem; 1222 + squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1228 1223 1229 - srem = sdiv % spre; 1230 - if (srem > spre / 2) 1231 - srem = spre - srem; 1232 - squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1233 - 1234 - if (srem == 0) { 1235 - tcr = tc; 1236 - cpr = cp; 1237 - quot = sdiv / spre; 1238 - break; 1239 - } else if (squot < best_squot) { 1240 - best_squot = squot; 1241 - tcr = tc; 1242 - cpr = cp; 1243 - quot = DIV_ROUND_CLOSEST(sdiv, spre); 1244 - } 1224 + if (srem == 0) { 1225 + tcr = tc; 1226 + cpr = cp; 1227 + quot = sdiv / spre; 1228 + break; 1229 + } else if (squot < best_squot) { 1230 + best_squot = squot; 1231 + tcr = tc; 1232 + cpr = cp; 1233 + quot = DIV_ROUND_CLOSEST(sdiv, spre); 1245 1234 } 1246 - while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1247 - quot % 2 == 0) { 1235 + } 1236 + while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1237 + quot % 2 == 0) { 1238 + quot >>= 1; 1239 + tcr <<= 1; 1240 + } 1241 + while (quot > UART_DIV_MAX) { 1242 + if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1248 1243 quot >>= 1; 1249 1244 tcr <<= 1; 1250 - } 1251 - while (quot > UART_DIV_MAX) { 1252 - if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1253 - quot >>= 1; 1254 - tcr <<= 1; 1255 - } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1256 - quot >>= 1; 1257 - cpr <<= 1; 1258 - } else { 1259 - quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1260 - cpr = OXSEMI_TORNADO_CPR_MASK; 1261 - } 1245 + } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1246 + quot >>= 1; 1247 + cpr <<= 1; 1248 + } else { 1249 + quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1250 + cpr = OXSEMI_TORNADO_CPR_MASK; 1262 1251 } 1263 1252 } 1264 1253

+48 -47

drivers/tty/serial/8250/Kconfig

··· 116 116 117 117 config SERIAL_8250_PCILIB 118 118 bool 119 + depends on SERIAL_8250 && PCI 119 120 120 121 config SERIAL_8250_PCI 121 122 tristate "8250/16550 PCI device support" ··· 206 205 kernel: saying N will just cause the configurator to skip all 207 206 the questions about serial driver options. If unsure, say N. 208 207 208 + config SERIAL_8250_SHARE_IRQ 209 + bool "Support for sharing serial interrupts" 210 + depends on SERIAL_8250_EXTENDED 211 + help 212 + Some serial boards have hardware support which allows multiple dumb 213 + serial ports on the same board to share a single IRQ. To enable 214 + support for this in the serial driver, say Y here. 215 + 216 + config SERIAL_8250_DETECT_IRQ 217 + bool "Autodetect IRQ on standard ports (unsafe)" 218 + depends on SERIAL_8250_EXTENDED 219 + help 220 + Say Y here if you want the kernel to try to guess which IRQ 221 + to use for your serial port. 222 + 223 + This is considered unsafe; it is far better to configure the IRQ in 224 + a boot script using the setserial command. 225 + 226 + If unsure, say N. 227 + 228 + config SERIAL_8250_RSA 229 + bool "Support RSA serial ports" 230 + depends on SERIAL_8250_EXTENDED 231 + help 232 + Say Y here if you have a IODATA RSA-DV II/S ISA card and 233 + would like to use its >115kbps speeds. 234 + You will need to provide module parameter "probe_rsa", or boot-time 235 + parameter 8250.probe_rsa with I/O addresses of this card then. 236 + 237 + If you don't have such card, or if unsure, say N. 238 + 209 239 config SERIAL_8250_MANY_PORTS 210 240 bool "Support more than 4 legacy serial ports" 211 241 depends on SERIAL_8250_EXTENDED ··· 271 239 272 240 To compile this driver as a module, choose M here: the module 273 241 will be called 8250_accent. 274 - 275 - config SERIAL_8250_ASPEED_VUART 276 - tristate "Aspeed Virtual UART" 277 - depends on SERIAL_8250 278 - depends on OF 279 - depends on MFD_SYSCON 280 - depends on ARCH_ASPEED || COMPILE_TEST 281 - select REGMAP 282 - help 283 - If you want to use the virtual UART (VUART) device on Aspeed 284 - BMC platforms, enable this option. This enables the 16550A- 285 - compatible device on the local LPC bus, giving a UART device 286 - with no physical RS232 connections. 287 242 288 243 config SERIAL_8250_BOCA 289 244 tristate "Support Boca cards" ··· 312 293 serial driver for the serial interface. This driver support 313 294 will ensure to support baud rates upto 1.5Mpbs. 314 295 296 + config SERIAL_8250_ASPEED_VUART 297 + tristate "Aspeed Virtual UART" 298 + depends on SERIAL_8250 299 + depends on OF 300 + depends on MFD_SYSCON 301 + depends on ARCH_ASPEED || COMPILE_TEST 302 + select REGMAP 303 + help 304 + If you want to use the virtual UART (VUART) device on Aspeed 305 + BMC platforms, enable this option. This enables the 16550A- 306 + compatible device on the local LPC bus, giving a UART device 307 + with no physical RS232 connections. 308 + 315 309 # 316 310 # Misc. options/drivers. 317 311 # 318 - 319 - config SERIAL_8250_SHARE_IRQ 320 - bool "Support for sharing serial interrupts" 321 - depends on SERIAL_8250_EXTENDED 322 - help 323 - Some serial boards have hardware support which allows multiple dumb 324 - serial ports on the same board to share a single IRQ. To enable 325 - support for this in the serial driver, say Y here. 326 - 327 - config SERIAL_8250_DETECT_IRQ 328 - bool "Autodetect IRQ on standard ports (unsafe)" 329 - depends on SERIAL_8250_EXTENDED 330 - help 331 - Say Y here if you want the kernel to try to guess which IRQ 332 - to use for your serial port. 333 - 334 - This is considered unsafe; it is far better to configure the IRQ in 335 - a boot script using the setserial command. 336 - 337 - If unsure, say N. 338 - 339 - config SERIAL_8250_RSA 340 - bool "Support RSA serial ports" 341 - depends on SERIAL_8250_EXTENDED 342 - help 343 - Say Y here if you have a IODATA RSA-DV II/S ISA card and 344 - would like to use its >115kbps speeds. 345 - You will need to provide module parameter "probe_rsa", or boot-time 346 - parameter 8250.probe_rsa with I/O addresses of this card then. 347 - 348 - If you don't have such card, or if unsure, say N. 349 - 350 - config SERIAL_8250_DWLIB 351 - bool 352 312 353 313 config SERIAL_8250_ACORN 354 314 tristate "Acorn expansion card serial port support" ··· 594 596 are probed through devicetree, including Open Firmware based 595 597 PowerPC systems and embedded systems on architectures using the 596 598 flattened device tree format. 599 + 600 + config SERIAL_8250_DWLIB 601 + bool

+17 -17

drivers/tty/serial/Kconfig

··· 413 413 your boot loader (lilo or loadlin) about how to pass options to the 414 414 kernel at boot time.) 415 415 416 + config SERIAL_PXA_NON8250 417 + bool 418 + depends on !SERIAL_8250 || COMPILE_TEST 419 + 416 420 config SERIAL_PXA 417 421 bool "PXA serial port support (DEPRECATED)" 418 422 depends on ARCH_PXA || ARCH_MMP ··· 429 425 430 426 Unless you have a specific need, you should use SERIAL_8250_PXA 431 427 instead of this. 432 - 433 - config SERIAL_PXA_NON8250 434 - bool 435 - depends on !SERIAL_8250 || COMPILE_TEST 436 428 437 429 config SERIAL_PXA_CONSOLE 438 430 bool "Console on PXA serial port (DEPRECATED)" ··· 486 486 can enable its onboard serial port by enabling this option. 487 487 488 488 config SERIAL_IMX_CONSOLE 489 - tristate "Console on IMX serial port" 489 + bool "Console on IMX serial port" 490 490 depends on SERIAL_IMX 491 491 select SERIAL_CORE_CONSOLE 492 492 help 493 493 If you have enabled the serial port on the Freescale IMX 494 - CPU you can make it the console by answering Y/M to this option. 494 + CPU you can make it the console by answering Y to this option. 495 495 496 - Even if you say Y/M here, the currently visible virtual console 496 + Even if you say Y here, the currently visible virtual console 497 497 (/dev/tty0) will still be used as the system console by default, but 498 498 you can alter that using a kernel command line option such as 499 499 "console=ttymxc0". (Try "man bootparam" or see the documentation of ··· 671 671 default ARCH_RENESAS 672 672 673 673 config SERIAL_SH_SCI_DMA 674 - bool "DMA support" if EXPERT 674 + bool "Support for DMA on SuperH SCI(F)" if EXPERT 675 675 depends on SERIAL_SH_SCI && DMA_ENGINE 676 676 default ARCH_RENESAS 677 677 ··· 863 863 This driver can also be built as a module. If so, the module 864 864 will be called icom. 865 865 866 + config HAS_TXX9_SERIAL 867 + bool 868 + 866 869 config SERIAL_TXX9 867 870 bool "TMPTX39XX/49XX SIO support" 868 871 depends on HAS_TXX9_SERIAL 869 872 select SERIAL_CORE 870 873 default y 871 - 872 - config HAS_TXX9_SERIAL 873 - bool 874 874 875 875 config SERIAL_TXX9_NR_UARTS 876 876 int "Maximum number of TMPTX39XX/49XX SIO ports" ··· 1251 1251 Set this to the number of serial ports you want the driver 1252 1252 to support. 1253 1253 1254 - config SERIAL_MPS2_UART_CONSOLE 1255 - bool "MPS2 UART console support" 1256 - depends on SERIAL_MPS2_UART 1257 - select SERIAL_CORE_CONSOLE 1258 - select SERIAL_EARLYCON 1259 - 1260 1254 config SERIAL_MPS2_UART 1261 1255 bool "MPS2 UART port" 1262 1256 depends on ARCH_MPS2 || COMPILE_TEST 1263 1257 select SERIAL_CORE 1264 1258 help 1265 1259 This driver support the UART ports on ARM MPS2. 1260 + 1261 + config SERIAL_MPS2_UART_CONSOLE 1262 + bool "MPS2 UART console support" 1263 + depends on SERIAL_MPS2_UART 1264 + select SERIAL_CORE_CONSOLE 1265 + select SERIAL_EARLYCON 1266 1266 1267 1267 config SERIAL_ARC 1268 1268 tristate "ARC UART driver support"

-1

drivers/tty/serial/men_z135_uart.c

··· 919 919 MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>"); 920 920 MODULE_LICENSE("GPL v2"); 921 921 MODULE_DESCRIPTION("MEN 16z135 High Speed UART"); 922 - MODULE_ALIAS("mcb:16z135"); 923 922 MODULE_IMPORT_NS("MCB");

+277 -32

drivers/tty/serial/rsci.c

··· 11 11 #include <linux/serial_core.h> 12 12 #include <linux/serial_sci.h> 13 13 #include <linux/tty_flip.h> 14 + 15 + #include "serial_mctrl_gpio.h" 14 16 #include "rsci.h" 15 17 16 18 MODULE_IMPORT_NS("SH_SCI"); ··· 26 24 #define CCR3 0x14 27 25 #define CCR4 0x18 28 26 #define FCR 0x24 29 - #define DCR 0x30 30 27 #define CSR 0x48 31 28 #define FRSR 0x50 32 29 #define FTSR 0x54 ··· 36 35 #define RDR_FFER BIT(12) /* FIFO Framing Error */ 37 36 #define RDR_FPER BIT(11) /* FIFO Parity Error */ 38 37 #define RDR_RDAT_MSK GENMASK(8, 0) 39 - 40 - /* TDR (Transmit Data Register) */ 41 - #define TDR_MPBT BIT(9) /* Multiprocessor Transfer */ 42 - #define TDR_TDAT_9BIT_LSHIFT 0 43 - #define TDR_TDAT_9BIT_VAL 0x1FF 44 - #define TDR_TDAT_9BIT_MSK (TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT) 45 38 46 39 /* CCR0 (Common Control Register 0) */ 47 40 #define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */ ··· 60 65 #define CCR1_SPB2DT BIT(4) /* Serial Port Break Data Select */ 61 66 #define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */ 62 67 #define CCR1_CTSE BIT(0) /* CTS Enable */ 68 + 69 + /* CCR2 (Common Control Register 2) */ 70 + #define CCR2_INIT 0xFF000004 71 + #define CCR2_CKS_TCLK (0) /* TCLK clock */ 72 + #define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */ 73 + #define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */ 74 + #define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */ 75 + #define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */ 76 + #define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Select */ 77 + #define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */ 78 + #define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select */ 79 + 80 + /* CCR3 (Common Control Register 3) */ 81 + #define CCR3_INIT 0x1203 82 + #define CCR3_BLK BIT(29) /* Block Transfer Mode */ 83 + #define CCR3_GM BIT(28) /* GSM Mode */ 84 + #define CCR3_CKE1 BIT(25) /* Clock Enable 1 */ 85 + #define CCR3_CKE0 BIT(24) /* Clock Enable 0 */ 86 + #define CCR3_DEN BIT(21) /* Driver Enabled */ 87 + #define CCR3_FM BIT(20) /* FIFO Mode Select */ 88 + #define CCR3_MP BIT(19) /* Multi-Processor Mode */ 89 + #define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */ 90 + #define CCR3_MOD_IRDA BIT(16) /* Smart card interface mode */ 91 + #define CCR3_MOD_CLK_SYNC BIT(17) /* Clock synchronous mode */ 92 + #define CCR3_MOD_SPI (BIT(17) | BIT(16)) /* Simple SPI mode */ 93 + #define CCR3_MOD_I2C BIT(18) /* Simple I2C mode */ 94 + #define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Select */ 95 + #define CCR3_STP BIT(14) /* Stop bit Length */ 96 + #define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */ 97 + #define CCR3_LSBF BIT(12) /* LSB First select */ 98 + #define CCR3_CHR1 BIT(9) /* Character Length */ 99 + #define CCR3_CHR0 BIT(8) /* Character Length */ 100 + #define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */ 101 + #define CCR3_CPOL BIT(1) /* Clock Polarity Select */ 102 + #define CCR3_CPHA BIT(0) /* Clock Phase Select */ 63 103 64 104 /* FCR (FIFO Control Register) */ 65 105 #define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */ ··· 149 119 /* FFCLR (FIFO Flag CLear Register) */ 150 120 #define FFCLR_DRC BIT(0) /* DR Clear */ 151 121 152 - #define DCR_DEPOL BIT(0) 153 - 154 122 static u32 rsci_serial_in(struct uart_port *p, int offset) 155 123 { 156 124 return readl(p->membase + offset); ··· 165 137 rsci_serial_out(port, FFCLR, FFCLR_DRC); 166 138 } 167 139 168 - static void rsci_clear_SCxSR(struct uart_port *port, unsigned int mask) 169 - { 170 - rsci_serial_out(port, CFCLR, mask); 171 - } 172 140 173 141 static void rsci_start_rx(struct uart_port *port) 174 142 { ··· 175 151 rsci_serial_out(port, CCR0, ctrl); 176 152 } 177 153 154 + static void rsci_enable_ms(struct uart_port *port) 155 + { 156 + mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 157 + } 158 + 159 + static void rsci_init_pins(struct uart_port *port, unsigned int cflag) 160 + { 161 + struct sci_port *s = to_sci_port(port); 162 + 163 + /* Use port-specific handler if provided */ 164 + if (s->cfg->ops && s->cfg->ops->init_pins) { 165 + s->cfg->ops->init_pins(port, cflag); 166 + return; 167 + } 168 + 169 + if (!s->has_rtscts) 170 + return; 171 + 172 + if (s->autorts) 173 + rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | 174 + CCR1_CTSE | CCR1_CTSPEN); 175 + } 176 + 177 + static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig) 178 + { 179 + u32 fcr = rsci_serial_in(port, FCR); 180 + 181 + if (rx_trig >= port->fifosize) 182 + rx_trig = port->fifosize - 1; 183 + else if (rx_trig < 1) 184 + rx_trig = 0; 185 + 186 + FIELD_MODIFY(FCR_RTRG4_0, &fcr, rx_trig); 187 + rsci_serial_out(port, FCR, fcr); 188 + 189 + return rx_trig; 190 + } 191 + 178 192 static void rsci_set_termios(struct uart_port *port, struct ktermios *termios, 179 193 const struct ktermios *old) 180 194 { 195 + unsigned int ccr2_val = CCR2_INIT, ccr3_val = CCR3_INIT; 196 + unsigned int ccr0_val = 0, ccr1_val = 0, ccr4_val = 0; 197 + unsigned int brr1 = 255, cks1 = 0, srr1 = 15; 181 198 struct sci_port *s = to_sci_port(port); 199 + unsigned int brr = 255, cks = 0; 200 + int min_err = INT_MAX, err; 201 + unsigned long max_freq = 0; 202 + unsigned int baud, i; 182 203 unsigned long flags; 204 + unsigned int ctrl; 205 + int best_clk = -1; 206 + 207 + if ((termios->c_cflag & CSIZE) == CS7) { 208 + ccr3_val |= CCR3_CHR0; 209 + } else { 210 + termios->c_cflag &= ~CSIZE; 211 + termios->c_cflag |= CS8; 212 + } 213 + 214 + if (termios->c_cflag & PARENB) 215 + ccr1_val |= CCR1_PE; 216 + 217 + if (termios->c_cflag & PARODD) 218 + ccr1_val |= (CCR1_PE | CCR1_PM); 219 + 220 + if (termios->c_cflag & CSTOPB) 221 + ccr3_val |= CCR3_STP; 222 + 223 + /* Enable noise filter function */ 224 + ccr1_val |= CCR1_NFEN; 225 + 226 + /* 227 + * earlyprintk comes here early on with port->uartclk set to zero. 228 + * the clock framework is not up and running at this point so here 229 + * we assume that 115200 is the maximum baud rate. please note that 230 + * the baud rate is not programmed during earlyprintk - it is assumed 231 + * that the previous boot loader has enabled required clocks and 232 + * setup the baud rate generator hardware for us already. 233 + */ 234 + if (!port->uartclk) { 235 + max_freq = 115200; 236 + } else { 237 + for (i = 0; i < SCI_NUM_CLKS; i++) 238 + max_freq = max(max_freq, s->clk_rates[i]); 239 + 240 + max_freq /= min_sr(s); 241 + } 242 + 243 + baud = uart_get_baud_rate(port, termios, old, 0, max_freq); 244 + if (!baud) 245 + goto done; 246 + 247 + /* Divided Functional Clock using standard Bit Rate Register */ 248 + err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 249 + if (abs(err) < abs(min_err)) { 250 + best_clk = SCI_FCK; 251 + ccr0_val = 0; 252 + min_err = err; 253 + brr = brr1; 254 + cks = cks1; 255 + } 256 + 257 + done: 258 + if (best_clk >= 0) 259 + dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 260 + s->clks[best_clk], baud, min_err); 183 261 184 262 sci_port_enable(s); 185 263 uart_port_lock_irqsave(port, &flags); 186 264 187 - /* For now, only RX enabling is supported */ 188 - if (termios->c_cflag & CREAD) 265 + uart_update_timeout(port, termios->c_cflag, baud); 266 + 267 + rsci_serial_out(port, CCR0, ccr0_val); 268 + 269 + ccr3_val |= CCR3_FM; 270 + rsci_serial_out(port, CCR3, ccr3_val); 271 + 272 + ccr2_val |= (cks << 20) | (brr << 8); 273 + rsci_serial_out(port, CCR2, ccr2_val); 274 + 275 + rsci_serial_out(port, CCR1, ccr1_val); 276 + rsci_serial_out(port, CCR4, ccr4_val); 277 + 278 + ctrl = rsci_serial_in(port, FCR); 279 + ctrl |= (FCR_RFRST | FCR_TFRST); 280 + rsci_serial_out(port, FCR, ctrl); 281 + 282 + if (s->rx_trigger > 1) 283 + rsci_scif_set_rtrg(port, s->rx_trigger); 284 + 285 + port->status &= ~UPSTAT_AUTOCTS; 286 + s->autorts = false; 287 + 288 + if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) { 289 + port->status |= UPSTAT_AUTOCTS; 290 + s->autorts = true; 291 + } 292 + 293 + rsci_init_pins(port, termios->c_cflag); 294 + rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG); 295 + rsci_serial_out(port, FFCLR, FFCLR_DRC); 296 + 297 + ccr0_val |= CCR0_RE; 298 + rsci_serial_out(port, CCR0, ccr0_val); 299 + 300 + if ((termios->c_cflag & CREAD) != 0) 189 301 rsci_start_rx(port); 190 302 191 303 uart_port_unlock_irqrestore(port, flags); 192 304 sci_port_disable(s); 305 + 306 + if (UART_ENABLE_MS(port, termios->c_cflag)) 307 + rsci_enable_ms(port); 193 308 } 194 309 195 310 static int rsci_txfill(struct uart_port *port) ··· 353 190 354 191 static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl) 355 192 { 356 - /* Not supported yet */ 193 + if (mctrl & TIOCM_LOOP) { 194 + /* Standard loopback mode */ 195 + rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP); 196 + } 357 197 } 358 198 359 199 static unsigned int rsci_get_mctrl(struct uart_port *port) 360 200 { 361 - /* Not supported yet */ 362 - return 0; 201 + struct sci_port *s = to_sci_port(port); 202 + struct mctrl_gpios *gpios = s->gpios; 203 + unsigned int mctrl = 0; 204 + 205 + mctrl_gpio_get(gpios, &mctrl); 206 + 207 + /* 208 + * CTS/RTS is handled in hardware when supported, while nothing 209 + * else is wired up. 210 + */ 211 + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) 212 + mctrl |= TIOCM_CTS; 213 + 214 + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 215 + mctrl |= TIOCM_DSR; 216 + 217 + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 218 + mctrl |= TIOCM_CAR; 219 + 220 + return mctrl; 363 221 } 364 222 365 223 static void rsci_clear_CFC(struct uart_port *port, unsigned int mask) ··· 510 326 continue; 511 327 } 512 328 513 - /* Store data and status. 329 + /* 330 + * Store data and status. 514 331 * Non FIFO mode is not supported 515 332 */ 516 333 if (rdat & RDR_FFER) { ··· 545 360 } 546 361 } 547 362 363 + static void rsci_break_ctl(struct uart_port *port, int break_state) 364 + { 365 + unsigned short ccr0_val, ccr1_val; 366 + unsigned long flags; 367 + 368 + uart_port_lock_irqsave(port, &flags); 369 + ccr1_val = rsci_serial_in(port, CCR1); 370 + ccr0_val = rsci_serial_in(port, CCR0); 371 + 372 + if (break_state == -1) { 373 + ccr1_val = (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT; 374 + ccr0_val &= ~CCR0_TE; 375 + } else { 376 + ccr1_val = (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO; 377 + ccr0_val |= CCR0_TE; 378 + } 379 + 380 + rsci_serial_out(port, CCR1, ccr1_val); 381 + rsci_serial_out(port, CCR0, ccr0_val); 382 + uart_port_unlock_irqrestore(port, flags); 383 + } 384 + 548 385 static void rsci_poll_put_char(struct uart_port *port, unsigned char c) 549 386 { 550 387 u32 status; ··· 582 375 } 583 376 rsci_serial_out(port, TDR, c); 584 377 done: 585 - rsci_clear_SCxSR(port, CFCLR_TDREC); 378 + rsci_clear_CFC(port, CFCLR_TDREC); 586 379 } 587 380 588 381 static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl) 589 382 { 590 383 struct sci_port *s = to_sci_port(port); 591 - u32 ctrl_temp = 592 - s->params->param_bits->rxtx_enable | CCR0_TIE | 593 - s->hscif_tot; 384 + u32 ctrl_temp = s->params->param_bits->rxtx_enable; 385 + 386 + if (s->type == RSCI_PORT_SCIF16) 387 + ctrl_temp |= CCR0_TIE | s->hscif_tot; 388 + 594 389 rsci_serial_out(port, CCR0, ctrl_temp); 390 + } 391 + 392 + static void rsci_finish_console_write(struct uart_port *port, u32 ctrl) 393 + { 394 + /* First set TE = 0 and then restore the CCR0 value */ 395 + rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE); 396 + rsci_serial_out(port, CCR0, ctrl); 595 397 } 596 398 597 399 static const char *rsci_type(struct uart_port *port) ··· 632 416 .poll_sent_bits = CSR_TDRE | CSR_TEND, 633 417 }; 634 418 635 - static const struct sci_port_params rsci_port_params = { 419 + static const struct sci_port_params rsci_rzg3e_port_params = { 420 + .fifosize = 32, 421 + .overrun_reg = CSR, 422 + .overrun_mask = CSR_ORER, 423 + .sampling_rate_mask = SCI_SR(32), 424 + .error_mask = RSCI_DEFAULT_ERROR_MASK, 425 + .error_clear = RSCI_ERROR_CLEAR, 426 + .param_bits = &rsci_port_param_bits, 427 + .common_regs = &rsci_common_regs, 428 + }; 429 + 430 + static const struct sci_port_params rsci_rzt2h_port_params = { 636 431 .fifosize = 16, 637 432 .overrun_reg = CSR, 638 433 .overrun_mask = CSR_ORER, ··· 661 434 .start_tx = rsci_start_tx, 662 435 .stop_tx = rsci_stop_tx, 663 436 .stop_rx = rsci_stop_rx, 437 + .enable_ms = rsci_enable_ms, 438 + .break_ctl = rsci_break_ctl, 664 439 .startup = sci_startup, 665 440 .shutdown = sci_shutdown, 666 441 .set_termios = rsci_set_termios, ··· 677 448 static const struct sci_port_ops rsci_port_ops = { 678 449 .read_reg = rsci_serial_in, 679 450 .write_reg = rsci_serial_out, 680 - .clear_SCxSR = rsci_clear_SCxSR, 451 + .clear_SCxSR = rsci_clear_CFC, 681 452 .transmit_chars = rsci_transmit_chars, 682 453 .receive_chars = rsci_receive_chars, 683 454 .poll_put_char = rsci_poll_put_char, 684 455 .prepare_console_write = rsci_prepare_console_write, 456 + .finish_console_write = rsci_finish_console_write, 685 457 .suspend_regs_size = rsci_suspend_regs_size, 458 + .set_rtrg = rsci_scif_set_rtrg, 686 459 .shutdown_complete = rsci_shutdown_complete, 687 460 }; 688 461 689 - struct sci_of_data of_sci_rsci_data = { 690 - .type = SCI_PORT_RSCI, 462 + struct sci_of_data of_rsci_rzg3e_data = { 463 + .type = RSCI_PORT_SCIF32, 691 464 .ops = &rsci_port_ops, 692 465 .uart_ops = &rsci_uart_ops, 693 - .params = &rsci_port_params, 466 + .params = &rsci_rzg3e_port_params, 467 + }; 468 + 469 + struct sci_of_data of_rsci_rzt2h_data = { 470 + .type = RSCI_PORT_SCIF16, 471 + .ops = &rsci_port_ops, 472 + .uart_ops = &rsci_uart_ops, 473 + .params = &rsci_rzt2h_port_params, 694 474 }; 695 475 696 476 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 697 477 698 - static int __init rsci_early_console_setup(struct earlycon_device *device, 699 - const char *opt) 478 + static int __init rsci_rzg3e_early_console_setup(struct earlycon_device *device, 479 + const char *opt) 700 480 { 701 - return scix_early_console_setup(device, &of_sci_rsci_data); 481 + return scix_early_console_setup(device, &of_rsci_rzg3e_data); 702 482 } 703 483 704 - OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_setup); 484 + static int __init rsci_rzt2h_early_console_setup(struct earlycon_device *device, 485 + const char *opt) 486 + { 487 + return scix_early_console_setup(device, &of_rsci_rzt2h_data); 488 + } 489 + 490 + OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_early_console_setup); 491 + OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_console_setup); 705 492 706 493 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 707 494

+2 -1

drivers/tty/serial/rsci.h

··· 5 5 6 6 #include "sh-sci-common.h" 7 7 8 - extern struct sci_of_data of_sci_rsci_data; 8 + extern struct sci_of_data of_rsci_rzg3e_data; 9 + extern struct sci_of_data of_rsci_rzt2h_data; 9 10 10 11 #endif /* __RSCI_H__ */

+9 -1

drivers/tty/serial/sh-sci-common.h

··· 7 7 8 8 /* Private port IDs */ 9 9 enum SCI_PORT_TYPE { 10 - SCI_PORT_RSCI = BIT(7) | 0, 10 + RSCI_PORT_SCIF16 = BIT(7) | 0, 11 + RSCI_PORT_SCIF32 = BIT(7) | 1, 11 12 }; 12 13 13 14 enum SCI_CLKS { ··· 16 15 SCI_SCK, /* Optional External Clock */ 17 16 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 18 17 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 18 + SCI_FCK_DIV4, /* Optional Functional Clock frequency-divided by 4 */ 19 + SCI_FCK_DIV16, /* Optional Functional Clock frequency-divided by 16 */ 20 + SCI_FCK_DIV64, /* Optional Functional Clock frequency-divided by 64 */ 19 21 SCI_NUM_CLKS 20 22 }; 21 23 ··· 93 89 void (*shutdown_complete)(struct uart_port *port); 94 90 95 91 void (*prepare_console_write)(struct uart_port *port, u32 ctrl); 92 + void (*finish_console_write)(struct uart_port *port, u32 ctrl); 96 93 void (*console_save)(struct uart_port *port); 97 94 void (*console_restore)(struct uart_port *port); 98 95 size_t (*suspend_regs_size)(void); ··· 169 164 170 165 int sci_startup(struct uart_port *port); 171 166 void sci_shutdown(struct uart_port *port); 167 + 168 + int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr, 169 + unsigned int *srr, unsigned int *cks); 172 170 173 171 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 174 172 #define max_sr(_port) fls((_port)->sampling_rate_mask)

+45 -35

drivers/tty/serial/sh-sci.c

··· 1182 1182 return copied; 1183 1183 } 1184 1184 1185 + static bool sci_is_rsci_type(u8 type) 1186 + { 1187 + return (type == RSCI_PORT_SCIF16 || type == RSCI_PORT_SCIF32); 1188 + } 1189 + 1185 1190 static int sci_handle_fifo_overrun(struct uart_port *port) 1186 1191 { 1187 1192 struct tty_port *tport = &port->state->port; ··· 1195 1190 int copied = 0; 1196 1191 u32 status; 1197 1192 1198 - if (s->type != SCI_PORT_RSCI) { 1193 + if (!sci_is_rsci_type(s->type)) { 1199 1194 reg = sci_getreg(port, s->params->overrun_reg); 1200 1195 if (!reg->size) 1201 1196 return 0; ··· 1203 1198 1204 1199 status = s->ops->read_reg(port, s->params->overrun_reg); 1205 1200 if (status & s->params->overrun_mask) { 1206 - if (s->type == SCI_PORT_RSCI) { 1201 + if (sci_is_rsci_type(s->type)) { 1207 1202 /* 1208 1203 * All of the CFCLR_*C clearing bits match the corresponding 1209 1204 * CSR_*status bits. So, reuse the overrun mask for clearing. ··· 2020 2015 unsigned long flags; 2021 2016 u32 ctrl; 2022 2017 2023 - if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI) 2018 + if (s->type != PORT_SCI && !sci_is_rsci_type(s->type)) 2024 2019 return sci_tx_interrupt(irq, ptr); 2025 2020 2026 2021 uart_port_lock_irqsave(port, &flags); ··· 2573 2568 } 2574 2569 2575 2570 /* calculate sample rate, BRR, and clock select */ 2576 - static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2577 - unsigned int *brr, unsigned int *srr, 2578 - unsigned int *cks) 2571 + int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr, 2572 + unsigned int *srr, unsigned int *cks) 2579 2573 { 2580 2574 unsigned long freq = s->clk_rates[SCI_FCK]; 2581 2575 unsigned int sr, br, prediv, scrate, c; ··· 2638 2634 min_err, *brr, *srr + 1, *cks); 2639 2635 return min_err; 2640 2636 } 2637 + EXPORT_SYMBOL_NS_GPL(sci_scbrr_calc, "SH_SCI"); 2641 2638 2642 2639 static void sci_reset(struct uart_port *port) 2643 2640 { ··· 3172 3167 [SCI_SCK] = "sck", 3173 3168 [SCI_BRG_INT] = "brg_int", 3174 3169 [SCI_SCIF_CLK] = "scif_clk", 3170 + [SCI_FCK_DIV4] = "tclk_div4", 3171 + [SCI_FCK_DIV16] = "tclk_div16", 3172 + [SCI_FCK_DIV64] = "tclk_div64", 3175 3173 }; 3176 3174 struct clk *clk; 3177 3175 unsigned int i; 3178 3176 3179 3177 if (sci_port->type == PORT_HSCIF) { 3180 3178 clk_names[SCI_SCK] = "hsck"; 3181 - } else if (sci_port->type == SCI_PORT_RSCI) { 3179 + } else if (sci_port->type == RSCI_PORT_SCIF16) { 3182 3180 clk_names[SCI_FCK] = "operation"; 3183 3181 clk_names[SCI_BRG_INT] = "bus"; 3182 + } else if (sci_port->type == RSCI_PORT_SCIF32) { 3183 + clk_names[SCI_FCK] = "tclk"; 3184 + clk_names[SCI_BRG_INT] = "pclk"; 3184 3185 } 3185 3186 3186 3187 for (i = 0; i < SCI_NUM_CLKS; i++) { ··· 3196 3185 if (IS_ERR(clk)) 3197 3186 return PTR_ERR(clk); 3198 3187 3199 - if (!clk && sci_port->type == SCI_PORT_RSCI && 3200 - (i == SCI_FCK || i == SCI_BRG_INT)) { 3201 - return dev_err_probe(dev, -ENODEV, 3202 - "failed to get %s\n", 3203 - name); 3204 - } 3188 + if (!clk && sci_port->type == RSCI_PORT_SCIF16 && 3189 + (i == SCI_FCK || i == SCI_BRG_INT)) 3190 + return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name); 3191 + 3192 + if (!clk && sci_port->type == RSCI_PORT_SCIF32 && 3193 + (i != SCI_SCK && i != SCI_SCIF_CLK)) 3194 + return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name); 3205 3195 3206 3196 if (!clk && i == SCI_FCK) { 3207 3197 /* ··· 3212 3200 */ 3213 3201 clk = devm_clk_get(dev, "peripheral_clk"); 3214 3202 if (IS_ERR(clk)) 3215 - return dev_err_probe(dev, PTR_ERR(clk), 3216 - "failed to get %s\n", 3217 - name); 3203 + return dev_err_probe(dev, PTR_ERR(clk), "failed to get %s\n", name); 3218 3204 } 3219 3205 3220 3206 if (!clk) 3221 3207 dev_dbg(dev, "failed to get %s\n", name); 3222 3208 else 3223 - dev_dbg(dev, "clk %s is %pC rate %lu\n", name, 3224 - clk, clk_get_rate(clk)); 3209 + dev_dbg(dev, "clk %s is %pC rate %lu\n", name, clk, clk_get_rate(clk)); 3225 3210 sci_port->clks[i] = clk; 3226 3211 } 3227 3212 return 0; ··· 3304 3295 * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so 3305 3296 * shuffle the interrupts. 3306 3297 */ 3307 - if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI) 3298 + if (p->type == PORT_SCI || sci_is_rsci_type(p->type)) 3308 3299 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 3309 3300 3310 3301 /* The SCI generates several interrupts. They can be muxed together or ··· 3329 3320 sci_port->rx_trigger = 64; 3330 3321 break; 3331 3322 case PORT_SCIFA: 3323 + case RSCI_PORT_SCIF32: 3332 3324 sci_port->rx_trigger = 32; 3333 3325 break; 3334 3326 case PORT_SCIF: ··· 3339 3329 else 3340 3330 sci_port->rx_trigger = 8; 3341 3331 break; 3342 - case SCI_PORT_RSCI: 3343 - sci_port->rx_trigger = 15; 3332 + case RSCI_PORT_SCIF16: 3333 + sci_port->rx_trigger = 16; 3344 3334 break; 3345 3335 default: 3346 3336 sci_port->rx_trigger = 1; ··· 3432 3422 cpu_relax(); 3433 3423 3434 3424 /* restore the SCSCR */ 3435 - sci_port->ops->write_reg(port, regs->control, ctrl); 3425 + if (sci_port->ops->finish_console_write) 3426 + sci_port->ops->finish_console_write(port, ctrl); 3427 + else 3428 + sci_port->ops->write_reg(port, regs->control, ctrl); 3436 3429 3437 3430 if (locked) 3438 3431 uart_port_unlock_irqrestore(port, flags); ··· 3562 3549 static void sci_remove(struct platform_device *dev) 3563 3550 { 3564 3551 struct sci_port *s = platform_get_drvdata(dev); 3565 - unsigned int type = s->type; /* uart_remove_... clears it */ 3566 3552 3567 3553 sci_ports_in_use &= ~BIT(s->port.line); 3568 3554 uart_remove_one_port(&sci_uart_driver, &s->port); 3569 3555 3570 - if (s->port.fifosize > 1) 3556 + if (s->port.fifosize > 1) { 3571 3557 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3572 - if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF || 3573 - type == SCI_PORT_RSCI) 3574 3558 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3559 + } 3575 3560 } 3576 3561 3577 3562 static const struct sci_of_data of_sci_scif_sh2 = { ··· 3664 3653 }, 3665 3654 #ifdef CONFIG_SERIAL_RSCI 3666 3655 { 3656 + .compatible = "renesas,r9a09g047-rsci", 3657 + .data = &of_rsci_rzg3e_data, 3658 + }, 3659 + { 3667 3660 .compatible = "renesas,r9a09g077-rsci", 3668 - .data = &of_sci_rsci_data, 3661 + .data = &of_rsci_rzt2h_data, 3669 3662 }, 3670 3663 #endif /* CONFIG_SERIAL_RSCI */ 3671 3664 /* Family-specific types */ ··· 3731 3716 3732 3717 data = of_device_get_match_data(&pdev->dev); 3733 3718 3734 - rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3719 + rstc = devm_reset_control_array_get_optional_exclusive(&pdev->dev); 3735 3720 if (IS_ERR(rstc)) 3736 3721 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3737 3722 "failed to get reset ctrl\n")); ··· 3932 3917 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3933 3918 if (ret) 3934 3919 return ret; 3935 - } 3936 - if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB || 3937 - sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) { 3920 + 3938 3921 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3939 3922 if (ret) { 3940 - if (sp->port.fifosize > 1) { 3941 - device_remove_file(&dev->dev, 3942 - &dev_attr_rx_fifo_trigger); 3943 - } 3923 + device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3944 3924 return ret; 3945 3925 } 3946 3926 }

+121 -112

drivers/tty/vt/keyboard.c

··· 1649 1649 1650 1650 /* Ioctl support code */ 1651 1651 1652 + static int vt_do_kdgkbdiacr(void __user *udp) 1653 + { 1654 + struct kbdiacrs __user *a = udp; 1655 + int i, asize; 1656 + 1657 + struct kbdiacr __free(kfree) *dia = kmalloc_array(MAX_DIACR, sizeof(struct kbdiacr), 1658 + GFP_KERNEL); 1659 + if (!dia) 1660 + return -ENOMEM; 1661 + 1662 + /* Lock the diacriticals table, make a copy and then 1663 + copy it after we unlock */ 1664 + scoped_guard(spinlock_irqsave, &kbd_event_lock) { 1665 + asize = accent_table_size; 1666 + for (i = 0; i < asize; i++) { 1667 + dia[i].diacr = conv_uni_to_8bit(accent_table[i].diacr); 1668 + dia[i].base = conv_uni_to_8bit(accent_table[i].base); 1669 + dia[i].result = conv_uni_to_8bit(accent_table[i].result); 1670 + } 1671 + } 1672 + 1673 + if (put_user(asize, &a->kb_cnt)) 1674 + return -EFAULT; 1675 + if (copy_to_user(a->kbdiacr, dia, asize * sizeof(struct kbdiacr))) 1676 + return -EFAULT; 1677 + return 0; 1678 + } 1679 + 1680 + static int vt_do_kdgkbdiacruc(void __user *udp) 1681 + { 1682 + struct kbdiacrsuc __user *a = udp; 1683 + int asize; 1684 + 1685 + void __free(kfree) *buf = kmalloc_array(MAX_DIACR, sizeof(struct kbdiacruc), 1686 + GFP_KERNEL); 1687 + if (buf == NULL) 1688 + return -ENOMEM; 1689 + 1690 + /* Lock the diacriticals table, make a copy and then 1691 + copy it after we unlock */ 1692 + scoped_guard(spinlock_irqsave, &kbd_event_lock) { 1693 + asize = accent_table_size; 1694 + memcpy(buf, accent_table, asize * sizeof(struct kbdiacruc)); 1695 + } 1696 + 1697 + if (put_user(asize, &a->kb_cnt)) 1698 + return -EFAULT; 1699 + if (copy_to_user(a->kbdiacruc, buf, asize * sizeof(struct kbdiacruc))) 1700 + return -EFAULT; 1701 + 1702 + return 0; 1703 + } 1704 + 1705 + static int vt_do_kdskbdiacr(void __user *udp, int perm) 1706 + { 1707 + struct kbdiacrs __user *a = udp; 1708 + struct kbdiacr __free(kfree) *dia = NULL; 1709 + unsigned int ct; 1710 + int i; 1711 + 1712 + if (!perm) 1713 + return -EPERM; 1714 + if (get_user(ct, &a->kb_cnt)) 1715 + return -EFAULT; 1716 + if (ct >= MAX_DIACR) 1717 + return -EINVAL; 1718 + 1719 + if (ct) { 1720 + dia = memdup_array_user(a->kbdiacr, 1721 + ct, sizeof(struct kbdiacr)); 1722 + if (IS_ERR(dia)) 1723 + return PTR_ERR(dia); 1724 + } 1725 + 1726 + guard(spinlock_irqsave)(&kbd_event_lock); 1727 + accent_table_size = ct; 1728 + for (i = 0; i < ct; i++) { 1729 + accent_table[i].diacr = 1730 + conv_8bit_to_uni(dia[i].diacr); 1731 + accent_table[i].base = 1732 + conv_8bit_to_uni(dia[i].base); 1733 + accent_table[i].result = 1734 + conv_8bit_to_uni(dia[i].result); 1735 + } 1736 + 1737 + return 0; 1738 + } 1739 + 1740 + static int vt_do_kdskbdiacruc(void __user *udp, int perm) 1741 + { 1742 + struct kbdiacrsuc __user *a = udp; 1743 + unsigned int ct; 1744 + void __free(kfree) *buf = NULL; 1745 + 1746 + if (!perm) 1747 + return -EPERM; 1748 + 1749 + if (get_user(ct, &a->kb_cnt)) 1750 + return -EFAULT; 1751 + 1752 + if (ct >= MAX_DIACR) 1753 + return -EINVAL; 1754 + 1755 + if (ct) { 1756 + buf = memdup_array_user(a->kbdiacruc, 1757 + ct, sizeof(struct kbdiacruc)); 1758 + if (IS_ERR(buf)) 1759 + return PTR_ERR(buf); 1760 + } 1761 + guard(spinlock_irqsave)(&kbd_event_lock); 1762 + if (ct) 1763 + memcpy(accent_table, buf, 1764 + ct * sizeof(struct kbdiacruc)); 1765 + accent_table_size = ct; 1766 + return 0; 1767 + } 1768 + 1652 1769 /** 1653 1770 * vt_do_diacrit - diacritical table updates 1654 1771 * @cmd: ioctl request ··· 1777 1660 */ 1778 1661 int vt_do_diacrit(unsigned int cmd, void __user *udp, int perm) 1779 1662 { 1780 - int asize; 1781 - 1782 1663 switch (cmd) { 1783 1664 case KDGKBDIACR: 1784 - { 1785 - struct kbdiacrs __user *a = udp; 1786 - int i; 1787 - 1788 - struct kbdiacr __free(kfree) *dia = kmalloc_array(MAX_DIACR, sizeof(struct kbdiacr), 1789 - GFP_KERNEL); 1790 - if (!dia) 1791 - return -ENOMEM; 1792 - 1793 - /* Lock the diacriticals table, make a copy and then 1794 - copy it after we unlock */ 1795 - scoped_guard(spinlock_irqsave, &kbd_event_lock) { 1796 - asize = accent_table_size; 1797 - for (i = 0; i < asize; i++) { 1798 - dia[i].diacr = conv_uni_to_8bit(accent_table[i].diacr); 1799 - dia[i].base = conv_uni_to_8bit(accent_table[i].base); 1800 - dia[i].result = conv_uni_to_8bit(accent_table[i].result); 1801 - } 1802 - } 1803 - 1804 - if (put_user(asize, &a->kb_cnt)) 1805 - return -EFAULT; 1806 - if (copy_to_user(a->kbdiacr, dia, asize * sizeof(struct kbdiacr))) 1807 - return -EFAULT; 1808 - return 0; 1809 - } 1665 + return vt_do_kdgkbdiacr(udp); 1810 1666 case KDGKBDIACRUC: 1811 - { 1812 - struct kbdiacrsuc __user *a = udp; 1813 - 1814 - void __free(kfree) *buf = kmalloc_array(MAX_DIACR, sizeof(struct kbdiacruc), 1815 - GFP_KERNEL); 1816 - if (buf == NULL) 1817 - return -ENOMEM; 1818 - 1819 - /* Lock the diacriticals table, make a copy and then 1820 - copy it after we unlock */ 1821 - scoped_guard(spinlock_irqsave, &kbd_event_lock) { 1822 - asize = accent_table_size; 1823 - memcpy(buf, accent_table, asize * sizeof(struct kbdiacruc)); 1824 - } 1825 - 1826 - if (put_user(asize, &a->kb_cnt)) 1827 - return -EFAULT; 1828 - if (copy_to_user(a->kbdiacruc, buf, asize * sizeof(struct kbdiacruc))) 1829 - return -EFAULT; 1830 - 1831 - return 0; 1832 - } 1833 - 1667 + return vt_do_kdgkbdiacruc(udp); 1834 1668 case KDSKBDIACR: 1835 - { 1836 - struct kbdiacrs __user *a = udp; 1837 - struct kbdiacr __free(kfree) *dia = NULL; 1838 - unsigned int ct; 1839 - int i; 1840 - 1841 - if (!perm) 1842 - return -EPERM; 1843 - if (get_user(ct, &a->kb_cnt)) 1844 - return -EFAULT; 1845 - if (ct >= MAX_DIACR) 1846 - return -EINVAL; 1847 - 1848 - if (ct) { 1849 - dia = memdup_array_user(a->kbdiacr, 1850 - ct, sizeof(struct kbdiacr)); 1851 - if (IS_ERR(dia)) 1852 - return PTR_ERR(dia); 1853 - } 1854 - 1855 - guard(spinlock_irqsave)(&kbd_event_lock); 1856 - accent_table_size = ct; 1857 - for (i = 0; i < ct; i++) { 1858 - accent_table[i].diacr = 1859 - conv_8bit_to_uni(dia[i].diacr); 1860 - accent_table[i].base = 1861 - conv_8bit_to_uni(dia[i].base); 1862 - accent_table[i].result = 1863 - conv_8bit_to_uni(dia[i].result); 1864 - } 1865 - 1866 - return 0; 1867 - } 1868 - 1669 + return vt_do_kdskbdiacr(udp, perm); 1869 1670 case KDSKBDIACRUC: 1870 - { 1871 - struct kbdiacrsuc __user *a = udp; 1872 - unsigned int ct; 1873 - void __free(kfree) *buf = NULL; 1874 - 1875 - if (!perm) 1876 - return -EPERM; 1877 - 1878 - if (get_user(ct, &a->kb_cnt)) 1879 - return -EFAULT; 1880 - 1881 - if (ct >= MAX_DIACR) 1882 - return -EINVAL; 1883 - 1884 - if (ct) { 1885 - buf = memdup_array_user(a->kbdiacruc, 1886 - ct, sizeof(struct kbdiacruc)); 1887 - if (IS_ERR(buf)) 1888 - return PTR_ERR(buf); 1889 - } 1890 - guard(spinlock_irqsave)(&kbd_event_lock); 1891 - if (ct) 1892 - memcpy(accent_table, buf, 1893 - ct * sizeof(struct kbdiacruc)); 1894 - accent_table_size = ct; 1895 - return 0; 1896 - } 1671 + return vt_do_kdskbdiacruc(udp, perm); 1897 1672 } 1898 1673 return 0; 1899 1674 }

+1

include/linux/serdev.h

··· 65 65 struct device_driver driver; 66 66 int (*probe)(struct serdev_device *); 67 67 void (*remove)(struct serdev_device *); 68 + void (*shutdown)(struct serdev_device *); 68 69 }; 69 70 70 71 static inline struct serdev_device_driver *to_serdev_device_driver(struct device_driver *d)

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