Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull more clk updates from Stephen Boyd:
"This is the second batch of clk driver updates that needed a little
more time to soak in linux-next.
- Use modern i2c probe in vc5
- Cleanup some includes
- Update links to datasheets
- Add UniPhier NX1 SoC clk support
- Fix DT bindings for SiFive FU740
- Revert the module platform driver support for Rockchip because it
wasn't actually tested
- Fix the composite clk code again as the previous fix had a one line
bug that broke rate changes for clks that want to use the same
parent still
- Use the right table for a divider in ast2600 driver
- Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because
its critical but unused"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clk
clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites
clk/ast2600: Fix soc revision for AHB
clk: composite: Fix 'switching' to same clock
clk: rockchip: drop module parts from rk3399 and rk3568 drivers
Revert "clk: rockchip: use module_platform_driver_probe"
clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.c
dt-bindings: clock: fu740-prci: add reset-cells
clk: uniphier: Add SoC-glue clock source selector support for Pro4
dt-bindings: clock: uniphier: Add clock binding for SoC-glue
clk: uniphier: Add NX1 clock support
dt-bindings: clock: uniphier: Add NX1 clock binding
clk: uniphier: Add audio system and video input clock control for PXs3
clk: si5351: Update datasheet references
clk: vc5: Use i2c .probe_new
clk/actions/owl-factor.c: remove superfluous headers
clk: ingenic: Fix bugs with divided dividers
+105
-48
+4
Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml
+4
Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml
+1
-1
Documentation/devicetree/bindings/clock/silabs,si5351.txt
+1
-1
Documentation/devicetree/bindings/clock/silabs,si5351.txt
···
2
2
3
3
Reference
4
4
[1] Si5351A/B/C Data Sheet
5
-
https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
5
+
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
6
6
7
7
The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8
8
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
+6
Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml
+6
Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml
···
23
23
- socionext,uniphier-ld11-clock
24
24
- socionext,uniphier-ld20-clock
25
25
- socionext,uniphier-pxs3-clock
26
+
- socionext,uniphier-nx1-clock
26
27
- description: Media I/O (MIO) clock, SD clock
27
28
enum:
28
29
- socionext,uniphier-ld4-mio-clock
···
34
33
- socionext,uniphier-ld11-mio-clock
35
34
- socionext,uniphier-ld20-sd-clock
36
35
- socionext,uniphier-pxs3-sd-clock
36
+
- socionext,uniphier-nx1-sd-clock
37
37
- description: Peripheral clock
38
38
enum:
39
39
- socionext,uniphier-ld4-peri-clock
···
45
43
- socionext,uniphier-ld11-peri-clock
46
44
- socionext,uniphier-ld20-peri-clock
47
45
- socionext,uniphier-pxs3-peri-clock
46
+
- socionext,uniphier-nx1-peri-clock
47
+
- description: SoC-glue clock
48
+
enum:
49
+
- socionext,uniphier-pro4-sg-clock
48
50
49
51
"#clock-cells":
50
52
const: 1
-1
drivers/clk/actions/owl-factor.c
-1
drivers/clk/actions/owl-factor.c
+7
-5
drivers/clk/clk-ast2600.c
+7
-5
drivers/clk/clk-ast2600.c
···
51
51
static struct clk_hw_onecell_data *aspeed_g6_clk_data;
52
52
53
53
static void __iomem *scu_g6_base;
54
+
/* AST2600 revision: A0, A1, A2, etc */
55
+
static u8 soc_rev;
54
56
55
57
/*
56
58
* Clocks marked with CLK_IS_CRITICAL:
···
193
191
static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
194
192
{
195
193
unsigned int mult, div;
196
-
u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV);
197
194
198
-
if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) {
195
+
if (soc_rev >= 2) {
199
196
if (val & BIT(24)) {
200
197
/* Pass through mode */
201
198
mult = div = 1;
···
708
707
static void __init aspeed_g6_cc(struct regmap *map)
709
708
{
710
709
struct clk_hw *hw;
711
-
u32 val, div, divbits, chip_id, axi_div, ahb_div;
710
+
u32 val, div, divbits, axi_div, ahb_div;
712
711
713
712
clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
714
713
···
739
738
axi_div = 2;
740
739
741
740
divbits = (val >> 11) & 0x3;
742
-
regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
743
-
if (chip_id & BIT(16)) {
741
+
if (soc_rev >= 1) {
744
742
if (!divbits) {
745
743
ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
746
744
if (val & BIT(16))
···
783
783
scu_g6_base = of_iomap(np, 0);
784
784
if (!scu_g6_base)
785
785
return;
786
+
787
+
soc_rev = (readl(scu_g6_base + ASPEED_G6_SILICON_REV) & CHIP_REVISION_ID) >> 16;
786
788
787
789
aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
788
790
ASPEED_G6_NUM_CLKS), GFP_KERNEL);
+1
drivers/clk/clk-composite.c
+1
drivers/clk/clk-composite.c
+4
-4
drivers/clk/clk-si5351.c
+4
-4
drivers/clk/clk-si5351.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-or-later
2
2
/*
3
-
* clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator
3
+
* clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
4
4
*
5
5
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6
6
* Rabeeh Khoury <rabeeh@solid-run.com>
7
7
*
8
8
* References:
9
9
* [1] "Si5351A/B/C Data Sheet"
10
-
* https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
11
-
* [2] "Manually Generating an Si5351 Register Map"
12
-
* https://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
10
+
* https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
11
+
* [2] "AN619: Manually Generating an Si5351 Register Map"
12
+
* https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
13
13
*/
14
14
15
15
#include <linux/module.h>
+1
-1
drivers/clk/clk-si5351.h
+1
-1
drivers/clk/clk-si5351.h
···
1
1
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
2
/*
3
-
* clk-si5351.h: Silicon Laboratories Si5351A/B/C I2C Clock Generator
3
+
* clk-si5351.h: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
4
4
*
5
5
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6
6
* Rabeeh Khoury <rabeeh@solid-run.com>
+2
-2
drivers/clk/clk-versaclock5.c
+2
-2
drivers/clk/clk-versaclock5.c
···
905
905
906
906
static const struct of_device_id clk_vc5_of_match[];
907
907
908
-
static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)
908
+
static int vc5_probe(struct i2c_client *client)
909
909
{
910
910
unsigned int oe, sd, src_mask = 0, src_val = 0;
911
911
struct vc5_driver_data *vc5;
···
1244
1244
.pm = &vc5_pm_ops,
1245
1245
.of_match_table = clk_vc5_of_match,
1246
1246
},
1247
-
.probe = vc5_probe,
1247
+
.probe_new = vc5_probe,
1248
1248
.remove = vc5_remove,
1249
1249
.id_table = vc5_id,
1250
1250
};
+2
-2
drivers/clk/imx/clk.h
+2
-2
drivers/clk/imx/clk.h
···
391
391
392
392
#define imx8m_clk_hw_composite(name, parent_names, reg) \
393
393
_imx8m_clk_hw_composite(name, parent_names, reg, \
394
-
IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
394
+
0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
395
395
396
396
#define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
397
397
_imx8m_clk_hw_composite(name, parent_names, reg, \
398
-
IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
398
+
0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
399
399
400
400
#define imx8m_clk_hw_composite_bus(name, parent_names, reg) \
401
401
_imx8m_clk_hw_composite(name, parent_names, reg, \
+3
-3
drivers/clk/ingenic/cgu.c
+3
-3
drivers/clk/ingenic/cgu.c
···
453
453
}
454
454
455
455
/* Impose hardware constraints */
456
-
div = min_t(unsigned, div, 1 << clk_info->div.bits);
457
-
div = max_t(unsigned, div, 1);
456
+
div = clamp_t(unsigned int, div, clk_info->div.div,
457
+
clk_info->div.div << clk_info->div.bits);
458
458
459
459
/*
460
460
* If the divider value itself must be divided before being written to
461
461
* the divider register, we must ensure we don't have any bits set that
462
462
* would be lost as a result of doing so.
463
463
*/
464
-
div /= clk_info->div.div;
464
+
div = DIV_ROUND_UP(div, clk_info->div.div);
465
465
div *= clk_info->div.div;
466
466
467
467
return div;
-2
drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
-2
drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
-15
drivers/clk/qcom/gcc-msm8996.c
-15
drivers/clk/qcom/gcc-msm8996.c
···
2937
2937
},
2938
2938
};
2939
2939
2940
-
static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
2941
-
.halt_reg = 0x82014,
2942
-
.clkr = {
2943
-
.enable_reg = 0x82014,
2944
-
.enable_mask = BIT(0),
2945
-
.hw.init = &(struct clk_init_data){
2946
-
.name = "gcc_aggre1_pnoc_ahb_clk",
2947
-
.parent_names = (const char *[]){ "periph_noc_clk_src" },
2948
-
.num_parents = 1,
2949
-
.ops = &clk_branch2_ops,
2950
-
},
2951
-
},
2952
-
};
2953
-
2954
2940
static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2955
2941
.halt_reg = 0x83014,
2956
2942
.clkr = {
···
3460
3474
[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3461
3475
[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3462
3476
[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3463
-
[GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
3464
3477
[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3465
3478
[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3466
3479
[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
+2
-2
drivers/clk/rockchip/Kconfig
+2
-2
drivers/clk/rockchip/Kconfig
···
80
80
Build the driver for RK3368 Clock Driver.
81
81
82
82
config CLK_RK3399
83
-
tristate "Rockchip RK3399 clock controller support"
83
+
bool "Rockchip RK3399 clock controller support"
84
84
depends on ARM64 || COMPILE_TEST
85
85
default y
86
86
help
87
87
Build the driver for RK3399 Clock Driver.
88
88
89
89
config CLK_RK3568
90
-
tristate "Rockchip RK3568 clock controller support"
90
+
bool "Rockchip RK3568 clock controller support"
91
91
depends on ARM64 || COMPILE_TEST
92
92
default y
93
93
help
+1
-5
drivers/clk/rockchip/clk-rk3399.c
+1
-5
drivers/clk/rockchip/clk-rk3399.c
···
1630
1630
},
1631
1631
{ }
1632
1632
};
1633
-
MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
1634
1633
1635
1634
static int __init clk_rk3399_probe(struct platform_device *pdev)
1636
1635
{
···
1655
1656
.suppress_bind_attrs = true,
1656
1657
},
1657
1658
};
1658
-
module_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
1659
-
1660
-
MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
1661
-
MODULE_LICENSE("GPL");
1659
+
builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
+1
-5
drivers/clk/rockchip/clk-rk3568.c
+1
-5
drivers/clk/rockchip/clk-rk3568.c
···
1693
1693
},
1694
1694
{ }
1695
1695
};
1696
-
MODULE_DEVICE_TABLE(of, clk_rk3568_match_table);
1697
1696
1698
1697
static int __init clk_rk3568_probe(struct platform_device *pdev)
1699
1698
{
···
1718
1719
.suppress_bind_attrs = true,
1719
1720
},
1720
1721
};
1721
-
module_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
1722
-
1723
-
MODULE_DESCRIPTION("Rockchip RK3568 Clock Driver");
1724
-
MODULE_LICENSE("GPL");
1722
+
builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
+17
drivers/clk/uniphier/clk-uniphier-core.c
+17
drivers/clk/uniphier/clk-uniphier-core.c
···
132
132
.compatible = "socionext,uniphier-pxs3-clock",
133
133
.data = uniphier_pxs3_sys_clk_data,
134
134
},
135
+
{
136
+
.compatible = "socionext,uniphier-nx1-clock",
137
+
.data = uniphier_nx1_sys_clk_data,
138
+
},
135
139
/* Media I/O clock, SD clock */
136
140
{
137
141
.compatible = "socionext,uniphier-ld4-mio-clock",
···
167
163
},
168
164
{
169
165
.compatible = "socionext,uniphier-pxs3-sd-clock",
166
+
.data = uniphier_pro5_sd_clk_data,
167
+
},
168
+
{
169
+
.compatible = "socionext,uniphier-nx1-sd-clock",
170
170
.data = uniphier_pro5_sd_clk_data,
171
171
},
172
172
/* Peripheral clock */
···
205
197
{
206
198
.compatible = "socionext,uniphier-pxs3-peri-clock",
207
199
.data = uniphier_pro4_peri_clk_data,
200
+
},
201
+
{
202
+
.compatible = "socionext,uniphier-nx1-peri-clock",
203
+
.data = uniphier_pro4_peri_clk_data,
204
+
},
205
+
/* SoC-glue clock */
206
+
{
207
+
.compatible = "socionext,uniphier-pro4-sg-clock",
208
+
.data = uniphier_pro4_sg_clk_data,
208
209
},
209
210
{ /* sentinel */ }
210
211
};
+47
drivers/clk/uniphier/clk-uniphier-sys.c
+47
drivers/clk/uniphier/clk-uniphier-sys.c
···
20
20
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21
21
UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
22
22
23
+
#define UNIPHIER_NX1_SYS_CLK_SD \
24
+
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25
+
UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
26
+
23
27
#define UNIPHIER_LD4_SYS_CLK_NAND(idx) \
24
28
UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
25
29
UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
···
292
288
UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
293
289
UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
294
290
UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
291
+
UNIPHIER_LD11_SYS_CLK_AIO(40),
292
+
UNIPHIER_LD11_SYS_CLK_EXIV(42),
295
293
/* CPU gears */
296
294
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
297
295
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
···
304
298
UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
305
299
"s2pll/2", "spll/2", "s2pll/3", "spll/3",
306
300
"spll/4", "spll/8", "s2pll/4", "s2pll/8"),
301
+
{ /* sentinel */ }
302
+
};
303
+
304
+
const struct uniphier_clk_data uniphier_nx1_sys_clk_data[] = {
305
+
UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 100, 1), /* ARM: 2500 MHz */
306
+
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 32, 1), /* 800 MHz */
307
+
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 6),
308
+
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
309
+
UNIPHIER_NX1_SYS_CLK_SD,
310
+
UNIPHIER_CLK_GATE("emmc", 4, NULL, 0x2108, 8),
311
+
UNIPHIER_CLK_GATE("ether", 6, NULL, 0x210c, 0),
312
+
UNIPHIER_CLK_GATE("usb30-0", 12, NULL, 0x210c, 16), /* =GIO */
313
+
UNIPHIER_CLK_GATE("usb30-1", 13, NULL, 0x210c, 20), /* =GIO1P */
314
+
UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 24),
315
+
UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 25),
316
+
UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 26),
317
+
UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 8),
318
+
UNIPHIER_CLK_GATE("voc", 52, NULL, 0x2110, 0),
319
+
UNIPHIER_CLK_GATE("hdmitx", 58, NULL, 0x2110, 8),
320
+
/* CPU gears */
321
+
UNIPHIER_CLK_DIV5("cpll", 2, 4, 8, 16, 32),
322
+
UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 5,
323
+
"cpll/2", "cpll/4", "cpll/8", "cpll/16",
324
+
"cpll/32"),
325
+
{ /* sentinel */ }
326
+
};
327
+
328
+
const struct uniphier_clk_data uniphier_pro4_sg_clk_data[] = {
329
+
UNIPHIER_CLK_DIV("gpll", 4),
330
+
{
331
+
.name = "sata-ref",
332
+
.type = UNIPHIER_CLK_TYPE_MUX,
333
+
.idx = 0,
334
+
.data.mux = {
335
+
.parent_names = { "gpll/4", "ref", },
336
+
.num_parents = 2,
337
+
.reg = 0x1a28,
338
+
.masks = { 0x1, 0x1, },
339
+
.vals = { 0x0, 0x1, },
340
+
},
341
+
},
307
342
{ /* sentinel */ }
308
343
};
+6
drivers/clk/uniphier/clk-uniphier.h
+6
drivers/clk/uniphier/clk-uniphier.h
···
119
119
UNIPHIER_CLK_DIV2(parent, div0, div1), \
120
120
UNIPHIER_CLK_DIV2(parent, div2, div3)
121
121
122
+
#define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \
123
+
UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3), \
124
+
UNIPHIER_CLK_DIV(parent, div4)
125
+
122
126
struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
123
127
struct regmap *regmap,
124
128
const char *name,
···
150
146
extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
151
147
extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
152
148
extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];
149
+
extern const struct uniphier_clk_data uniphier_nx1_sys_clk_data[];
153
150
extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[];
154
151
extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
155
152
extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
156
153
extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
154
+
extern const struct uniphier_clk_data uniphier_pro4_sg_clk_data[];
157
155
158
156
#endif /* __CLK_UNIPHIER_H__ */