Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mfd-next-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"New Drivers:
- Add support for Renesas RZ/G2L MTU3
New Device Support:
- Add support for Lenovo Yoga Book X90F to Intel CHT WC
- Add support for MAX5970 and MAX5978 to Simple MFD (I2C)
- Add support for Meteor Lake PCH-S LPSS PCI to Intel LPSS PCI
- Add support for AXP15060 PMIC to X-Powers PMIC collection
Remove Device Support:
- Remove support for Samsung 5M8751 and S5M8763 PMIC devices
New Functionality:
- Convert deprecated QCOM IRQ Chip to config registers
- Add support for 32-bit address spaces to Renesas SMUs
Fix-ups:
- Make use of APIs / MACROs designed to simplify and demystify
- Add / improve Device Tree bindings
- Memory saving struct layout optimisations
- Remove old / deprecated functionality
- Factor out unassigned register addresses from ranges
- Trivial: Spelling fixes, renames and coding style fixes
- Rid 'defined but not used' warnings
- Remove ineffective casts and pointer stubs
Bug Fixes:
- Fix incorrectly non-inverted mask/unmask IRQs on QCOM platforms
- Remove MODULE_*() helpers from non-tristate drivers
- Do not attempt to use out-of-range memory addresses associated with io_base
- Provide missing export helpers
- Fix remap bulk read optimisation fallout
- Fix memory leak issues in error paths"
* tag 'mfd-next-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (88 commits)
dt-bindings: mfd: ti,j721e-system-controller: Add SoC chip ID
leds: bd2606mvv: Driver for the Rohm 6 Channel i2c LED driver
dt-bindings: mfd: qcom,spmi-pmic: Document flash LED controller
dt-bindings: mfd: x-powers,axp152: Document the AXP15060 variant
mfd: axp20x: Add support for AXP15060 PMIC
dt-bindings: mfd: x-powers,axp152: Document the AXP313a variant
counter: rz-mtu3-cnt: Unlock on error in rz_mtu3_count_ceiling_write()
dt-bindings: mfd: dlg,da9063: Document voltage monitoring
dt-bindings: mfd: stm32: Remove unnecessary blank lines
dt-bindings: mfd: qcom,spmi-pmic: Use generic ADC node name in examples
dt-bindings: mfd: syscon: Add nuvoton,ma35d1-sys compatible
MAINTAINERS: Add entries for Renesas RZ/G2L MTU3a counter driver
counter: Add Renesas RZ/G2L MTU3a counter driver
Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and external_input_phase_clock_select
mfd: Add Renesas RZ/G2L MTU3a core driver
dt-bindings: timer: Document RZ/G2L MTU3a bindings
mfd: rsmu_i2c: Convert to i2c's .probe_new() again
mfd: intel-lpss: Add Intel Meteor Lake PCH-S LPSS PCI IDs
mfd: dln2: Fix memory leak in dln2_probe()
mfd: axp20x: Fix axp288 writable-ranges
...
+3521
-847
+32
Documentation/ABI/testing/sysfs-bus-counter
+32
Documentation/ABI/testing/sysfs-bus-counter
···
1
+
What: /sys/bus/counter/devices/counterX/cascade_counts_enable
2
+
KernelVersion: 6.4
3
+
Contact: linux-iio@vger.kernel.org
4
+
Description:
5
+
Indicates the cascading of Counts on Counter X.
6
+
7
+
Valid attribute values are boolean.
8
+
9
+
What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select
10
+
KernelVersion: 6.4
11
+
Contact: linux-iio@vger.kernel.org
12
+
Description:
13
+
Selects the external clock pin for phase counting mode of
14
+
Counter X.
15
+
16
+
MTCLKA-MTCLKB:
17
+
MTCLKA and MTCLKB pins are selected for the external
18
+
phase clock.
19
+
20
+
MTCLKC-MTCLKD:
21
+
MTCLKC and MTCLKD pins are selected for the external
22
+
phase clock.
23
+
24
+
What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select_available
25
+
KernelVersion: 6.4
26
+
Contact: linux-iio@vger.kernel.org
27
+
Description:
28
+
Discrete set of available values for the respective device
29
+
configuration are listed in this file.
30
+
1
31
What: /sys/bus/counter/devices/counterX/countY/count
2
32
KernelVersion: 5.2
3
33
Contact: linux-iio@vger.kernel.org
···
245
215
Description:
246
216
This attribute indicates the number of overflows of count Y.
247
217
218
+
What: /sys/bus/counter/devices/counterX/cascade_counts_enable_component_id
219
+
What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select_component_id
248
220
What: /sys/bus/counter/devices/counterX/countY/capture_component_id
249
221
What: /sys/bus/counter/devices/counterX/countY/ceiling_component_id
250
222
What: /sys/bus/counter/devices/counterX/countY/floor_component_id
+3
-3
Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml
+3
-3
Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml
···
36
36
clock-controller:
37
37
# Child node
38
38
type: object
39
-
$ref: "../clock/canaan,k210-clk.yaml"
39
+
$ref: ../clock/canaan,k210-clk.yaml
40
40
description:
41
41
Clock controller for the SoC clocks. This child node definition
42
42
should follow the bindings specified in
···
45
45
reset-controller:
46
46
# Child node
47
47
type: object
48
-
$ref: "../reset/canaan,k210-rst.yaml"
48
+
$ref: ../reset/canaan,k210-rst.yaml
49
49
description:
50
50
Reset controller for the SoC. This child node definition
51
51
should follow the bindings specified in
···
54
54
syscon-reboot:
55
55
# Child node
56
56
type: object
57
-
$ref: "../power/reset/syscon-reboot.yaml"
57
+
$ref: ../power/reset/syscon-reboot.yaml
58
58
description:
59
59
Reboot method for the SoC. This child node definition
60
60
should follow the bindings specified in
+11
-11
Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
+11
-11
Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
···
65
65
ARM Cortex M4 Co-processor. Contains the name of the rpmsg
66
66
device. Used to match the subnode to the rpmsg device announced by
67
67
the SCP.
68
-
$ref: "/schemas/types.yaml#/definitions/string"
68
+
$ref: /schemas/types.yaml#/definitions/string
69
69
70
70
spi-max-frequency: true
71
71
···
94
94
const: 0
95
95
96
96
typec:
97
-
$ref: "/schemas/chrome/google,cros-ec-typec.yaml#"
97
+
$ref: /schemas/chrome/google,cros-ec-typec.yaml#
98
98
99
99
ec-pwm:
100
-
$ref: "/schemas/pwm/google,cros-ec-pwm.yaml#"
100
+
$ref: /schemas/pwm/google,cros-ec-pwm.yaml#
101
101
deprecated: true
102
102
103
103
pwm:
104
-
$ref: "/schemas/pwm/google,cros-ec-pwm.yaml#"
104
+
$ref: /schemas/pwm/google,cros-ec-pwm.yaml#
105
105
106
106
kbd-led-backlight:
107
-
$ref: "/schemas/chrome/google,cros-kbd-led-backlight.yaml#"
107
+
$ref: /schemas/chrome/google,cros-kbd-led-backlight.yaml#
108
108
109
109
keyboard-controller:
110
-
$ref: "/schemas/input/google,cros-ec-keyb.yaml#"
110
+
$ref: /schemas/input/google,cros-ec-keyb.yaml#
111
111
112
112
proximity:
113
-
$ref: "/schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml#"
113
+
$ref: /schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml#
114
114
115
115
codecs:
116
116
type: object
···
126
126
patternProperties:
127
127
"^ec-codec@[a-f0-9]+$":
128
128
type: object
129
-
$ref: "/schemas/sound/google,cros-ec-codec.yaml#"
129
+
$ref: /schemas/sound/google,cros-ec-codec.yaml#
130
130
131
131
required:
132
132
- "#address-cells"
···
151
151
patternProperties:
152
152
"^i2c-tunnel[0-9]*$":
153
153
type: object
154
-
$ref: "/schemas/i2c/google,cros-ec-i2c-tunnel.yaml#"
154
+
$ref: /schemas/i2c/google,cros-ec-i2c-tunnel.yaml#
155
155
156
156
"^regulator@[0-9]+$":
157
157
type: object
158
-
$ref: "/schemas/regulator/google,cros-ec-regulator.yaml#"
158
+
$ref: /schemas/regulator/google,cros-ec-regulator.yaml#
159
159
160
160
"^extcon[0-9]*$":
161
161
type: object
162
-
$ref: "/schemas/extcon/extcon-usbc-cros-ec.yaml#"
162
+
$ref: /schemas/extcon/extcon-usbc-cros-ec.yaml#
163
163
164
164
required:
165
165
- compatible
+1
-1
Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml
+1
-1
Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml
+151
Documentation/devicetree/bindings/mfd/maxim,max5970.yaml
+151
Documentation/devicetree/bindings/mfd/maxim,max5970.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mfd/maxim,max5970.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Regulator for MAX5970 Smart Switch from Maxim Integrated
8
+
9
+
maintainers:
10
+
- Patrick Rudolph <patrick.rudolph@9elements.com>
11
+
12
+
description: |
13
+
The smart switch provides no output regulation, but independent fault protection
14
+
and voltage and current sensing.
15
+
Programming is done through I2C bus.
16
+
17
+
Datasheets:
18
+
https://datasheets.maximintegrated.com/en/ds/MAX5970.pdf
19
+
https://datasheets.maximintegrated.com/en/ds/MAX5978.pdf
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- maxim,max5970
25
+
- maxim,max5978
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
interrupts:
31
+
maxItems: 1
32
+
33
+
leds:
34
+
type: object
35
+
description:
36
+
Properties for four LEDS.
37
+
38
+
properties:
39
+
"#address-cells":
40
+
const: 1
41
+
42
+
"#size-cells":
43
+
const: 0
44
+
45
+
patternProperties:
46
+
"^led@[0-3]$":
47
+
$ref: /schemas/leds/common.yaml#
48
+
type: object
49
+
50
+
additionalProperties: false
51
+
52
+
vss1-supply:
53
+
description: Supply of the first channel.
54
+
55
+
vss2-supply:
56
+
description: Supply of the second channel.
57
+
58
+
regulators:
59
+
type: object
60
+
description:
61
+
Properties for both hot swap control/switch.
62
+
63
+
patternProperties:
64
+
"^sw[0-1]$":
65
+
$ref: /schemas/regulator/regulator.yaml#
66
+
type: object
67
+
properties:
68
+
shunt-resistor-micro-ohms:
69
+
description: |
70
+
The value of current sense resistor in microohms.
71
+
72
+
required:
73
+
- shunt-resistor-micro-ohms
74
+
75
+
unevaluatedProperties: false
76
+
77
+
additionalProperties: false
78
+
79
+
required:
80
+
- compatible
81
+
- reg
82
+
- regulators
83
+
- vss1-supply
84
+
85
+
allOf:
86
+
- if:
87
+
properties:
88
+
compatible:
89
+
enum:
90
+
- maxim,max5970
91
+
then:
92
+
required:
93
+
- vss2-supply
94
+
95
+
additionalProperties: false
96
+
97
+
examples:
98
+
- |
99
+
i2c {
100
+
#address-cells = <1>;
101
+
#size-cells = <0>;
102
+
regulator@3a {
103
+
compatible = "maxim,max5978";
104
+
reg = <0x3a>;
105
+
vss1-supply = <&p3v3>;
106
+
107
+
regulators {
108
+
sw0_ref_0: sw0 {
109
+
shunt-resistor-micro-ohms = <12000>;
110
+
};
111
+
};
112
+
113
+
leds {
114
+
#address-cells = <1>;
115
+
#size-cells = <0>;
116
+
led@0 {
117
+
reg = <0>;
118
+
label = "led0";
119
+
default-state = "on";
120
+
};
121
+
led@1 {
122
+
reg = <1>;
123
+
label = "led1";
124
+
default-state = "on";
125
+
};
126
+
};
127
+
};
128
+
};
129
+
130
+
- |
131
+
i2c {
132
+
#address-cells = <1>;
133
+
#size-cells = <0>;
134
+
135
+
regulator@3a {
136
+
compatible = "maxim,max5970";
137
+
reg = <0x3a>;
138
+
vss1-supply = <&p3v3>;
139
+
vss2-supply = <&p5v>;
140
+
141
+
regulators {
142
+
sw0_ref_1: sw0 {
143
+
shunt-resistor-micro-ohms = <12000>;
144
+
};
145
+
sw1_ref_1: sw1 {
146
+
shunt-resistor-micro-ohms = <10000>;
147
+
};
148
+
};
149
+
};
150
+
};
151
+
...
+13
-2
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+13
-2
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
···
33
33
compatible:
34
34
items:
35
35
- enum:
36
+
- qcom,pm2250
36
37
- qcom,pm6125
37
38
- qcom,pm6150
38
39
- qcom,pm6150l
···
79
78
- qcom,pmk8350
80
79
- qcom,pmk8550
81
80
- qcom,pmm8155au
81
+
- qcom,pmm8654au
82
82
- qcom,pmp8074
83
83
- qcom,pmr735a
84
84
- qcom,pmr735b
···
117
115
type: object
118
116
oneOf:
119
117
- $ref: /schemas/iio/adc/qcom,spmi-iadc.yaml#
118
+
- $ref: /schemas/iio/adc/qcom,spmi-rradc.yaml#
120
119
- $ref: /schemas/iio/adc/qcom,spmi-vadc.yaml#
121
120
122
121
"^adc-tm@[0-9a-f]+$":
···
137
134
"gpio@[0-9a-f]+$":
138
135
type: object
139
136
$ref: /schemas/pinctrl/qcom,pmic-gpio.yaml#
137
+
138
+
"^led-controller@[0-9a-f]+$":
139
+
type: object
140
+
$ref: /schemas/leds/qcom,spmi-flash-led.yaml#
141
+
142
+
"^nvram@[0-9a-f]+$":
143
+
type: object
144
+
$ref: /schemas/nvmem/qcom,spmi-sdam.yaml#
140
145
141
146
"pon@[0-9a-f]+$":
142
147
type: object
···
287
276
#size-cells = <0>;
288
277
#io-channel-cells = <1>;
289
278
290
-
adc-chan@6 {
279
+
channel@6 {
291
280
reg = <ADC5_DIE_TEMP>;
292
281
label = "die_temp";
293
282
};
294
283
295
-
adc-chan@4f {
284
+
channel@4f {
296
285
reg = <ADC5_AMUX_THM3_100K_PU>;
297
286
qcom,ratiometric;
298
287
qcom,hw-settle-time = <200>;
+4
Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+4
Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
···
25
25
- qcom,sc8280xp-tcsr
26
26
- qcom,sdm630-tcsr
27
27
- qcom,sdm845-tcsr
28
+
- qcom,sdx55-tcsr
29
+
- qcom,sdx65-tcsr
28
30
- qcom,sm8150-tcsr
31
+
- qcom,sm8450-tcsr
29
32
- qcom,tcsr-apq8064
30
33
- qcom,tcsr-apq8084
31
34
- qcom,tcsr-ipq5332
32
35
- qcom,tcsr-ipq6018
33
36
- qcom,tcsr-ipq8064
37
+
- qcom,tcsr-ipq9574
34
38
- qcom,tcsr-mdm9615
35
39
- qcom,tcsr-msm8226
36
40
- qcom,tcsr-msm8660
+1
-1
Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml
+1
-1
Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml
+1
-1
Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml
+1
-1
Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml
+1
-1
Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
+1
-1
Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
+2
Documentation/devicetree/bindings/mfd/syscon.yaml
+2
Documentation/devicetree/bindings/mfd/syscon.yaml
···
56
56
- microchip,lan966x-cpu-syscon
57
57
- microchip,sparx5-cpu-syscon
58
58
- mstar,msc313-pmsleep
59
+
- nuvoton,ma35d1-sys
59
60
- nuvoton,wpcm450-shm
60
61
- rockchip,px30-qos
61
62
- rockchip,rk3036-qos
···
68
67
- rockchip,rk3568-qos
69
68
- rockchip,rk3588-qos
70
69
- rockchip,rv1126-qos
70
+
- starfive,jh7100-sysmain
71
71
72
72
- const: syscon
73
73
+11
Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+11
Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
···
62
62
description:
63
63
The phy node corresponding to the ethernet MAC.
64
64
65
+
"^chipid@[0-9a-f]+$":
66
+
type: object
67
+
$ref: /schemas/hwinfo/ti,k3-socinfo.yaml#
68
+
description:
69
+
The node corresponding to SoC chip identification.
70
+
65
71
required:
66
72
- compatible
67
73
- reg
···
104
98
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
105
99
reg = <0x4140 0x18>;
106
100
#clock-cells = <1>;
101
+
};
102
+
103
+
chipid@14 {
104
+
compatible = "ti,am654-chipid";
105
+
reg = <0x14 0x4>;
107
106
};
108
107
};
109
108
...
+51
Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml
+51
Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/mfd/ti,nspire-misc.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: TI Nspire MISC hardware block
9
+
10
+
maintainers:
11
+
- Andrew Davis <afd@ti.com>
12
+
13
+
description:
14
+
System controller node represents a register region containing a set
15
+
of miscellaneous registers. The registers are not cohesive enough to
16
+
represent as any specific type of device. Currently there is a reset
17
+
controller.
18
+
19
+
properties:
20
+
compatible:
21
+
items:
22
+
- enum:
23
+
- ti,nspire-misc
24
+
- const: syscon
25
+
- const: simple-mfd
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
reboot:
31
+
$ref: /schemas/power/reset/syscon-reboot.yaml#
32
+
33
+
required:
34
+
- compatible
35
+
- reg
36
+
- reboot
37
+
38
+
additionalProperties: false
39
+
40
+
examples:
41
+
- |
42
+
misc: misc@900a0000 {
43
+
compatible = "ti,nspire-misc", "syscon", "simple-mfd";
44
+
reg = <0x900a0000 0x1000>;
45
+
46
+
reboot {
47
+
compatible = "syscon-reboot";
48
+
offset = <0x08>;
49
+
value = <0x02>;
50
+
};
51
+
};
+1
-1
Documentation/devicetree/bindings/mfd/wlf,arizona.yaml
+1
-1
Documentation/devicetree/bindings/mfd/wlf,arizona.yaml
···
156
156
entry has a value that is out of range for a 16 bit register then the
157
157
chip default will be used. If present exactly five values must be
158
158
specified.
159
-
$ref: "/schemas/types.yaml#/definitions/uint32-array"
159
+
$ref: /schemas/types.yaml#/definitions/uint32-array
160
160
minItems: 1
161
161
maxItems: 5
162
162
+2
-2
Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
+2
-2
Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/mfd/x-powers,ac100.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/mfd/x-powers,ac100.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: X-Powers AC100
8
8
+20
-12
Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
+20
-12
Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
···
47
47
- x-powers,axp209
48
48
49
49
then:
50
-
not:
51
-
required:
52
-
- x-powers,drive-vbus-en
50
+
properties:
51
+
x-powers,drive-vbus-en: false
53
52
54
53
- if:
55
54
not:
···
58
59
const: x-powers,axp806
59
60
60
61
then:
61
-
allOf:
62
-
- not:
63
-
required:
64
-
- x-powers,self-working-mode
65
-
66
-
- not:
67
-
required:
68
-
- x-powers,master-mode
62
+
properties:
63
+
x-powers,self-working-mode: false
64
+
x-powers,master-mode: false
69
65
70
66
- if:
71
67
not:
···
73
79
required:
74
80
- interrupts
75
81
82
+
- if:
83
+
properties:
84
+
compatible:
85
+
contains:
86
+
enum:
87
+
- x-powers,axp313a
88
+
- x-powers,axp15060
89
+
90
+
then:
91
+
properties:
92
+
x-powers,dcdc-freq: false
93
+
76
94
properties:
77
95
compatible:
78
96
oneOf:
···
94
88
- x-powers,axp209
95
89
- x-powers,axp221
96
90
- x-powers,axp223
91
+
- x-powers,axp313a
97
92
- x-powers,axp803
98
93
- x-powers,axp806
99
94
- x-powers,axp809
100
95
- x-powers,axp813
96
+
- x-powers,axp15060
101
97
- items:
102
98
- const: x-powers,axp228
103
99
- const: x-powers,axp221
···
268
260
Defines the work frequency of DC-DC in kHz.
269
261
270
262
patternProperties:
271
-
"^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|drivevbus|dc5ldo)$":
263
+
"^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo)$":
272
264
$ref: /schemas/regulator/regulator.yaml#
273
265
type: object
274
266
unevaluatedProperties: false
+2
-2
Documentation/devicetree/bindings/mfd/xylon,logicvc.yaml
+2
-2
Documentation/devicetree/bindings/mfd/xylon,logicvc.yaml
···
2
2
# Copyright 2019 Bootlin
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/mfd/xylon,logicvc.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/mfd/xylon,logicvc.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Xylon LogiCVC multi-function device
9
9
+302
Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
+302
Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
8
+
9
+
maintainers:
10
+
- Biju Das <biju.das.jz@bp.renesas.com>
11
+
12
+
description: |
13
+
This hardware block consists of eight 16-bit timer channels and one
14
+
32- bit timer channel. It supports the following specifications:
15
+
- Pulse input/output: 28 lines max.
16
+
- Pulse input 3 lines
17
+
- Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
18
+
for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
19
+
(when LWA = 1))
20
+
- Operating frequency Up to 100 MHz
21
+
- Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
22
+
- Waveform output on compare match
23
+
- Input capture function (noise filter setting available)
24
+
- Counter-clearing operation
25
+
- Simultaneous writing to multiple timer counters (TCNT)
26
+
(excluding MTU8).
27
+
- Simultaneous clearing on compare match or input capture
28
+
(excluding MTU8).
29
+
- Simultaneous input and output to registers in synchronization with
30
+
counter operations (excluding MTU8).
31
+
- Up to 12-phase PWM output in combination with synchronous operation
32
+
(excluding MTU8)
33
+
- [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
34
+
- Buffer operation specifiable
35
+
- [MTU1, MTU2]
36
+
- Phase counting mode can be specified independently
37
+
- 32-bit phase counting mode can be specified for interlocked operation
38
+
of MTU1 and MTU2 (when TMDR3.LWA = 1)
39
+
- Cascade connection operation available
40
+
- [MTU3, MTU4, MTU6, and MTU7]
41
+
- Through interlocked operation of MTU3/4 and MTU6/7, the positive and
42
+
negative signals in six phases (12 phases in total) can be output in
43
+
complementary PWM and reset-synchronized PWM operation.
44
+
- In complementary PWM mode, values can be transferred from buffer
45
+
registers to temporary registers at crests and troughs of the timer-
46
+
counter values or when the buffer registers (TGRD registers in MTU4
47
+
and MTU7) are written to.
48
+
- Double-buffering selectable in complementary PWM mode.
49
+
- [MTU3 and MTU4]
50
+
- Through interlocking with MTU0, a mode for driving AC synchronous
51
+
motors (brushless DC motors) by using complementary PWM output and
52
+
reset-synchronized PWM output is settable and allows the selection
53
+
of two types of waveform output (chopping or level).
54
+
- [MTU5]
55
+
- Capable of operation as a dead-time compensation counter.
56
+
- [MTU0/MTU5, MTU1, MTU2, and MTU8]
57
+
- 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
58
+
through interlocked operation with MTU0/MTU5 and MTU8.
59
+
- Interrupt-skipping function
60
+
- In complementary PWM mode, interrupts on crests and troughs of counter
61
+
values and triggers to start conversion by the A/D converter can be
62
+
skipped.
63
+
- Interrupt sources: 43 sources.
64
+
- Buffer operation:
65
+
- Automatic transfer of register data (transfer from the buffer
66
+
register to the timer register).
67
+
- Trigger generation
68
+
- A/D converter start triggers can be generated
69
+
- A/D converter start request delaying function enables A/D converter
70
+
to be started with any desired timing and to be synchronized with
71
+
PWM output.
72
+
- Low power consumption function
73
+
- The MTU3a can be placed in the module-stop state.
74
+
75
+
There are two phase counting modes. 16-bit phase counting mode in which
76
+
MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
77
+
counting mode in which MTU1 and MTU2 are cascaded.
78
+
79
+
In phase counting mode, the phase difference between two external input
80
+
clocks is detected and the corresponding TCNT is incremented or
81
+
decremented.
82
+
The below counters are supported
83
+
count0 - MTU1 16-bit phase counting
84
+
count1 - MTU2 16-bit phase counting
85
+
count2 - MTU1+ MTU2 32-bit phase counting
86
+
87
+
The module supports PWM mode{1,2}, Reset-synchronized PWM mode and
88
+
complementary PWM mode{1,2,3}.
89
+
90
+
In complementary PWM mode, six positive-phase and six negative-phase PWM
91
+
waveforms (12 phases in total) with dead time can be output by
92
+
combining MTU{3,4} and MTU{6,7}.
93
+
94
+
The below pwm channels are supported in pwm mode 1.
95
+
pwm0 - MTU0.MTIOC0A PWM mode 1
96
+
pwm1 - MTU0.MTIOC0C PWM mode 1
97
+
pwm2 - MTU1.MTIOC1A PWM mode 1
98
+
pwm3 - MTU2.MTIOC2A PWM mode 1
99
+
pwm4 - MTU3.MTIOC3A PWM mode 1
100
+
pwm5 - MTU3.MTIOC3C PWM mode 1
101
+
pwm6 - MTU4.MTIOC4A PWM mode 1
102
+
pwm7 - MTU4.MTIOC4C PWM mode 1
103
+
pwm8 - MTU6.MTIOC6A PWM mode 1
104
+
pwm9 - MTU6.MTIOC6C PWM mode 1
105
+
pwm10 - MTU7.MTIOC7A PWM mode 1
106
+
pwm11 - MTU7.MTIOC7C PWM mode 1
107
+
108
+
properties:
109
+
compatible:
110
+
items:
111
+
- enum:
112
+
- renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
113
+
- renesas,r9a07g054-mtu3 # RZ/V2L
114
+
- const: renesas,rz-mtu3
115
+
116
+
reg:
117
+
maxItems: 1
118
+
119
+
interrupts:
120
+
items:
121
+
- description: MTU0.TGRA input capture/compare match
122
+
- description: MTU0.TGRB input capture/compare match
123
+
- description: MTU0.TGRC input capture/compare match
124
+
- description: MTU0.TGRD input capture/compare match
125
+
- description: MTU0.TCNT overflow
126
+
- description: MTU0.TGRE compare match
127
+
- description: MTU0.TGRF compare match
128
+
- description: MTU1.TGRA input capture/compare match
129
+
- description: MTU1.TGRB input capture/compare match
130
+
- description: MTU1.TCNT overflow
131
+
- description: MTU1.TCNT underflow
132
+
- description: MTU2.TGRA input capture/compare match
133
+
- description: MTU2.TGRB input capture/compare match
134
+
- description: MTU2.TCNT overflow
135
+
- description: MTU2.TCNT underflow
136
+
- description: MTU3.TGRA input capture/compare match
137
+
- description: MTU3.TGRB input capture/compare match
138
+
- description: MTU3.TGRC input capture/compare match
139
+
- description: MTU3.TGRD input capture/compare match
140
+
- description: MTU3.TCNT overflow
141
+
- description: MTU4.TGRA input capture/compare match
142
+
- description: MTU4.TGRB input capture/compare match
143
+
- description: MTU4.TGRC input capture/compare match
144
+
- description: MTU4.TGRD input capture/compare match
145
+
- description: MTU4.TCNT overflow/underflow
146
+
- description: MTU5.TGRU input capture/compare match
147
+
- description: MTU5.TGRV input capture/compare match
148
+
- description: MTU5.TGRW input capture/compare match
149
+
- description: MTU6.TGRA input capture/compare match
150
+
- description: MTU6.TGRB input capture/compare match
151
+
- description: MTU6.TGRC input capture/compare match
152
+
- description: MTU6.TGRD input capture/compare match
153
+
- description: MTU6.TCNT overflow
154
+
- description: MTU7.TGRA input capture/compare match
155
+
- description: MTU7.TGRB input capture/compare match
156
+
- description: MTU7.TGRC input capture/compare match
157
+
- description: MTU7.TGRD input capture/compare match
158
+
- description: MTU7.TCNT overflow/underflow
159
+
- description: MTU8.TGRA input capture/compare match
160
+
- description: MTU8.TGRB input capture/compare match
161
+
- description: MTU8.TGRC input capture/compare match
162
+
- description: MTU8.TGRD input capture/compare match
163
+
- description: MTU8.TCNT overflow
164
+
- description: MTU8.TCNT underflow
165
+
166
+
interrupt-names:
167
+
items:
168
+
- const: tgia0
169
+
- const: tgib0
170
+
- const: tgic0
171
+
- const: tgid0
172
+
- const: tgiv0
173
+
- const: tgie0
174
+
- const: tgif0
175
+
- const: tgia1
176
+
- const: tgib1
177
+
- const: tgiv1
178
+
- const: tgiu1
179
+
- const: tgia2
180
+
- const: tgib2
181
+
- const: tgiv2
182
+
- const: tgiu2
183
+
- const: tgia3
184
+
- const: tgib3
185
+
- const: tgic3
186
+
- const: tgid3
187
+
- const: tgiv3
188
+
- const: tgia4
189
+
- const: tgib4
190
+
- const: tgic4
191
+
- const: tgid4
192
+
- const: tgiv4
193
+
- const: tgiu5
194
+
- const: tgiv5
195
+
- const: tgiw5
196
+
- const: tgia6
197
+
- const: tgib6
198
+
- const: tgic6
199
+
- const: tgid6
200
+
- const: tgiv6
201
+
- const: tgia7
202
+
- const: tgib7
203
+
- const: tgic7
204
+
- const: tgid7
205
+
- const: tgiv7
206
+
- const: tgia8
207
+
- const: tgib8
208
+
- const: tgic8
209
+
- const: tgid8
210
+
- const: tgiv8
211
+
- const: tgiu8
212
+
213
+
clocks:
214
+
maxItems: 1
215
+
216
+
power-domains:
217
+
maxItems: 1
218
+
219
+
resets:
220
+
maxItems: 1
221
+
222
+
"#pwm-cells":
223
+
const: 2
224
+
225
+
required:
226
+
- compatible
227
+
- reg
228
+
- interrupts
229
+
- interrupt-names
230
+
- clocks
231
+
- power-domains
232
+
- resets
233
+
234
+
additionalProperties: false
235
+
236
+
examples:
237
+
- |
238
+
#include <dt-bindings/clock/r9a07g044-cpg.h>
239
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
240
+
241
+
mtu3: timer@10001200 {
242
+
compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";
243
+
reg = <0x10001200 0xb00>;
244
+
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
245
+
<GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
246
+
<GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
247
+
<GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
248
+
<GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
249
+
<GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
250
+
<GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
251
+
<GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
252
+
<GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
253
+
<GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
254
+
<GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
255
+
<GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
256
+
<GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
257
+
<GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
258
+
<GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
259
+
<GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
260
+
<GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
261
+
<GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
262
+
<GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
263
+
<GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
264
+
<GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
265
+
<GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
266
+
<GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
267
+
<GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
268
+
<GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
269
+
<GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
270
+
<GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
271
+
<GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
272
+
<GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
273
+
<GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
274
+
<GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
275
+
<GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
276
+
<GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
277
+
<GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
278
+
<GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
279
+
<GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
280
+
<GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
281
+
<GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
282
+
<GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
283
+
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
284
+
<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
285
+
<GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
286
+
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
287
+
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
288
+
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
289
+
"tgif0",
290
+
"tgia1", "tgib1", "tgiv1", "tgiu1",
291
+
"tgia2", "tgib2", "tgiv2", "tgiu2",
292
+
"tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
293
+
"tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
294
+
"tgiu5", "tgiv5", "tgiw5",
295
+
"tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
296
+
"tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
297
+
"tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
298
+
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
299
+
power-domains = <&cpg>;
300
+
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
301
+
#pwm-cells = <2>;
302
+
};
+8
MAINTAINERS
+8
MAINTAINERS
···
17972
17972
F: Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
17973
17973
F: drivers/iio/adc/rzg2l_adc.c
17974
17974
17975
+
RENESAS RZ/G2L MTU3a COUNTER DRIVER
17976
+
M: Biju Das <biju.das.jz@bp.renesas.com>
17977
+
L: linux-iio@vger.kernel.org
17978
+
L: linux-renesas-soc@vger.kernel.org
17979
+
S: Supported
17980
+
F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
17981
+
F: drivers/counter/rz-mtu3-cnt.c
17982
+
17975
17983
RENESAS RZ/N1 A5PSW SWITCH DRIVER
17976
17984
M: Clément Léger <clement.leger@bootlin.com>
17977
17985
L: linux-renesas-soc@vger.kernel.org
+11
drivers/counter/Kconfig
+11
drivers/counter/Kconfig
···
73
73
To compile this driver as a module, choose M here: the
74
74
module will be called microchip-tcb-capture.
75
75
76
+
config RZ_MTU3_CNT
77
+
tristate "Renesas RZ/G2L MTU3a counter driver"
78
+
depends on RZ_MTU3 || COMPILE_TEST
79
+
help
80
+
Enable support for MTU3a counter driver found on Renesas RZ/G2L alike
81
+
SoCs. This IP supports both 16-bit and 32-bit phase counting mode
82
+
support.
83
+
84
+
To compile this driver as a module, choose M here: the
85
+
module will be called rz-mtu3-cnt.
86
+
76
87
config STM32_LPTIMER_CNT
77
88
tristate "STM32 LP Timer encoder counter driver"
78
89
depends on MFD_STM32_LPTIMER || COMPILE_TEST
+1
drivers/counter/Makefile
+1
drivers/counter/Makefile
···
8
8
9
9
obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o
10
10
obj-$(CONFIG_INTERRUPT_CNT) += interrupt-cnt.o
11
+
obj-$(CONFIG_RZ_MTU3_CNT) += rz-mtu3-cnt.o
11
12
obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o
12
13
obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o
13
14
obj-$(CONFIG_TI_EQEP) += ti-eqep.o
+906
drivers/counter/rz-mtu3-cnt.c
+906
drivers/counter/rz-mtu3-cnt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Renesas RZ/G2L MTU3a Counter driver
4
+
*
5
+
* Copyright (C) 2022 Renesas Electronics Corporation
6
+
*/
7
+
8
+
#include <linux/clk.h>
9
+
#include <linux/counter.h>
10
+
#include <linux/mfd/rz-mtu3.h>
11
+
#include <linux/module.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/pm_runtime.h>
14
+
#include <linux/types.h>
15
+
16
+
/*
17
+
* Register descriptions
18
+
* TSR: Timer Status Register
19
+
* TMDR1: Timer Mode Register 1
20
+
* TMDR3: Timer Mode Register 3
21
+
* TIOR: Timer I/O Control Register
22
+
* TCR: Timer Control Register
23
+
* TCNT: Timer Counter
24
+
* TGRA: Timer general register A
25
+
* TCNTLW: Timer Longword Counter
26
+
* TGRALW: Timer longword general register A
27
+
*/
28
+
29
+
#define RZ_MTU3_TSR_TCFD BIT(7) /* Count Direction Flag */
30
+
31
+
#define RZ_MTU3_TMDR1_PH_CNT_MODE_1 (4) /* Phase counting mode 1 */
32
+
#define RZ_MTU3_TMDR1_PH_CNT_MODE_2 (5) /* Phase counting mode 2 */
33
+
#define RZ_MTU3_TMDR1_PH_CNT_MODE_3 (6) /* Phase counting mode 3 */
34
+
#define RZ_MTU3_TMDR1_PH_CNT_MODE_4 (7) /* Phase counting mode 4 */
35
+
#define RZ_MTU3_TMDR1_PH_CNT_MODE_5 (9) /* Phase counting mode 5 */
36
+
#define RZ_MTU3_TMDR1_PH_CNT_MODE_MASK (0xf)
37
+
38
+
/*
39
+
* LWA: MTU1/MTU2 Combination Longword Access Control
40
+
* 0: 16-bit, 1: 32-bit
41
+
*/
42
+
#define RZ_MTU3_TMDR3_LWA (0)
43
+
44
+
/*
45
+
* PHCKSEL: External Input Phase Clock Select
46
+
* 0: MTCLKA and MTCLKB, 1: MTCLKC and MTCLKD
47
+
*/
48
+
#define RZ_MTU3_TMDR3_PHCKSEL (1)
49
+
50
+
#define RZ_MTU3_16_BIT_MTU1_CH (0)
51
+
#define RZ_MTU3_16_BIT_MTU2_CH (1)
52
+
#define RZ_MTU3_32_BIT_CH (2)
53
+
54
+
#define RZ_MTU3_TIOR_NO_OUTPUT (0) /* Output prohibited */
55
+
#define RZ_MTU3_TIOR_IC_BOTH (10) /* Input capture at both edges */
56
+
57
+
#define SIGNAL_A_ID (0)
58
+
#define SIGNAL_B_ID (1)
59
+
#define SIGNAL_C_ID (2)
60
+
#define SIGNAL_D_ID (3)
61
+
62
+
#define RZ_MTU3_MAX_HW_CNTR_CHANNELS (2)
63
+
#define RZ_MTU3_MAX_LOGICAL_CNTR_CHANNELS (3)
64
+
65
+
/**
66
+
* struct rz_mtu3_cnt - MTU3 counter private data
67
+
*
68
+
* @clk: MTU3 module clock
69
+
* @lock: Lock to prevent concurrent access for ceiling and count
70
+
* @ch: HW channels for the counters
71
+
* @count_is_enabled: Enabled state of Counter value channel
72
+
* @mtu_16bit_max: Cache for 16-bit counters
73
+
* @mtu_32bit_max: Cache for 32-bit counters
74
+
*/
75
+
struct rz_mtu3_cnt {
76
+
struct clk *clk;
77
+
struct mutex lock;
78
+
struct rz_mtu3_channel *ch;
79
+
bool count_is_enabled[RZ_MTU3_MAX_LOGICAL_CNTR_CHANNELS];
80
+
union {
81
+
u16 mtu_16bit_max[RZ_MTU3_MAX_HW_CNTR_CHANNELS];
82
+
u32 mtu_32bit_max;
83
+
};
84
+
};
85
+
86
+
static const enum counter_function rz_mtu3_count_functions[] = {
87
+
COUNTER_FUNCTION_QUADRATURE_X4,
88
+
COUNTER_FUNCTION_PULSE_DIRECTION,
89
+
COUNTER_FUNCTION_QUADRATURE_X2_B,
90
+
};
91
+
92
+
static inline size_t rz_mtu3_get_hw_ch(const size_t id)
93
+
{
94
+
return (id == RZ_MTU3_32_BIT_CH) ? 0 : id;
95
+
}
96
+
97
+
static inline struct rz_mtu3_channel *rz_mtu3_get_ch(struct counter_device *counter, int id)
98
+
{
99
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
100
+
const size_t ch_id = rz_mtu3_get_hw_ch(id);
101
+
102
+
return &priv->ch[ch_id];
103
+
}
104
+
105
+
static bool rz_mtu3_is_counter_invalid(struct counter_device *counter, int id)
106
+
{
107
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
108
+
unsigned long tmdr;
109
+
110
+
pm_runtime_get_sync(priv->ch->dev);
111
+
tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
112
+
pm_runtime_put(priv->ch->dev);
113
+
114
+
if (id == RZ_MTU3_32_BIT_CH && test_bit(RZ_MTU3_TMDR3_LWA, &tmdr))
115
+
return false;
116
+
117
+
if (id != RZ_MTU3_32_BIT_CH && !test_bit(RZ_MTU3_TMDR3_LWA, &tmdr))
118
+
return false;
119
+
120
+
return true;
121
+
}
122
+
123
+
static int rz_mtu3_lock_if_counter_is_valid(struct counter_device *counter,
124
+
struct rz_mtu3_channel *const ch,
125
+
struct rz_mtu3_cnt *const priv,
126
+
int id)
127
+
{
128
+
mutex_lock(&priv->lock);
129
+
130
+
if (ch->is_busy && !priv->count_is_enabled[id]) {
131
+
mutex_unlock(&priv->lock);
132
+
return -EINVAL;
133
+
}
134
+
135
+
if (rz_mtu3_is_counter_invalid(counter, id)) {
136
+
mutex_unlock(&priv->lock);
137
+
return -EBUSY;
138
+
}
139
+
140
+
return 0;
141
+
}
142
+
143
+
static int rz_mtu3_lock_if_count_is_enabled(struct rz_mtu3_channel *const ch,
144
+
struct rz_mtu3_cnt *const priv,
145
+
int id)
146
+
{
147
+
mutex_lock(&priv->lock);
148
+
149
+
if (ch->is_busy && !priv->count_is_enabled[id]) {
150
+
mutex_unlock(&priv->lock);
151
+
return -EINVAL;
152
+
}
153
+
154
+
return 0;
155
+
}
156
+
157
+
static int rz_mtu3_count_read(struct counter_device *counter,
158
+
struct counter_count *count, u64 *val)
159
+
{
160
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
161
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
162
+
int ret;
163
+
164
+
ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id);
165
+
if (ret)
166
+
return ret;
167
+
168
+
pm_runtime_get_sync(ch->dev);
169
+
if (count->id == RZ_MTU3_32_BIT_CH)
170
+
*val = rz_mtu3_32bit_ch_read(ch, RZ_MTU3_TCNTLW);
171
+
else
172
+
*val = rz_mtu3_16bit_ch_read(ch, RZ_MTU3_TCNT);
173
+
pm_runtime_put(ch->dev);
174
+
mutex_unlock(&priv->lock);
175
+
176
+
return 0;
177
+
}
178
+
179
+
static int rz_mtu3_count_write(struct counter_device *counter,
180
+
struct counter_count *count, const u64 val)
181
+
{
182
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
183
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
184
+
int ret;
185
+
186
+
ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id);
187
+
if (ret)
188
+
return ret;
189
+
190
+
pm_runtime_get_sync(ch->dev);
191
+
if (count->id == RZ_MTU3_32_BIT_CH)
192
+
rz_mtu3_32bit_ch_write(ch, RZ_MTU3_TCNTLW, val);
193
+
else
194
+
rz_mtu3_16bit_ch_write(ch, RZ_MTU3_TCNT, val);
195
+
pm_runtime_put(ch->dev);
196
+
mutex_unlock(&priv->lock);
197
+
198
+
return 0;
199
+
}
200
+
201
+
static int rz_mtu3_count_function_read_helper(struct rz_mtu3_channel *const ch,
202
+
struct rz_mtu3_cnt *const priv,
203
+
enum counter_function *function)
204
+
{
205
+
u8 timer_mode;
206
+
207
+
pm_runtime_get_sync(ch->dev);
208
+
timer_mode = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TMDR1);
209
+
pm_runtime_put(ch->dev);
210
+
211
+
switch (timer_mode & RZ_MTU3_TMDR1_PH_CNT_MODE_MASK) {
212
+
case RZ_MTU3_TMDR1_PH_CNT_MODE_1:
213
+
*function = COUNTER_FUNCTION_QUADRATURE_X4;
214
+
return 0;
215
+
case RZ_MTU3_TMDR1_PH_CNT_MODE_2:
216
+
*function = COUNTER_FUNCTION_PULSE_DIRECTION;
217
+
return 0;
218
+
case RZ_MTU3_TMDR1_PH_CNT_MODE_4:
219
+
*function = COUNTER_FUNCTION_QUADRATURE_X2_B;
220
+
return 0;
221
+
default:
222
+
/*
223
+
* TODO:
224
+
* - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_3
225
+
* - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_5
226
+
*/
227
+
return -EINVAL;
228
+
}
229
+
}
230
+
231
+
static int rz_mtu3_count_function_read(struct counter_device *counter,
232
+
struct counter_count *count,
233
+
enum counter_function *function)
234
+
{
235
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
236
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
237
+
int ret;
238
+
239
+
ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id);
240
+
if (ret)
241
+
return ret;
242
+
243
+
ret = rz_mtu3_count_function_read_helper(ch, priv, function);
244
+
mutex_unlock(&priv->lock);
245
+
246
+
return ret;
247
+
}
248
+
249
+
static int rz_mtu3_count_function_write(struct counter_device *counter,
250
+
struct counter_count *count,
251
+
enum counter_function function)
252
+
{
253
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
254
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
255
+
u8 timer_mode;
256
+
int ret;
257
+
258
+
ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id);
259
+
if (ret)
260
+
return ret;
261
+
262
+
switch (function) {
263
+
case COUNTER_FUNCTION_QUADRATURE_X4:
264
+
timer_mode = RZ_MTU3_TMDR1_PH_CNT_MODE_1;
265
+
break;
266
+
case COUNTER_FUNCTION_PULSE_DIRECTION:
267
+
timer_mode = RZ_MTU3_TMDR1_PH_CNT_MODE_2;
268
+
break;
269
+
case COUNTER_FUNCTION_QUADRATURE_X2_B:
270
+
timer_mode = RZ_MTU3_TMDR1_PH_CNT_MODE_4;
271
+
break;
272
+
default:
273
+
/*
274
+
* TODO:
275
+
* - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_3
276
+
* - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_5
277
+
*/
278
+
mutex_unlock(&priv->lock);
279
+
return -EINVAL;
280
+
}
281
+
282
+
pm_runtime_get_sync(ch->dev);
283
+
rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TMDR1, timer_mode);
284
+
pm_runtime_put(ch->dev);
285
+
mutex_unlock(&priv->lock);
286
+
287
+
return 0;
288
+
}
289
+
290
+
static int rz_mtu3_count_direction_read(struct counter_device *counter,
291
+
struct counter_count *count,
292
+
enum counter_count_direction *direction)
293
+
{
294
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
295
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
296
+
int ret;
297
+
u8 tsr;
298
+
299
+
ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id);
300
+
if (ret)
301
+
return ret;
302
+
303
+
pm_runtime_get_sync(ch->dev);
304
+
tsr = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TSR);
305
+
pm_runtime_put(ch->dev);
306
+
307
+
*direction = (tsr & RZ_MTU3_TSR_TCFD) ?
308
+
COUNTER_COUNT_DIRECTION_FORWARD : COUNTER_COUNT_DIRECTION_BACKWARD;
309
+
mutex_unlock(&priv->lock);
310
+
311
+
return 0;
312
+
}
313
+
314
+
static int rz_mtu3_count_ceiling_read(struct counter_device *counter,
315
+
struct counter_count *count,
316
+
u64 *ceiling)
317
+
{
318
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
319
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
320
+
const size_t ch_id = rz_mtu3_get_hw_ch(count->id);
321
+
int ret;
322
+
323
+
ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id);
324
+
if (ret)
325
+
return ret;
326
+
327
+
switch (count->id) {
328
+
case RZ_MTU3_16_BIT_MTU1_CH:
329
+
case RZ_MTU3_16_BIT_MTU2_CH:
330
+
*ceiling = priv->mtu_16bit_max[ch_id];
331
+
break;
332
+
case RZ_MTU3_32_BIT_CH:
333
+
*ceiling = priv->mtu_32bit_max;
334
+
break;
335
+
default:
336
+
/* should never reach this path */
337
+
mutex_unlock(&priv->lock);
338
+
return -EINVAL;
339
+
}
340
+
341
+
mutex_unlock(&priv->lock);
342
+
return 0;
343
+
}
344
+
345
+
static int rz_mtu3_count_ceiling_write(struct counter_device *counter,
346
+
struct counter_count *count,
347
+
u64 ceiling)
348
+
{
349
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
350
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
351
+
const size_t ch_id = rz_mtu3_get_hw_ch(count->id);
352
+
int ret;
353
+
354
+
ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id);
355
+
if (ret)
356
+
return ret;
357
+
358
+
switch (count->id) {
359
+
case RZ_MTU3_16_BIT_MTU1_CH:
360
+
case RZ_MTU3_16_BIT_MTU2_CH:
361
+
if (ceiling > U16_MAX) {
362
+
mutex_unlock(&priv->lock);
363
+
return -ERANGE;
364
+
}
365
+
priv->mtu_16bit_max[ch_id] = ceiling;
366
+
break;
367
+
case RZ_MTU3_32_BIT_CH:
368
+
if (ceiling > U32_MAX) {
369
+
mutex_unlock(&priv->lock);
370
+
return -ERANGE;
371
+
}
372
+
priv->mtu_32bit_max = ceiling;
373
+
break;
374
+
default:
375
+
/* should never reach this path */
376
+
mutex_unlock(&priv->lock);
377
+
return -EINVAL;
378
+
}
379
+
380
+
pm_runtime_get_sync(ch->dev);
381
+
if (count->id == RZ_MTU3_32_BIT_CH)
382
+
rz_mtu3_32bit_ch_write(ch, RZ_MTU3_TGRALW, ceiling);
383
+
else
384
+
rz_mtu3_16bit_ch_write(ch, RZ_MTU3_TGRA, ceiling);
385
+
386
+
rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TCR, RZ_MTU3_TCR_CCLR_TGRA);
387
+
pm_runtime_put(ch->dev);
388
+
mutex_unlock(&priv->lock);
389
+
390
+
return 0;
391
+
}
392
+
393
+
static void rz_mtu3_32bit_cnt_setting(struct counter_device *counter)
394
+
{
395
+
struct rz_mtu3_channel *const ch1 = rz_mtu3_get_ch(counter, 0);
396
+
struct rz_mtu3_channel *const ch2 = rz_mtu3_get_ch(counter, 1);
397
+
398
+
/* Phase counting mode 1 is used as default in initialization. */
399
+
rz_mtu3_8bit_ch_write(ch1, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_PH_CNT_MODE_1);
400
+
401
+
rz_mtu3_8bit_ch_write(ch1, RZ_MTU3_TCR, RZ_MTU3_TCR_CCLR_TGRA);
402
+
rz_mtu3_8bit_ch_write(ch1, RZ_MTU3_TIOR, RZ_MTU3_TIOR_IC_BOTH);
403
+
404
+
rz_mtu3_enable(ch1);
405
+
rz_mtu3_enable(ch2);
406
+
}
407
+
408
+
static void rz_mtu3_16bit_cnt_setting(struct counter_device *counter, int id)
409
+
{
410
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, id);
411
+
412
+
/* Phase counting mode 1 is used as default in initialization. */
413
+
rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_PH_CNT_MODE_1);
414
+
415
+
rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TCR, RZ_MTU3_TCR_CCLR_TGRA);
416
+
rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TIOR, RZ_MTU3_TIOR_NO_OUTPUT);
417
+
rz_mtu3_enable(ch);
418
+
}
419
+
420
+
static int rz_mtu3_initialize_counter(struct counter_device *counter, int id)
421
+
{
422
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, id);
423
+
struct rz_mtu3_channel *const ch1 = rz_mtu3_get_ch(counter, 0);
424
+
struct rz_mtu3_channel *const ch2 = rz_mtu3_get_ch(counter, 1);
425
+
426
+
switch (id) {
427
+
case RZ_MTU3_16_BIT_MTU1_CH:
428
+
case RZ_MTU3_16_BIT_MTU2_CH:
429
+
if (!rz_mtu3_request_channel(ch))
430
+
return -EBUSY;
431
+
432
+
rz_mtu3_16bit_cnt_setting(counter, id);
433
+
return 0;
434
+
case RZ_MTU3_32_BIT_CH:
435
+
/*
436
+
* 32-bit phase counting need MTU1 and MTU2 to create 32-bit
437
+
* cascade counter.
438
+
*/
439
+
if (!rz_mtu3_request_channel(ch1))
440
+
return -EBUSY;
441
+
442
+
if (!rz_mtu3_request_channel(ch2)) {
443
+
rz_mtu3_release_channel(ch1);
444
+
return -EBUSY;
445
+
}
446
+
447
+
rz_mtu3_32bit_cnt_setting(counter);
448
+
return 0;
449
+
default:
450
+
/* should never reach this path */
451
+
return -EINVAL;
452
+
}
453
+
}
454
+
455
+
static void rz_mtu3_terminate_counter(struct counter_device *counter, int id)
456
+
{
457
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, id);
458
+
struct rz_mtu3_channel *const ch1 = rz_mtu3_get_ch(counter, 0);
459
+
struct rz_mtu3_channel *const ch2 = rz_mtu3_get_ch(counter, 1);
460
+
461
+
if (id == RZ_MTU3_32_BIT_CH) {
462
+
rz_mtu3_release_channel(ch2);
463
+
rz_mtu3_release_channel(ch1);
464
+
rz_mtu3_disable(ch2);
465
+
rz_mtu3_disable(ch1);
466
+
} else {
467
+
rz_mtu3_release_channel(ch);
468
+
rz_mtu3_disable(ch);
469
+
}
470
+
}
471
+
472
+
static int rz_mtu3_count_enable_read(struct counter_device *counter,
473
+
struct counter_count *count, u8 *enable)
474
+
{
475
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
476
+
struct rz_mtu3_channel *const ch1 = rz_mtu3_get_ch(counter, 0);
477
+
struct rz_mtu3_channel *const ch2 = rz_mtu3_get_ch(counter, 1);
478
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
479
+
int ret;
480
+
481
+
ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id);
482
+
if (ret)
483
+
return ret;
484
+
485
+
if (count->id == RZ_MTU3_32_BIT_CH)
486
+
*enable = rz_mtu3_is_enabled(ch1) && rz_mtu3_is_enabled(ch2);
487
+
else
488
+
*enable = rz_mtu3_is_enabled(ch);
489
+
490
+
mutex_unlock(&priv->lock);
491
+
492
+
return 0;
493
+
}
494
+
495
+
static int rz_mtu3_count_enable_write(struct counter_device *counter,
496
+
struct counter_count *count, u8 enable)
497
+
{
498
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
499
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
500
+
int ret = 0;
501
+
502
+
if (enable) {
503
+
pm_runtime_get_sync(ch->dev);
504
+
mutex_lock(&priv->lock);
505
+
ret = rz_mtu3_initialize_counter(counter, count->id);
506
+
if (ret == 0)
507
+
priv->count_is_enabled[count->id] = true;
508
+
mutex_unlock(&priv->lock);
509
+
} else {
510
+
mutex_lock(&priv->lock);
511
+
rz_mtu3_terminate_counter(counter, count->id);
512
+
priv->count_is_enabled[count->id] = false;
513
+
mutex_unlock(&priv->lock);
514
+
pm_runtime_put(ch->dev);
515
+
}
516
+
517
+
return ret;
518
+
}
519
+
520
+
static int rz_mtu3_lock_if_ch0_is_enabled(struct rz_mtu3_cnt *const priv)
521
+
{
522
+
mutex_lock(&priv->lock);
523
+
if (priv->ch->is_busy && !(priv->count_is_enabled[RZ_MTU3_16_BIT_MTU1_CH] ||
524
+
priv->count_is_enabled[RZ_MTU3_32_BIT_CH])) {
525
+
mutex_unlock(&priv->lock);
526
+
return -EINVAL;
527
+
}
528
+
529
+
return 0;
530
+
}
531
+
532
+
static int rz_mtu3_cascade_counts_enable_get(struct counter_device *counter,
533
+
u8 *cascade_enable)
534
+
{
535
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
536
+
unsigned long tmdr;
537
+
int ret;
538
+
539
+
ret = rz_mtu3_lock_if_ch0_is_enabled(priv);
540
+
if (ret)
541
+
return ret;
542
+
543
+
pm_runtime_get_sync(priv->ch->dev);
544
+
tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
545
+
pm_runtime_put(priv->ch->dev);
546
+
*cascade_enable = test_bit(RZ_MTU3_TMDR3_LWA, &tmdr);
547
+
mutex_unlock(&priv->lock);
548
+
549
+
return 0;
550
+
}
551
+
552
+
static int rz_mtu3_cascade_counts_enable_set(struct counter_device *counter,
553
+
u8 cascade_enable)
554
+
{
555
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
556
+
int ret;
557
+
558
+
ret = rz_mtu3_lock_if_ch0_is_enabled(priv);
559
+
if (ret)
560
+
return ret;
561
+
562
+
pm_runtime_get_sync(priv->ch->dev);
563
+
rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3,
564
+
RZ_MTU3_TMDR3_LWA, cascade_enable);
565
+
pm_runtime_put(priv->ch->dev);
566
+
mutex_unlock(&priv->lock);
567
+
568
+
return 0;
569
+
}
570
+
571
+
static int rz_mtu3_ext_input_phase_clock_select_get(struct counter_device *counter,
572
+
u32 *ext_input_phase_clock_select)
573
+
{
574
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
575
+
unsigned long tmdr;
576
+
int ret;
577
+
578
+
ret = rz_mtu3_lock_if_ch0_is_enabled(priv);
579
+
if (ret)
580
+
return ret;
581
+
582
+
pm_runtime_get_sync(priv->ch->dev);
583
+
tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
584
+
pm_runtime_put(priv->ch->dev);
585
+
*ext_input_phase_clock_select = test_bit(RZ_MTU3_TMDR3_PHCKSEL, &tmdr);
586
+
mutex_unlock(&priv->lock);
587
+
588
+
return 0;
589
+
}
590
+
591
+
static int rz_mtu3_ext_input_phase_clock_select_set(struct counter_device *counter,
592
+
u32 ext_input_phase_clock_select)
593
+
{
594
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
595
+
int ret;
596
+
597
+
ret = rz_mtu3_lock_if_ch0_is_enabled(priv);
598
+
if (ret)
599
+
return ret;
600
+
601
+
pm_runtime_get_sync(priv->ch->dev);
602
+
rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3,
603
+
RZ_MTU3_TMDR3_PHCKSEL,
604
+
ext_input_phase_clock_select);
605
+
pm_runtime_put(priv->ch->dev);
606
+
mutex_unlock(&priv->lock);
607
+
608
+
return 0;
609
+
}
610
+
611
+
static struct counter_comp rz_mtu3_count_ext[] = {
612
+
COUNTER_COMP_DIRECTION(rz_mtu3_count_direction_read),
613
+
COUNTER_COMP_ENABLE(rz_mtu3_count_enable_read,
614
+
rz_mtu3_count_enable_write),
615
+
COUNTER_COMP_CEILING(rz_mtu3_count_ceiling_read,
616
+
rz_mtu3_count_ceiling_write),
617
+
};
618
+
619
+
static const enum counter_synapse_action rz_mtu3_synapse_actions[] = {
620
+
COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
621
+
COUNTER_SYNAPSE_ACTION_RISING_EDGE,
622
+
COUNTER_SYNAPSE_ACTION_NONE,
623
+
};
624
+
625
+
static int rz_mtu3_action_read(struct counter_device *counter,
626
+
struct counter_count *count,
627
+
struct counter_synapse *synapse,
628
+
enum counter_synapse_action *action)
629
+
{
630
+
const bool is_signal_ab = (synapse->signal->id == SIGNAL_A_ID) ||
631
+
(synapse->signal->id == SIGNAL_B_ID);
632
+
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
633
+
struct rz_mtu3_cnt *const priv = counter_priv(counter);
634
+
enum counter_function function;
635
+
bool mtclkc_mtclkd;
636
+
unsigned long tmdr;
637
+
int ret;
638
+
639
+
ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id);
640
+
if (ret)
641
+
return ret;
642
+
643
+
ret = rz_mtu3_count_function_read_helper(ch, priv, &function);
644
+
if (ret) {
645
+
mutex_unlock(&priv->lock);
646
+
return ret;
647
+
}
648
+
649
+
/* Default action mode */
650
+
*action = COUNTER_SYNAPSE_ACTION_NONE;
651
+
652
+
if (count->id != RZ_MTU3_16_BIT_MTU1_CH) {
653
+
tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
654
+
mtclkc_mtclkd = test_bit(RZ_MTU3_TMDR3_PHCKSEL, &tmdr);
655
+
if ((mtclkc_mtclkd && is_signal_ab) ||
656
+
(!mtclkc_mtclkd && !is_signal_ab)) {
657
+
mutex_unlock(&priv->lock);
658
+
return 0;
659
+
}
660
+
}
661
+
662
+
switch (function) {
663
+
case COUNTER_FUNCTION_PULSE_DIRECTION:
664
+
/*
665
+
* Rising edges on signal A (signal C) updates the respective
666
+
* count. The input level of signal B (signal D) determines
667
+
* direction.
668
+
*/
669
+
if (synapse->signal->id == SIGNAL_A_ID ||
670
+
synapse->signal->id == SIGNAL_C_ID)
671
+
*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
672
+
break;
673
+
case COUNTER_FUNCTION_QUADRATURE_X2_B:
674
+
/*
675
+
* Any state transition on quadrature pair signal B (signal D)
676
+
* updates the respective count.
677
+
*/
678
+
if (synapse->signal->id == SIGNAL_B_ID ||
679
+
synapse->signal->id == SIGNAL_D_ID)
680
+
*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
681
+
break;
682
+
case COUNTER_FUNCTION_QUADRATURE_X4:
683
+
/* counts up/down on both edges of A (C) and B (D) signal */
684
+
*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
685
+
break;
686
+
default:
687
+
/* should never reach this path */
688
+
mutex_unlock(&priv->lock);
689
+
return -EINVAL;
690
+
}
691
+
692
+
mutex_unlock(&priv->lock);
693
+
694
+
return 0;
695
+
}
696
+
697
+
static const struct counter_ops rz_mtu3_cnt_ops = {
698
+
.count_read = rz_mtu3_count_read,
699
+
.count_write = rz_mtu3_count_write,
700
+
.function_read = rz_mtu3_count_function_read,
701
+
.function_write = rz_mtu3_count_function_write,
702
+
.action_read = rz_mtu3_action_read,
703
+
};
704
+
705
+
#define RZ_MTU3_PHASE_SIGNAL(_id, _name) { \
706
+
.id = (_id), \
707
+
.name = (_name), \
708
+
}
709
+
710
+
static struct counter_signal rz_mtu3_signals[] = {
711
+
RZ_MTU3_PHASE_SIGNAL(SIGNAL_A_ID, "MTU1 MTCLKA"),
712
+
RZ_MTU3_PHASE_SIGNAL(SIGNAL_B_ID, "MTU1 MTCLKB"),
713
+
RZ_MTU3_PHASE_SIGNAL(SIGNAL_C_ID, "MTU2 MTCLKC"),
714
+
RZ_MTU3_PHASE_SIGNAL(SIGNAL_D_ID, "MTU2 MTCLKD"),
715
+
};
716
+
717
+
static struct counter_synapse rz_mtu3_mtu1_count_synapses[] = {
718
+
{
719
+
.actions_list = rz_mtu3_synapse_actions,
720
+
.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
721
+
.signal = rz_mtu3_signals,
722
+
},
723
+
{
724
+
.actions_list = rz_mtu3_synapse_actions,
725
+
.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
726
+
.signal = rz_mtu3_signals + 1,
727
+
}
728
+
};
729
+
730
+
static struct counter_synapse rz_mtu3_mtu2_count_synapses[] = {
731
+
{
732
+
.actions_list = rz_mtu3_synapse_actions,
733
+
.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
734
+
.signal = rz_mtu3_signals,
735
+
},
736
+
{
737
+
.actions_list = rz_mtu3_synapse_actions,
738
+
.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
739
+
.signal = rz_mtu3_signals + 1,
740
+
},
741
+
{
742
+
.actions_list = rz_mtu3_synapse_actions,
743
+
.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
744
+
.signal = rz_mtu3_signals + 2,
745
+
},
746
+
{
747
+
.actions_list = rz_mtu3_synapse_actions,
748
+
.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
749
+
.signal = rz_mtu3_signals + 3,
750
+
}
751
+
};
752
+
753
+
static struct counter_count rz_mtu3_counts[] = {
754
+
{
755
+
.id = RZ_MTU3_16_BIT_MTU1_CH,
756
+
.name = "Channel 1 Count",
757
+
.functions_list = rz_mtu3_count_functions,
758
+
.num_functions = ARRAY_SIZE(rz_mtu3_count_functions),
759
+
.synapses = rz_mtu3_mtu1_count_synapses,
760
+
.num_synapses = ARRAY_SIZE(rz_mtu3_mtu1_count_synapses),
761
+
.ext = rz_mtu3_count_ext,
762
+
.num_ext = ARRAY_SIZE(rz_mtu3_count_ext),
763
+
},
764
+
{
765
+
.id = RZ_MTU3_16_BIT_MTU2_CH,
766
+
.name = "Channel 2 Count",
767
+
.functions_list = rz_mtu3_count_functions,
768
+
.num_functions = ARRAY_SIZE(rz_mtu3_count_functions),
769
+
.synapses = rz_mtu3_mtu2_count_synapses,
770
+
.num_synapses = ARRAY_SIZE(rz_mtu3_mtu2_count_synapses),
771
+
.ext = rz_mtu3_count_ext,
772
+
.num_ext = ARRAY_SIZE(rz_mtu3_count_ext),
773
+
},
774
+
{
775
+
.id = RZ_MTU3_32_BIT_CH,
776
+
.name = "Channel 1 and 2 (cascaded) Count",
777
+
.functions_list = rz_mtu3_count_functions,
778
+
.num_functions = ARRAY_SIZE(rz_mtu3_count_functions),
779
+
.synapses = rz_mtu3_mtu2_count_synapses,
780
+
.num_synapses = ARRAY_SIZE(rz_mtu3_mtu2_count_synapses),
781
+
.ext = rz_mtu3_count_ext,
782
+
.num_ext = ARRAY_SIZE(rz_mtu3_count_ext),
783
+
}
784
+
};
785
+
786
+
static const char *const rz_mtu3_ext_input_phase_clock_select[] = {
787
+
"MTCLKA-MTCLKB",
788
+
"MTCLKC-MTCLKD",
789
+
};
790
+
791
+
static DEFINE_COUNTER_ENUM(rz_mtu3_ext_input_phase_clock_select_enum,
792
+
rz_mtu3_ext_input_phase_clock_select);
793
+
794
+
static struct counter_comp rz_mtu3_device_ext[] = {
795
+
COUNTER_COMP_DEVICE_BOOL("cascade_counts_enable",
796
+
rz_mtu3_cascade_counts_enable_get,
797
+
rz_mtu3_cascade_counts_enable_set),
798
+
COUNTER_COMP_DEVICE_ENUM("external_input_phase_clock_select",
799
+
rz_mtu3_ext_input_phase_clock_select_get,
800
+
rz_mtu3_ext_input_phase_clock_select_set,
801
+
rz_mtu3_ext_input_phase_clock_select_enum),
802
+
};
803
+
804
+
static int rz_mtu3_cnt_pm_runtime_suspend(struct device *dev)
805
+
{
806
+
struct clk *const clk = dev_get_drvdata(dev);
807
+
808
+
clk_disable_unprepare(clk);
809
+
810
+
return 0;
811
+
}
812
+
813
+
static int rz_mtu3_cnt_pm_runtime_resume(struct device *dev)
814
+
{
815
+
struct clk *const clk = dev_get_drvdata(dev);
816
+
817
+
clk_prepare_enable(clk);
818
+
819
+
return 0;
820
+
}
821
+
822
+
static DEFINE_RUNTIME_DEV_PM_OPS(rz_mtu3_cnt_pm_ops,
823
+
rz_mtu3_cnt_pm_runtime_suspend,
824
+
rz_mtu3_cnt_pm_runtime_resume, NULL);
825
+
826
+
static void rz_mtu3_cnt_pm_disable(void *data)
827
+
{
828
+
struct device *dev = data;
829
+
830
+
pm_runtime_disable(dev);
831
+
pm_runtime_set_suspended(dev);
832
+
}
833
+
834
+
static int rz_mtu3_cnt_probe(struct platform_device *pdev)
835
+
{
836
+
struct rz_mtu3 *ddata = dev_get_drvdata(pdev->dev.parent);
837
+
struct device *dev = &pdev->dev;
838
+
struct counter_device *counter;
839
+
struct rz_mtu3_channel *ch;
840
+
struct rz_mtu3_cnt *priv;
841
+
unsigned int i;
842
+
int ret;
843
+
844
+
counter = devm_counter_alloc(dev, sizeof(*priv));
845
+
if (!counter)
846
+
return -ENOMEM;
847
+
848
+
priv = counter_priv(counter);
849
+
priv->clk = ddata->clk;
850
+
priv->mtu_32bit_max = U32_MAX;
851
+
priv->ch = &ddata->channels[RZ_MTU3_CHAN_1];
852
+
ch = &priv->ch[0];
853
+
for (i = 0; i < RZ_MTU3_MAX_HW_CNTR_CHANNELS; i++) {
854
+
ch->dev = dev;
855
+
priv->mtu_16bit_max[i] = U16_MAX;
856
+
ch++;
857
+
}
858
+
859
+
mutex_init(&priv->lock);
860
+
platform_set_drvdata(pdev, priv->clk);
861
+
clk_prepare_enable(priv->clk);
862
+
pm_runtime_set_active(&pdev->dev);
863
+
pm_runtime_enable(&pdev->dev);
864
+
ret = devm_add_action_or_reset(&pdev->dev, rz_mtu3_cnt_pm_disable, dev);
865
+
if (ret < 0)
866
+
goto disable_clock;
867
+
868
+
counter->name = dev_name(dev);
869
+
counter->parent = dev;
870
+
counter->ops = &rz_mtu3_cnt_ops;
871
+
counter->counts = rz_mtu3_counts;
872
+
counter->num_counts = ARRAY_SIZE(rz_mtu3_counts);
873
+
counter->signals = rz_mtu3_signals;
874
+
counter->num_signals = ARRAY_SIZE(rz_mtu3_signals);
875
+
counter->ext = rz_mtu3_device_ext;
876
+
counter->num_ext = ARRAY_SIZE(rz_mtu3_device_ext);
877
+
878
+
/* Register Counter device */
879
+
ret = devm_counter_add(dev, counter);
880
+
if (ret < 0) {
881
+
dev_err_probe(dev, ret, "Failed to add counter\n");
882
+
goto disable_clock;
883
+
}
884
+
885
+
return 0;
886
+
887
+
disable_clock:
888
+
clk_disable_unprepare(priv->clk);
889
+
890
+
return ret;
891
+
}
892
+
893
+
static struct platform_driver rz_mtu3_cnt_driver = {
894
+
.probe = rz_mtu3_cnt_probe,
895
+
.driver = {
896
+
.name = "rz-mtu3-counter",
897
+
.pm = pm_ptr(&rz_mtu3_cnt_pm_ops),
898
+
},
899
+
};
900
+
module_platform_driver(rz_mtu3_cnt_driver);
901
+
902
+
MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
903
+
MODULE_ALIAS("platform:rz-mtu3-counter");
904
+
MODULE_DESCRIPTION("Renesas RZ/G2L MTU3a counter driver");
905
+
MODULE_LICENSE("GPL");
906
+
MODULE_IMPORT_NS(COUNTER);
+12
drivers/gpio/Kconfig
+12
drivers/gpio/Kconfig
···
1292
1292
This driver can also be built as a module. If so, the module will be
1293
1293
called gpio-kempld.
1294
1294
1295
+
config GPIO_LJCA
1296
+
tristate "INTEL La Jolla Cove Adapter GPIO support"
1297
+
depends on MFD_LJCA
1298
+
select GPIOLIB_IRQCHIP
1299
+
default MFD_LJCA
1300
+
help
1301
+
Select this option to enable GPIO driver for the INTEL
1302
+
La Jolla Cove Adapter (LJCA) board.
1303
+
1304
+
This driver can also be built as a module. If so, the module
1305
+
will be called gpio-ljca.
1306
+
1295
1307
config GPIO_LP3943
1296
1308
tristate "TI/National Semiconductor LP3943 GPIO expander"
1297
1309
depends on MFD_LP3943
+1
drivers/gpio/Makefile
+1
drivers/gpio/Makefile
···
79
79
obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
80
80
obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o
81
81
obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o
82
+
obj-$(CONFIG_GPIO_LJCA) += gpio-ljca.o
82
83
obj-$(CONFIG_GPIO_LOGICVC) += gpio-logicvc.o
83
84
obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o
84
85
obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o
+454
drivers/gpio/gpio-ljca.c
+454
drivers/gpio/gpio-ljca.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Intel La Jolla Cove Adapter USB-GPIO driver
4
+
*
5
+
* Copyright (c) 2023, Intel Corporation.
6
+
*/
7
+
8
+
#include <linux/acpi.h>
9
+
#include <linux/bitfield.h>
10
+
#include <linux/bitops.h>
11
+
#include <linux/dev_printk.h>
12
+
#include <linux/gpio/driver.h>
13
+
#include <linux/irq.h>
14
+
#include <linux/kernel.h>
15
+
#include <linux/kref.h>
16
+
#include <linux/mfd/ljca.h>
17
+
#include <linux/module.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/slab.h>
20
+
#include <linux/types.h>
21
+
22
+
/* GPIO commands */
23
+
#define LJCA_GPIO_CONFIG 1
24
+
#define LJCA_GPIO_READ 2
25
+
#define LJCA_GPIO_WRITE 3
26
+
#define LJCA_GPIO_INT_EVENT 4
27
+
#define LJCA_GPIO_INT_MASK 5
28
+
#define LJCA_GPIO_INT_UNMASK 6
29
+
30
+
#define LJCA_GPIO_CONF_DISABLE BIT(0)
31
+
#define LJCA_GPIO_CONF_INPUT BIT(1)
32
+
#define LJCA_GPIO_CONF_OUTPUT BIT(2)
33
+
#define LJCA_GPIO_CONF_PULLUP BIT(3)
34
+
#define LJCA_GPIO_CONF_PULLDOWN BIT(4)
35
+
#define LJCA_GPIO_CONF_DEFAULT BIT(5)
36
+
#define LJCA_GPIO_CONF_INTERRUPT BIT(6)
37
+
#define LJCA_GPIO_INT_TYPE BIT(7)
38
+
39
+
#define LJCA_GPIO_CONF_EDGE FIELD_PREP(LJCA_GPIO_INT_TYPE, 1)
40
+
#define LJCA_GPIO_CONF_LEVEL FIELD_PREP(LJCA_GPIO_INT_TYPE, 0)
41
+
42
+
/* Intentional overlap with PULLUP / PULLDOWN */
43
+
#define LJCA_GPIO_CONF_SET BIT(3)
44
+
#define LJCA_GPIO_CONF_CLR BIT(4)
45
+
46
+
struct gpio_op {
47
+
u8 index;
48
+
u8 value;
49
+
} __packed;
50
+
51
+
struct gpio_packet {
52
+
u8 num;
53
+
struct gpio_op item[];
54
+
} __packed;
55
+
56
+
#define LJCA_GPIO_BUF_SIZE 60
57
+
struct ljca_gpio_dev {
58
+
struct platform_device *pdev;
59
+
struct gpio_chip gc;
60
+
struct ljca_gpio_info *gpio_info;
61
+
DECLARE_BITMAP(unmasked_irqs, LJCA_MAX_GPIO_NUM);
62
+
DECLARE_BITMAP(enabled_irqs, LJCA_MAX_GPIO_NUM);
63
+
DECLARE_BITMAP(reenable_irqs, LJCA_MAX_GPIO_NUM);
64
+
u8 *connect_mode;
65
+
/* mutex to protect irq bus */
66
+
struct mutex irq_lock;
67
+
struct work_struct work;
68
+
/* lock to protect package transfer to Hardware */
69
+
struct mutex trans_lock;
70
+
71
+
u8 obuf[LJCA_GPIO_BUF_SIZE];
72
+
u8 ibuf[LJCA_GPIO_BUF_SIZE];
73
+
};
74
+
75
+
static int gpio_config(struct ljca_gpio_dev *ljca_gpio, u8 gpio_id, u8 config)
76
+
{
77
+
struct gpio_packet *packet = (struct gpio_packet *)ljca_gpio->obuf;
78
+
int ret;
79
+
80
+
mutex_lock(&ljca_gpio->trans_lock);
81
+
packet->item[0].index = gpio_id;
82
+
packet->item[0].value = config | ljca_gpio->connect_mode[gpio_id];
83
+
packet->num = 1;
84
+
85
+
ret = ljca_transfer(ljca_gpio->gpio_info->ljca, LJCA_GPIO_CONFIG, packet,
86
+
struct_size(packet, item, packet->num), NULL, NULL);
87
+
mutex_unlock(&ljca_gpio->trans_lock);
88
+
return ret;
89
+
}
90
+
91
+
static int ljca_gpio_read(struct ljca_gpio_dev *ljca_gpio, u8 gpio_id)
92
+
{
93
+
struct gpio_packet *packet = (struct gpio_packet *)ljca_gpio->obuf;
94
+
struct gpio_packet *ack_packet = (struct gpio_packet *)ljca_gpio->ibuf;
95
+
unsigned int ibuf_len = LJCA_GPIO_BUF_SIZE;
96
+
int ret;
97
+
98
+
mutex_lock(&ljca_gpio->trans_lock);
99
+
packet->num = 1;
100
+
packet->item[0].index = gpio_id;
101
+
ret = ljca_transfer(ljca_gpio->gpio_info->ljca, LJCA_GPIO_READ, packet,
102
+
struct_size(packet, item, packet->num), ljca_gpio->ibuf, &ibuf_len);
103
+
if (ret)
104
+
goto out_unlock;
105
+
106
+
if (!ibuf_len || ack_packet->num != packet->num) {
107
+
dev_err(&ljca_gpio->pdev->dev, "failed gpio_id:%u %u", gpio_id, ack_packet->num);
108
+
ret = -EIO;
109
+
}
110
+
111
+
out_unlock:
112
+
mutex_unlock(&ljca_gpio->trans_lock);
113
+
if (ret)
114
+
return ret;
115
+
return ack_packet->item[0].value > 0;
116
+
}
117
+
118
+
static int ljca_gpio_write(struct ljca_gpio_dev *ljca_gpio, u8 gpio_id,
119
+
int value)
120
+
{
121
+
struct gpio_packet *packet = (struct gpio_packet *)ljca_gpio->obuf;
122
+
int ret;
123
+
124
+
mutex_lock(&ljca_gpio->trans_lock);
125
+
packet->num = 1;
126
+
packet->item[0].index = gpio_id;
127
+
packet->item[0].value = value & 1;
128
+
129
+
ret = ljca_transfer(ljca_gpio->gpio_info->ljca, LJCA_GPIO_WRITE, packet,
130
+
struct_size(packet, item, packet->num), NULL, NULL);
131
+
mutex_unlock(&ljca_gpio->trans_lock);
132
+
return ret;
133
+
}
134
+
135
+
static int ljca_gpio_get_value(struct gpio_chip *chip, unsigned int offset)
136
+
{
137
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(chip);
138
+
139
+
return ljca_gpio_read(ljca_gpio, offset);
140
+
}
141
+
142
+
static void ljca_gpio_set_value(struct gpio_chip *chip, unsigned int offset,
143
+
int val)
144
+
{
145
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(chip);
146
+
int ret;
147
+
148
+
ret = ljca_gpio_write(ljca_gpio, offset, val);
149
+
if (ret)
150
+
dev_err(chip->parent, "offset:%u val:%d set value failed %d\n", offset, val, ret);
151
+
}
152
+
153
+
static int ljca_gpio_direction_input(struct gpio_chip *chip,
154
+
unsigned int offset)
155
+
{
156
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(chip);
157
+
u8 config = LJCA_GPIO_CONF_INPUT | LJCA_GPIO_CONF_CLR;
158
+
159
+
return gpio_config(ljca_gpio, offset, config);
160
+
}
161
+
162
+
static int ljca_gpio_direction_output(struct gpio_chip *chip,
163
+
unsigned int offset, int val)
164
+
{
165
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(chip);
166
+
u8 config = LJCA_GPIO_CONF_OUTPUT | LJCA_GPIO_CONF_CLR;
167
+
int ret;
168
+
169
+
ret = gpio_config(ljca_gpio, offset, config);
170
+
if (ret)
171
+
return ret;
172
+
173
+
ljca_gpio_set_value(chip, offset, val);
174
+
return 0;
175
+
}
176
+
177
+
static int ljca_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
178
+
unsigned long config)
179
+
{
180
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(chip);
181
+
182
+
ljca_gpio->connect_mode[offset] = 0;
183
+
switch (pinconf_to_config_param(config)) {
184
+
case PIN_CONFIG_BIAS_PULL_UP:
185
+
ljca_gpio->connect_mode[offset] |= LJCA_GPIO_CONF_PULLUP;
186
+
break;
187
+
case PIN_CONFIG_BIAS_PULL_DOWN:
188
+
ljca_gpio->connect_mode[offset] |= LJCA_GPIO_CONF_PULLDOWN;
189
+
break;
190
+
case PIN_CONFIG_DRIVE_PUSH_PULL:
191
+
case PIN_CONFIG_PERSIST_STATE:
192
+
break;
193
+
default:
194
+
return -ENOTSUPP;
195
+
}
196
+
197
+
return 0;
198
+
}
199
+
200
+
static int ljca_gpio_init_valid_mask(struct gpio_chip *chip, unsigned long *valid_mask,
201
+
unsigned int ngpios)
202
+
{
203
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(chip);
204
+
205
+
WARN_ON_ONCE(ngpios != ljca_gpio->gpio_info->num);
206
+
bitmap_copy(valid_mask, ljca_gpio->gpio_info->valid_pin_map, ngpios);
207
+
208
+
return 0;
209
+
}
210
+
211
+
static void ljca_gpio_irq_init_valid_mask(struct gpio_chip *chip, unsigned long *valid_mask,
212
+
unsigned int ngpios)
213
+
{
214
+
ljca_gpio_init_valid_mask(chip, valid_mask, ngpios);
215
+
}
216
+
217
+
static int ljca_enable_irq(struct ljca_gpio_dev *ljca_gpio, int gpio_id, bool enable)
218
+
{
219
+
struct gpio_packet *packet = (struct gpio_packet *)ljca_gpio->obuf;
220
+
int ret;
221
+
222
+
mutex_lock(&ljca_gpio->trans_lock);
223
+
packet->num = 1;
224
+
packet->item[0].index = gpio_id;
225
+
packet->item[0].value = 0;
226
+
227
+
ret = ljca_transfer(ljca_gpio->gpio_info->ljca,
228
+
enable ? LJCA_GPIO_INT_UNMASK : LJCA_GPIO_INT_MASK, packet,
229
+
struct_size(packet, item, packet->num), NULL, NULL);
230
+
mutex_unlock(&ljca_gpio->trans_lock);
231
+
return ret;
232
+
}
233
+
234
+
static void ljca_gpio_async(struct work_struct *work)
235
+
{
236
+
struct ljca_gpio_dev *ljca_gpio = container_of(work, struct ljca_gpio_dev, work);
237
+
int gpio_id;
238
+
int unmasked;
239
+
240
+
for_each_set_bit(gpio_id, ljca_gpio->reenable_irqs, ljca_gpio->gc.ngpio) {
241
+
clear_bit(gpio_id, ljca_gpio->reenable_irqs);
242
+
unmasked = test_bit(gpio_id, ljca_gpio->unmasked_irqs);
243
+
if (unmasked)
244
+
ljca_enable_irq(ljca_gpio, gpio_id, true);
245
+
}
246
+
}
247
+
248
+
static void ljca_gpio_event_cb(void *context, u8 cmd, const void *evt_data, int len)
249
+
{
250
+
const struct gpio_packet *packet = evt_data;
251
+
struct ljca_gpio_dev *ljca_gpio = context;
252
+
int i;
253
+
int irq;
254
+
255
+
if (cmd != LJCA_GPIO_INT_EVENT)
256
+
return;
257
+
258
+
for (i = 0; i < packet->num; i++) {
259
+
irq = irq_find_mapping(ljca_gpio->gc.irq.domain, packet->item[i].index);
260
+
if (!irq) {
261
+
dev_err(ljca_gpio->gc.parent, "gpio_id %u does not mapped to IRQ yet\n",
262
+
packet->item[i].index);
263
+
return;
264
+
}
265
+
266
+
generic_handle_domain_irq(ljca_gpio->gc.irq.domain, irq);
267
+
set_bit(packet->item[i].index, ljca_gpio->reenable_irqs);
268
+
}
269
+
270
+
schedule_work(&ljca_gpio->work);
271
+
}
272
+
273
+
static void ljca_irq_unmask(struct irq_data *irqd)
274
+
{
275
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
276
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(gc);
277
+
int gpio_id = irqd_to_hwirq(irqd);
278
+
279
+
gpiochip_enable_irq(gc, gpio_id);
280
+
set_bit(gpio_id, ljca_gpio->unmasked_irqs);
281
+
}
282
+
283
+
static void ljca_irq_mask(struct irq_data *irqd)
284
+
{
285
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
286
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(gc);
287
+
int gpio_id = irqd_to_hwirq(irqd);
288
+
289
+
clear_bit(gpio_id, ljca_gpio->unmasked_irqs);
290
+
gpiochip_disable_irq(gc, gpio_id);
291
+
}
292
+
293
+
static int ljca_irq_set_type(struct irq_data *irqd, unsigned int type)
294
+
{
295
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
296
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(gc);
297
+
int gpio_id = irqd_to_hwirq(irqd);
298
+
299
+
ljca_gpio->connect_mode[gpio_id] = LJCA_GPIO_CONF_INTERRUPT;
300
+
switch (type) {
301
+
case IRQ_TYPE_LEVEL_HIGH:
302
+
ljca_gpio->connect_mode[gpio_id] |= (LJCA_GPIO_CONF_LEVEL | LJCA_GPIO_CONF_PULLUP);
303
+
break;
304
+
case IRQ_TYPE_LEVEL_LOW:
305
+
ljca_gpio->connect_mode[gpio_id] |= (LJCA_GPIO_CONF_LEVEL | LJCA_GPIO_CONF_PULLDOWN);
306
+
break;
307
+
case IRQ_TYPE_EDGE_BOTH:
308
+
break;
309
+
case IRQ_TYPE_EDGE_RISING:
310
+
ljca_gpio->connect_mode[gpio_id] |= (LJCA_GPIO_CONF_EDGE | LJCA_GPIO_CONF_PULLUP);
311
+
break;
312
+
case IRQ_TYPE_EDGE_FALLING:
313
+
ljca_gpio->connect_mode[gpio_id] |= (LJCA_GPIO_CONF_EDGE | LJCA_GPIO_CONF_PULLDOWN);
314
+
break;
315
+
default:
316
+
return -EINVAL;
317
+
}
318
+
319
+
return 0;
320
+
}
321
+
322
+
static void ljca_irq_bus_lock(struct irq_data *irqd)
323
+
{
324
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
325
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(gc);
326
+
327
+
mutex_lock(&ljca_gpio->irq_lock);
328
+
}
329
+
330
+
static void ljca_irq_bus_unlock(struct irq_data *irqd)
331
+
{
332
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
333
+
struct ljca_gpio_dev *ljca_gpio = gpiochip_get_data(gc);
334
+
int gpio_id = irqd_to_hwirq(irqd);
335
+
int enabled;
336
+
int unmasked;
337
+
338
+
enabled = test_bit(gpio_id, ljca_gpio->enabled_irqs);
339
+
unmasked = test_bit(gpio_id, ljca_gpio->unmasked_irqs);
340
+
341
+
if (enabled != unmasked) {
342
+
if (unmasked) {
343
+
gpio_config(ljca_gpio, gpio_id, 0);
344
+
ljca_enable_irq(ljca_gpio, gpio_id, true);
345
+
set_bit(gpio_id, ljca_gpio->enabled_irqs);
346
+
} else {
347
+
ljca_enable_irq(ljca_gpio, gpio_id, false);
348
+
clear_bit(gpio_id, ljca_gpio->enabled_irqs);
349
+
}
350
+
}
351
+
352
+
mutex_unlock(&ljca_gpio->irq_lock);
353
+
}
354
+
355
+
static const struct irq_chip ljca_gpio_irqchip = {
356
+
.name = "ljca-irq",
357
+
.irq_mask = ljca_irq_mask,
358
+
.irq_unmask = ljca_irq_unmask,
359
+
.irq_set_type = ljca_irq_set_type,
360
+
.irq_bus_lock = ljca_irq_bus_lock,
361
+
.irq_bus_sync_unlock = ljca_irq_bus_unlock,
362
+
.flags = IRQCHIP_IMMUTABLE,
363
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
364
+
};
365
+
366
+
static int ljca_gpio_probe(struct platform_device *pdev)
367
+
{
368
+
struct ljca_gpio_dev *ljca_gpio;
369
+
struct gpio_irq_chip *girq;
370
+
int ret;
371
+
372
+
ljca_gpio = devm_kzalloc(&pdev->dev, sizeof(*ljca_gpio), GFP_KERNEL);
373
+
if (!ljca_gpio)
374
+
return -ENOMEM;
375
+
376
+
ljca_gpio->gpio_info = dev_get_platdata(&pdev->dev);
377
+
ljca_gpio->connect_mode = devm_kcalloc(&pdev->dev, ljca_gpio->gpio_info->num,
378
+
sizeof(*ljca_gpio->connect_mode), GFP_KERNEL);
379
+
if (!ljca_gpio->connect_mode)
380
+
return -ENOMEM;
381
+
382
+
mutex_init(&ljca_gpio->irq_lock);
383
+
mutex_init(&ljca_gpio->trans_lock);
384
+
ljca_gpio->pdev = pdev;
385
+
ljca_gpio->gc.direction_input = ljca_gpio_direction_input;
386
+
ljca_gpio->gc.direction_output = ljca_gpio_direction_output;
387
+
ljca_gpio->gc.get = ljca_gpio_get_value;
388
+
ljca_gpio->gc.set = ljca_gpio_set_value;
389
+
ljca_gpio->gc.set_config = ljca_gpio_set_config;
390
+
ljca_gpio->gc.init_valid_mask = ljca_gpio_init_valid_mask;
391
+
ljca_gpio->gc.can_sleep = true;
392
+
ljca_gpio->gc.parent = &pdev->dev;
393
+
394
+
ljca_gpio->gc.base = -1;
395
+
ljca_gpio->gc.ngpio = ljca_gpio->gpio_info->num;
396
+
ljca_gpio->gc.label = ACPI_COMPANION(&pdev->dev) ?
397
+
acpi_dev_name(ACPI_COMPANION(&pdev->dev)) :
398
+
dev_name(&pdev->dev);
399
+
ljca_gpio->gc.owner = THIS_MODULE;
400
+
401
+
platform_set_drvdata(pdev, ljca_gpio);
402
+
ljca_register_event_cb(ljca_gpio->gpio_info->ljca, ljca_gpio_event_cb, ljca_gpio);
403
+
404
+
girq = &ljca_gpio->gc.irq;
405
+
gpio_irq_chip_set_chip(girq, &ljca_gpio_irqchip);
406
+
girq->parent_handler = NULL;
407
+
girq->num_parents = 0;
408
+
girq->parents = NULL;
409
+
girq->default_type = IRQ_TYPE_NONE;
410
+
girq->handler = handle_simple_irq;
411
+
girq->init_valid_mask = ljca_gpio_irq_init_valid_mask;
412
+
413
+
INIT_WORK(&ljca_gpio->work, ljca_gpio_async);
414
+
ret = gpiochip_add_data(&ljca_gpio->gc, ljca_gpio);
415
+
if (ret) {
416
+
ljca_unregister_event_cb(ljca_gpio->gpio_info->ljca);
417
+
mutex_destroy(&ljca_gpio->irq_lock);
418
+
mutex_destroy(&ljca_gpio->trans_lock);
419
+
}
420
+
421
+
return ret;
422
+
}
423
+
424
+
static int ljca_gpio_remove(struct platform_device *pdev)
425
+
{
426
+
struct ljca_gpio_dev *ljca_gpio = platform_get_drvdata(pdev);
427
+
428
+
gpiochip_remove(&ljca_gpio->gc);
429
+
ljca_unregister_event_cb(ljca_gpio->gpio_info->ljca);
430
+
mutex_destroy(&ljca_gpio->irq_lock);
431
+
mutex_destroy(&ljca_gpio->trans_lock);
432
+
return 0;
433
+
}
434
+
435
+
#define LJCA_GPIO_DRV_NAME "ljca-gpio"
436
+
static const struct platform_device_id ljca_gpio_id[] = {
437
+
{ LJCA_GPIO_DRV_NAME, 0 },
438
+
{ /* sentinel */ }
439
+
};
440
+
MODULE_DEVICE_TABLE(platform, ljca_gpio_id);
441
+
442
+
static struct platform_driver ljca_gpio_driver = {
443
+
.driver.name = LJCA_GPIO_DRV_NAME,
444
+
.probe = ljca_gpio_probe,
445
+
.remove = ljca_gpio_remove,
446
+
};
447
+
module_platform_driver(ljca_gpio_driver);
448
+
449
+
MODULE_AUTHOR("Ye Xiang <xiang.ye@intel.com>");
450
+
MODULE_AUTHOR("Wang Zhifeng <zhifeng.wang@intel.com>");
451
+
MODULE_AUTHOR("Zhang Lixu <lixu.zhang@intel.com>");
452
+
MODULE_DESCRIPTION("Intel La Jolla Cove Adapter USB-GPIO driver");
453
+
MODULE_LICENSE("GPL");
454
+
MODULE_IMPORT_NS(LJCA);
+1
-3
drivers/mfd/88pm860x-core.c
+1
-3
drivers/mfd/88pm860x-core.c
···
1117
1117
{
1118
1118
int ret;
1119
1119
1120
-
if (of_get_property(np, "marvell,88pm860x-irq-read-clr", NULL))
1121
-
pdata->irq_mode = 1;
1120
+
pdata->irq_mode = of_property_read_bool(np, "marvell,88pm860x-irq-read-clr");
1122
1121
ret = of_property_read_u32(np, "marvell,88pm860x-slave-addr",
1123
1122
&pdata->companion_addr);
1124
1123
if (ret) {
···
1275
1276
1276
1277
MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM860x");
1277
1278
MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com>");
1278
-
MODULE_LICENSE("GPL");
+20
-3
drivers/mfd/Kconfig
+20
-3
drivers/mfd/Kconfig
···
266
266
Support for the Cirrus Logic Madera platform audio SoC
267
267
core functionality controlled via SPI.
268
268
269
+
config MFD_MAX597X
270
+
tristate "Maxim 597x power switch and monitor"
271
+
depends on (I2C && OF)
272
+
select MFD_SIMPLE_MFD_I2C
273
+
help
274
+
This driver controls a Maxim 5970/5978 switch via I2C bus.
275
+
The MAX5970/5978 is a smart switch with no output regulation, but
276
+
fault protection and voltage and current monitoring capabilities.
277
+
Also it supports upto 4 indication leds.
278
+
269
279
config MFD_CS47L15
270
280
bool "Cirrus Logic CS47L15"
271
281
select PINCTRL_CS47L15
···
362
352
accessing the device as well as the I2C interface to the chip itself.
363
353
Additional drivers must be enabled in order to use the functionality
364
354
of the device.
365
-
366
-
This driver can be built as a module. If built as a module it will be
367
-
called "da9055"
368
355
369
356
config MFD_DA9062
370
357
tristate "Dialog Semiconductor DA9062/61 PMIC Support"
···
1314
1307
1315
1308
This driver provides common support for accessing the SC27xx PMICs,
1316
1309
and it also adds the irq_chip parts for handling the PMIC chip events.
1310
+
1311
+
config RZ_MTU3
1312
+
bool "Renesas RZ/G2L MTU3a core driver"
1313
+
depends on (ARCH_RZG2L && OF) || COMPILE_TEST
1314
+
help
1315
+
Select this option to enable Renesas RZ/G2L MTU3a core driver for
1316
+
the Multi-Function Timer Pulse Unit 3 (MTU3a) hardware available
1317
+
on SoCs from Renesas. The core driver shares the clk and channel
1318
+
register access for the other child devices like Counter, PWM,
1319
+
Clock Source, and Clock event.
1317
1320
1318
1321
config ABX500_CORE
1319
1322
bool "ST-Ericsson ABX500 Mixed Signal Circuit register functions"
+1
drivers/mfd/Makefile
+1
drivers/mfd/Makefile
···
174
174
obj-$(CONFIG_MFD_PCF50633) += pcf50633.o
175
175
obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o
176
176
obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
177
+
obj-$(CONFIG_RZ_MTU3) += rz-mtu3.o
177
178
obj-$(CONFIG_ABX500_CORE) += abx500-core.o
178
179
obj-$(CONFIG_MFD_DB8500_PRCMU) += db8500-prcmu.o
179
180
# ab8500-core need to come after db8500-prcmu (which provides the channel)
+1
drivers/mfd/arizona-i2c.c
+1
drivers/mfd/arizona-i2c.c
+1
drivers/mfd/arizona-spi.c
+1
drivers/mfd/arizona-spi.c
+1
-1
drivers/mfd/atc260x-i2c.c
+1
-1
drivers/mfd/atc260x-i2c.c
+1
-3
drivers/mfd/atmel-flexcom.c
+1
-3
drivers/mfd/atmel-flexcom.c
···
37
37
static int atmel_flexcom_probe(struct platform_device *pdev)
38
38
{
39
39
struct device_node *np = pdev->dev.of_node;
40
-
struct resource *res;
41
40
struct atmel_flexcom *ddata;
42
41
int err;
43
42
···
54
55
ddata->opmode > ATMEL_FLEXCOM_MODE_TWI)
55
56
return -EINVAL;
56
57
57
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
58
-
ddata->base = devm_ioremap_resource(&pdev->dev, res);
58
+
ddata->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
59
59
if (IS_ERR(ddata->base))
60
60
return PTR_ERR(ddata->base);
61
61
+1
-1
drivers/mfd/atmel-smc.c
+1
-1
drivers/mfd/atmel-smc.c
···
323
323
.timing_regs_offset = 0x700,
324
324
};
325
325
326
-
static const struct of_device_id atmel_smc_ids[] = {
326
+
static const struct of_device_id atmel_smc_ids[] __maybe_unused = {
327
327
{ .compatible = "atmel,at91sam9260-smc", .data = NULL },
328
328
{ .compatible = "atmel,sama5d3-smc", .data = &sama5d3_reg_layout },
329
329
{ .compatible = "atmel,sama5d2-smc", .data = &sama5d2_reg_layout },
+2
drivers/mfd/axp20x-i2c.c
+2
drivers/mfd/axp20x-i2c.c
···
65
65
{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
66
66
{ .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
67
67
{ .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },
68
+
{ .compatible = "x-powers,axp15060", .data = (void *)AXP15060_ID },
68
69
{ },
69
70
};
70
71
MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match);
···
79
78
{ "axp223", 0 },
80
79
{ "axp803", 0 },
81
80
{ "axp806", 0 },
81
+
{ "axp15060", 0 },
82
82
{ },
83
83
};
84
84
MODULE_DEVICE_TABLE(i2c, axp20x_i2c_id);
+108
drivers/mfd/axp20x.c
+108
drivers/mfd/axp20x.c
···
43
43
"AXP806",
44
44
"AXP809",
45
45
"AXP813",
46
+
"AXP15060",
46
47
};
47
48
48
49
static const struct regmap_range axp152_writeable_ranges[] = {
···
120
119
121
120
/* AXP288 ranges are shared with the AXP803, as they cover the same range */
122
121
static const struct regmap_range axp288_writeable_ranges[] = {
122
+
regmap_reg_range(AXP288_POWER_REASON, AXP288_POWER_REASON),
123
123
regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
124
124
regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
125
125
};
···
168
166
static const struct regmap_access_table axp806_volatile_table = {
169
167
.yes_ranges = axp806_volatile_ranges,
170
168
.n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
169
+
};
170
+
171
+
static const struct regmap_range axp15060_writeable_ranges[] = {
172
+
regmap_reg_range(AXP15060_PWR_OUT_CTRL1, AXP15060_DCDC_MODE_CTRL2),
173
+
regmap_reg_range(AXP15060_OUTPUT_MONITOR_DISCHARGE, AXP15060_CPUSLDO_V_CTRL),
174
+
regmap_reg_range(AXP15060_PWR_WAKEUP_CTRL, AXP15060_PWR_DISABLE_DOWN_SEQ),
175
+
regmap_reg_range(AXP15060_PEK_KEY, AXP15060_PEK_KEY),
176
+
regmap_reg_range(AXP15060_IRQ1_EN, AXP15060_IRQ2_EN),
177
+
regmap_reg_range(AXP15060_IRQ1_STATE, AXP15060_IRQ2_STATE),
178
+
};
179
+
180
+
static const struct regmap_range axp15060_volatile_ranges[] = {
181
+
regmap_reg_range(AXP15060_STARTUP_SRC, AXP15060_STARTUP_SRC),
182
+
regmap_reg_range(AXP15060_PWR_WAKEUP_CTRL, AXP15060_PWR_DISABLE_DOWN_SEQ),
183
+
regmap_reg_range(AXP15060_IRQ1_STATE, AXP15060_IRQ2_STATE),
184
+
};
185
+
186
+
static const struct regmap_access_table axp15060_writeable_table = {
187
+
.yes_ranges = axp15060_writeable_ranges,
188
+
.n_yes_ranges = ARRAY_SIZE(axp15060_writeable_ranges),
189
+
};
190
+
191
+
static const struct regmap_access_table axp15060_volatile_table = {
192
+
.yes_ranges = axp15060_volatile_ranges,
193
+
.n_yes_ranges = ARRAY_SIZE(axp15060_volatile_ranges),
171
194
};
172
195
173
196
static const struct resource axp152_pek_resources[] = {
···
263
236
DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
264
237
};
265
238
239
+
static const struct resource axp15060_pek_resources[] = {
240
+
DEFINE_RES_IRQ_NAMED(AXP15060_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
241
+
DEFINE_RES_IRQ_NAMED(AXP15060_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
242
+
};
243
+
266
244
static const struct regmap_config axp152_regmap_config = {
267
245
.reg_bits = 8,
268
246
.val_bits = 8,
···
310
278
.wr_table = &axp806_writeable_table,
311
279
.volatile_table = &axp806_volatile_table,
312
280
.max_register = AXP806_REG_ADDR_EXT,
281
+
.cache_type = REGCACHE_RBTREE,
282
+
};
283
+
284
+
static const struct regmap_config axp15060_regmap_config = {
285
+
.reg_bits = 8,
286
+
.val_bits = 8,
287
+
.wr_table = &axp15060_writeable_table,
288
+
.volatile_table = &axp15060_volatile_table,
289
+
.max_register = AXP15060_IRQ2_STATE,
313
290
.cache_type = REGCACHE_RBTREE,
314
291
};
315
292
···
543
502
INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
544
503
};
545
504
505
+
static const struct regmap_irq axp15060_regmap_irqs[] = {
506
+
INIT_REGMAP_IRQ(AXP15060, DIE_TEMP_HIGH_LV1, 0, 0),
507
+
INIT_REGMAP_IRQ(AXP15060, DIE_TEMP_HIGH_LV2, 0, 1),
508
+
INIT_REGMAP_IRQ(AXP15060, DCDC1_V_LOW, 0, 2),
509
+
INIT_REGMAP_IRQ(AXP15060, DCDC2_V_LOW, 0, 3),
510
+
INIT_REGMAP_IRQ(AXP15060, DCDC3_V_LOW, 0, 4),
511
+
INIT_REGMAP_IRQ(AXP15060, DCDC4_V_LOW, 0, 5),
512
+
INIT_REGMAP_IRQ(AXP15060, DCDC5_V_LOW, 0, 6),
513
+
INIT_REGMAP_IRQ(AXP15060, DCDC6_V_LOW, 0, 7),
514
+
INIT_REGMAP_IRQ(AXP15060, PEK_LONG, 1, 0),
515
+
INIT_REGMAP_IRQ(AXP15060, PEK_SHORT, 1, 1),
516
+
INIT_REGMAP_IRQ(AXP15060, GPIO1_INPUT, 1, 2),
517
+
INIT_REGMAP_IRQ(AXP15060, PEK_FAL_EDGE, 1, 3),
518
+
INIT_REGMAP_IRQ(AXP15060, PEK_RIS_EDGE, 1, 4),
519
+
INIT_REGMAP_IRQ(AXP15060, GPIO2_INPUT, 1, 5),
520
+
};
521
+
546
522
static const struct regmap_irq_chip axp152_regmap_irq_chip = {
547
523
.name = "axp152_irq_chip",
548
524
.status_base = AXP152_IRQ1_STATE,
···
637
579
.irqs = axp809_regmap_irqs,
638
580
.num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
639
581
.num_regs = 5,
582
+
};
583
+
584
+
static const struct regmap_irq_chip axp15060_regmap_irq_chip = {
585
+
.name = "axp15060",
586
+
.status_base = AXP15060_IRQ1_STATE,
587
+
.ack_base = AXP15060_IRQ1_STATE,
588
+
.unmask_base = AXP15060_IRQ1_EN,
589
+
.init_ack_masked = true,
590
+
.irqs = axp15060_regmap_irqs,
591
+
.num_irqs = ARRAY_SIZE(axp15060_regmap_irqs),
592
+
.num_regs = 2,
640
593
};
641
594
642
595
static const struct mfd_cell axp20x_cells[] = {
···
894
825
},
895
826
};
896
827
828
+
static const struct mfd_cell axp15060_cells[] = {
829
+
{
830
+
.name = "axp221-pek",
831
+
.num_resources = ARRAY_SIZE(axp15060_pek_resources),
832
+
.resources = axp15060_pek_resources,
833
+
}, {
834
+
.name = "axp20x-regulator",
835
+
},
836
+
};
837
+
838
+
/* For boards that don't have IRQ line connected to SOC. */
839
+
static const struct mfd_cell axp_regulator_only_cells[] = {
840
+
{
841
+
.name = "axp20x-regulator",
842
+
},
843
+
};
844
+
897
845
static int axp20x_power_off(struct sys_off_data *data)
898
846
{
899
847
struct axp20x_dev *axp20x = data->cb_data;
···
1019
933
* as the AXP803, rather than the AXP288.
1020
934
*/
1021
935
axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
936
+
break;
937
+
case AXP15060_ID:
938
+
/*
939
+
* Don't register the power key part if there is no interrupt
940
+
* line.
941
+
*
942
+
* Since most use cases of AXP PMICs are Allwinner SOCs, board
943
+
* designers follow Allwinner's reference design and connects
944
+
* IRQ line to SOC, there's no need for those variants to deal
945
+
* with cases that IRQ isn't connected. However, AXP15660 is
946
+
* used by some other vendors' SOCs that didn't connect IRQ
947
+
* line, we need to deal with this case.
948
+
*/
949
+
if (axp20x->irq > 0) {
950
+
axp20x->nr_cells = ARRAY_SIZE(axp15060_cells);
951
+
axp20x->cells = axp15060_cells;
952
+
} else {
953
+
axp20x->nr_cells = ARRAY_SIZE(axp_regulator_only_cells);
954
+
axp20x->cells = axp_regulator_only_cells;
955
+
}
956
+
axp20x->regmap_cfg = &axp15060_regmap_config;
957
+
axp20x->regmap_irq_chip = &axp15060_regmap_irq_chip;
1022
958
break;
1023
959
default:
1024
960
dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
+1
-2
drivers/mfd/bcm2835-pm.c
+1
-2
drivers/mfd/bcm2835-pm.c
···
28
28
static int bcm2835_pm_get_pdata(struct platform_device *pdev,
29
29
struct bcm2835_pm *pm)
30
30
{
31
-
if (of_find_property(pm->dev->of_node, "reg-names", NULL)) {
31
+
if (of_property_present(pm->dev->of_node, "reg-names")) {
32
32
struct resource *res;
33
33
34
34
pm->base = devm_platform_ioremap_resource_byname(pdev, "pm");
···
123
123
124
124
MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
125
125
MODULE_DESCRIPTION("Driver for Broadcom BCM2835 PM MFD");
126
-
MODULE_LICENSE("GPL");
-1
drivers/mfd/da903x.c
-1
drivers/mfd/da903x.c
-1
drivers/mfd/da9052-core.c
-1
drivers/mfd/da9052-core.c
-1
drivers/mfd/da9052-i2c.c
-1
drivers/mfd/da9052-i2c.c
-1
drivers/mfd/da9052-spi.c
-1
drivers/mfd/da9052-spi.c
-1
drivers/mfd/da9055-core.c
-1
drivers/mfd/da9055-core.c
-1
drivers/mfd/da9055-i2c.c
-1
drivers/mfd/da9055-i2c.c
+79
-97
drivers/mfd/da9062-core.c
+79
-97
drivers/mfd/da9062-core.c
···
181
181
DEFINE_RES_IRQ_NAMED(DA9061_IRQ_ONKEY, "ONKEY"),
182
182
};
183
183
184
-
static const struct mfd_cell da9061_devs[] = {
185
-
{
186
-
.name = "da9061-core",
187
-
.num_resources = ARRAY_SIZE(da9061_core_resources),
188
-
.resources = da9061_core_resources,
189
-
},
190
-
{
191
-
.name = "da9062-regulators",
192
-
.num_resources = ARRAY_SIZE(da9061_regulators_resources),
193
-
.resources = da9061_regulators_resources,
194
-
},
195
-
{
196
-
.name = "da9061-watchdog",
197
-
.num_resources = ARRAY_SIZE(da9061_wdt_resources),
198
-
.resources = da9061_wdt_resources,
199
-
.of_compatible = "dlg,da9061-watchdog",
200
-
},
201
-
{
202
-
.name = "da9061-thermal",
203
-
.num_resources = ARRAY_SIZE(da9061_thermal_resources),
204
-
.resources = da9061_thermal_resources,
205
-
.of_compatible = "dlg,da9061-thermal",
206
-
},
207
-
{
208
-
.name = "da9061-onkey",
209
-
.num_resources = ARRAY_SIZE(da9061_onkey_resources),
210
-
.resources = da9061_onkey_resources,
211
-
.of_compatible = "dlg,da9061-onkey",
212
-
},
184
+
static const struct mfd_cell da9061_devs_irq[] = {
185
+
MFD_CELL_OF("da9061-core", da9061_core_resources, NULL, 0, 0,
186
+
NULL),
187
+
MFD_CELL_OF("da9062-regulators", da9061_regulators_resources, NULL, 0, 0,
188
+
NULL),
189
+
MFD_CELL_OF("da9061-watchdog", da9061_wdt_resources, NULL, 0, 0,
190
+
"dlg,da9061-watchdog"),
191
+
MFD_CELL_OF("da9061-thermal", da9061_thermal_resources, NULL, 0, 0,
192
+
"dlg,da9061-thermal"),
193
+
MFD_CELL_OF("da9061-onkey", da9061_onkey_resources, NULL, 0, 0,
194
+
"dlg,da9061-onkey"),
195
+
};
196
+
197
+
static const struct mfd_cell da9061_devs_noirq[] = {
198
+
MFD_CELL_OF("da9061-core", NULL, NULL, 0, 0, NULL),
199
+
MFD_CELL_OF("da9062-regulators", NULL, NULL, 0, 0, NULL),
200
+
MFD_CELL_OF("da9061-watchdog", NULL, NULL, 0, 0, "dlg,da9061-watchdog"),
201
+
MFD_CELL_OF("da9061-thermal", NULL, NULL, 0, 0, "dlg,da9061-thermal"),
202
+
MFD_CELL_OF("da9061-onkey", NULL, NULL, 0, 0, "dlg,da9061-onkey"),
213
203
};
214
204
215
205
static const struct resource da9062_core_resources[] = {
···
235
245
DEFINE_RES_NAMED(DA9062_IRQ_GPI4, 1, "GPI4", IORESOURCE_IRQ),
236
246
};
237
247
238
-
static const struct mfd_cell da9062_devs[] = {
239
-
{
240
-
.name = "da9062-core",
241
-
.num_resources = ARRAY_SIZE(da9062_core_resources),
242
-
.resources = da9062_core_resources,
243
-
},
244
-
{
245
-
.name = "da9062-regulators",
246
-
.num_resources = ARRAY_SIZE(da9062_regulators_resources),
247
-
.resources = da9062_regulators_resources,
248
-
},
249
-
{
250
-
.name = "da9062-watchdog",
251
-
.num_resources = ARRAY_SIZE(da9062_wdt_resources),
252
-
.resources = da9062_wdt_resources,
253
-
.of_compatible = "dlg,da9062-watchdog",
254
-
},
255
-
{
256
-
.name = "da9062-thermal",
257
-
.num_resources = ARRAY_SIZE(da9062_thermal_resources),
258
-
.resources = da9062_thermal_resources,
259
-
.of_compatible = "dlg,da9062-thermal",
260
-
},
261
-
{
262
-
.name = "da9062-rtc",
263
-
.num_resources = ARRAY_SIZE(da9062_rtc_resources),
264
-
.resources = da9062_rtc_resources,
265
-
.of_compatible = "dlg,da9062-rtc",
266
-
},
267
-
{
268
-
.name = "da9062-onkey",
269
-
.num_resources = ARRAY_SIZE(da9062_onkey_resources),
270
-
.resources = da9062_onkey_resources,
271
-
.of_compatible = "dlg,da9062-onkey",
272
-
},
273
-
{
274
-
.name = "da9062-gpio",
275
-
.num_resources = ARRAY_SIZE(da9062_gpio_resources),
276
-
.resources = da9062_gpio_resources,
277
-
.of_compatible = "dlg,da9062-gpio",
278
-
},
248
+
static const struct mfd_cell da9062_devs_irq[] = {
249
+
MFD_CELL_OF("da9062-core", da9062_core_resources, NULL, 0, 0,
250
+
NULL),
251
+
MFD_CELL_OF("da9062-regulators", da9062_regulators_resources, NULL, 0, 0,
252
+
NULL),
253
+
MFD_CELL_OF("da9062-watchdog", da9062_wdt_resources, NULL, 0, 0,
254
+
"dlg,da9062-watchdog"),
255
+
MFD_CELL_OF("da9062-thermal", da9062_thermal_resources, NULL, 0, 0,
256
+
"dlg,da9062-thermal"),
257
+
MFD_CELL_OF("da9062-rtc", da9062_rtc_resources, NULL, 0, 0,
258
+
"dlg,da9062-rtc"),
259
+
MFD_CELL_OF("da9062-onkey", da9062_onkey_resources, NULL, 0, 0,
260
+
"dlg,da9062-onkey"),
261
+
MFD_CELL_OF("da9062-gpio", da9062_gpio_resources, NULL, 0, 0,
262
+
"dlg,da9062-gpio"),
263
+
};
264
+
265
+
static const struct mfd_cell da9062_devs_noirq[] = {
266
+
MFD_CELL_OF("da9062-core", NULL, NULL, 0, 0, NULL),
267
+
MFD_CELL_OF("da9062-regulators", NULL, NULL, 0, 0, NULL),
268
+
MFD_CELL_OF("da9062-watchdog", NULL, NULL, 0, 0, "dlg,da9062-watchdog"),
269
+
MFD_CELL_OF("da9062-thermal", NULL, NULL, 0, 0, "dlg,da9062-thermal"),
270
+
MFD_CELL_OF("da9062-rtc", NULL, NULL, 0, 0, "dlg,da9062-rtc"),
271
+
MFD_CELL_OF("da9062-onkey", NULL, NULL, 0, 0, "dlg,da9062-onkey"),
272
+
MFD_CELL_OF("da9062-gpio", NULL, NULL, 0, 0, "dlg,da9062-gpio"),
279
273
};
280
274
281
275
static int da9062_clear_fault_log(struct da9062 *chip)
···
599
625
{
600
626
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
601
627
struct da9062 *chip;
602
-
unsigned int irq_base;
628
+
unsigned int irq_base = 0;
603
629
const struct mfd_cell *cell;
604
630
const struct regmap_irq_chip *irq_chip;
605
631
const struct regmap_config *config;
···
619
645
i2c_set_clientdata(i2c, chip);
620
646
chip->dev = &i2c->dev;
621
647
622
-
if (!i2c->irq) {
623
-
dev_err(chip->dev, "No IRQ configured\n");
624
-
return -EINVAL;
625
-
}
626
-
648
+
/* Start with a base configuration without IRQ */
627
649
switch (chip->chip_type) {
628
650
case COMPAT_TYPE_DA9061:
629
-
cell = da9061_devs;
630
-
cell_num = ARRAY_SIZE(da9061_devs);
631
-
irq_chip = &da9061_irq_chip;
651
+
cell = da9061_devs_noirq;
652
+
cell_num = ARRAY_SIZE(da9061_devs_noirq);
632
653
config = &da9061_regmap_config;
633
654
break;
634
655
case COMPAT_TYPE_DA9062:
635
-
cell = da9062_devs;
636
-
cell_num = ARRAY_SIZE(da9062_devs);
637
-
irq_chip = &da9062_irq_chip;
656
+
cell = da9062_devs_noirq;
657
+
cell_num = ARRAY_SIZE(da9062_devs_noirq);
638
658
config = &da9062_regmap_config;
639
659
break;
640
660
default:
···
663
695
if (ret)
664
696
return ret;
665
697
666
-
ret = da9062_configure_irq_type(chip, i2c->irq, &trigger_type);
667
-
if (ret < 0) {
668
-
dev_err(chip->dev, "Failed to configure IRQ type\n");
669
-
return ret;
670
-
}
698
+
/* If IRQ is available, reconfigure it accordingly */
699
+
if (i2c->irq) {
700
+
if (chip->chip_type == COMPAT_TYPE_DA9061) {
701
+
cell = da9061_devs_irq;
702
+
cell_num = ARRAY_SIZE(da9061_devs_irq);
703
+
irq_chip = &da9061_irq_chip;
704
+
} else {
705
+
cell = da9062_devs_irq;
706
+
cell_num = ARRAY_SIZE(da9062_devs_irq);
707
+
irq_chip = &da9062_irq_chip;
708
+
}
671
709
672
-
ret = regmap_add_irq_chip(chip->regmap, i2c->irq,
673
-
trigger_type | IRQF_SHARED | IRQF_ONESHOT,
674
-
-1, irq_chip, &chip->regmap_irq);
675
-
if (ret) {
676
-
dev_err(chip->dev, "Failed to request IRQ %d: %d\n",
677
-
i2c->irq, ret);
678
-
return ret;
679
-
}
710
+
ret = da9062_configure_irq_type(chip, i2c->irq, &trigger_type);
711
+
if (ret < 0) {
712
+
dev_err(chip->dev, "Failed to configure IRQ type\n");
713
+
return ret;
714
+
}
680
715
681
-
irq_base = regmap_irq_chip_get_base(chip->regmap_irq);
716
+
ret = regmap_add_irq_chip(chip->regmap, i2c->irq,
717
+
trigger_type | IRQF_SHARED | IRQF_ONESHOT,
718
+
-1, irq_chip, &chip->regmap_irq);
719
+
if (ret) {
720
+
dev_err(chip->dev, "Failed to request IRQ %d: %d\n",
721
+
i2c->irq, ret);
722
+
return ret;
723
+
}
724
+
725
+
irq_base = regmap_irq_chip_get_base(chip->regmap_irq);
726
+
}
682
727
683
728
ret = mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, cell,
684
729
cell_num, NULL, irq_base,
685
730
NULL);
686
731
if (ret) {
687
732
dev_err(chip->dev, "Cannot register child devices\n");
688
-
regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
733
+
if (i2c->irq)
734
+
regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
689
735
return ret;
690
736
}
691
737
+1
drivers/mfd/dln2.c
+1
drivers/mfd/dln2.c
-1
drivers/mfd/ezx-pcap.c
-1
drivers/mfd/ezx-pcap.c
+1
-3
drivers/mfd/hi6421-pmic-core.c
+1
-3
drivers/mfd/hi6421-pmic-core.c
···
50
50
static int hi6421_pmic_probe(struct platform_device *pdev)
51
51
{
52
52
struct hi6421_pmic *pmic;
53
-
struct resource *res;
54
53
const struct of_device_id *id;
55
54
const struct mfd_cell *subdevs;
56
55
enum hi6421_type type;
···
65
66
if (!pmic)
66
67
return -ENOMEM;
67
68
68
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
69
-
base = devm_ioremap_resource(&pdev->dev, res);
69
+
base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
70
70
if (IS_ERR(base))
71
71
return PTR_ERR(base);
72
72
+15
drivers/mfd/intel-lpss-pci.c
+15
drivers/mfd/intel-lpss-pci.c
···
447
447
{ PCI_VDEVICE(INTEL, 0x7e79), (kernel_ulong_t)&bxt_i2c_info },
448
448
{ PCI_VDEVICE(INTEL, 0x7e7a), (kernel_ulong_t)&bxt_i2c_info },
449
449
{ PCI_VDEVICE(INTEL, 0x7e7b), (kernel_ulong_t)&bxt_i2c_info },
450
+
/* MTP-S */
451
+
{ PCI_VDEVICE(INTEL, 0x7f28), (kernel_ulong_t)&bxt_uart_info },
452
+
{ PCI_VDEVICE(INTEL, 0x7f29), (kernel_ulong_t)&bxt_uart_info },
453
+
{ PCI_VDEVICE(INTEL, 0x7f2a), (kernel_ulong_t)&tgl_info },
454
+
{ PCI_VDEVICE(INTEL, 0x7f2b), (kernel_ulong_t)&tgl_info },
455
+
{ PCI_VDEVICE(INTEL, 0x7f4c), (kernel_ulong_t)&bxt_i2c_info },
456
+
{ PCI_VDEVICE(INTEL, 0x7f4d), (kernel_ulong_t)&bxt_i2c_info },
457
+
{ PCI_VDEVICE(INTEL, 0x7f4e), (kernel_ulong_t)&bxt_i2c_info },
458
+
{ PCI_VDEVICE(INTEL, 0x7f4f), (kernel_ulong_t)&bxt_i2c_info },
459
+
{ PCI_VDEVICE(INTEL, 0x7f5c), (kernel_ulong_t)&bxt_uart_info },
460
+
{ PCI_VDEVICE(INTEL, 0x7f5d), (kernel_ulong_t)&bxt_uart_info },
461
+
{ PCI_VDEVICE(INTEL, 0x7f5e), (kernel_ulong_t)&tgl_info },
462
+
{ PCI_VDEVICE(INTEL, 0x7f5f), (kernel_ulong_t)&tgl_info },
463
+
{ PCI_VDEVICE(INTEL, 0x7f7a), (kernel_ulong_t)&bxt_i2c_info },
464
+
{ PCI_VDEVICE(INTEL, 0x7f7b), (kernel_ulong_t)&bxt_i2c_info },
450
465
/* LKF */
451
466
{ PCI_VDEVICE(INTEL, 0x98a8), (kernel_ulong_t)&bxt_uart_info },
452
467
{ PCI_VDEVICE(INTEL, 0x98a9), (kernel_ulong_t)&bxt_uart_info },
+11
-3
drivers/mfd/intel_soc_pmic_chtwc.c
+11
-3
drivers/mfd/intel_soc_pmic_chtwc.c
···
159
159
DMI_MATCH(DMI_PRODUCT_NAME, "Mipad2"),
160
160
},
161
161
}, {
162
-
/* Lenovo Yoga Book X90F / X91F / X91L */
162
+
/* Lenovo Yoga Book X90F / X90L */
163
163
.driver_data = (void *)(long)INTEL_CHT_WC_LENOVO_YOGABOOK1,
164
164
.matches = {
165
-
/* Non exact match to match all versions */
166
-
DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X9"),
165
+
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
166
+
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
167
+
DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "YETI-11"),
168
+
},
169
+
}, {
170
+
/* Lenovo Yoga Book X91F / X91L */
171
+
.driver_data = (void *)(long)INTEL_CHT_WC_LENOVO_YOGABOOK1,
172
+
.matches = {
173
+
/* Non exact match to match F + L versions */
174
+
DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X91"),
167
175
},
168
176
}, {
169
177
/* Lenovo Yoga Tab 3 Pro YT3-X90F */
-1
drivers/mfd/intel_soc_pmic_crc.c
-1
drivers/mfd/intel_soc_pmic_crc.c
+1
-3
drivers/mfd/ipaq-micro.c
+1
-3
drivers/mfd/ipaq-micro.c
···
381
381
static int __init micro_probe(struct platform_device *pdev)
382
382
{
383
383
struct ipaq_micro *micro;
384
-
struct resource *res;
385
384
int ret;
386
385
int irq;
387
386
···
390
391
391
392
micro->dev = &pdev->dev;
392
393
393
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
394
-
micro->base = devm_ioremap_resource(&pdev->dev, res);
394
+
micro->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
395
395
if (IS_ERR(micro->base))
396
396
return PTR_ERR(micro->base);
397
397
+1
-1
drivers/mfd/khadas-mcu.c
+1
-1
drivers/mfd/khadas-mcu.c
···
112
112
if (ret)
113
113
return ret;
114
114
115
-
if (of_find_property(dev->of_node, "#cooling-cells", NULL))
115
+
if (of_property_present(dev->of_node, "#cooling-cells"))
116
116
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
117
117
khadas_mcu_fan_cells,
118
118
ARRAY_SIZE(khadas_mcu_fan_cells),
-1
drivers/mfd/lp8788.c
-1
drivers/mfd/lp8788.c
-26
drivers/mfd/mfd-core.c
-26
drivers/mfd/mfd-core.c
···
33
33
.name = "mfd_device",
34
34
};
35
35
36
-
int mfd_cell_enable(struct platform_device *pdev)
37
-
{
38
-
const struct mfd_cell *cell = mfd_get_cell(pdev);
39
-
40
-
if (!cell->enable) {
41
-
dev_dbg(&pdev->dev, "No .enable() call-back registered\n");
42
-
return 0;
43
-
}
44
-
45
-
return cell->enable(pdev);
46
-
}
47
-
EXPORT_SYMBOL(mfd_cell_enable);
48
-
49
-
int mfd_cell_disable(struct platform_device *pdev)
50
-
{
51
-
const struct mfd_cell *cell = mfd_get_cell(pdev);
52
-
53
-
if (!cell->disable) {
54
-
dev_dbg(&pdev->dev, "No .disable() call-back registered\n");
55
-
return 0;
56
-
}
57
-
58
-
return cell->disable(pdev);
59
-
}
60
-
EXPORT_SYMBOL(mfd_cell_disable);
61
-
62
36
#if IS_ENABLED(CONFIG_ACPI)
63
37
struct match_ids_walk_data {
64
38
struct acpi_device_id *ids;
+1
drivers/mfd/ocelot-spi.c
+1
drivers/mfd/ocelot-spi.c
-1
drivers/mfd/omap-usb-host.c
-1
drivers/mfd/omap-usb-host.c
···
853
853
MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
854
854
MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
855
855
MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
856
-
MODULE_LICENSE("GPL v2");
857
856
MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
858
857
859
858
static int omap_usbhs_drvinit(void)
-6
drivers/mfd/omap-usb-tll.c
-6
drivers/mfd/omap-usb-tll.c
···
125
125
writeb_relaxed(val, base + reg);
126
126
}
127
127
128
-
static inline u8 usbtll_readb(void __iomem *base, u32 reg)
129
-
{
130
-
return readb_relaxed(base + reg);
131
-
}
132
-
133
128
/*-------------------------------------------------------------------------*/
134
129
135
130
static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
···
445
450
446
451
MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
447
452
MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
448
-
MODULE_LICENSE("GPL v2");
449
453
MODULE_DESCRIPTION("usb tll driver for TI OMAP EHCI and OHCI controllers");
450
454
451
455
static int __init omap_usbtll_drvinit(void)
+49
-83
drivers/mfd/qcom-pm8008.c
+49
-83
drivers/mfd/qcom-pm8008.c
···
44
44
#define PM8008_GPIO1_ADDR PM8008_PERIPH_2_BASE
45
45
#define PM8008_GPIO2_ADDR PM8008_PERIPH_3_BASE
46
46
47
-
#define PM8008_STATUS_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_STS_OFFSET)
48
-
#define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET)
49
-
#define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET)
50
-
#define PM8008_TYPE_BASE (PM8008_PERIPH_0_BASE | INT_SET_TYPE_OFFSET)
51
-
#define PM8008_ACK_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_CLR_OFFSET)
52
-
#define PM8008_POLARITY_HI_BASE (PM8008_PERIPH_0_BASE | INT_POL_HIGH_OFFSET)
53
-
#define PM8008_POLARITY_LO_BASE (PM8008_PERIPH_0_BASE | INT_POL_LOW_OFFSET)
54
-
55
-
#define PM8008_PERIPH_OFFSET(paddr) (paddr - PM8008_PERIPH_0_BASE)
56
-
57
-
static unsigned int p0_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BASE)};
58
-
static unsigned int p1_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BASE)};
59
-
static unsigned int p2_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BASE)};
60
-
static unsigned int p3_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_3_BASE)};
61
-
62
-
static struct regmap_irq_sub_irq_map pm8008_sub_reg_offsets[] = {
63
-
REGMAP_IRQ_MAIN_REG_OFFSET(p0_offs),
64
-
REGMAP_IRQ_MAIN_REG_OFFSET(p1_offs),
65
-
REGMAP_IRQ_MAIN_REG_OFFSET(p2_offs),
66
-
REGMAP_IRQ_MAIN_REG_OFFSET(p3_offs),
67
-
};
68
-
69
-
static unsigned int pm8008_virt_regs[] = {
70
-
PM8008_POLARITY_HI_BASE,
71
-
PM8008_POLARITY_LO_BASE,
72
-
};
73
-
74
47
enum {
48
+
SET_TYPE_INDEX,
75
49
POLARITY_HI_INDEX,
76
50
POLARITY_LO_INDEX,
77
-
PM8008_NUM_VIRT_REGS,
51
+
};
52
+
53
+
static unsigned int pm8008_config_regs[] = {
54
+
INT_SET_TYPE_OFFSET,
55
+
INT_POL_HIGH_OFFSET,
56
+
INT_POL_LOW_OFFSET,
78
57
};
79
58
80
59
static struct regmap_irq pm8008_irqs[] = {
···
67
88
REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)),
68
89
};
69
90
70
-
static int pm8008_set_type_virt(unsigned int **virt_buf,
71
-
unsigned int type, unsigned long hwirq,
72
-
int reg)
91
+
static const unsigned int pm8008_periph_base[] = {
92
+
PM8008_PERIPH_0_BASE,
93
+
PM8008_PERIPH_1_BASE,
94
+
PM8008_PERIPH_2_BASE,
95
+
PM8008_PERIPH_3_BASE,
96
+
};
97
+
98
+
static unsigned int pm8008_get_irq_reg(struct regmap_irq_chip_data *data,
99
+
unsigned int base, int index)
100
+
{
101
+
/* Simple linear addressing for the main status register */
102
+
if (base == I2C_INTR_STATUS_BASE)
103
+
return base + index;
104
+
105
+
return pm8008_periph_base[index] + base;
106
+
}
107
+
108
+
static int pm8008_set_type_config(unsigned int **buf, unsigned int type,
109
+
const struct regmap_irq *irq_data, int idx,
110
+
void *irq_drv_data)
73
111
{
74
112
switch (type) {
75
113
case IRQ_TYPE_EDGE_FALLING:
76
114
case IRQ_TYPE_LEVEL_LOW:
77
-
virt_buf[POLARITY_HI_INDEX][reg] &= ~pm8008_irqs[hwirq].mask;
78
-
virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask;
115
+
buf[POLARITY_HI_INDEX][idx] &= ~irq_data->mask;
116
+
buf[POLARITY_LO_INDEX][idx] |= irq_data->mask;
79
117
break;
80
118
81
119
case IRQ_TYPE_EDGE_RISING:
82
120
case IRQ_TYPE_LEVEL_HIGH:
83
-
virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask;
84
-
virt_buf[POLARITY_LO_INDEX][reg] &= ~pm8008_irqs[hwirq].mask;
121
+
buf[POLARITY_HI_INDEX][idx] |= irq_data->mask;
122
+
buf[POLARITY_LO_INDEX][idx] &= ~irq_data->mask;
85
123
break;
86
124
87
125
case IRQ_TYPE_EDGE_BOTH:
88
-
virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask;
89
-
virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask;
126
+
buf[POLARITY_HI_INDEX][idx] |= irq_data->mask;
127
+
buf[POLARITY_LO_INDEX][idx] |= irq_data->mask;
90
128
break;
91
129
92
130
default:
93
131
return -EINVAL;
94
132
}
133
+
134
+
if (type & IRQ_TYPE_EDGE_BOTH)
135
+
buf[SET_TYPE_INDEX][idx] |= irq_data->mask;
136
+
else
137
+
buf[SET_TYPE_INDEX][idx] &= ~irq_data->mask;
95
138
96
139
return 0;
97
140
}
···
122
121
.name = "pm8008_irq",
123
122
.main_status = I2C_INTR_STATUS_BASE,
124
123
.num_main_regs = 1,
125
-
.num_virt_regs = PM8008_NUM_VIRT_REGS,
126
124
.irqs = pm8008_irqs,
127
125
.num_irqs = ARRAY_SIZE(pm8008_irqs),
128
126
.num_regs = PM8008_NUM_PERIPHS,
129
-
.not_fixed_stride = true,
130
-
.sub_reg_offsets = pm8008_sub_reg_offsets,
131
-
.set_type_virt = pm8008_set_type_virt,
132
-
.status_base = PM8008_STATUS_BASE,
133
-
.mask_base = PM8008_MASK_BASE,
134
-
.unmask_base = PM8008_UNMASK_BASE,
135
-
.type_base = PM8008_TYPE_BASE,
136
-
.ack_base = PM8008_ACK_BASE,
137
-
.virt_reg_base = pm8008_virt_regs,
138
-
.num_type_reg = PM8008_NUM_PERIPHS,
127
+
.status_base = INT_LATCHED_STS_OFFSET,
128
+
.mask_base = INT_EN_CLR_OFFSET,
129
+
.unmask_base = INT_EN_SET_OFFSET,
130
+
.mask_unmask_non_inverted = true,
131
+
.ack_base = INT_LATCHED_CLR_OFFSET,
132
+
.config_base = pm8008_config_regs,
133
+
.num_config_bases = ARRAY_SIZE(pm8008_config_regs),
134
+
.num_config_regs = PM8008_NUM_PERIPHS,
135
+
.set_type_config = pm8008_set_type_config,
136
+
.get_irq_reg = pm8008_get_irq_reg,
139
137
};
140
138
141
139
static struct regmap_config qcom_mfd_regmap_cfg = {
···
142
142
.val_bits = 8,
143
143
.max_register = 0xFFFF,
144
144
};
145
-
146
-
static int pm8008_init(struct regmap *regmap)
147
-
{
148
-
int rc;
149
-
150
-
/*
151
-
* Set TEMP_ALARM peripheral's TYPE so that the regmap-irq framework
152
-
* reads this as the default value instead of zero, the HW default.
153
-
* This is required to enable the writing of TYPE registers in
154
-
* regmap_irq_sync_unlock().
155
-
*/
156
-
rc = regmap_write(regmap, (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
157
-
if (rc)
158
-
return rc;
159
-
160
-
/* Do the same for GPIO1 and GPIO2 peripherals */
161
-
rc = regmap_write(regmap, (PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
162
-
if (rc)
163
-
return rc;
164
-
165
-
rc = regmap_write(regmap, (PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
166
-
167
-
return rc;
168
-
}
169
145
170
146
static int pm8008_probe_irq_peripherals(struct device *dev,
171
147
struct regmap *regmap,
···
151
175
struct regmap_irq_type *type;
152
176
struct regmap_irq_chip_data *irq_data;
153
177
154
-
rc = pm8008_init(regmap);
155
-
if (rc) {
156
-
dev_err(dev, "Init failed: %d\n", rc);
157
-
return rc;
158
-
}
159
-
160
178
for (i = 0; i < ARRAY_SIZE(pm8008_irqs); i++) {
161
179
type = &pm8008_irqs[i].type;
162
180
163
-
type->type_reg_offset = pm8008_irqs[i].reg_offset;
164
-
type->type_rising_val = pm8008_irqs[i].mask;
165
-
type->type_falling_val = pm8008_irqs[i].mask;
166
-
type->type_level_high_val = 0;
167
-
type->type_level_low_val = 0;
181
+
type->type_reg_offset = pm8008_irqs[i].reg_offset;
168
182
169
183
if (type->type_reg_offset == PM8008_MISC)
170
184
type->types_supported = IRQ_TYPE_EDGE_RISING;
+1
-3
drivers/mfd/qcom_rpm.c
+1
-3
drivers/mfd/qcom_rpm.c
···
530
530
{
531
531
const struct of_device_id *match;
532
532
struct device_node *syscon_np;
533
-
struct resource *res;
534
533
struct qcom_rpm *rpm;
535
534
u32 fw_version[3];
536
535
int irq_wakeup;
···
575
576
return -ENODEV;
576
577
rpm->data = match->data;
577
578
578
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
579
-
rpm->status_regs = devm_ioremap_resource(&pdev->dev, res);
579
+
rpm->status_regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
580
580
if (IS_ERR(rpm->status_regs))
581
581
return PTR_ERR(rpm->status_regs);
582
582
rpm->ctrl_regs = rpm->status_regs + 0x400;
+2
drivers/mfd/rsmu.h
+2
drivers/mfd/rsmu.h
+134
-35
drivers/mfd/rsmu_i2c.c
+134
-35
drivers/mfd/rsmu_i2c.c
···
18
18
#include "rsmu.h"
19
19
20
20
/*
21
-
* 16-bit register address: the lower 8 bits of the register address come
22
-
* from the offset addr byte and the upper 8 bits come from the page register.
21
+
* 32-bit register address: the lower 8 bits of the register address come
22
+
* from the offset addr byte and the upper 24 bits come from the page register.
23
23
*/
24
-
#define RSMU_CM_PAGE_ADDR 0xFD
25
-
#define RSMU_CM_PAGE_WINDOW 256
24
+
#define RSMU_CM_PAGE_ADDR 0xFC
25
+
#define RSMU_CM_PAGE_MASK 0xFFFFFF00
26
+
#define RSMU_CM_ADDRESS_MASK 0x000000FF
26
27
27
28
/*
28
29
* 15-bit register address: the lower 7 bits of the register address come
···
31
30
*/
32
31
#define RSMU_SABRE_PAGE_ADDR 0x7F
33
32
#define RSMU_SABRE_PAGE_WINDOW 128
34
-
35
-
static const struct regmap_range_cfg rsmu_cm_range_cfg[] = {
36
-
{
37
-
.range_min = 0,
38
-
.range_max = 0xD000,
39
-
.selector_reg = RSMU_CM_PAGE_ADDR,
40
-
.selector_mask = 0xFF,
41
-
.selector_shift = 0,
42
-
.window_start = 0,
43
-
.window_len = RSMU_CM_PAGE_WINDOW,
44
-
}
45
-
};
46
33
47
34
static const struct regmap_range_cfg rsmu_sabre_range_cfg[] = {
48
35
{
···
44
55
}
45
56
};
46
57
47
-
static bool rsmu_cm_volatile_reg(struct device *dev, unsigned int reg)
48
-
{
49
-
switch (reg) {
50
-
case RSMU_CM_PAGE_ADDR:
51
-
return false;
52
-
default:
53
-
return true;
54
-
}
55
-
}
56
-
57
58
static bool rsmu_sabre_volatile_reg(struct device *dev, unsigned int reg)
58
59
{
59
60
switch (reg) {
···
54
75
}
55
76
}
56
77
78
+
static int rsmu_read_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
79
+
{
80
+
struct i2c_client *client = to_i2c_client(rsmu->dev);
81
+
struct i2c_msg msg[2];
82
+
int cnt;
83
+
84
+
msg[0].addr = client->addr;
85
+
msg[0].flags = 0;
86
+
msg[0].len = 1;
87
+
msg[0].buf = ®
88
+
89
+
msg[1].addr = client->addr;
90
+
msg[1].flags = I2C_M_RD;
91
+
msg[1].len = bytes;
92
+
msg[1].buf = buf;
93
+
94
+
cnt = i2c_transfer(client->adapter, msg, 2);
95
+
96
+
if (cnt < 0) {
97
+
dev_err(rsmu->dev, "i2c_transfer failed at addr: %04x!", reg);
98
+
return cnt;
99
+
} else if (cnt != 2) {
100
+
dev_err(rsmu->dev,
101
+
"i2c_transfer sent only %d of 2 messages", cnt);
102
+
return -EIO;
103
+
}
104
+
105
+
return 0;
106
+
}
107
+
108
+
static int rsmu_write_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
109
+
{
110
+
struct i2c_client *client = to_i2c_client(rsmu->dev);
111
+
u8 msg[RSMU_MAX_WRITE_COUNT + 1]; /* 1 Byte added for the device register */
112
+
int cnt;
113
+
114
+
if (bytes > RSMU_MAX_WRITE_COUNT)
115
+
return -EINVAL;
116
+
117
+
msg[0] = reg;
118
+
memcpy(&msg[1], buf, bytes);
119
+
120
+
cnt = i2c_master_send(client, msg, bytes + 1);
121
+
122
+
if (cnt < 0) {
123
+
dev_err(&client->dev,
124
+
"i2c_master_send failed at addr: %04x!", reg);
125
+
return cnt;
126
+
}
127
+
128
+
return 0;
129
+
}
130
+
131
+
static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u32 reg)
132
+
{
133
+
u32 page = reg & RSMU_CM_PAGE_MASK;
134
+
u8 buf[4];
135
+
int err;
136
+
137
+
/* Do not modify offset register for none-scsr registers */
138
+
if (reg < RSMU_CM_SCSR_BASE)
139
+
return 0;
140
+
141
+
/* Simply return if we are on the same page */
142
+
if (rsmu->page == page)
143
+
return 0;
144
+
145
+
buf[0] = 0x0;
146
+
buf[1] = (u8)((page >> 8) & 0xFF);
147
+
buf[2] = (u8)((page >> 16) & 0xFF);
148
+
buf[3] = (u8)((page >> 24) & 0xFF);
149
+
150
+
err = rsmu_write_device(rsmu, RSMU_CM_PAGE_ADDR, buf, sizeof(buf));
151
+
if (err)
152
+
dev_err(rsmu->dev, "Failed to set page offset 0x%x\n", page);
153
+
else
154
+
/* Remember the last page */
155
+
rsmu->page = page;
156
+
157
+
return err;
158
+
}
159
+
160
+
static int rsmu_reg_read(void *context, unsigned int reg, unsigned int *val)
161
+
{
162
+
struct rsmu_ddata *rsmu = i2c_get_clientdata((struct i2c_client *)context);
163
+
u8 addr = (u8)(reg & RSMU_CM_ADDRESS_MASK);
164
+
int err;
165
+
166
+
err = rsmu_write_page_register(rsmu, reg);
167
+
if (err)
168
+
return err;
169
+
170
+
err = rsmu_read_device(rsmu, addr, (u8 *)val, 1);
171
+
if (err)
172
+
dev_err(rsmu->dev, "Failed to read offset address 0x%x\n", addr);
173
+
174
+
return err;
175
+
}
176
+
177
+
static int rsmu_reg_write(void *context, unsigned int reg, unsigned int val)
178
+
{
179
+
struct rsmu_ddata *rsmu = i2c_get_clientdata((struct i2c_client *)context);
180
+
u8 addr = (u8)(reg & RSMU_CM_ADDRESS_MASK);
181
+
u8 data = (u8)val;
182
+
int err;
183
+
184
+
err = rsmu_write_page_register(rsmu, reg);
185
+
if (err)
186
+
return err;
187
+
188
+
err = rsmu_write_device(rsmu, addr, &data, 1);
189
+
if (err)
190
+
dev_err(rsmu->dev,
191
+
"Failed to write offset address 0x%x\n", addr);
192
+
193
+
return err;
194
+
}
195
+
57
196
static const struct regmap_config rsmu_cm_regmap_config = {
58
-
.reg_bits = 8,
197
+
.reg_bits = 32,
59
198
.val_bits = 8,
60
-
.max_register = 0xD000,
61
-
.ranges = rsmu_cm_range_cfg,
62
-
.num_ranges = ARRAY_SIZE(rsmu_cm_range_cfg),
63
-
.volatile_reg = rsmu_cm_volatile_reg,
64
-
.cache_type = REGCACHE_RBTREE,
65
-
.can_multi_write = true,
199
+
.max_register = 0x20120000,
200
+
.reg_read = rsmu_reg_read,
201
+
.reg_write = rsmu_reg_write,
202
+
.cache_type = REGCACHE_NONE,
66
203
};
67
204
68
205
static const struct regmap_config rsmu_sabre_regmap_config = {
···
196
101
.reg_bits = 16,
197
102
.val_bits = 8,
198
103
.reg_format_endian = REGMAP_ENDIAN_BIG,
199
-
.max_register = 0x339,
104
+
.max_register = 0x340,
200
105
.cache_type = REGCACHE_NONE,
201
106
.can_multi_write = true,
202
107
};
···
231
136
dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
232
137
return -ENODEV;
233
138
}
234
-
rsmu->regmap = devm_regmap_init_i2c(client, cfg);
139
+
140
+
if (rsmu->type == RSMU_CM)
141
+
rsmu->regmap = devm_regmap_init(&client->dev, NULL, client, cfg);
142
+
else
143
+
rsmu->regmap = devm_regmap_init_i2c(client, cfg);
235
144
if (IS_ERR(rsmu->regmap)) {
236
145
ret = PTR_ERR(rsmu->regmap);
237
146
dev_err(rsmu->dev, "Failed to allocate register map: %d\n", ret);
+31
-17
drivers/mfd/rsmu_spi.c
+31
-17
drivers/mfd/rsmu_spi.c
···
19
19
20
20
#define RSMU_CM_PAGE_ADDR 0x7C
21
21
#define RSMU_SABRE_PAGE_ADDR 0x7F
22
-
#define RSMU_HIGHER_ADDR_MASK 0xFF80
23
-
#define RSMU_HIGHER_ADDR_SHIFT 7
24
-
#define RSMU_LOWER_ADDR_MASK 0x7F
22
+
#define RSMU_PAGE_MASK 0xFFFFFF80
23
+
#define RSMU_ADDR_MASK 0x7F
25
24
26
25
static int rsmu_read_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
27
26
{
28
27
struct spi_device *client = to_spi_device(rsmu->dev);
29
28
struct spi_transfer xfer = {0};
30
29
struct spi_message msg;
31
-
u8 cmd[256] = {0};
32
-
u8 rsp[256] = {0};
30
+
u8 cmd[RSMU_MAX_READ_COUNT + 1] = {0};
31
+
u8 rsp[RSMU_MAX_READ_COUNT + 1] = {0};
33
32
int ret;
33
+
34
+
if (bytes > RSMU_MAX_READ_COUNT)
35
+
return -EINVAL;
34
36
35
37
cmd[0] = reg | 0x80;
36
38
xfer.rx_buf = rsp;
···
68
66
struct spi_device *client = to_spi_device(rsmu->dev);
69
67
struct spi_transfer xfer = {0};
70
68
struct spi_message msg;
71
-
u8 cmd[256] = {0};
69
+
u8 cmd[RSMU_MAX_WRITE_COUNT + 1] = {0};
70
+
71
+
if (bytes > RSMU_MAX_WRITE_COUNT)
72
+
return -EINVAL;
72
73
73
74
cmd[0] = reg;
74
75
memcpy(&cmd[1], buf, bytes);
···
91
86
* 16-bit register address: the lower 7 bits of the register address come
92
87
* from the offset addr byte and the upper 9 bits come from the page register.
93
88
*/
94
-
static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u16 reg)
89
+
static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u32 reg)
95
90
{
96
91
u8 page_reg;
97
-
u8 buf[2];
92
+
u8 buf[4];
98
93
u16 bytes;
99
-
u16 page;
94
+
u32 page;
100
95
int err;
101
96
102
97
switch (rsmu->type) {
103
98
case RSMU_CM:
99
+
/* Do not modify page register for none-scsr registers */
100
+
if (reg < RSMU_CM_SCSR_BASE)
101
+
return 0;
104
102
page_reg = RSMU_CM_PAGE_ADDR;
105
-
page = reg & RSMU_HIGHER_ADDR_MASK;
103
+
page = reg & RSMU_PAGE_MASK;
106
104
buf[0] = (u8)(page & 0xff);
107
105
buf[1] = (u8)((page >> 8) & 0xff);
108
-
bytes = 2;
106
+
buf[2] = (u8)((page >> 16) & 0xff);
107
+
buf[3] = (u8)((page >> 24) & 0xff);
108
+
bytes = 4;
109
109
break;
110
110
case RSMU_SABRE:
111
+
/* Do not modify page register if reg is page register itself */
112
+
if ((reg & RSMU_ADDR_MASK) == RSMU_ADDR_MASK)
113
+
return 0;
111
114
page_reg = RSMU_SABRE_PAGE_ADDR;
112
-
page = reg >> RSMU_HIGHER_ADDR_SHIFT;
113
-
buf[0] = (u8)(page & 0xff);
115
+
page = reg & RSMU_PAGE_MASK;
116
+
/* The three page bits are located in the single Page Register */
117
+
buf[0] = (u8)((page >> 7) & 0x7);
114
118
bytes = 1;
115
119
break;
116
120
default:
···
144
130
static int rsmu_reg_read(void *context, unsigned int reg, unsigned int *val)
145
131
{
146
132
struct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context);
147
-
u8 addr = (u8)(reg & RSMU_LOWER_ADDR_MASK);
133
+
u8 addr = (u8)(reg & RSMU_ADDR_MASK);
148
134
int err;
149
135
150
136
err = rsmu_write_page_register(rsmu, reg);
···
161
147
static int rsmu_reg_write(void *context, unsigned int reg, unsigned int val)
162
148
{
163
149
struct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context);
164
-
u8 addr = (u8)(reg & RSMU_LOWER_ADDR_MASK);
150
+
u8 addr = (u8)(reg & RSMU_ADDR_MASK);
165
151
u8 data = (u8)val;
166
152
int err;
167
153
···
178
164
}
179
165
180
166
static const struct regmap_config rsmu_cm_regmap_config = {
181
-
.reg_bits = 16,
167
+
.reg_bits = 32,
182
168
.val_bits = 8,
183
-
.max_register = 0xD000,
169
+
.max_register = 0x20120000,
184
170
.reg_read = rsmu_reg_read,
185
171
.reg_write = rsmu_reg_write,
186
172
.cache_type = REGCACHE_NONE,
+391
drivers/mfd/rz-mtu3.c
+391
drivers/mfd/rz-mtu3.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Renesas RZ/G2L Multi-Function Timer Pulse Unit 3(MTU3a) Core driver
4
+
*
5
+
* Copyright (C) 2023 Renesas Electronics Corporation
6
+
*/
7
+
8
+
#include <linux/bitfield.h>
9
+
#include <linux/clk.h>
10
+
#include <linux/interrupt.h>
11
+
#include <linux/irq.h>
12
+
#include <linux/mfd/core.h>
13
+
#include <linux/mfd/rz-mtu3.h>
14
+
#include <linux/of_platform.h>
15
+
#include <linux/reset.h>
16
+
#include <linux/spinlock.h>
17
+
18
+
#include "rz-mtu3.h"
19
+
20
+
struct rz_mtu3_priv {
21
+
void __iomem *mmio;
22
+
struct reset_control *rstc;
23
+
raw_spinlock_t lock;
24
+
};
25
+
26
+
/******* MTU3 registers (original offset is +0x1200) *******/
27
+
static const unsigned long rz_mtu3_8bit_ch_reg_offs[][13] = {
28
+
[RZ_MTU3_CHAN_0] = MTU_8BIT_CH_0(0x104, 0x090, 0x100, 0x128, 0x101, 0x102, 0x103, 0x126),
29
+
[RZ_MTU3_CHAN_1] = MTU_8BIT_CH_1_2(0x184, 0x091, 0x185, 0x180, 0x194, 0x181, 0x182),
30
+
[RZ_MTU3_CHAN_2] = MTU_8BIT_CH_1_2(0x204, 0x092, 0x205, 0x200, 0x20c, 0x201, 0x202),
31
+
[RZ_MTU3_CHAN_3] = MTU_8BIT_CH_3_4_6_7(0x008, 0x093, 0x02c, 0x000, 0x04c, 0x002, 0x004, 0x005, 0x038),
32
+
[RZ_MTU3_CHAN_4] = MTU_8BIT_CH_3_4_6_7(0x009, 0x094, 0x02d, 0x001, 0x04d, 0x003, 0x006, 0x007, 0x039),
33
+
[RZ_MTU3_CHAN_5] = MTU_8BIT_CH_5(0xab2, 0x1eb, 0xab4, 0xab6, 0xa84, 0xa85, 0xa86, 0xa94, 0xa95, 0xa96, 0xaa4, 0xaa5, 0xaa6),
34
+
[RZ_MTU3_CHAN_6] = MTU_8BIT_CH_3_4_6_7(0x808, 0x893, 0x82c, 0x800, 0x84c, 0x802, 0x804, 0x805, 0x838),
35
+
[RZ_MTU3_CHAN_7] = MTU_8BIT_CH_3_4_6_7(0x809, 0x894, 0x82d, 0x801, 0x84d, 0x803, 0x806, 0x807, 0x839),
36
+
[RZ_MTU3_CHAN_8] = MTU_8BIT_CH_8(0x404, 0x098, 0x400, 0x406, 0x401, 0x402, 0x403)
37
+
};
38
+
39
+
static const unsigned long rz_mtu3_16bit_ch_reg_offs[][12] = {
40
+
[RZ_MTU3_CHAN_0] = MTU_16BIT_CH_0(0x106, 0x108, 0x10a, 0x10c, 0x10e, 0x120, 0x122),
41
+
[RZ_MTU3_CHAN_1] = MTU_16BIT_CH_1_2(0x186, 0x188, 0x18a),
42
+
[RZ_MTU3_CHAN_2] = MTU_16BIT_CH_1_2(0x206, 0x208, 0x20a),
43
+
[RZ_MTU3_CHAN_3] = MTU_16BIT_CH_3_6(0x010, 0x018, 0x01a, 0x024, 0x026, 0x072),
44
+
[RZ_MTU3_CHAN_4] = MTU_16BIT_CH_4_7(0x012, 0x01c, 0x01e, 0x028, 0x2a, 0x074, 0x076, 0x040, 0x044, 0x046, 0x048, 0x04a),
45
+
[RZ_MTU3_CHAN_5] = MTU_16BIT_CH_5(0xa80, 0xa82, 0xa90, 0xa92, 0xaa0, 0xaa2),
46
+
[RZ_MTU3_CHAN_6] = MTU_16BIT_CH_3_6(0x810, 0x818, 0x81a, 0x824, 0x826, 0x872),
47
+
[RZ_MTU3_CHAN_7] = MTU_16BIT_CH_4_7(0x812, 0x81c, 0x81e, 0x828, 0x82a, 0x874, 0x876, 0x840, 0x844, 0x846, 0x848, 0x84a)
48
+
};
49
+
50
+
static const unsigned long rz_mtu3_32bit_ch_reg_offs[][5] = {
51
+
[RZ_MTU3_CHAN_1] = MTU_32BIT_CH_1(0x1a0, 0x1a4, 0x1a8),
52
+
[RZ_MTU3_CHAN_8] = MTU_32BIT_CH_8(0x408, 0x40c, 0x410, 0x414, 0x418)
53
+
};
54
+
55
+
static bool rz_mtu3_is_16bit_shared_reg(u16 offset)
56
+
{
57
+
return (offset == RZ_MTU3_TDDRA || offset == RZ_MTU3_TDDRB ||
58
+
offset == RZ_MTU3_TCDRA || offset == RZ_MTU3_TCDRB ||
59
+
offset == RZ_MTU3_TCBRA || offset == RZ_MTU3_TCBRB ||
60
+
offset == RZ_MTU3_TCNTSA || offset == RZ_MTU3_TCNTSB);
61
+
}
62
+
63
+
u16 rz_mtu3_shared_reg_read(struct rz_mtu3_channel *ch, u16 offset)
64
+
{
65
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
66
+
struct rz_mtu3_priv *priv = mtu->priv_data;
67
+
68
+
if (rz_mtu3_is_16bit_shared_reg(offset))
69
+
return readw(priv->mmio + offset);
70
+
else
71
+
return readb(priv->mmio + offset);
72
+
}
73
+
EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_read);
74
+
75
+
u8 rz_mtu3_8bit_ch_read(struct rz_mtu3_channel *ch, u16 offset)
76
+
{
77
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
78
+
struct rz_mtu3_priv *priv = mtu->priv_data;
79
+
u16 ch_offs;
80
+
81
+
ch_offs = rz_mtu3_8bit_ch_reg_offs[ch->channel_number][offset];
82
+
83
+
return readb(priv->mmio + ch_offs);
84
+
}
85
+
EXPORT_SYMBOL_GPL(rz_mtu3_8bit_ch_read);
86
+
87
+
u16 rz_mtu3_16bit_ch_read(struct rz_mtu3_channel *ch, u16 offset)
88
+
{
89
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
90
+
struct rz_mtu3_priv *priv = mtu->priv_data;
91
+
u16 ch_offs;
92
+
93
+
/* MTU8 doesn't have 16-bit registers */
94
+
if (ch->channel_number == RZ_MTU3_CHAN_8)
95
+
return 0;
96
+
97
+
ch_offs = rz_mtu3_16bit_ch_reg_offs[ch->channel_number][offset];
98
+
99
+
return readw(priv->mmio + ch_offs);
100
+
}
101
+
EXPORT_SYMBOL_GPL(rz_mtu3_16bit_ch_read);
102
+
103
+
u32 rz_mtu3_32bit_ch_read(struct rz_mtu3_channel *ch, u16 offset)
104
+
{
105
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
106
+
struct rz_mtu3_priv *priv = mtu->priv_data;
107
+
u16 ch_offs;
108
+
109
+
if (ch->channel_number != RZ_MTU3_CHAN_1 && ch->channel_number != RZ_MTU3_CHAN_8)
110
+
return 0;
111
+
112
+
ch_offs = rz_mtu3_32bit_ch_reg_offs[ch->channel_number][offset];
113
+
114
+
return readl(priv->mmio + ch_offs);
115
+
}
116
+
EXPORT_SYMBOL_GPL(rz_mtu3_32bit_ch_read);
117
+
118
+
void rz_mtu3_8bit_ch_write(struct rz_mtu3_channel *ch, u16 offset, u8 val)
119
+
{
120
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
121
+
struct rz_mtu3_priv *priv = mtu->priv_data;
122
+
u16 ch_offs;
123
+
124
+
ch_offs = rz_mtu3_8bit_ch_reg_offs[ch->channel_number][offset];
125
+
writeb(val, priv->mmio + ch_offs);
126
+
}
127
+
EXPORT_SYMBOL_GPL(rz_mtu3_8bit_ch_write);
128
+
129
+
void rz_mtu3_16bit_ch_write(struct rz_mtu3_channel *ch, u16 offset, u16 val)
130
+
{
131
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
132
+
struct rz_mtu3_priv *priv = mtu->priv_data;
133
+
u16 ch_offs;
134
+
135
+
/* MTU8 doesn't have 16-bit registers */
136
+
if (ch->channel_number == RZ_MTU3_CHAN_8)
137
+
return;
138
+
139
+
ch_offs = rz_mtu3_16bit_ch_reg_offs[ch->channel_number][offset];
140
+
writew(val, priv->mmio + ch_offs);
141
+
}
142
+
EXPORT_SYMBOL_GPL(rz_mtu3_16bit_ch_write);
143
+
144
+
void rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 offset, u32 val)
145
+
{
146
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
147
+
struct rz_mtu3_priv *priv = mtu->priv_data;
148
+
u16 ch_offs;
149
+
150
+
if (ch->channel_number != RZ_MTU3_CHAN_1 && ch->channel_number != RZ_MTU3_CHAN_8)
151
+
return;
152
+
153
+
ch_offs = rz_mtu3_32bit_ch_reg_offs[ch->channel_number][offset];
154
+
writel(val, priv->mmio + ch_offs);
155
+
}
156
+
EXPORT_SYMBOL_GPL(rz_mtu3_32bit_ch_write);
157
+
158
+
void rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 offset, u16 value)
159
+
{
160
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
161
+
struct rz_mtu3_priv *priv = mtu->priv_data;
162
+
163
+
if (rz_mtu3_is_16bit_shared_reg(offset))
164
+
writew(value, priv->mmio + offset);
165
+
else
166
+
writeb((u8)value, priv->mmio + offset);
167
+
}
168
+
EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_write);
169
+
170
+
void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 offset,
171
+
u16 pos, u8 val)
172
+
{
173
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
174
+
struct rz_mtu3_priv *priv = mtu->priv_data;
175
+
unsigned long tmdr, flags;
176
+
177
+
raw_spin_lock_irqsave(&priv->lock, flags);
178
+
tmdr = rz_mtu3_shared_reg_read(ch, offset);
179
+
__assign_bit(pos, &tmdr, !!val);
180
+
rz_mtu3_shared_reg_write(ch, offset, tmdr);
181
+
raw_spin_unlock_irqrestore(&priv->lock, flags);
182
+
}
183
+
EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_update_bit);
184
+
185
+
static u16 rz_mtu3_get_tstr_offset(struct rz_mtu3_channel *ch)
186
+
{
187
+
u16 offset;
188
+
189
+
switch (ch->channel_number) {
190
+
case RZ_MTU3_CHAN_0:
191
+
case RZ_MTU3_CHAN_1:
192
+
case RZ_MTU3_CHAN_2:
193
+
case RZ_MTU3_CHAN_3:
194
+
case RZ_MTU3_CHAN_4:
195
+
case RZ_MTU3_CHAN_8:
196
+
offset = RZ_MTU3_TSTRA;
197
+
break;
198
+
case RZ_MTU3_CHAN_5:
199
+
offset = RZ_MTU3_TSTR;
200
+
break;
201
+
case RZ_MTU3_CHAN_6:
202
+
case RZ_MTU3_CHAN_7:
203
+
offset = RZ_MTU3_TSTRB;
204
+
break;
205
+
default:
206
+
offset = 0;
207
+
break;
208
+
}
209
+
210
+
return offset;
211
+
}
212
+
213
+
static u8 rz_mtu3_get_tstr_bit_pos(struct rz_mtu3_channel *ch)
214
+
{
215
+
u8 bitpos;
216
+
217
+
switch (ch->channel_number) {
218
+
case RZ_MTU3_CHAN_0:
219
+
case RZ_MTU3_CHAN_1:
220
+
case RZ_MTU3_CHAN_2:
221
+
case RZ_MTU3_CHAN_6:
222
+
case RZ_MTU3_CHAN_7:
223
+
bitpos = ch->channel_number;
224
+
break;
225
+
case RZ_MTU3_CHAN_3:
226
+
bitpos = 6;
227
+
break;
228
+
case RZ_MTU3_CHAN_4:
229
+
bitpos = 7;
230
+
break;
231
+
case RZ_MTU3_CHAN_5:
232
+
bitpos = 2;
233
+
break;
234
+
case RZ_MTU3_CHAN_8:
235
+
bitpos = 3;
236
+
break;
237
+
default:
238
+
bitpos = 0;
239
+
break;
240
+
}
241
+
242
+
return bitpos;
243
+
}
244
+
245
+
static void rz_mtu3_start_stop_ch(struct rz_mtu3_channel *ch, bool start)
246
+
{
247
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
248
+
struct rz_mtu3_priv *priv = mtu->priv_data;
249
+
unsigned long flags, tstr;
250
+
u16 offset;
251
+
u8 bitpos;
252
+
253
+
/* start stop register shared by multiple timer channels */
254
+
raw_spin_lock_irqsave(&priv->lock, flags);
255
+
256
+
offset = rz_mtu3_get_tstr_offset(ch);
257
+
bitpos = rz_mtu3_get_tstr_bit_pos(ch);
258
+
tstr = rz_mtu3_shared_reg_read(ch, offset);
259
+
__assign_bit(bitpos, &tstr, start);
260
+
rz_mtu3_shared_reg_write(ch, offset, tstr);
261
+
262
+
raw_spin_unlock_irqrestore(&priv->lock, flags);
263
+
}
264
+
265
+
bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch)
266
+
{
267
+
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
268
+
struct rz_mtu3_priv *priv = mtu->priv_data;
269
+
unsigned long flags, tstr;
270
+
bool ret = false;
271
+
u16 offset;
272
+
u8 bitpos;
273
+
274
+
/* start stop register shared by multiple timer channels */
275
+
raw_spin_lock_irqsave(&priv->lock, flags);
276
+
277
+
offset = rz_mtu3_get_tstr_offset(ch);
278
+
bitpos = rz_mtu3_get_tstr_bit_pos(ch);
279
+
tstr = rz_mtu3_shared_reg_read(ch, offset);
280
+
ret = tstr & BIT(bitpos);
281
+
282
+
raw_spin_unlock_irqrestore(&priv->lock, flags);
283
+
284
+
return ret;
285
+
}
286
+
EXPORT_SYMBOL_GPL(rz_mtu3_is_enabled);
287
+
288
+
int rz_mtu3_enable(struct rz_mtu3_channel *ch)
289
+
{
290
+
/* enable channel */
291
+
rz_mtu3_start_stop_ch(ch, true);
292
+
293
+
return 0;
294
+
}
295
+
EXPORT_SYMBOL_GPL(rz_mtu3_enable);
296
+
297
+
void rz_mtu3_disable(struct rz_mtu3_channel *ch)
298
+
{
299
+
/* disable channel */
300
+
rz_mtu3_start_stop_ch(ch, false);
301
+
}
302
+
EXPORT_SYMBOL_GPL(rz_mtu3_disable);
303
+
304
+
static void rz_mtu3_reset_assert(void *data)
305
+
{
306
+
struct rz_mtu3 *mtu = dev_get_drvdata(data);
307
+
struct rz_mtu3_priv *priv = mtu->priv_data;
308
+
309
+
mfd_remove_devices(data);
310
+
reset_control_assert(priv->rstc);
311
+
}
312
+
313
+
static const struct mfd_cell rz_mtu3_devs[] = {
314
+
{
315
+
.name = "rz-mtu3-counter",
316
+
},
317
+
{
318
+
.name = "pwm-rz-mtu3",
319
+
},
320
+
};
321
+
322
+
static int rz_mtu3_probe(struct platform_device *pdev)
323
+
{
324
+
struct rz_mtu3_priv *priv;
325
+
struct rz_mtu3 *ddata;
326
+
unsigned int i;
327
+
int ret;
328
+
329
+
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
330
+
if (!ddata)
331
+
return -ENOMEM;
332
+
333
+
ddata->priv_data = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
334
+
if (!ddata->priv_data)
335
+
return -ENOMEM;
336
+
337
+
priv = ddata->priv_data;
338
+
339
+
priv->mmio = devm_platform_ioremap_resource(pdev, 0);
340
+
if (IS_ERR(priv->mmio))
341
+
return PTR_ERR(priv->mmio);
342
+
343
+
priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
344
+
if (IS_ERR(priv->rstc))
345
+
return PTR_ERR(priv->rstc);
346
+
347
+
ddata->clk = devm_clk_get(&pdev->dev, NULL);
348
+
if (IS_ERR(ddata->clk))
349
+
return PTR_ERR(ddata->clk);
350
+
351
+
reset_control_deassert(priv->rstc);
352
+
raw_spin_lock_init(&priv->lock);
353
+
platform_set_drvdata(pdev, ddata);
354
+
355
+
for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) {
356
+
ddata->channels[i].channel_number = i;
357
+
ddata->channels[i].is_busy = false;
358
+
mutex_init(&ddata->channels[i].lock);
359
+
}
360
+
361
+
ret = mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs,
362
+
ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL);
363
+
if (ret < 0)
364
+
goto err_assert;
365
+
366
+
return devm_add_action_or_reset(&pdev->dev, rz_mtu3_reset_assert,
367
+
&pdev->dev);
368
+
369
+
err_assert:
370
+
reset_control_assert(priv->rstc);
371
+
return ret;
372
+
}
373
+
374
+
static const struct of_device_id rz_mtu3_of_match[] = {
375
+
{ .compatible = "renesas,rz-mtu3", },
376
+
{ /* sentinel */ }
377
+
};
378
+
MODULE_DEVICE_TABLE(of, rz_mtu3_of_match);
379
+
380
+
static struct platform_driver rz_mtu3_driver = {
381
+
.probe = rz_mtu3_probe,
382
+
.driver = {
383
+
.name = "rz-mtu3",
384
+
.of_match_table = rz_mtu3_of_match,
385
+
},
386
+
};
387
+
module_platform_driver(rz_mtu3_driver);
388
+
389
+
MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
390
+
MODULE_DESCRIPTION("Renesas RZ/G2L MTU3a Core Driver");
391
+
MODULE_LICENSE("GPL");
+147
drivers/mfd/rz-mtu3.h
+147
drivers/mfd/rz-mtu3.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* MFD internals for Renesas RZ/G2L MTU3 Core driver
4
+
*
5
+
* Copyright (C) 2023 Renesas Electronics Corporation
6
+
*/
7
+
8
+
#ifndef RZ_MTU3_MFD_H
9
+
#define RZ_MTU3_MFD_H
10
+
11
+
#define MTU_8BIT_CH_0(_tier, _nfcr, _tcr, _tcr2, _tmdr1, _tiorh, _tiorl, _tbtm) \
12
+
{ \
13
+
[RZ_MTU3_TIER] = _tier, \
14
+
[RZ_MTU3_NFCR] = _nfcr, \
15
+
[RZ_MTU3_TCR] = _tcr, \
16
+
[RZ_MTU3_TCR2] = _tcr2, \
17
+
[RZ_MTU3_TMDR1] = _tmdr1, \
18
+
[RZ_MTU3_TIORH] = _tiorh, \
19
+
[RZ_MTU3_TIORL] = _tiorl, \
20
+
[RZ_MTU3_TBTM] = _tbtm \
21
+
}
22
+
23
+
#define MTU_8BIT_CH_1_2(_tier, _nfcr, _tsr, _tcr, _tcr2, _tmdr1, _tior) \
24
+
{ \
25
+
[RZ_MTU3_TIER] = _tier, \
26
+
[RZ_MTU3_NFCR] = _nfcr, \
27
+
[RZ_MTU3_TSR] = _tsr, \
28
+
[RZ_MTU3_TCR] = _tcr, \
29
+
[RZ_MTU3_TCR2] = _tcr2, \
30
+
[RZ_MTU3_TMDR1] = _tmdr1, \
31
+
[RZ_MTU3_TIOR] = _tior \
32
+
} \
33
+
34
+
#define MTU_8BIT_CH_3_4_6_7(_tier, _nfcr, _tsr, _tcr, _tcr2, _tmdr1, _tiorh, _tiorl, _tbtm) \
35
+
{ \
36
+
[RZ_MTU3_TIER] = _tier, \
37
+
[RZ_MTU3_NFCR] = _nfcr, \
38
+
[RZ_MTU3_TSR] = _tsr, \
39
+
[RZ_MTU3_TCR] = _tcr, \
40
+
[RZ_MTU3_TCR2] = _tcr2, \
41
+
[RZ_MTU3_TMDR1] = _tmdr1, \
42
+
[RZ_MTU3_TIORH] = _tiorh, \
43
+
[RZ_MTU3_TIORL] = _tiorl, \
44
+
[RZ_MTU3_TBTM] = _tbtm \
45
+
} \
46
+
47
+
#define MTU_8BIT_CH_5(_tier, _nfcr, _tstr, _tcntcmpclr, _tcru, _tcr2u, _tioru, \
48
+
_tcrv, _tcr2v, _tiorv, _tcrw, _tcr2w, _tiorw) \
49
+
{ \
50
+
[RZ_MTU3_TIER] = _tier, \
51
+
[RZ_MTU3_NFCR] = _nfcr, \
52
+
[RZ_MTU3_TSTR] = _tstr, \
53
+
[RZ_MTU3_TCNTCMPCLR] = _tcntcmpclr, \
54
+
[RZ_MTU3_TCRU] = _tcru, \
55
+
[RZ_MTU3_TCR2U] = _tcr2u, \
56
+
[RZ_MTU3_TIORU] = _tioru, \
57
+
[RZ_MTU3_TCRV] = _tcrv, \
58
+
[RZ_MTU3_TCR2V] = _tcr2v, \
59
+
[RZ_MTU3_TIORV] = _tiorv, \
60
+
[RZ_MTU3_TCRW] = _tcrw, \
61
+
[RZ_MTU3_TCR2W] = _tcr2w, \
62
+
[RZ_MTU3_TIORW] = _tiorw \
63
+
} \
64
+
65
+
#define MTU_8BIT_CH_8(_tier, _nfcr, _tcr, _tcr2, _tmdr1, _tiorh, _tiorl) \
66
+
{ \
67
+
[RZ_MTU3_TIER] = _tier, \
68
+
[RZ_MTU3_NFCR] = _nfcr, \
69
+
[RZ_MTU3_TCR] = _tcr, \
70
+
[RZ_MTU3_TCR2] = _tcr2, \
71
+
[RZ_MTU3_TMDR1] = _tmdr1, \
72
+
[RZ_MTU3_TIORH] = _tiorh, \
73
+
[RZ_MTU3_TIORL] = _tiorl \
74
+
} \
75
+
76
+
#define MTU_16BIT_CH_0(_tcnt, _tgra, _tgrb, _tgrc, _tgrd, _tgre, _tgrf) \
77
+
{ \
78
+
[RZ_MTU3_TCNT] = _tcnt, \
79
+
[RZ_MTU3_TGRA] = _tgra, \
80
+
[RZ_MTU3_TGRB] = _tgrb, \
81
+
[RZ_MTU3_TGRC] = _tgrc, \
82
+
[RZ_MTU3_TGRD] = _tgrd, \
83
+
[RZ_MTU3_TGRE] = _tgre, \
84
+
[RZ_MTU3_TGRF] = _tgrf \
85
+
}
86
+
87
+
#define MTU_16BIT_CH_1_2(_tcnt, _tgra, _tgrb) \
88
+
{ \
89
+
[RZ_MTU3_TCNT] = _tcnt, \
90
+
[RZ_MTU3_TGRA] = _tgra, \
91
+
[RZ_MTU3_TGRB] = _tgrb \
92
+
}
93
+
94
+
#define MTU_16BIT_CH_3_6(_tcnt, _tgra, _tgrb, _tgrc, _tgrd, _tgre) \
95
+
{ \
96
+
[RZ_MTU3_TCNT] = _tcnt, \
97
+
[RZ_MTU3_TGRA] = _tgra, \
98
+
[RZ_MTU3_TGRB] = _tgrb, \
99
+
[RZ_MTU3_TGRC] = _tgrc, \
100
+
[RZ_MTU3_TGRD] = _tgrd, \
101
+
[RZ_MTU3_TGRE] = _tgre \
102
+
}
103
+
104
+
#define MTU_16BIT_CH_4_7(_tcnt, _tgra, _tgrb, _tgrc, _tgrd, _tgre, _tgrf, \
105
+
_tadcr, _tadcora, _tadcorb, _tadcobra, _tadcobrb) \
106
+
{ \
107
+
[RZ_MTU3_TCNT] = _tcnt, \
108
+
[RZ_MTU3_TGRA] = _tgra, \
109
+
[RZ_MTU3_TGRB] = _tgrb, \
110
+
[RZ_MTU3_TGRC] = _tgrc, \
111
+
[RZ_MTU3_TGRD] = _tgrd, \
112
+
[RZ_MTU3_TGRE] = _tgre, \
113
+
[RZ_MTU3_TGRF] = _tgrf, \
114
+
[RZ_MTU3_TADCR] = _tadcr, \
115
+
[RZ_MTU3_TADCORA] = _tadcora, \
116
+
[RZ_MTU3_TADCORB] = _tadcorb, \
117
+
[RZ_MTU3_TADCOBRA] = _tadcobra, \
118
+
[RZ_MTU3_TADCOBRB] = _tadcobrb \
119
+
}
120
+
121
+
#define MTU_16BIT_CH_5(_tcntu, _tgru, _tcntv, _tgrv, _tcntw, _tgrw) \
122
+
{ \
123
+
[RZ_MTU3_TCNTU] = _tcntu, \
124
+
[RZ_MTU3_TGRU] = _tgru, \
125
+
[RZ_MTU3_TCNTV] = _tcntv, \
126
+
[RZ_MTU3_TGRV] = _tgrv, \
127
+
[RZ_MTU3_TCNTW] = _tcntw, \
128
+
[RZ_MTU3_TGRW] = _tgrw \
129
+
}
130
+
131
+
#define MTU_32BIT_CH_1(_tcntlw, _tgralw, _tgrblw) \
132
+
{ \
133
+
[RZ_MTU3_TCNTLW] = _tcntlw, \
134
+
[RZ_MTU3_TGRALW] = _tgralw, \
135
+
[RZ_MTU3_TGRBLW] = _tgrblw \
136
+
}
137
+
138
+
#define MTU_32BIT_CH_8(_tcnt, _tgra, _tgrb, _tgrc, _tgrd) \
139
+
{ \
140
+
[RZ_MTU3_TCNT] = _tcnt, \
141
+
[RZ_MTU3_TGRA] = _tgra, \
142
+
[RZ_MTU3_TGRB] = _tgrb, \
143
+
[RZ_MTU3_TGRC] = _tgrc, \
144
+
[RZ_MTU3_TGRD] = _tgrd \
145
+
}
146
+
147
+
#endif
-46
drivers/mfd/sec-core.c
-46
drivers/mfd/sec-core.c
···
24
24
#include <linux/mfd/samsung/s2mps14.h>
25
25
#include <linux/mfd/samsung/s2mps15.h>
26
26
#include <linux/mfd/samsung/s2mpu02.h>
27
-
#include <linux/mfd/samsung/s5m8763.h>
28
27
#include <linux/mfd/samsung/s5m8767.h>
29
28
#include <linux/regmap.h>
30
-
31
-
static const struct mfd_cell s5m8751_devs[] = {
32
-
{ .name = "s5m8751-pmic", },
33
-
{ .name = "s5m-charger", },
34
-
{ .name = "s5m8751-codec", },
35
-
};
36
-
37
-
static const struct mfd_cell s5m8763_devs[] = {
38
-
{ .name = "s5m8763-pmic", },
39
-
{ .name = "s5m-rtc", },
40
-
{ .name = "s5m-charger", },
41
-
};
42
29
43
30
static const struct mfd_cell s5m8767_devs[] = {
44
31
{ .name = "s5m8767-pmic", },
···
145
158
}
146
159
}
147
160
148
-
static bool s5m8763_volatile(struct device *dev, unsigned int reg)
149
-
{
150
-
switch (reg) {
151
-
case S5M8763_REG_IRQM1:
152
-
case S5M8763_REG_IRQM2:
153
-
case S5M8763_REG_IRQM3:
154
-
case S5M8763_REG_IRQM4:
155
-
return false;
156
-
default:
157
-
return true;
158
-
}
159
-
}
160
-
161
161
static const struct regmap_config sec_regmap_config = {
162
162
.reg_bits = 8,
163
163
.val_bits = 8,
···
201
227
202
228
.max_register = S2MPU02_REG_DVSDATA,
203
229
.volatile_reg = s2mpu02_volatile,
204
-
.cache_type = REGCACHE_FLAT,
205
-
};
206
-
207
-
static const struct regmap_config s5m8763_regmap_config = {
208
-
.reg_bits = 8,
209
-
.val_bits = 8,
210
-
211
-
.max_register = S5M8763_REG_LBCNFG2,
212
-
.volatile_reg = s5m8763_volatile,
213
230
.cache_type = REGCACHE_FLAT,
214
231
};
215
232
···
313
348
case S2MPS15X:
314
349
regmap = &s2mps15_regmap_config;
315
350
break;
316
-
case S5M8763X:
317
-
regmap = &s5m8763_regmap_config;
318
-
break;
319
351
case S5M8767X:
320
352
regmap = &s5m8767_regmap_config;
321
353
break;
···
337
375
pm_runtime_set_active(sec_pmic->dev);
338
376
339
377
switch (sec_pmic->device_type) {
340
-
case S5M8751X:
341
-
sec_devs = s5m8751_devs;
342
-
num_sec_devs = ARRAY_SIZE(s5m8751_devs);
343
-
break;
344
-
case S5M8763X:
345
-
sec_devs = s5m8763_devs;
346
-
num_sec_devs = ARRAY_SIZE(s5m8763_devs);
347
-
break;
348
378
case S5M8767X:
349
379
sec_devs = s5m8767_devs;
350
380
num_sec_devs = ARRAY_SIZE(s5m8767_devs);
-89
drivers/mfd/sec-irq.c
-89
drivers/mfd/sec-irq.c
···
14
14
#include <linux/mfd/samsung/s2mps11.h>
15
15
#include <linux/mfd/samsung/s2mps14.h>
16
16
#include <linux/mfd/samsung/s2mpu02.h>
17
-
#include <linux/mfd/samsung/s5m8763.h>
18
17
#include <linux/mfd/samsung/s5m8767.h>
19
18
20
19
static const struct regmap_irq s2mps11_irqs[] = {
···
296
297
},
297
298
};
298
299
299
-
static const struct regmap_irq s5m8763_irqs[] = {
300
-
[S5M8763_IRQ_DCINF] = {
301
-
.reg_offset = 0,
302
-
.mask = S5M8763_IRQ_DCINF_MASK,
303
-
},
304
-
[S5M8763_IRQ_DCINR] = {
305
-
.reg_offset = 0,
306
-
.mask = S5M8763_IRQ_DCINR_MASK,
307
-
},
308
-
[S5M8763_IRQ_JIGF] = {
309
-
.reg_offset = 0,
310
-
.mask = S5M8763_IRQ_JIGF_MASK,
311
-
},
312
-
[S5M8763_IRQ_JIGR] = {
313
-
.reg_offset = 0,
314
-
.mask = S5M8763_IRQ_JIGR_MASK,
315
-
},
316
-
[S5M8763_IRQ_PWRONF] = {
317
-
.reg_offset = 0,
318
-
.mask = S5M8763_IRQ_PWRONF_MASK,
319
-
},
320
-
[S5M8763_IRQ_PWRONR] = {
321
-
.reg_offset = 0,
322
-
.mask = S5M8763_IRQ_PWRONR_MASK,
323
-
},
324
-
[S5M8763_IRQ_WTSREVNT] = {
325
-
.reg_offset = 1,
326
-
.mask = S5M8763_IRQ_WTSREVNT_MASK,
327
-
},
328
-
[S5M8763_IRQ_SMPLEVNT] = {
329
-
.reg_offset = 1,
330
-
.mask = S5M8763_IRQ_SMPLEVNT_MASK,
331
-
},
332
-
[S5M8763_IRQ_ALARM1] = {
333
-
.reg_offset = 1,
334
-
.mask = S5M8763_IRQ_ALARM1_MASK,
335
-
},
336
-
[S5M8763_IRQ_ALARM0] = {
337
-
.reg_offset = 1,
338
-
.mask = S5M8763_IRQ_ALARM0_MASK,
339
-
},
340
-
[S5M8763_IRQ_ONKEY1S] = {
341
-
.reg_offset = 2,
342
-
.mask = S5M8763_IRQ_ONKEY1S_MASK,
343
-
},
344
-
[S5M8763_IRQ_TOPOFFR] = {
345
-
.reg_offset = 2,
346
-
.mask = S5M8763_IRQ_TOPOFFR_MASK,
347
-
},
348
-
[S5M8763_IRQ_DCINOVPR] = {
349
-
.reg_offset = 2,
350
-
.mask = S5M8763_IRQ_DCINOVPR_MASK,
351
-
},
352
-
[S5M8763_IRQ_CHGRSTF] = {
353
-
.reg_offset = 2,
354
-
.mask = S5M8763_IRQ_CHGRSTF_MASK,
355
-
},
356
-
[S5M8763_IRQ_DONER] = {
357
-
.reg_offset = 2,
358
-
.mask = S5M8763_IRQ_DONER_MASK,
359
-
},
360
-
[S5M8763_IRQ_CHGFAULT] = {
361
-
.reg_offset = 2,
362
-
.mask = S5M8763_IRQ_CHGFAULT_MASK,
363
-
},
364
-
[S5M8763_IRQ_LOBAT1] = {
365
-
.reg_offset = 3,
366
-
.mask = S5M8763_IRQ_LOBAT1_MASK,
367
-
},
368
-
[S5M8763_IRQ_LOBAT2] = {
369
-
.reg_offset = 3,
370
-
.mask = S5M8763_IRQ_LOBAT2_MASK,
371
-
},
372
-
};
373
-
374
300
static const struct regmap_irq_chip s2mps11_irq_chip = {
375
301
.name = "s2mps11",
376
302
.irqs = s2mps11_irqs,
···
349
425
.ack_base = S5M8767_REG_INT1,
350
426
};
351
427
352
-
static const struct regmap_irq_chip s5m8763_irq_chip = {
353
-
.name = "s5m8763",
354
-
.irqs = s5m8763_irqs,
355
-
.num_irqs = ARRAY_SIZE(s5m8763_irqs),
356
-
.num_regs = 4,
357
-
.status_base = S5M8763_REG_IRQ1,
358
-
.mask_base = S5M8763_REG_IRQM1,
359
-
.ack_base = S5M8763_REG_IRQ1,
360
-
};
361
-
362
428
int sec_irq_init(struct sec_pmic_dev *sec_pmic)
363
429
{
364
430
int ret = 0;
···
362
448
}
363
449
364
450
switch (type) {
365
-
case S5M8763X:
366
-
sec_irq_chip = &s5m8763_irq_chip;
367
-
break;
368
451
case S5M8767X:
369
452
sec_irq_chip = &s5m8767_irq_chip;
370
453
break;
+7
-7
drivers/mfd/si476x-cmd.c
+7
-7
drivers/mfd/si476x-cmd.c
···
251
251
* @usecs: amount of time to wait before reading the response (in
252
252
* usecs)
253
253
*
254
-
* Function returns 0 on succsess and negative error code on
254
+
* Function returns 0 on success and negative error code on
255
255
* failure
256
256
*/
257
257
static int si476x_core_send_command(struct si476x_core *core,
···
398
398
* The command requests the firmware and patch version for currently
399
399
* loaded firmware (dependent on the function of the device FM/AM/WB)
400
400
*
401
-
* Function returns 0 on succsess and negative error code on
401
+
* Function returns 0 on success and negative error code on
402
402
* failure
403
403
*/
404
404
int si476x_core_cmd_func_info(struct si476x_core *core,
···
429
429
* @property: property address
430
430
* @value: property value
431
431
*
432
-
* Function returns 0 on succsess and negative error code on
432
+
* Function returns 0 on success and negative error code on
433
433
* failure
434
434
*/
435
435
int si476x_core_cmd_set_property(struct si476x_core *core,
···
545
545
* SI476X_IQCLK_NOOP - do not modify the behaviour
546
546
* SI476X_IQCLK_TRISTATE - put the pin in tristate condition,
547
547
* enable 1MOhm pulldown
548
-
* SI476X_IQCLK_IQ - set pin to be a part of I/Q interace
548
+
* SI476X_IQCLK_IQ - set pin to be a part of I/Q interface
549
549
* in master mode
550
550
* @iqfs: - IQFS pin function configuration:
551
551
* SI476X_IQFS_NOOP - do not modify the behaviour
552
552
* SI476X_IQFS_TRISTATE - put the pin in tristate condition,
553
553
* enable 1MOhm pulldown
554
-
* SI476X_IQFS_IQ - set pin to be a part of I/Q interace
554
+
* SI476X_IQFS_IQ - set pin to be a part of I/Q interface
555
555
* in master mode
556
556
* @iout: - IOUT pin function configuration:
557
557
* SI476X_IOUT_NOOP - do not modify the behaviour
···
589
589
590
590
/**
591
591
* si476x_core_cmd_ic_link_gpo_ctl_pin_cfg - send
592
-
* 'IC_LINK_GPIO_CTL_PIN_CFG' comand to the device
592
+
* 'IC_LINK_GPIO_CTL_PIN_CFG' command to the device
593
593
* @core: - device to send the command to
594
594
* @icin: - ICIN pin function configuration:
595
595
* SI476X_ICIN_NOOP - do not modify the behaviour
···
1014
1014
* NOTE caller must hold core lock
1015
1015
*
1016
1016
* Function returns the value of the status bit in case of success and
1017
-
* negative error code in case of failre.
1017
+
* negative error code in case of failure.
1018
1018
*/
1019
1019
int si476x_core_cmd_fm_phase_div_status(struct si476x_core *core)
1020
1020
{
+13
drivers/mfd/simple-mfd-i2c.c
+13
drivers/mfd/simple-mfd-i2c.c
···
72
72
.mfd_cell_size = ARRAY_SIZE(sy7636a_cells),
73
73
};
74
74
75
+
static const struct mfd_cell max597x_cells[] = {
76
+
{ .name = "max597x-regulator", },
77
+
{ .name = "max597x-iio", },
78
+
{ .name = "max597x-led", },
79
+
};
80
+
81
+
static const struct simple_mfd_data maxim_max597x = {
82
+
.mfd_cell = max597x_cells,
83
+
.mfd_cell_size = ARRAY_SIZE(max597x_cells),
84
+
};
85
+
75
86
static const struct of_device_id simple_mfd_i2c_of_match[] = {
76
87
{ .compatible = "kontron,sl28cpld" },
77
88
{ .compatible = "silergy,sy7636a", .data = &silergy_sy7636a},
89
+
{ .compatible = "maxim,max5970", .data = &maxim_max597x},
90
+
{ .compatible = "maxim,max5978", .data = &maxim_max597x},
78
91
{}
79
92
};
80
93
MODULE_DEVICE_TABLE(of, simple_mfd_i2c_of_match);
+1
-3
drivers/mfd/ssbi.c
+1
-3
drivers/mfd/ssbi.c
···
262
262
static int ssbi_probe(struct platform_device *pdev)
263
263
{
264
264
struct device_node *np = pdev->dev.of_node;
265
-
struct resource *mem_res;
266
265
struct ssbi *ssbi;
267
266
const char *type;
268
267
···
269
270
if (!ssbi)
270
271
return -ENOMEM;
271
272
272
-
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
273
-
ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res);
273
+
ssbi->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
274
274
if (IS_ERR(ssbi->base))
275
275
return PTR_ERR(ssbi->base);
276
276
-1
drivers/mfd/stmpe-i2c.c
-1
drivers/mfd/stmpe-i2c.c
-1
drivers/mfd/stmpe-spi.c
-1
drivers/mfd/stmpe-spi.c
+1
-1
drivers/mfd/stmpe.c
+1
-1
drivers/mfd/stmpe.c
+1
-3
drivers/mfd/sun4i-gpadc.c
+1
-3
drivers/mfd/sun4i-gpadc.c
···
93
93
static int sun4i_gpadc_probe(struct platform_device *pdev)
94
94
{
95
95
struct sun4i_gpadc_dev *dev;
96
-
struct resource *mem;
97
96
const struct of_device_id *of_id;
98
97
const struct mfd_cell *cells;
99
98
unsigned int irq, size;
···
123
124
if (!dev)
124
125
return -ENOMEM;
125
126
126
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
127
-
dev->base = devm_ioremap_resource(&pdev->dev, mem);
127
+
dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
128
128
if (IS_ERR(dev->base))
129
129
return PTR_ERR(dev->base);
130
130
-1
drivers/mfd/tc3589x.c
-1
drivers/mfd/tc3589x.c
-1
drivers/mfd/tps6586x.c
-1
drivers/mfd/tps6586x.c
+29
-23
drivers/mfd/tqmx86.c
+29
-23
drivers/mfd/tqmx86.c
···
16
16
#include <linux/platform_data/i2c-ocores.h>
17
17
#include <linux/platform_device.h>
18
18
19
-
#define TQMX86_IOBASE 0x160
20
-
#define TQMX86_IOSIZE 0x3f
19
+
#define TQMX86_IOBASE 0x180
20
+
#define TQMX86_IOSIZE 0x20
21
21
#define TQMX86_IOBASE_I2C 0x1a0
22
22
#define TQMX86_IOSIZE_I2C 0xa
23
23
#define TQMX86_IOBASE_WATCHDOG 0x18b
···
25
25
#define TQMX86_IOBASE_GPIO 0x18d
26
26
#define TQMX86_IOSIZE_GPIO 0x4
27
27
28
-
#define TQMX86_REG_BOARD_ID 0x20
28
+
#define TQMX86_REG_BOARD_ID 0x00
29
29
#define TQMX86_REG_BOARD_ID_E38M 1
30
30
#define TQMX86_REG_BOARD_ID_50UC 2
31
31
#define TQMX86_REG_BOARD_ID_E38C 3
32
32
#define TQMX86_REG_BOARD_ID_60EB 4
33
-
#define TQMX86_REG_BOARD_ID_E39M 5
34
-
#define TQMX86_REG_BOARD_ID_E39C 6
35
-
#define TQMX86_REG_BOARD_ID_E39x 7
33
+
#define TQMX86_REG_BOARD_ID_E39MS 5
34
+
#define TQMX86_REG_BOARD_ID_E39C1 6
35
+
#define TQMX86_REG_BOARD_ID_E39C2 7
36
36
#define TQMX86_REG_BOARD_ID_70EB 8
37
37
#define TQMX86_REG_BOARD_ID_80UC 9
38
38
#define TQMX86_REG_BOARD_ID_110EB 11
···
40
40
#define TQMX86_REG_BOARD_ID_E40S 13
41
41
#define TQMX86_REG_BOARD_ID_E40C1 14
42
42
#define TQMX86_REG_BOARD_ID_E40C2 15
43
-
#define TQMX86_REG_BOARD_REV 0x21
44
-
#define TQMX86_REG_IO_EXT_INT 0x26
43
+
#define TQMX86_REG_BOARD_REV 0x01
44
+
#define TQMX86_REG_IO_EXT_INT 0x06
45
45
#define TQMX86_REG_IO_EXT_INT_NONE 0
46
46
#define TQMX86_REG_IO_EXT_INT_7 1
47
47
#define TQMX86_REG_IO_EXT_INT_9 2
48
48
#define TQMX86_REG_IO_EXT_INT_12 3
49
49
#define TQMX86_REG_IO_EXT_INT_MASK 0x3
50
50
#define TQMX86_REG_IO_EXT_INT_GPIO_SHIFT 4
51
+
#define TQMX86_REG_SAUC 0x17
51
52
52
-
#define TQMX86_REG_I2C_DETECT 0x47
53
+
#define TQMX86_REG_I2C_DETECT 0x1a7
53
54
#define TQMX86_REG_I2C_DETECT_SOFT 0xa5
54
-
#define TQMX86_REG_I2C_INT_EN 0x49
55
55
56
56
static uint gpio_irq;
57
57
module_param(gpio_irq, uint, 0);
···
111
111
},
112
112
};
113
113
114
-
static const char *tqmx86_board_id_to_name(u8 board_id)
114
+
static const char *tqmx86_board_id_to_name(u8 board_id, u8 sauc)
115
115
{
116
116
switch (board_id) {
117
117
case TQMX86_REG_BOARD_ID_E38M:
···
122
122
return "TQMxE38C";
123
123
case TQMX86_REG_BOARD_ID_60EB:
124
124
return "TQMx60EB";
125
-
case TQMX86_REG_BOARD_ID_E39M:
126
-
return "TQMxE39M";
127
-
case TQMX86_REG_BOARD_ID_E39C:
128
-
return "TQMxE39C";
129
-
case TQMX86_REG_BOARD_ID_E39x:
130
-
return "TQMxE39x";
125
+
case TQMX86_REG_BOARD_ID_E39MS:
126
+
return (sauc == 0xff) ? "TQMxE39M" : "TQMxE39S";
127
+
case TQMX86_REG_BOARD_ID_E39C1:
128
+
return "TQMxE39C1";
129
+
case TQMX86_REG_BOARD_ID_E39C2:
130
+
return "TQMxE39C2";
131
131
case TQMX86_REG_BOARD_ID_70EB:
132
132
return "TQMx70EB";
133
133
case TQMX86_REG_BOARD_ID_80UC:
···
160
160
case TQMX86_REG_BOARD_ID_E40C1:
161
161
case TQMX86_REG_BOARD_ID_E40C2:
162
162
return 24000;
163
-
case TQMX86_REG_BOARD_ID_E39M:
164
-
case TQMX86_REG_BOARD_ID_E39C:
165
-
case TQMX86_REG_BOARD_ID_E39x:
163
+
case TQMX86_REG_BOARD_ID_E39MS:
164
+
case TQMX86_REG_BOARD_ID_E39C1:
165
+
case TQMX86_REG_BOARD_ID_E39C2:
166
166
return 25000;
167
167
case TQMX86_REG_BOARD_ID_E38M:
168
168
case TQMX86_REG_BOARD_ID_E38C:
···
176
176
177
177
static int tqmx86_probe(struct platform_device *pdev)
178
178
{
179
-
u8 board_id, rev, i2c_det, io_ext_int_val;
179
+
u8 board_id, sauc, rev, i2c_det, io_ext_int_val;
180
180
struct device *dev = &pdev->dev;
181
181
u8 gpio_irq_cfg, readback;
182
182
const char *board_name;
···
206
206
return -ENOMEM;
207
207
208
208
board_id = ioread8(io_base + TQMX86_REG_BOARD_ID);
209
-
board_name = tqmx86_board_id_to_name(board_id);
209
+
sauc = ioread8(io_base + TQMX86_REG_SAUC);
210
+
board_name = tqmx86_board_id_to_name(board_id, sauc);
210
211
rev = ioread8(io_base + TQMX86_REG_BOARD_REV);
211
212
212
213
dev_info(dev,
213
214
"Found %s - Board ID %d, PCB Revision %d, PLD Revision %d\n",
214
215
board_name, board_id, rev >> 4, rev & 0xf);
215
216
216
-
i2c_det = ioread8(io_base + TQMX86_REG_I2C_DETECT);
217
+
/*
218
+
* The I2C_DETECT register is in the range assigned to the I2C driver
219
+
* later, so we don't extend TQMX86_IOSIZE. Use inb() for this one-off
220
+
* access instead of ioport_map + unmap.
221
+
*/
222
+
i2c_det = inb(TQMX86_REG_I2C_DETECT);
217
223
218
224
if (gpio_irq_cfg) {
219
225
io_ext_int_val =
-65
drivers/mfd/twl-core.c
-65
drivers/mfd/twl-core.c
···
594
594
}
595
595
EXPORT_SYMBOL_GPL(twl_get_hfclk_rate);
596
596
597
-
static struct device *
598
-
add_numbered_child(unsigned mod_no, const char *name, int num,
599
-
void *pdata, unsigned pdata_len,
600
-
bool can_wakeup, int irq0, int irq1)
601
-
{
602
-
struct platform_device *pdev;
603
-
struct twl_client *twl;
604
-
int status, sid;
605
-
606
-
if (unlikely(mod_no >= twl_get_last_module())) {
607
-
pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
608
-
return ERR_PTR(-EPERM);
609
-
}
610
-
sid = twl_priv->twl_map[mod_no].sid;
611
-
twl = &twl_priv->twl_modules[sid];
612
-
613
-
pdev = platform_device_alloc(name, num);
614
-
if (!pdev)
615
-
return ERR_PTR(-ENOMEM);
616
-
617
-
pdev->dev.parent = &twl->client->dev;
618
-
619
-
if (pdata) {
620
-
status = platform_device_add_data(pdev, pdata, pdata_len);
621
-
if (status < 0) {
622
-
dev_dbg(&pdev->dev, "can't add platform_data\n");
623
-
goto put_device;
624
-
}
625
-
}
626
-
627
-
if (irq0) {
628
-
struct resource r[2] = {
629
-
{ .start = irq0, .flags = IORESOURCE_IRQ, },
630
-
{ .start = irq1, .flags = IORESOURCE_IRQ, },
631
-
};
632
-
633
-
status = platform_device_add_resources(pdev, r, irq1 ? 2 : 1);
634
-
if (status < 0) {
635
-
dev_dbg(&pdev->dev, "can't add irqs\n");
636
-
goto put_device;
637
-
}
638
-
}
639
-
640
-
status = platform_device_add(pdev);
641
-
if (status)
642
-
goto put_device;
643
-
644
-
device_init_wakeup(&pdev->dev, can_wakeup);
645
-
646
-
return &pdev->dev;
647
-
648
-
put_device:
649
-
platform_device_put(pdev);
650
-
dev_err(&twl->client->dev, "failed to add device %s\n", name);
651
-
return ERR_PTR(status);
652
-
}
653
-
654
-
static inline struct device *add_child(unsigned mod_no, const char *name,
655
-
void *pdata, unsigned pdata_len,
656
-
bool can_wakeup, int irq0, int irq1)
657
-
{
658
-
return add_numbered_child(mod_no, name, -1, pdata, pdata_len,
659
-
can_wakeup, irq0, irq1);
660
-
}
661
-
662
597
/*----------------------------------------------------------------------*/
663
598
664
599
/*
-1
drivers/mfd/twl4030-audio.c
-1
drivers/mfd/twl4030-audio.c
-1
drivers/mfd/twl6040.c
-1
drivers/mfd/twl6040.c
+5
-14
drivers/mfd/wm8994-core.c
+5
-14
drivers/mfd/wm8994-core.c
···
279
279
of_property_read_u32_array(np, "wlf,micbias-cfg", pdata->micbias,
280
280
ARRAY_SIZE(pdata->micbias));
281
281
282
-
pdata->lineout1_diff = true;
283
-
pdata->lineout2_diff = true;
284
-
if (of_find_property(np, "wlf,lineout1-se", NULL))
285
-
pdata->lineout1_diff = false;
286
-
if (of_find_property(np, "wlf,lineout2-se", NULL))
287
-
pdata->lineout2_diff = false;
288
-
289
-
if (of_find_property(np, "wlf,lineout1-feedback", NULL))
290
-
pdata->lineout1fb = true;
291
-
if (of_find_property(np, "wlf,lineout2-feedback", NULL))
292
-
pdata->lineout2fb = true;
293
-
294
-
if (of_find_property(np, "wlf,ldoena-always-driven", NULL))
295
-
pdata->lineout2fb = true;
282
+
pdata->lineout1_diff = !of_property_read_bool(np, "wlf,lineout1-se");
283
+
pdata->lineout2_diff = !of_property_read_bool(np, "wlf,lineout2-se");
284
+
pdata->lineout1fb = of_property_read_bool(np, "wlf,lineout1-feedback");
285
+
pdata->lineout2fb = of_property_read_bool(np, "wlf,lineout2-feedback") ||
286
+
of_property_read_bool(np, "wlf,ldoena-always-driven");
296
287
297
288
pdata->spkmode_pu = of_property_read_bool(np, "wlf,spkmode-pu");
298
289
+3
-79
drivers/rtc/rtc-s5m.c
+3
-79
drivers/rtc/rtc-s5m.c
···
85
85
unsigned int write_alarm_udr_mask;
86
86
};
87
87
88
-
/* Register map for S5M8763 and S5M8767 */
88
+
/* Register map for S5M8767 */
89
89
static const struct s5m_rtc_reg_config s5m_rtc_regs = {
90
90
.regs_count = 8,
91
91
.time = S5M_RTC_SEC,
···
236
236
237
237
switch (info->device_type) {
238
238
case S5M8767X:
239
-
case S5M8763X:
240
239
ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val);
241
240
val &= S5M_ALARM0_STATUS;
242
241
break;
···
298
299
299
300
data |= info->regs->write_alarm_udr_mask;
300
301
switch (info->device_type) {
301
-
case S5M8763X:
302
302
case S5M8767X:
303
303
data &= ~S5M_RTC_TIME_EN_MASK;
304
304
break;
···
327
329
return ret;
328
330
}
329
331
330
-
static void s5m8763_data_to_tm(u8 *data, struct rtc_time *tm)
331
-
{
332
-
tm->tm_sec = bcd2bin(data[RTC_SEC]);
333
-
tm->tm_min = bcd2bin(data[RTC_MIN]);
334
-
335
-
if (data[RTC_HOUR] & HOUR_12) {
336
-
tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x1f);
337
-
if (data[RTC_HOUR] & HOUR_PM)
338
-
tm->tm_hour += 12;
339
-
} else {
340
-
tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3f);
341
-
}
342
-
343
-
tm->tm_wday = data[RTC_WEEKDAY] & 0x07;
344
-
tm->tm_mday = bcd2bin(data[RTC_DATE]);
345
-
tm->tm_mon = bcd2bin(data[RTC_MONTH]);
346
-
tm->tm_year = bcd2bin(data[RTC_YEAR1]) + bcd2bin(data[RTC_YEAR2]) * 100;
347
-
tm->tm_year -= 1900;
348
-
}
349
-
350
-
static void s5m8763_tm_to_data(struct rtc_time *tm, u8 *data)
351
-
{
352
-
data[RTC_SEC] = bin2bcd(tm->tm_sec);
353
-
data[RTC_MIN] = bin2bcd(tm->tm_min);
354
-
data[RTC_HOUR] = bin2bcd(tm->tm_hour);
355
-
data[RTC_WEEKDAY] = tm->tm_wday;
356
-
data[RTC_DATE] = bin2bcd(tm->tm_mday);
357
-
data[RTC_MONTH] = bin2bcd(tm->tm_mon);
358
-
data[RTC_YEAR1] = bin2bcd(tm->tm_year % 100);
359
-
data[RTC_YEAR2] = bin2bcd((tm->tm_year + 1900) / 100);
360
-
}
361
-
362
332
static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm)
363
333
{
364
334
struct s5m_rtc_info *info = dev_get_drvdata(dev);
···
351
385
return ret;
352
386
353
387
switch (info->device_type) {
354
-
case S5M8763X:
355
-
s5m8763_data_to_tm(data, tm);
356
-
break;
357
-
358
388
case S5M8767X:
359
389
case S2MPS15X:
360
390
case S2MPS14X:
···
374
412
int ret = 0;
375
413
376
414
switch (info->device_type) {
377
-
case S5M8763X:
378
-
s5m8763_tm_to_data(tm, data);
379
-
break;
380
415
case S5M8767X:
381
416
case S2MPS15X:
382
417
case S2MPS14X:
···
403
444
{
404
445
struct s5m_rtc_info *info = dev_get_drvdata(dev);
405
446
u8 data[RTC_MAX_NUM_TIME_REGS];
406
-
unsigned int val;
407
447
int ret, i;
408
448
409
449
ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
···
411
453
return ret;
412
454
413
455
switch (info->device_type) {
414
-
case S5M8763X:
415
-
s5m8763_data_to_tm(data, &alrm->time);
416
-
ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val);
417
-
if (ret < 0)
418
-
return ret;
419
-
420
-
alrm->enabled = !!val;
421
-
break;
422
-
423
456
case S5M8767X:
424
457
case S2MPS15X:
425
458
case S2MPS14X:
···
449
500
dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
450
501
451
502
switch (info->device_type) {
452
-
case S5M8763X:
453
-
ret = regmap_write(info->regmap, S5M_ALARM0_CONF, 0);
454
-
break;
455
-
456
503
case S5M8767X:
457
504
case S2MPS15X:
458
505
case S2MPS14X:
···
476
531
{
477
532
int ret;
478
533
u8 data[RTC_MAX_NUM_TIME_REGS];
479
-
u8 alarm0_conf;
480
534
struct rtc_time tm;
481
535
482
536
ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
···
487
543
dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
488
544
489
545
switch (info->device_type) {
490
-
case S5M8763X:
491
-
alarm0_conf = 0x77;
492
-
ret = regmap_write(info->regmap, S5M_ALARM0_CONF, alarm0_conf);
493
-
break;
494
-
495
546
case S5M8767X:
496
547
case S2MPS15X:
497
548
case S2MPS14X:
···
524
585
int ret;
525
586
526
587
switch (info->device_type) {
527
-
case S5M8763X:
528
-
s5m8763_tm_to_data(&alrm->time, data);
529
-
break;
530
-
531
588
case S5M8767X:
532
589
case S2MPS15X:
533
590
case S2MPS14X:
···
590
655
int ret;
591
656
592
657
switch (info->device_type) {
593
-
case S5M8763X:
594
658
case S5M8767X:
595
659
/* UDR update time. Default of 7.32 ms is too long. */
596
660
ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON,
···
663
729
info->regs = &s2mps13_rtc_regs;
664
730
alarm_irq = S2MPS14_IRQ_RTCA0;
665
731
break;
666
-
case S5M8763X:
667
-
regmap_cfg = &s5m_rtc_regmap_config;
668
-
info->regs = &s5m_rtc_regs;
669
-
alarm_irq = S5M8763_IRQ_ALARM0;
670
-
break;
671
732
case S5M8767X:
672
733
regmap_cfg = &s5m_rtc_regmap_config;
673
734
info->regs = &s5m_rtc_regs;
···
715
786
716
787
info->rtc_dev->ops = &s5m_rtc_ops;
717
788
718
-
if (info->device_type == S5M8763X) {
719
-
info->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_0000;
720
-
info->rtc_dev->range_max = RTC_TIMESTAMP_END_9999;
721
-
} else {
722
-
info->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
723
-
info->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
724
-
}
789
+
info->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
790
+
info->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
725
791
726
792
if (!info->irq) {
727
793
clear_bit(RTC_FEATURE_ALARM, info->rtc_dev->features);
-1
include/dt-bindings/mfd/stm32f4-rcc.h
-1
include/dt-bindings/mfd/stm32f4-rcc.h
+85
include/linux/mfd/axp20x.h
+85
include/linux/mfd/axp20x.h
···
21
21
AXP806_ID,
22
22
AXP809_ID,
23
23
AXP813_ID,
24
+
AXP15060_ID,
24
25
NR_AXP20X_VARIANTS,
25
26
};
26
27
···
132
131
/* Other DCDC regulator control registers are the same as AXP803 */
133
132
#define AXP813_DCDC7_V_OUT 0x26
134
133
134
+
#define AXP15060_STARTUP_SRC 0x00
135
+
#define AXP15060_PWR_OUT_CTRL1 0x10
136
+
#define AXP15060_PWR_OUT_CTRL2 0x11
137
+
#define AXP15060_PWR_OUT_CTRL3 0x12
138
+
#define AXP15060_DCDC1_V_CTRL 0x13
139
+
#define AXP15060_DCDC2_V_CTRL 0x14
140
+
#define AXP15060_DCDC3_V_CTRL 0x15
141
+
#define AXP15060_DCDC4_V_CTRL 0x16
142
+
#define AXP15060_DCDC5_V_CTRL 0x17
143
+
#define AXP15060_DCDC6_V_CTRL 0x18
144
+
#define AXP15060_ALDO1_V_CTRL 0x19
145
+
#define AXP15060_DCDC_MODE_CTRL1 0x1a
146
+
#define AXP15060_DCDC_MODE_CTRL2 0x1b
147
+
#define AXP15060_OUTPUT_MONITOR_DISCHARGE 0x1e
148
+
#define AXP15060_IRQ_PWROK_VOFF 0x1f
149
+
#define AXP15060_ALDO2_V_CTRL 0x20
150
+
#define AXP15060_ALDO3_V_CTRL 0x21
151
+
#define AXP15060_ALDO4_V_CTRL 0x22
152
+
#define AXP15060_ALDO5_V_CTRL 0x23
153
+
#define AXP15060_BLDO1_V_CTRL 0x24
154
+
#define AXP15060_BLDO2_V_CTRL 0x25
155
+
#define AXP15060_BLDO3_V_CTRL 0x26
156
+
#define AXP15060_BLDO4_V_CTRL 0x27
157
+
#define AXP15060_BLDO5_V_CTRL 0x28
158
+
#define AXP15060_CLDO1_V_CTRL 0x29
159
+
#define AXP15060_CLDO2_V_CTRL 0x2a
160
+
#define AXP15060_CLDO3_V_CTRL 0x2b
161
+
#define AXP15060_CLDO4_V_CTRL 0x2d
162
+
#define AXP15060_CPUSLDO_V_CTRL 0x2e
163
+
#define AXP15060_PWR_WAKEUP_CTRL 0x31
164
+
#define AXP15060_PWR_DISABLE_DOWN_SEQ 0x32
165
+
#define AXP15060_PEK_KEY 0x36
166
+
135
167
/* Interrupt */
136
168
#define AXP152_IRQ1_EN 0x40
137
169
#define AXP152_IRQ2_EN 0x41
···
185
151
#define AXP20X_IRQ4_STATE 0x4b
186
152
#define AXP20X_IRQ5_STATE 0x4c
187
153
#define AXP20X_IRQ6_STATE 0x4d
154
+
155
+
#define AXP15060_IRQ1_EN 0x40
156
+
#define AXP15060_IRQ2_EN 0x41
157
+
#define AXP15060_IRQ1_STATE 0x48
158
+
#define AXP15060_IRQ2_STATE 0x49
188
159
189
160
/* ADC */
190
161
#define AXP20X_ACIN_V_ADC_H 0x56
···
260
221
#define AXP22X_LDO_IO1_V_OUT 0x93
261
222
#define AXP22X_GPIO_STATE 0x94
262
223
#define AXP22X_GPIO_PULL_DOWN 0x95
224
+
225
+
#define AXP15060_CLDO4_GPIO2_MODESET 0x2c
263
226
264
227
/* Battery */
265
228
#define AXP20X_CHRG_CC_31_24 0xb0
···
458
417
AXP813_LDO_IO1,
459
418
AXP813_SW,
460
419
AXP813_REG_ID_MAX,
420
+
};
421
+
422
+
enum {
423
+
AXP15060_DCDC1 = 0,
424
+
AXP15060_DCDC2,
425
+
AXP15060_DCDC3,
426
+
AXP15060_DCDC4,
427
+
AXP15060_DCDC5,
428
+
AXP15060_DCDC6,
429
+
AXP15060_ALDO1,
430
+
AXP15060_ALDO2,
431
+
AXP15060_ALDO3,
432
+
AXP15060_ALDO4,
433
+
AXP15060_ALDO5,
434
+
AXP15060_BLDO1,
435
+
AXP15060_BLDO2,
436
+
AXP15060_BLDO3,
437
+
AXP15060_BLDO4,
438
+
AXP15060_BLDO5,
439
+
AXP15060_CLDO1,
440
+
AXP15060_CLDO2,
441
+
AXP15060_CLDO3,
442
+
AXP15060_CLDO4,
443
+
AXP15060_CPUSLDO,
444
+
AXP15060_SW,
445
+
AXP15060_RTC_LDO,
446
+
AXP15060_REG_ID_MAX,
461
447
};
462
448
463
449
/* IRQs */
···
703
635
AXP809_IRQ_PEK_OVER_OFF,
704
636
AXP809_IRQ_GPIO1_INPUT,
705
637
AXP809_IRQ_GPIO0_INPUT,
638
+
};
639
+
640
+
enum axp15060_irqs {
641
+
AXP15060_IRQ_DIE_TEMP_HIGH_LV1 = 1,
642
+
AXP15060_IRQ_DIE_TEMP_HIGH_LV2,
643
+
AXP15060_IRQ_DCDC1_V_LOW,
644
+
AXP15060_IRQ_DCDC2_V_LOW,
645
+
AXP15060_IRQ_DCDC3_V_LOW,
646
+
AXP15060_IRQ_DCDC4_V_LOW,
647
+
AXP15060_IRQ_DCDC5_V_LOW,
648
+
AXP15060_IRQ_DCDC6_V_LOW,
649
+
AXP15060_IRQ_PEK_LONG,
650
+
AXP15060_IRQ_PEK_SHORT,
651
+
AXP15060_IRQ_GPIO1_INPUT,
652
+
AXP15060_IRQ_PEK_FAL_EDGE,
653
+
AXP15060_IRQ_PEK_RIS_EDGE,
654
+
AXP15060_IRQ_GPIO2_INPUT,
706
655
};
707
656
708
657
struct axp20x_dev {
+4
-16
include/linux/mfd/core.h
+4
-16
include/linux/mfd/core.h
···
68
68
int id;
69
69
int level;
70
70
71
-
int (*enable)(struct platform_device *dev);
72
-
int (*disable)(struct platform_device *dev);
73
-
74
71
int (*suspend)(struct platform_device *dev);
75
72
int (*resume)(struct platform_device *dev);
76
73
77
74
/* platform data passed to the sub devices drivers */
78
75
void *platform_data;
79
76
size_t pdata_size;
77
+
78
+
/* Matches ACPI */
79
+
const struct mfd_cell_acpi_match *acpi_match;
80
80
81
81
/* Software node for the device. */
82
82
const struct software_node *swnode;
···
97
97
/* Set to 'true' to use 'of_reg' (above) - allows for of_reg=0 */
98
98
bool use_of_reg;
99
99
100
-
/* Matches ACPI */
101
-
const struct mfd_cell_acpi_match *acpi_match;
102
-
103
100
/*
104
101
* These resources can be specified relative to the parent device.
105
102
* For accessing hardware you should use resources from the platform dev
···
116
119
/* A list of regulator supplies that should be mapped to the MFD
117
120
* device rather than the child device when requested
118
121
*/
119
-
const char * const *parent_supplies;
120
122
int num_parent_supplies;
123
+
const char * const *parent_supplies;
121
124
};
122
-
123
-
/*
124
-
* Convenience functions for clients using shared cells. Refcounting
125
-
* happens automatically, with the cell's enable/disable callbacks
126
-
* being called only when a device is first being enabled or no other
127
-
* clients are making use of it.
128
-
*/
129
-
extern int mfd_cell_enable(struct platform_device *pdev);
130
-
extern int mfd_cell_disable(struct platform_device *pdev);
131
125
132
126
/*
133
127
* Given a platform device that's been created by mfd_add_devices(), fetch
+96
include/linux/mfd/max597x.h
+96
include/linux/mfd/max597x.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Device driver for regulators in MAX5970 and MAX5978 IC
4
+
*
5
+
* Copyright (c) 2022 9elements GmbH
6
+
*
7
+
* Author: Patrick Rudolph <patrick.rudolph@9elements.com>
8
+
*/
9
+
10
+
#ifndef _MFD_MAX597X_H
11
+
#define _MFD_MAX597X_H
12
+
13
+
#include <linux/regmap.h>
14
+
15
+
#define MAX5970_NUM_SWITCHES 2
16
+
#define MAX5978_NUM_SWITCHES 1
17
+
#define MAX597X_NUM_LEDS 4
18
+
19
+
struct max597x_data {
20
+
int num_switches;
21
+
u32 irng[MAX5970_NUM_SWITCHES];
22
+
u32 mon_rng[MAX5970_NUM_SWITCHES];
23
+
u32 shunt_micro_ohms[MAX5970_NUM_SWITCHES];
24
+
};
25
+
26
+
enum max597x_chip_type {
27
+
MAX597x_TYPE_MAX5978 = 1,
28
+
MAX597x_TYPE_MAX5970,
29
+
};
30
+
31
+
#define MAX5970_REG_CURRENT_L(ch) (0x01 + (ch) * 4)
32
+
#define MAX5970_REG_CURRENT_H(ch) (0x00 + (ch) * 4)
33
+
#define MAX5970_REG_VOLTAGE_L(ch) (0x03 + (ch) * 4)
34
+
#define MAX5970_REG_VOLTAGE_H(ch) (0x02 + (ch) * 4)
35
+
#define MAX5970_REG_MON_RANGE 0x18
36
+
#define MAX5970_MON_MASK 0x3
37
+
#define MAX5970_MON(reg, ch) (((reg) >> ((ch) * 2)) & MAX5970_MON_MASK)
38
+
#define MAX5970_MON_MAX_RANGE_UV 16000000
39
+
40
+
#define MAX5970_REG_CH_UV_WARN_H(ch) (0x1A + (ch) * 10)
41
+
#define MAX5970_REG_CH_UV_WARN_L(ch) (0x1B + (ch) * 10)
42
+
#define MAX5970_REG_CH_UV_CRIT_H(ch) (0x1C + (ch) * 10)
43
+
#define MAX5970_REG_CH_UV_CRIT_L(ch) (0x1D + (ch) * 10)
44
+
#define MAX5970_REG_CH_OV_WARN_H(ch) (0x1E + (ch) * 10)
45
+
#define MAX5970_REG_CH_OV_WARN_L(ch) (0x1F + (ch) * 10)
46
+
#define MAX5970_REG_CH_OV_CRIT_H(ch) (0x20 + (ch) * 10)
47
+
#define MAX5970_REG_CH_OV_CRIT_L(ch) (0x21 + (ch) * 10)
48
+
49
+
#define MAX5970_VAL2REG_H(x) (((x) >> 2) & 0xFF)
50
+
#define MAX5970_VAL2REG_L(x) ((x) & 0x3)
51
+
52
+
#define MAX5970_REG_DAC_FAST(ch) (0x2E + (ch))
53
+
54
+
#define MAX5970_FAST2SLOW_RATIO 200
55
+
56
+
#define MAX5970_REG_STATUS0 0x31
57
+
#define MAX5970_CB_IFAULTF(ch) (1 << (ch))
58
+
#define MAX5970_CB_IFAULTS(ch) (1 << ((ch) + 4))
59
+
60
+
#define MAX5970_REG_STATUS1 0x32
61
+
#define STATUS1_PROT_MASK 0x3
62
+
#define STATUS1_PROT(reg) \
63
+
(((reg) >> 6) & STATUS1_PROT_MASK)
64
+
#define STATUS1_PROT_SHUTDOWN 0
65
+
#define STATUS1_PROT_CLEAR_PG 1
66
+
#define STATUS1_PROT_ALERT_ONLY 2
67
+
68
+
#define MAX5970_REG_STATUS2 0x33
69
+
#define MAX5970_IRNG_MASK 0x3
70
+
#define MAX5970_IRNG(reg, ch) \
71
+
(((reg) >> ((ch) * 2)) & MAX5970_IRNG_MASK)
72
+
73
+
#define MAX5970_REG_STATUS3 0x34
74
+
#define MAX5970_STATUS3_ALERT BIT(4)
75
+
#define MAX5970_STATUS3_PG(ch) BIT(ch)
76
+
77
+
#define MAX5970_REG_FAULT0 0x35
78
+
#define UV_STATUS_WARN(ch) (1 << (ch))
79
+
#define UV_STATUS_CRIT(ch) (1 << ((ch) + 4))
80
+
81
+
#define MAX5970_REG_FAULT1 0x36
82
+
#define OV_STATUS_WARN(ch) (1 << (ch))
83
+
#define OV_STATUS_CRIT(ch) (1 << ((ch) + 4))
84
+
85
+
#define MAX5970_REG_FAULT2 0x37
86
+
#define OC_STATUS_WARN(ch) (1 << (ch))
87
+
88
+
#define MAX5970_REG_CHXEN 0x3b
89
+
#define CHXEN(ch) (3 << ((ch) * 2))
90
+
91
+
#define MAX5970_REG_LED_FLASH 0x43
92
+
93
+
#define MAX_REGISTERS 0x49
94
+
#define ADC_MASK 0x3FF
95
+
96
+
#endif /* _MFD_MAX597X_H */
+4
-1
include/linux/mfd/rsmu.h
+4
-1
include/linux/mfd/rsmu.h
···
8
8
#ifndef __LINUX_MFD_RSMU_H
9
9
#define __LINUX_MFD_RSMU_H
10
10
11
+
#define RSMU_MAX_WRITE_COUNT (255)
12
+
#define RSMU_MAX_READ_COUNT (255)
13
+
11
14
/* The supported devices are ClockMatrix, Sabre and SnowLotus */
12
15
enum rsmu_type {
13
16
RSMU_CM = 0x34000,
···
34
31
struct regmap *regmap;
35
32
struct mutex lock;
36
33
enum rsmu_type type;
37
-
u16 page;
34
+
u32 page;
38
35
};
39
36
#endif /* __LINUX_MFD_RSMU_H */
+7
-10
include/linux/mfd/rt5033-private.h
+7
-10
include/linux/mfd/rt5033-private.h
···
107
107
#define RT5033_LDO_CTRL_MASK 0x1f
108
108
109
109
/* RT5033 charger property - model, manufacturer */
110
-
111
110
#define RT5033_CHARGER_MODEL "RT5033WSC Charger"
112
111
#define RT5033_MANUFACTURER "Richtek Technology Corporation"
113
112
114
113
/*
115
-
* RT5033 charger fast-charge current lmits (as in CHGCTRL1 register),
116
-
* AICR mode limits the input current for example,
117
-
* the AIRC 100 mode limits the input current to 100 mA.
114
+
* While RT5033 charger can limit the fast-charge current (as in CHGCTRL1
115
+
* register), AICR mode limits the input current. For example, the AIRC 100
116
+
* mode limits the input current to 100 mA.
118
117
*/
119
118
#define RT5033_AICR_100_MODE 0x20
120
119
#define RT5033_AICR_500_MODE 0x40
···
138
139
#define RT5033_TE_ENABLE_MASK 0x08
139
140
140
141
/*
141
-
* RT5033 charger opa mode. RT50300 have two opa mode charger mode
142
-
* and boost mode for OTG
142
+
* RT5033 charger opa mode. RT5033 has two opa modes for OTG: charger mode
143
+
* and boost mode.
143
144
*/
144
-
145
145
#define RT5033_CHARGER_MODE 0x00
146
146
#define RT5033_BOOST_MODE 0x01
147
147
···
179
181
* RT5033 charger pre-charge threshold volt limits
180
182
* (as in CHGCTRL5 register), uV
181
183
*/
182
-
183
184
#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN 2300000U
184
185
#define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM 100000U
185
186
#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX 3800000U
186
187
187
188
/*
188
-
* RT5033 charger enable UUG, If UUG enable MOS auto control by H/W charger
189
+
* RT5033 charger UUG. It enables MOS auto control by H/W charger
189
190
* circuit.
190
191
*/
191
192
#define RT5033_CHARGER_UUG_ENABLE 0x02
192
193
193
-
/* RT5033 charger High impedance mode */
194
+
/* RT5033 charger high impedance mode */
194
195
#define RT5033_CHARGER_HZ_DISABLE 0x00
195
196
#define RT5033_CHARGER_HZ_ENABLE 0x01
196
197
+3
-4
include/linux/mfd/rt5033.h
+3
-4
include/linux/mfd/rt5033.h
+257
include/linux/mfd/rz-mtu3.h
+257
include/linux/mfd/rz-mtu3.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2022 Renesas Electronics Corporation
4
+
*/
5
+
#ifndef __MFD_RZ_MTU3_H__
6
+
#define __MFD_RZ_MTU3_H__
7
+
8
+
#include <linux/clk.h>
9
+
#include <linux/device.h>
10
+
#include <linux/mutex.h>
11
+
12
+
/* 8-bit shared register offsets macros */
13
+
#define RZ_MTU3_TSTRA 0x080 /* Timer start register A */
14
+
#define RZ_MTU3_TSTRB 0x880 /* Timer start register B */
15
+
16
+
/* 16-bit shared register offset macros */
17
+
#define RZ_MTU3_TDDRA 0x016 /* Timer dead time data register A */
18
+
#define RZ_MTU3_TDDRB 0x816 /* Timer dead time data register B */
19
+
#define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20
+
#define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21
+
#define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22
+
#define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
23
+
#define RZ_MTU3_TCNTSA 0x020 /* Timer subcounter A */
24
+
#define RZ_MTU3_TCNTSB 0x820 /* Timer subcounter B */
25
+
26
+
/*
27
+
* MTU5 contains 3 timer counter registers and is totaly different
28
+
* from other channels, so we must separate its offset
29
+
*/
30
+
31
+
/* 8-bit register offset macros of MTU3 channels except MTU5 */
32
+
#define RZ_MTU3_TIER 0 /* Timer interrupt register */
33
+
#define RZ_MTU3_NFCR 1 /* Noise filter control register */
34
+
#define RZ_MTU3_TSR 2 /* Timer status register */
35
+
#define RZ_MTU3_TCR 3 /* Timer control register */
36
+
#define RZ_MTU3_TCR2 4 /* Timer control register 2 */
37
+
38
+
/* Timer mode register 1 */
39
+
#define RZ_MTU3_TMDR1 5
40
+
#define RZ_MTU3_TMDR1_MD GENMASK(3, 0)
41
+
#define RZ_MTU3_TMDR1_MD_NORMAL FIELD_PREP(RZ_MTU3_TMDR1_MD, 0)
42
+
#define RZ_MTU3_TMDR1_MD_PWMMODE1 FIELD_PREP(RZ_MTU3_TMDR1_MD, 2)
43
+
44
+
#define RZ_MTU3_TIOR 6 /* Timer I/O control register */
45
+
#define RZ_MTU3_TIORH 6 /* Timer I/O control register H */
46
+
#define RZ_MTU3_TIORL 7 /* Timer I/O control register L */
47
+
/* Only MTU3/4/6/7 have TBTM registers */
48
+
#define RZ_MTU3_TBTM 8 /* Timer buffer operation transfer mode register */
49
+
50
+
/* 8-bit MTU5 register offset macros */
51
+
#define RZ_MTU3_TSTR 2 /* MTU5 Timer start register */
52
+
#define RZ_MTU3_TCNTCMPCLR 3 /* MTU5 Timer compare match clear register */
53
+
#define RZ_MTU3_TCRU 4 /* Timer control register U */
54
+
#define RZ_MTU3_TCR2U 5 /* Timer control register 2U */
55
+
#define RZ_MTU3_TIORU 6 /* Timer I/O control register U */
56
+
#define RZ_MTU3_TCRV 7 /* Timer control register V */
57
+
#define RZ_MTU3_TCR2V 8 /* Timer control register 2V */
58
+
#define RZ_MTU3_TIORV 9 /* Timer I/O control register V */
59
+
#define RZ_MTU3_TCRW 10 /* Timer control register W */
60
+
#define RZ_MTU3_TCR2W 11 /* Timer control register 2W */
61
+
#define RZ_MTU3_TIORW 12 /* Timer I/O control register W */
62
+
63
+
/* 16-bit register offset macros of MTU3 channels except MTU5 */
64
+
#define RZ_MTU3_TCNT 0 /* Timer counter */
65
+
#define RZ_MTU3_TGRA 1 /* Timer general register A */
66
+
#define RZ_MTU3_TGRB 2 /* Timer general register B */
67
+
#define RZ_MTU3_TGRC 3 /* Timer general register C */
68
+
#define RZ_MTU3_TGRD 4 /* Timer general register D */
69
+
#define RZ_MTU3_TGRE 5 /* Timer general register E */
70
+
#define RZ_MTU3_TGRF 6 /* Timer general register F */
71
+
/* Timer A/D converter start request registers */
72
+
#define RZ_MTU3_TADCR 7 /* control register */
73
+
#define RZ_MTU3_TADCORA 8 /* cycle set register A */
74
+
#define RZ_MTU3_TADCORB 9 /* cycle set register B */
75
+
#define RZ_MTU3_TADCOBRA 10 /* cycle set buffer register A */
76
+
#define RZ_MTU3_TADCOBRB 11 /* cycle set buffer register B */
77
+
78
+
/* 16-bit MTU5 register offset macros */
79
+
#define RZ_MTU3_TCNTU 0 /* MTU5 Timer counter U */
80
+
#define RZ_MTU3_TGRU 1 /* MTU5 Timer general register U */
81
+
#define RZ_MTU3_TCNTV 2 /* MTU5 Timer counter V */
82
+
#define RZ_MTU3_TGRV 3 /* MTU5 Timer general register V */
83
+
#define RZ_MTU3_TCNTW 4 /* MTU5 Timer counter W */
84
+
#define RZ_MTU3_TGRW 5 /* MTU5 Timer general register W */
85
+
86
+
/* 32-bit register offset */
87
+
#define RZ_MTU3_TCNTLW 0 /* Timer longword counter */
88
+
#define RZ_MTU3_TGRALW 1 /* Timer longword general register A */
89
+
#define RZ_MTU3_TGRBLW 2 /* Timer longowrd general register B */
90
+
91
+
#define RZ_MTU3_TMDR3 0x191 /* MTU1 Timer Mode Register 3 */
92
+
93
+
/* Macros for setting registers */
94
+
#define RZ_MTU3_TCR_CCLR GENMASK(7, 5)
95
+
#define RZ_MTU3_TCR_CKEG GENMASK(4, 3)
96
+
#define RZ_MTU3_TCR_TPCS GENMASK(2, 0)
97
+
#define RZ_MTU3_TCR_CCLR_TGRA BIT(5)
98
+
#define RZ_MTU3_TCR_CCLR_TGRC FIELD_PREP(RZ_MTU3_TCR_CCLR, 5)
99
+
#define RZ_MTU3_TCR_CKEG_RISING FIELD_PREP(RZ_MTU3_TCR_CKEG, 0)
100
+
101
+
#define RZ_MTU3_TIOR_IOB GENMASK(7, 4)
102
+
#define RZ_MTU3_TIOR_IOA GENMASK(3, 0)
103
+
#define RZ_MTU3_TIOR_OC_RETAIN 0
104
+
#define RZ_MTU3_TIOR_OC_INIT_OUT_LO_HI_OUT 2
105
+
#define RZ_MTU3_TIOR_OC_INIT_OUT_HI_TOGGLE_OUT 7
106
+
107
+
#define RZ_MTU3_TIOR_OC_IOA_H_COMP_MATCH \
108
+
FIELD_PREP(RZ_MTU3_TIOR_IOA, RZ_MTU3_TIOR_OC_INIT_OUT_LO_HI_OUT)
109
+
#define RZ_MTU3_TIOR_OC_IOB_TOGGLE \
110
+
FIELD_PREP(RZ_MTU3_TIOR_IOB, RZ_MTU3_TIOR_OC_INIT_OUT_HI_TOGGLE_OUT)
111
+
112
+
enum rz_mtu3_channels {
113
+
RZ_MTU3_CHAN_0,
114
+
RZ_MTU3_CHAN_1,
115
+
RZ_MTU3_CHAN_2,
116
+
RZ_MTU3_CHAN_3,
117
+
RZ_MTU3_CHAN_4,
118
+
RZ_MTU3_CHAN_5,
119
+
RZ_MTU3_CHAN_6,
120
+
RZ_MTU3_CHAN_7,
121
+
RZ_MTU3_CHAN_8,
122
+
RZ_MTU_NUM_CHANNELS
123
+
};
124
+
125
+
/**
126
+
* struct rz_mtu3_channel - MTU3 channel private data
127
+
*
128
+
* @dev: device handle
129
+
* @channel_number: channel number
130
+
* @lock: Lock to protect channel state
131
+
* @is_busy: channel state
132
+
*/
133
+
struct rz_mtu3_channel {
134
+
struct device *dev;
135
+
unsigned int channel_number;
136
+
struct mutex lock;
137
+
bool is_busy;
138
+
};
139
+
140
+
/**
141
+
* struct rz_mtu3 - MTU3 core private data
142
+
*
143
+
* @clk: MTU3 module clock
144
+
* @rz_mtu3_channel: HW channels
145
+
* @priv_data: MTU3 core driver private data
146
+
*/
147
+
struct rz_mtu3 {
148
+
struct clk *clk;
149
+
struct rz_mtu3_channel channels[RZ_MTU_NUM_CHANNELS];
150
+
151
+
void *priv_data;
152
+
};
153
+
154
+
#if IS_ENABLED(CONFIG_RZ_MTU3)
155
+
static inline bool rz_mtu3_request_channel(struct rz_mtu3_channel *ch)
156
+
{
157
+
mutex_lock(&ch->lock);
158
+
if (ch->is_busy) {
159
+
mutex_unlock(&ch->lock);
160
+
return false;
161
+
}
162
+
163
+
ch->is_busy = true;
164
+
mutex_unlock(&ch->lock);
165
+
166
+
return true;
167
+
}
168
+
169
+
static inline void rz_mtu3_release_channel(struct rz_mtu3_channel *ch)
170
+
{
171
+
mutex_lock(&ch->lock);
172
+
ch->is_busy = false;
173
+
mutex_unlock(&ch->lock);
174
+
}
175
+
176
+
bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch);
177
+
void rz_mtu3_disable(struct rz_mtu3_channel *ch);
178
+
int rz_mtu3_enable(struct rz_mtu3_channel *ch);
179
+
180
+
u8 rz_mtu3_8bit_ch_read(struct rz_mtu3_channel *ch, u16 off);
181
+
u16 rz_mtu3_16bit_ch_read(struct rz_mtu3_channel *ch, u16 off);
182
+
u32 rz_mtu3_32bit_ch_read(struct rz_mtu3_channel *ch, u16 off);
183
+
u16 rz_mtu3_shared_reg_read(struct rz_mtu3_channel *ch, u16 off);
184
+
185
+
void rz_mtu3_8bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u8 val);
186
+
void rz_mtu3_16bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u16 val);
187
+
void rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u32 val);
188
+
void rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 off, u16 val);
189
+
void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 off,
190
+
u16 pos, u8 val);
191
+
#else
192
+
static inline bool rz_mtu3_request_channel(struct rz_mtu3_channel *ch)
193
+
{
194
+
return false;
195
+
}
196
+
197
+
static inline void rz_mtu3_release_channel(struct rz_mtu3_channel *ch)
198
+
{
199
+
}
200
+
201
+
static inline bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch)
202
+
{
203
+
return false;
204
+
}
205
+
206
+
static inline void rz_mtu3_disable(struct rz_mtu3_channel *ch)
207
+
{
208
+
}
209
+
210
+
static inline int rz_mtu3_enable(struct rz_mtu3_channel *ch)
211
+
{
212
+
return 0;
213
+
}
214
+
215
+
static inline u8 rz_mtu3_8bit_ch_read(struct rz_mtu3_channel *ch, u16 off)
216
+
{
217
+
return 0;
218
+
}
219
+
220
+
static inline u16 rz_mtu3_16bit_ch_read(struct rz_mtu3_channel *ch, u16 off)
221
+
{
222
+
return 0;
223
+
}
224
+
225
+
static inline u32 rz_mtu3_32bit_ch_read(struct rz_mtu3_channel *ch, u16 off)
226
+
{
227
+
return 0;
228
+
}
229
+
230
+
static inline u16 rz_mtu3_shared_reg_read(struct rz_mtu3_channel *ch, u16 off)
231
+
{
232
+
return 0;
233
+
}
234
+
235
+
static inline void rz_mtu3_8bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u8 val)
236
+
{
237
+
}
238
+
239
+
static inline void rz_mtu3_16bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u16 val)
240
+
{
241
+
}
242
+
243
+
static inline void rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u32 val)
244
+
{
245
+
}
246
+
247
+
static inline void rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 off, u16 val)
248
+
{
249
+
}
250
+
251
+
static inline void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch,
252
+
u16 off, u16 pos, u8 val)
253
+
{
254
+
}
255
+
#endif
256
+
257
+
#endif /* __MFD_RZ_MTU3_H__ */
-2
include/linux/mfd/samsung/core.h
-2
include/linux/mfd/samsung/core.h
-50
include/linux/mfd/samsung/irq.h
-50
include/linux/mfd/samsung/irq.h
···
194
194
#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
195
195
#define S5M8767_IRQ_WTSR_MASK (1 << 5)
196
196
197
-
enum s5m8763_irq {
198
-
S5M8763_IRQ_DCINF,
199
-
S5M8763_IRQ_DCINR,
200
-
S5M8763_IRQ_JIGF,
201
-
S5M8763_IRQ_JIGR,
202
-
S5M8763_IRQ_PWRONF,
203
-
S5M8763_IRQ_PWRONR,
204
-
205
-
S5M8763_IRQ_WTSREVNT,
206
-
S5M8763_IRQ_SMPLEVNT,
207
-
S5M8763_IRQ_ALARM1,
208
-
S5M8763_IRQ_ALARM0,
209
-
210
-
S5M8763_IRQ_ONKEY1S,
211
-
S5M8763_IRQ_TOPOFFR,
212
-
S5M8763_IRQ_DCINOVPR,
213
-
S5M8763_IRQ_CHGRSTF,
214
-
S5M8763_IRQ_DONER,
215
-
S5M8763_IRQ_CHGFAULT,
216
-
217
-
S5M8763_IRQ_LOBAT1,
218
-
S5M8763_IRQ_LOBAT2,
219
-
220
-
S5M8763_IRQ_NR,
221
-
};
222
-
223
-
#define S5M8763_IRQ_DCINF_MASK (1 << 2)
224
-
#define S5M8763_IRQ_DCINR_MASK (1 << 3)
225
-
#define S5M8763_IRQ_JIGF_MASK (1 << 4)
226
-
#define S5M8763_IRQ_JIGR_MASK (1 << 5)
227
-
#define S5M8763_IRQ_PWRONF_MASK (1 << 6)
228
-
#define S5M8763_IRQ_PWRONR_MASK (1 << 7)
229
-
230
-
#define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
231
-
#define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
232
-
#define S5M8763_IRQ_ALARM1_MASK (1 << 2)
233
-
#define S5M8763_IRQ_ALARM0_MASK (1 << 3)
234
-
235
-
#define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
236
-
#define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
237
-
#define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
238
-
#define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
239
-
#define S5M8763_IRQ_DONER_MASK (1 << 5)
240
-
#define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
241
-
242
-
#define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
243
-
#define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
244
-
245
-
#define S5M8763_ENRAMP (1 << 4)
246
-
247
197
#endif /* __LINUX_MFD_SEC_IRQ_H */
-90
include/linux/mfd/samsung/s5m8763.h
-90
include/linux/mfd/samsung/s5m8763.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0+ */
2
-
/*
3
-
* Copyright (c) 2011 Samsung Electronics Co., Ltd
4
-
* http://www.samsung.com
5
-
*/
6
-
7
-
#ifndef __LINUX_MFD_S5M8763_H
8
-
#define __LINUX_MFD_S5M8763_H
9
-
10
-
/* S5M8763 registers */
11
-
enum s5m8763_reg {
12
-
S5M8763_REG_IRQ1,
13
-
S5M8763_REG_IRQ2,
14
-
S5M8763_REG_IRQ3,
15
-
S5M8763_REG_IRQ4,
16
-
S5M8763_REG_IRQM1,
17
-
S5M8763_REG_IRQM2,
18
-
S5M8763_REG_IRQM3,
19
-
S5M8763_REG_IRQM4,
20
-
S5M8763_REG_STATUS1,
21
-
S5M8763_REG_STATUS2,
22
-
S5M8763_REG_STATUSM1,
23
-
S5M8763_REG_STATUSM2,
24
-
S5M8763_REG_CHGR1,
25
-
S5M8763_REG_CHGR2,
26
-
S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
27
-
S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
28
-
S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
29
-
S5M8763_REG_ONOFF1,
30
-
S5M8763_REG_ONOFF2,
31
-
S5M8763_REG_ONOFF3,
32
-
S5M8763_REG_ONOFF4,
33
-
S5M8763_REG_BUCK1_VOLTAGE1,
34
-
S5M8763_REG_BUCK1_VOLTAGE2,
35
-
S5M8763_REG_BUCK1_VOLTAGE3,
36
-
S5M8763_REG_BUCK1_VOLTAGE4,
37
-
S5M8763_REG_BUCK2_VOLTAGE1,
38
-
S5M8763_REG_BUCK2_VOLTAGE2,
39
-
S5M8763_REG_BUCK3,
40
-
S5M8763_REG_BUCK4,
41
-
S5M8763_REG_LDO1_LDO2,
42
-
S5M8763_REG_LDO3,
43
-
S5M8763_REG_LDO4,
44
-
S5M8763_REG_LDO5,
45
-
S5M8763_REG_LDO6,
46
-
S5M8763_REG_LDO7,
47
-
S5M8763_REG_LDO7_LDO8,
48
-
S5M8763_REG_LDO9_LDO10,
49
-
S5M8763_REG_LDO11,
50
-
S5M8763_REG_LDO12,
51
-
S5M8763_REG_LDO13,
52
-
S5M8763_REG_LDO14,
53
-
S5M8763_REG_LDO15,
54
-
S5M8763_REG_LDO16,
55
-
S5M8763_REG_BKCHR,
56
-
S5M8763_REG_LBCNFG1,
57
-
S5M8763_REG_LBCNFG2,
58
-
};
59
-
60
-
/* S5M8763 regulator ids */
61
-
enum s5m8763_regulators {
62
-
S5M8763_LDO1,
63
-
S5M8763_LDO2,
64
-
S5M8763_LDO3,
65
-
S5M8763_LDO4,
66
-
S5M8763_LDO5,
67
-
S5M8763_LDO6,
68
-
S5M8763_LDO7,
69
-
S5M8763_LDO8,
70
-
S5M8763_LDO9,
71
-
S5M8763_LDO10,
72
-
S5M8763_LDO11,
73
-
S5M8763_LDO12,
74
-
S5M8763_LDO13,
75
-
S5M8763_LDO14,
76
-
S5M8763_LDO15,
77
-
S5M8763_LDO16,
78
-
S5M8763_BUCK1,
79
-
S5M8763_BUCK2,
80
-
S5M8763_BUCK3,
81
-
S5M8763_BUCK4,
82
-
S5M8763_AP_EN32KHZ,
83
-
S5M8763_CP_EN32KHZ,
84
-
S5M8763_ENCHGVI,
85
-
S5M8763_ESAFEUSB1,
86
-
S5M8763_ESAFEUSB2,
87
-
};
88
-
89
-
#define S5M8763_ENRAMP (1 << 4)
90
-
#endif /* __LINUX_MFD_S5M8763_H */