Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm:
ARM: 7182/1: ARM cpu topology: fix warning
ARM: 7181/1: Restrict kprobes probing SWP instructions to ARMv5 and below
ARM: 7180/1: Change kprobes testcase with unpredictable STRD instruction
ARM: 7177/1: GIC: avoid skipping non-existent PPIs in irq_start calculation
ARM: 7176/1: cpu_pm: register GIC PM notifier only once
ARM: 7175/1: add subname parameter to mfp_set_groupg callers
ARM: 7174/1: Fix build error in kprobes test code on Thumb2 kernels
ARM: 7172/1: dma: Drop GFP_COMP for DMA memory allocations
ARM: 7171/1: unwind: add unwind directives to bitops assembly macros
ARM: 7170/2: fix compilation breakage in entry-armv.S
ARM: 7168/1: use cache type functions for arch_get_unmapped_area
ARM: perf: check that we have a platform device when reserving PMU
ARM: 7166/1: Use PMD_SHIFT instead of PGDIR_SHIFT in dma-consistent.c
ARM: 7165/2: PL330: Fix typo in _prepare_ccr()
ARM: 7163/2: PL330: Only register usable channels
ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workarounds
ARM: 7161/1: errata: no automatic store buffer drain
ARM: perf: initialise used_mask for fake PMU during validation
ARM: PMU: remove pmu_init declaration
ARM: PMU: re-export release_pmu symbol to modules
+200
-121
+16
-4
arch/arm/Kconfig
+16
-4
arch/arm/Kconfig
···
1231
1231
capabilities of the processor.
1232
1232
1233
1233
config PL310_ERRATA_588369
1234
-
bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1234
+
bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1235
1235
depends on CACHE_L2X0
1236
1236
help
1237
1237
The PL310 L2 cache controller implements three types of Clean &
···
1256
1256
entries regardless of the ASID.
1257
1257
1258
1258
config PL310_ERRATA_727915
1259
-
bool "Background Clean & Invalidate by Way operation can cause data corruption"
1259
+
bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1260
1260
depends on CACHE_L2X0
1261
1261
help
1262
1262
PL310 implements the Clean & Invalidate by Way L2 cache maintenance
···
1289
1289
operation is received by a CPU before the ICIALLUIS has completed,
1290
1290
potentially leading to corrupted entries in the cache or TLB.
1291
1291
1292
-
config ARM_ERRATA_753970
1293
-
bool "ARM errata: cache sync operation may be faulty"
1292
+
config PL310_ERRATA_753970
1293
+
bool "PL310 errata: cache sync operation may be faulty"
1294
1294
depends on CACHE_PL310
1295
1295
help
1296
1296
This option enables the workaround for the 753970 PL310 (r3p0) erratum.
···
1351
1351
system. This workaround adds a DSB instruction before the
1352
1352
relevant cache maintenance functions and sets a specific bit
1353
1353
in the diagnostic control register of the SCU.
1354
+
1355
+
config PL310_ERRATA_769419
1356
+
bool "PL310 errata: no automatic Store Buffer drain"
1357
+
depends on CACHE_L2X0
1358
+
help
1359
+
On revisions of the PL310 prior to r3p2, the Store Buffer does
1360
+
not automatically drain. This can cause normal, non-cacheable
1361
+
writes to be retained when the memory system is idle, leading
1362
+
to suboptimal I/O performance for drivers using coherent DMA.
1363
+
This option adds a write barrier to the cpu_idle loop so that,
1364
+
on systems with an outer cache, the store buffer is drained
1365
+
explicitly.
1354
1366
1355
1367
endmenu
1356
1368
+10
-6
arch/arm/common/gic.c
+10
-6
arch/arm/common/gic.c
···
526
526
sizeof(u32));
527
527
BUG_ON(!gic->saved_ppi_conf);
528
528
529
-
cpu_pm_register_notifier(&gic_notifier_block);
529
+
if (gic == &gic_data[0])
530
+
cpu_pm_register_notifier(&gic_notifier_block);
530
531
}
531
532
#else
532
533
static void __init gic_pm_init(struct gic_chip_data *gic)
···
582
581
* For primary GICs, skip over SGIs.
583
582
* For secondary GICs, skip over PPIs, too.
584
583
*/
584
+
domain->hwirq_base = 32;
585
585
if (gic_nr == 0) {
586
586
gic_cpu_base_addr = cpu_base;
587
-
domain->hwirq_base = 16;
588
-
if (irq_start > 0)
589
-
irq_start = (irq_start & ~31) + 16;
590
-
} else
591
-
domain->hwirq_base = 32;
587
+
588
+
if ((irq_start & 31) > 0) {
589
+
domain->hwirq_base = 16;
590
+
if (irq_start != -1)
591
+
irq_start = (irq_start & ~31) + 16;
592
+
}
593
+
}
592
594
593
595
/*
594
596
* Find out how many interrupts are supported.
+9
-3
arch/arm/common/pl330.c
+9
-3
arch/arm/common/pl330.c
···
1211
1211
ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1212
1212
ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1213
1213
1214
-
ccr |= (rqc->dcctl << CC_SRCCCTRL_SHFT);
1215
-
ccr |= (rqc->scctl << CC_DSTCCTRL_SHFT);
1214
+
ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1215
+
ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1216
1216
1217
1217
ccr |= (rqc->swap << CC_SWAP_SHFT);
1218
1218
···
1623
1623
return -1;
1624
1624
}
1625
1625
1626
+
static bool _chan_ns(const struct pl330_info *pi, int i)
1627
+
{
1628
+
return pi->pcfg.irq_ns & (1 << i);
1629
+
}
1630
+
1626
1631
/* Upon success, returns IdentityToken for the
1627
1632
* allocated channel, NULL otherwise.
1628
1633
*/
···
1652
1647
1653
1648
for (i = 0; i < chans; i++) {
1654
1649
thrd = &pl330->channels[i];
1655
-
if (thrd->free) {
1650
+
if ((thrd->free) && (!_manager_ns(thrd) ||
1651
+
_chan_ns(pi, i))) {
1656
1652
thrd->ev = _alloc_event(thrd);
1657
1653
if (thrd->ev >= 0) {
1658
1654
thrd->free = false;
-10
arch/arm/include/asm/pmu.h
-10
arch/arm/include/asm/pmu.h
···
55
55
extern void
56
56
release_pmu(enum arm_pmu_type type);
57
57
58
-
/**
59
-
* init_pmu() - Initialise the PMU.
60
-
*
61
-
* Initialise the system ready for PMU enabling. This should typically set the
62
-
* IRQ affinity and nothing else. The users (oprofile/perf events etc) will do
63
-
* the actual hardware initialisation.
64
-
*/
65
-
extern int
66
-
init_pmu(enum arm_pmu_type type);
67
-
68
58
#else /* CONFIG_CPU_HAS_PMU */
69
59
70
60
#include <linux/err.h>
+1
-1
arch/arm/include/asm/topology.h
+1
-1
arch/arm/include/asm/topology.h
+1
-1
arch/arm/kernel/entry-armv.S
+1
-1
arch/arm/kernel/entry-armv.S
+3
-1
arch/arm/kernel/kprobes-arm.c
+3
-1
arch/arm/kernel/kprobes-arm.c
···
519
519
static const union decode_item arm_cccc_0001_____1001_table[] = {
520
520
/* Synchronization primitives */
521
521
522
+
#if __LINUX_ARM_ARCH__ < 6
523
+
/* Deprecated on ARMv6 and may be UNDEFINED on v7 */
522
524
/* SMP/SWPB cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */
523
525
DECODE_EMULATEX (0x0fb000f0, 0x01000090, emulate_rd12rn16rm0_rwflags_nopc,
524
526
REGS(NOPC, NOPC, 0, 0, NOPC)),
525
-
527
+
#endif
526
528
/* LDREX/STREX{,D,B,H} cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */
527
529
/* And unallocated instructions... */
528
530
DECODE_END
+17
-10
arch/arm/kernel/kprobes-test-arm.c
+17
-10
arch/arm/kernel/kprobes-test-arm.c
···
427
427
428
428
TEST_GROUP("Synchronization primitives")
429
429
430
-
/*
431
-
* Use hard coded constants for SWP instructions to avoid warnings
432
-
* about deprecated instructions.
433
-
*/
434
-
TEST_RP( ".word 0xe108e097 @ swp lr, r",7,VAL2,", [r",8,0,"]")
435
-
TEST_R( ".word 0x610d0091 @ swpvs r0, r",1,VAL1,", [sp]")
436
-
TEST_RP( ".word 0xe10cd09e @ swp sp, r",14,VAL2,", [r",12,13*4,"]")
430
+
#if __LINUX_ARM_ARCH__ < 6
431
+
TEST_RP("swp lr, r",7,VAL2,", [r",8,0,"]")
432
+
TEST_R( "swpvs r0, r",1,VAL1,", [sp]")
433
+
TEST_RP("swp sp, r",14,VAL2,", [r",12,13*4,"]")
434
+
#else
435
+
TEST_UNSUPPORTED(".word 0xe108e097 @ swp lr, r7, [r8]")
436
+
TEST_UNSUPPORTED(".word 0x610d0091 @ swpvs r0, r1, [sp]")
437
+
TEST_UNSUPPORTED(".word 0xe10cd09e @ swp sp, r14 [r12]")
438
+
#endif
437
439
TEST_UNSUPPORTED(".word 0xe102f091 @ swp pc, r1, [r2]")
438
440
TEST_UNSUPPORTED(".word 0xe102009f @ swp r0, pc, [r2]")
439
441
TEST_UNSUPPORTED(".word 0xe10f0091 @ swp r0, r1, [pc]")
440
-
TEST_RP( ".word 0xe148e097 @ swpb lr, r",7,VAL2,", [r",8,0,"]")
441
-
TEST_R( ".word 0x614d0091 @ swpvsb r0, r",1,VAL1,", [sp]")
442
+
#if __LINUX_ARM_ARCH__ < 6
443
+
TEST_RP("swpb lr, r",7,VAL2,", [r",8,0,"]")
444
+
TEST_R( "swpvsb r0, r",1,VAL1,", [sp]")
445
+
#else
446
+
TEST_UNSUPPORTED(".word 0xe148e097 @ swpb lr, r7, [r8]")
447
+
TEST_UNSUPPORTED(".word 0x614d0091 @ swpvsb r0, r1, [sp]")
448
+
#endif
442
449
TEST_UNSUPPORTED(".word 0xe142f091 @ swpb pc, r1, [r2]")
443
450
444
451
TEST_UNSUPPORTED(".word 0xe1100090") /* Unallocated space */
···
557
550
TEST_RPR( "strccd r",8, VAL2,", [r",13,0, ", r",12,48,"]")
558
551
TEST_RPR( "strd r",4, VAL1,", [r",2, 24,", r",3, 48,"]!")
559
552
TEST_RPR( "strcsd r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
560
-
TEST_RPR( "strd r",2, VAL1,", [r",3, 24,"], r",4,48,"")
553
+
TEST_RPR( "strd r",2, VAL1,", [r",5, 24,"], r",4,48,"")
561
554
TEST_RPR( "strd r",10,VAL2,", [r",9, 48,"], -r",7,24,"")
562
555
TEST_UNSUPPORTED(".word 0xe1afc0fa @ strd r12, [pc, r10]!")
563
556
+8
-8
arch/arm/kernel/kprobes-test-thumb.c
+8
-8
arch/arm/kernel/kprobes-test-thumb.c
···
222
222
DONT_TEST_IN_ITBLOCK(
223
223
TEST_BF_R( "cbnz r",0,0, ", 2f")
224
224
TEST_BF_R( "cbz r",2,-1,", 2f")
225
-
TEST_BF_RX( "cbnz r",4,1, ", 2f",0x20)
226
-
TEST_BF_RX( "cbz r",7,0, ", 2f",0x40)
225
+
TEST_BF_RX( "cbnz r",4,1, ", 2f", SPACE_0x20)
226
+
TEST_BF_RX( "cbz r",7,0, ", 2f", SPACE_0x40)
227
227
)
228
228
TEST_R("sxth r0, r",7, HH1,"")
229
229
TEST_R("sxth r7, r",0, HH2,"")
···
246
246
TESTCASE_START(code) \
247
247
TEST_ARG_PTR(13, offset) \
248
248
TEST_ARG_END("") \
249
-
TEST_BRANCH_F(code,0) \
249
+
TEST_BRANCH_F(code) \
250
250
TESTCASE_END
251
251
252
252
TEST("push {r0}")
···
319
319
320
320
TEST_BF( "b 2f")
321
321
TEST_BB( "b 2b")
322
-
TEST_BF_X("b 2f", 0x400)
323
-
TEST_BB_X("b 2b", 0x400)
322
+
TEST_BF_X("b 2f", SPACE_0x400)
323
+
TEST_BB_X("b 2b", SPACE_0x400)
324
324
325
325
TEST_GROUP("Testing instructions in IT blocks")
326
326
···
746
746
TEST_BB("bne.w 2b")
747
747
TEST_BF("bgt.w 2f")
748
748
TEST_BB("blt.w 2b")
749
-
TEST_BF_X("bpl.w 2f",0x1000)
749
+
TEST_BF_X("bpl.w 2f", SPACE_0x1000)
750
750
)
751
751
752
752
TEST_UNSUPPORTED("msr cpsr, r0")
···
786
786
787
787
TEST_BF( "b.w 2f")
788
788
TEST_BB( "b.w 2b")
789
-
TEST_BF_X("b.w 2f", 0x1000)
789
+
TEST_BF_X("b.w 2f", SPACE_0x1000)
790
790
791
791
TEST_BF( "bl.w 2f")
792
792
TEST_BB( "bl.w 2b")
793
-
TEST_BB_X("bl.w 2b", 0x1000)
793
+
TEST_BB_X("bl.w 2b", SPACE_0x1000)
794
794
795
795
TEST_X( "blx __dummy_arm_subroutine",
796
796
".arm \n\t"
+71
-31
arch/arm/kernel/kprobes-test.h
+71
-31
arch/arm/kernel/kprobes-test.h
···
149
149
"1: "instruction" \n\t" \
150
150
" nop \n\t"
151
151
152
-
#define TEST_BRANCH_F(instruction, xtra_dist) \
152
+
#define TEST_BRANCH_F(instruction) \
153
153
TEST_INSTRUCTION(instruction) \
154
-
".if "#xtra_dist" \n\t" \
155
-
" b 99f \n\t" \
156
-
".space "#xtra_dist" \n\t" \
157
-
".endif \n\t" \
158
154
" b 99f \n\t" \
159
155
"2: nop \n\t"
160
156
161
-
#define TEST_BRANCH_B(instruction, xtra_dist) \
157
+
#define TEST_BRANCH_B(instruction) \
162
158
" b 50f \n\t" \
163
159
" b 99f \n\t" \
164
160
"2: nop \n\t" \
165
161
" b 99f \n\t" \
166
-
".if "#xtra_dist" \n\t" \
167
-
".space "#xtra_dist" \n\t" \
168
-
".endif \n\t" \
162
+
TEST_INSTRUCTION(instruction)
163
+
164
+
#define TEST_BRANCH_FX(instruction, codex) \
165
+
TEST_INSTRUCTION(instruction) \
166
+
" b 99f \n\t" \
167
+
codex" \n\t" \
168
+
" b 99f \n\t" \
169
+
"2: nop \n\t"
170
+
171
+
#define TEST_BRANCH_BX(instruction, codex) \
172
+
" b 50f \n\t" \
173
+
" b 99f \n\t" \
174
+
"2: nop \n\t" \
175
+
" b 99f \n\t" \
176
+
codex" \n\t" \
169
177
TEST_INSTRUCTION(instruction)
170
178
171
179
#define TESTCASE_END \
···
309
301
TESTCASE_START(code1 #reg1 code2) \
310
302
TEST_ARG_PTR(reg1, val1) \
311
303
TEST_ARG_END("") \
312
-
TEST_BRANCH_F(code1 #reg1 code2, 0) \
304
+
TEST_BRANCH_F(code1 #reg1 code2) \
313
305
TESTCASE_END
314
306
315
-
#define TEST_BF_X(code, xtra_dist) \
307
+
#define TEST_BF(code) \
316
308
TESTCASE_START(code) \
317
309
TEST_ARG_END("") \
318
-
TEST_BRANCH_F(code, xtra_dist) \
310
+
TEST_BRANCH_F(code) \
319
311
TESTCASE_END
320
312
321
-
#define TEST_BB_X(code, xtra_dist) \
313
+
#define TEST_BB(code) \
322
314
TESTCASE_START(code) \
323
315
TEST_ARG_END("") \
324
-
TEST_BRANCH_B(code, xtra_dist) \
316
+
TEST_BRANCH_B(code) \
325
317
TESTCASE_END
326
318
327
-
#define TEST_BF_RX(code1, reg, val, code2, xtra_dist) \
328
-
TESTCASE_START(code1 #reg code2) \
329
-
TEST_ARG_REG(reg, val) \
330
-
TEST_ARG_END("") \
331
-
TEST_BRANCH_F(code1 #reg code2, xtra_dist) \
319
+
#define TEST_BF_R(code1, reg, val, code2) \
320
+
TESTCASE_START(code1 #reg code2) \
321
+
TEST_ARG_REG(reg, val) \
322
+
TEST_ARG_END("") \
323
+
TEST_BRANCH_F(code1 #reg code2) \
332
324
TESTCASE_END
333
325
334
-
#define TEST_BB_RX(code1, reg, val, code2, xtra_dist) \
335
-
TESTCASE_START(code1 #reg code2) \
336
-
TEST_ARG_REG(reg, val) \
337
-
TEST_ARG_END("") \
338
-
TEST_BRANCH_B(code1 #reg code2, xtra_dist) \
326
+
#define TEST_BB_R(code1, reg, val, code2) \
327
+
TESTCASE_START(code1 #reg code2) \
328
+
TEST_ARG_REG(reg, val) \
329
+
TEST_ARG_END("") \
330
+
TEST_BRANCH_B(code1 #reg code2) \
339
331
TESTCASE_END
340
-
341
-
#define TEST_BF(code) TEST_BF_X(code, 0)
342
-
#define TEST_BB(code) TEST_BB_X(code, 0)
343
-
344
-
#define TEST_BF_R(code1, reg, val, code2) TEST_BF_RX(code1, reg, val, code2, 0)
345
-
#define TEST_BB_R(code1, reg, val, code2) TEST_BB_RX(code1, reg, val, code2, 0)
346
332
347
333
#define TEST_BF_RR(code1, reg1, val1, code2, reg2, val2, code3) \
348
334
TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
349
335
TEST_ARG_REG(reg1, val1) \
350
336
TEST_ARG_REG(reg2, val2) \
351
337
TEST_ARG_END("") \
352
-
TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3, 0) \
338
+
TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3) \
339
+
TESTCASE_END
340
+
341
+
#define TEST_BF_X(code, codex) \
342
+
TESTCASE_START(code) \
343
+
TEST_ARG_END("") \
344
+
TEST_BRANCH_FX(code, codex) \
345
+
TESTCASE_END
346
+
347
+
#define TEST_BB_X(code, codex) \
348
+
TESTCASE_START(code) \
349
+
TEST_ARG_END("") \
350
+
TEST_BRANCH_BX(code, codex) \
351
+
TESTCASE_END
352
+
353
+
#define TEST_BF_RX(code1, reg, val, code2, codex) \
354
+
TESTCASE_START(code1 #reg code2) \
355
+
TEST_ARG_REG(reg, val) \
356
+
TEST_ARG_END("") \
357
+
TEST_BRANCH_FX(code1 #reg code2, codex) \
353
358
TESTCASE_END
354
359
355
360
#define TEST_X(code, codex) \
···
391
370
" b 99f \n\t" \
392
371
" "codex" \n\t" \
393
372
TESTCASE_END
373
+
374
+
375
+
/*
376
+
* Macros for defining space directives spread over multiple lines.
377
+
* These are required so the compiler guesses better the length of inline asm
378
+
* code and will spill the literal pool early enough to avoid generating PC
379
+
* relative loads with out of range offsets.
380
+
*/
381
+
#define TWICE(x) x x
382
+
#define SPACE_0x8 TWICE(".space 4\n\t")
383
+
#define SPACE_0x10 TWICE(SPACE_0x8)
384
+
#define SPACE_0x20 TWICE(SPACE_0x10)
385
+
#define SPACE_0x40 TWICE(SPACE_0x20)
386
+
#define SPACE_0x80 TWICE(SPACE_0x40)
387
+
#define SPACE_0x100 TWICE(SPACE_0x80)
388
+
#define SPACE_0x200 TWICE(SPACE_0x100)
389
+
#define SPACE_0x400 TWICE(SPACE_0x200)
390
+
#define SPACE_0x800 TWICE(SPACE_0x400)
391
+
#define SPACE_0x1000 TWICE(SPACE_0x800)
394
392
395
393
396
394
/* Various values used in test cases... */
+10
-1
arch/arm/kernel/perf_event.c
+10
-1
arch/arm/kernel/perf_event.c
···
343
343
{
344
344
struct perf_event *sibling, *leader = event->group_leader;
345
345
struct pmu_hw_events fake_pmu;
346
+
DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
346
347
347
-
memset(&fake_pmu, 0, sizeof(fake_pmu));
348
+
/*
349
+
* Initialise the fake PMU. We only need to populate the
350
+
* used_mask for the purposes of validation.
351
+
*/
352
+
memset(fake_used_mask, 0, sizeof(fake_used_mask));
353
+
fake_pmu.used_mask = fake_used_mask;
348
354
349
355
if (!validate_event(&fake_pmu, leader))
350
356
return -ENOSPC;
···
401
395
irq_handler_t handle_irq;
402
396
int i, err, irq, irqs;
403
397
struct platform_device *pmu_device = armpmu->plat_device;
398
+
399
+
if (!pmu_device)
400
+
return -ENODEV;
404
401
405
402
err = reserve_pmu(armpmu->type);
406
403
if (err) {
+1
arch/arm/kernel/pmu.c
+1
arch/arm/kernel/pmu.c
+3
arch/arm/kernel/process.c
+3
arch/arm/kernel/process.c
+1
-1
arch/arm/kernel/topology.c
+1
-1
arch/arm/kernel/topology.c
+22
-4
arch/arm/lib/bitops.h
+22
-4
arch/arm/lib/bitops.h
···
1
+
#include <asm/unwind.h>
2
+
1
3
#if __LINUX_ARM_ARCH__ >= 6
2
-
.macro bitop, instr
4
+
.macro bitop, name, instr
5
+
ENTRY( \name )
6
+
UNWIND( .fnstart )
3
7
ands ip, r1, #3
4
8
strneb r1, [ip] @ assert word-aligned
5
9
mov r2, #1
···
17
13
cmp r0, #0
18
14
bne 1b
19
15
bx lr
16
+
UNWIND( .fnend )
17
+
ENDPROC(\name )
20
18
.endm
21
19
22
-
.macro testop, instr, store
20
+
.macro testop, name, instr, store
21
+
ENTRY( \name )
22
+
UNWIND( .fnstart )
23
23
ands ip, r1, #3
24
24
strneb r1, [ip] @ assert word-aligned
25
25
mov r2, #1
···
42
34
cmp r0, #0
43
35
movne r0, #1
44
36
2: bx lr
37
+
UNWIND( .fnend )
38
+
ENDPROC(\name )
45
39
.endm
46
40
#else
47
-
.macro bitop, instr
41
+
.macro bitop, name, instr
42
+
ENTRY( \name )
43
+
UNWIND( .fnstart )
48
44
ands ip, r1, #3
49
45
strneb r1, [ip] @ assert word-aligned
50
46
and r2, r0, #31
···
61
49
str r2, [r1, r0, lsl #2]
62
50
restore_irqs ip
63
51
mov pc, lr
52
+
UNWIND( .fnend )
53
+
ENDPROC(\name )
64
54
.endm
65
55
66
56
/**
···
73
59
* Note: we can trivially conditionalise the store instruction
74
60
* to avoid dirtying the data cache.
75
61
*/
76
-
.macro testop, instr, store
62
+
.macro testop, name, instr, store
63
+
ENTRY( \name )
64
+
UNWIND( .fnstart )
77
65
ands ip, r1, #3
78
66
strneb r1, [ip] @ assert word-aligned
79
67
and r3, r0, #31
···
89
73
moveq r0, #0
90
74
restore_irqs ip
91
75
mov pc, lr
76
+
UNWIND( .fnend )
77
+
ENDPROC(\name )
92
78
.endm
93
79
#endif
+1
-3
arch/arm/lib/changebit.S
+1
-3
arch/arm/lib/changebit.S
+1
-3
arch/arm/lib/clearbit.S
+1
-3
arch/arm/lib/clearbit.S
+1
-3
arch/arm/lib/setbit.S
+1
-3
arch/arm/lib/setbit.S
+1
-3
arch/arm/lib/testchangebit.S
+1
-3
arch/arm/lib/testchangebit.S
+1
-3
arch/arm/lib/testclearbit.S
+1
-3
arch/arm/lib/testclearbit.S
+1
-3
arch/arm/lib/testsetbit.S
+1
-3
arch/arm/lib/testsetbit.S
+1
-1
arch/arm/mm/cache-l2x0.c
+1
-1
arch/arm/mm/cache-l2x0.c
+10
-1
arch/arm/mm/dma-mapping.c
+10
-1
arch/arm/mm/dma-mapping.c
···
168
168
pte_t *pte;
169
169
int i = 0;
170
170
unsigned long base = consistent_base;
171
-
unsigned long num_ptes = (CONSISTENT_END - base) >> PGDIR_SHIFT;
171
+
unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT;
172
172
173
173
consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL);
174
174
if (!consistent_pte) {
···
331
331
{
332
332
struct page *page;
333
333
void *addr;
334
+
335
+
/*
336
+
* Following is a work-around (a.k.a. hack) to prevent pages
337
+
* with __GFP_COMP being passed to split_page() which cannot
338
+
* handle them. The real problem is that this flag probably
339
+
* should be 0 on ARM as it is not supported on this
340
+
* platform; see CONFIG_HUGETLBFS.
341
+
*/
342
+
gfp &= ~(__GFP_COMP);
334
343
335
344
*handle = ~0;
336
345
size = PAGE_ALIGN(size);
+6
-17
arch/arm/mm/mmap.c
+6
-17
arch/arm/mm/mmap.c
···
9
9
#include <linux/io.h>
10
10
#include <linux/personality.h>
11
11
#include <linux/random.h>
12
-
#include <asm/cputype.h>
13
-
#include <asm/system.h>
12
+
#include <asm/cachetype.h>
14
13
15
14
#define COLOUR_ALIGN(addr,pgoff) \
16
15
((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \
···
31
32
struct mm_struct *mm = current->mm;
32
33
struct vm_area_struct *vma;
33
34
unsigned long start_addr;
34
-
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
35
-
unsigned int cache_type;
36
-
int do_align = 0, aliasing = 0;
35
+
int do_align = 0;
36
+
int aliasing = cache_is_vipt_aliasing();
37
37
38
38
/*
39
39
* We only need to do colour alignment if either the I or D
40
-
* caches alias. This is indicated by bits 9 and 21 of the
41
-
* cache type register.
40
+
* caches alias.
42
41
*/
43
-
cache_type = read_cpuid_cachetype();
44
-
if (cache_type != read_cpuid_id()) {
45
-
aliasing = (cache_type | cache_type >> 12) & (1 << 11);
46
-
if (aliasing)
47
-
do_align = filp || flags & MAP_SHARED;
48
-
}
49
-
#else
50
-
#define do_align 0
51
-
#define aliasing 0
52
-
#endif
42
+
if (aliasing)
43
+
do_align = filp || (flags & MAP_SHARED);
53
44
54
45
/*
55
46
* We enforce the MAP_FIXED case.
+1
-1
drivers/i2c/busses/i2c-nuc900.c
+1
-1
drivers/i2c/busses/i2c-nuc900.c
+1
-1
drivers/spi/spi-nuc900.c
+1
-1
drivers/spi/spi-nuc900.c