tjh.dev / kernel
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phy: lynx-28g: use FIELD_GET() and FIELD_PREP()

Reduce the number of bit field definitions required in this driver (in
the worst case, a read form and a write form), by defining just the
mask, and using the FIELD_GET() and FIELD_PREP() API from
<linux/bitfield.h> with that.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://patch.msgid.link/20251125114847.804961-8-vladimir.oltean@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Vladimir Oltean and committed by
Vinod Koul 3b84377c 6e3d3e87

+57 -50
+57 -50
drivers/phy/freescale/phy-fsl-lynx-28g.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0+ 2 2 /* Copyright (c) 2021-2022 NXP. */ 3 3 4 + #include <linux/bitfield.h> 4 5 #include <linux/module.h> 5 6 #include <linux/of.h> 6 7 #include <linux/phy.h> ··· 30 29 #define PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23) 31 30 32 31 #define PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4) 33 - #define PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16))) 32 + #define PLLnCR0_REFCLK_SEL GENMASK(20, 16) 34 33 #define PLLnCR0_REFCLK_SEL_100MHZ 0x0 35 - #define PLLnCR0_REFCLK_SEL_125MHZ 0x10000 36 - #define PLLnCR0_REFCLK_SEL_156MHZ 0x20000 37 - #define PLLnCR0_REFCLK_SEL_150MHZ 0x30000 38 - #define PLLnCR0_REFCLK_SEL_161MHZ 0x40000 34 + #define PLLnCR0_REFCLK_SEL_125MHZ 0x1 35 + #define PLLnCR0_REFCLK_SEL_156MHZ 0x2 36 + #define PLLnCR0_REFCLK_SEL_150MHZ 0x3 37 + #define PLLnCR0_REFCLK_SEL_161MHZ 0x4 39 38 40 39 #define PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8) 41 - #define PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24))) 40 + #define PLLnCR1_FRATE_SEL GENMASK(28, 24) 42 41 #define PLLnCR1_FRATE_5G_10GVCO 0x0 43 - #define PLLnCR1_FRATE_5G_25GVCO 0x10000000 44 - #define PLLnCR1_FRATE_10G_20GVCO 0x6000000 42 + #define PLLnCR1_FRATE_5G_25GVCO 0x10 43 + #define PLLnCR1_FRATE_10G_20GVCO 0x6 45 44 46 45 /* Per SerDes lane registers */ 47 46 /* Lane a General Control Register */ 48 47 #define LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) 49 - #define LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3) 50 - #define LNaGCR0_PROTO_SEL_SGMII 0x8 51 - #define LNaGCR0_PROTO_SEL_XFI 0x50 52 - #define LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0) 48 + #define LNaGCR0_PROTO_SEL GENMASK(7, 3) 49 + #define LNaGCR0_PROTO_SEL_SGMII 0x1 50 + #define LNaGCR0_PROTO_SEL_XFI 0xa 51 + #define LNaGCR0_IF_WIDTH GENMASK(2, 0) 53 52 #define LNaGCR0_IF_WIDTH_10_BIT 0x0 54 53 #define LNaGCR0_IF_WIDTH_20_BIT 0x2 55 54 ··· 61 60 62 61 /* Lane a Tx General Control Register */ 63 62 #define LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) 63 + #define LNaTGCR0_USE_PLL BIT(28) 64 64 #define LNaTGCR0_USE_PLLF 0x0 65 - #define LNaTGCR0_USE_PLLS BIT(28) 66 - #define LNaTGCR0_USE_PLL_MSK BIT(28) 65 + #define LNaTGCR0_USE_PLLS 0x1 66 + #define LNaTGCR0_N_RATE GENMASK(26, 24) 67 67 #define LNaTGCR0_N_RATE_FULL 0x0 68 - #define LNaTGCR0_N_RATE_HALF 0x1000000 69 - #define LNaTGCR0_N_RATE_QUARTER 0x2000000 70 - #define LNaTGCR0_N_RATE_MSK GENMASK(26, 24) 68 + #define LNaTGCR0_N_RATE_HALF 0x1 69 + #define LNaTGCR0_N_RATE_QUARTER 0x2 71 70 72 71 #define LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) 73 72 ··· 80 79 81 80 /* Lane a Rx General Control Register */ 82 81 #define LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44) 82 + #define LNaRGCR0_USE_PLL BIT(28) 83 83 #define LNaRGCR0_USE_PLLF 0x0 84 - #define LNaRGCR0_USE_PLLS BIT(28) 85 - #define LNaRGCR0_USE_PLL_MSK BIT(28) 86 - #define LNaRGCR0_N_RATE_MSK GENMASK(26, 24) 84 + #define LNaRGCR0_USE_PLLS 0x1 85 + #define LNaRGCR0_N_RATE GENMASK(26, 24) 87 86 #define LNaRGCR0_N_RATE_FULL 0x0 88 - #define LNaRGCR0_N_RATE_HALF 0x1000000 89 - #define LNaRGCR0_N_RATE_QUARTER 0x2000000 90 - #define LNaRGCR0_N_RATE_MSK GENMASK(26, 24) 87 + #define LNaRGCR0_N_RATE_HALF 0x1 88 + #define LNaRGCR0_N_RATE_QUARTER 0x2 91 89 92 90 #define LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48) 93 91 ··· 97 97 #define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74) 98 98 99 99 #define LNaPSS(lane) (0x1000 + (lane) * 0x4) 100 - #define LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24) 100 + #define LNaPSS_TYPE GENMASK(30, 24) 101 101 #define LNaPSS_TYPE_SGMII 0x4 102 102 #define LNaPSS_TYPE_XFI 0x28 103 103 104 104 #define SGMIIaCR1(lane) (0x1804 + (lane) * 0x10) 105 105 #define SGMIIaCR1_SGPCS_EN BIT(11) 106 - #define SGMIIaCR1_SGPCS_MSK BIT(11) 107 106 108 107 struct lynx_28g_priv; 109 108 ··· 196 197 struct lynx_28g_pll *pll, 197 198 phy_interface_t intf) 198 199 { 199 - switch (PLLnCR1_FRATE_SEL(pll->cr1)) { 200 + switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) { 200 201 case PLLnCR1_FRATE_5G_10GVCO: 201 202 case PLLnCR1_FRATE_5G_25GVCO: 202 203 switch (intf) { 203 204 case PHY_INTERFACE_MODE_SGMII: 204 205 case PHY_INTERFACE_MODE_1000BASEX: 205 206 lynx_28g_lane_rmw(lane, LNaTGCR0, 206 - LNaTGCR0_N_RATE_QUARTER, 207 - LNaTGCR0_N_RATE_MSK); 207 + FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_QUARTER), 208 + LNaTGCR0_N_RATE); 208 209 lynx_28g_lane_rmw(lane, LNaRGCR0, 209 - LNaRGCR0_N_RATE_QUARTER, 210 - LNaRGCR0_N_RATE_MSK); 210 + FIELD_PREP(LNaRGCR0_N_RATE, LNaRGCR0_N_RATE_QUARTER), 211 + LNaRGCR0_N_RATE); 211 212 break; 212 213 default: 213 214 break; ··· 217 218 switch (intf) { 218 219 case PHY_INTERFACE_MODE_10GBASER: 219 220 case PHY_INTERFACE_MODE_USXGMII: 220 - lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_N_RATE_FULL, 221 - LNaTGCR0_N_RATE_MSK); 222 - lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_N_RATE_FULL, 223 - LNaRGCR0_N_RATE_MSK); 221 + lynx_28g_lane_rmw(lane, LNaTGCR0, 222 + FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_FULL), 223 + LNaTGCR0_N_RATE); 224 + lynx_28g_lane_rmw(lane, LNaRGCR0, 225 + FIELD_PREP(LNaRGCR0_N_RATE, LNaRGCR0_N_RATE_FULL), 226 + LNaRGCR0_N_RATE); 224 227 break; 225 228 default: 226 229 break; ··· 237 236 struct lynx_28g_pll *pll) 238 237 { 239 238 if (pll->id == 0) { 240 - lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_USE_PLLF, 241 - LNaTGCR0_USE_PLL_MSK); 242 - lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_USE_PLLF, 243 - LNaRGCR0_USE_PLL_MSK); 239 + lynx_28g_lane_rmw(lane, LNaTGCR0, 240 + FIELD_PREP(LNaTGCR0_USE_PLL, LNaTGCR0_USE_PLLF), 241 + LNaTGCR0_USE_PLL); 242 + lynx_28g_lane_rmw(lane, LNaRGCR0, 243 + FIELD_PREP(LNaRGCR0_USE_PLL, LNaRGCR0_USE_PLLF), 244 + LNaRGCR0_USE_PLL); 244 245 } else { 245 - lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_USE_PLLS, 246 - LNaTGCR0_USE_PLL_MSK); 247 - lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_USE_PLLS, 248 - LNaRGCR0_USE_PLL_MSK); 246 + lynx_28g_lane_rmw(lane, LNaTGCR0, 247 + FIELD_PREP(LNaTGCR0_USE_PLL, LNaTGCR0_USE_PLLS), 248 + LNaTGCR0_USE_PLL); 249 + lynx_28g_lane_rmw(lane, LNaRGCR0, 250 + FIELD_PREP(LNaRGCR0_USE_PLL, LNaRGCR0_USE_PLLS), 251 + LNaRGCR0_USE_PLL); 249 252 } 250 253 } 251 254 ··· 291 286 292 287 /* Setup the protocol select and SerDes parallel interface width */ 293 288 lynx_28g_lane_rmw(lane, LNaGCR0, 294 - LNaGCR0_PROTO_SEL_SGMII | LNaGCR0_IF_WIDTH_10_BIT, 295 - LNaGCR0_PROTO_SEL_MSK | LNaGCR0_IF_WIDTH_MSK); 289 + FIELD_PREP(LNaGCR0_PROTO_SEL, LNaGCR0_PROTO_SEL_SGMII) | 290 + FIELD_PREP(LNaGCR0_IF_WIDTH, LNaGCR0_IF_WIDTH_10_BIT), 291 + LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH); 296 292 297 293 /* Find the PLL that works with this interface type */ 298 294 pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_SGMII); ··· 308 302 309 303 /* Enable the SGMII PCS */ 310 304 lynx_28g_lane_rmw(lane, SGMIIaCR1, SGMIIaCR1_SGPCS_EN, 311 - SGMIIaCR1_SGPCS_MSK); 305 + SGMIIaCR1_SGPCS_EN); 312 306 313 307 /* Configure the appropriate equalization parameters for the protocol */ 314 308 iowrite32(0x00808006, priv->base + LNaTECR0(lane->id)); ··· 334 328 335 329 /* Setup the protocol select and SerDes parallel interface width */ 336 330 lynx_28g_lane_rmw(lane, LNaGCR0, 337 - LNaGCR0_PROTO_SEL_XFI | LNaGCR0_IF_WIDTH_20_BIT, 338 - LNaGCR0_PROTO_SEL_MSK | LNaGCR0_IF_WIDTH_MSK); 331 + FIELD_PREP(LNaGCR0_PROTO_SEL, LNaGCR0_PROTO_SEL_XFI) | 332 + FIELD_PREP(LNaGCR0_IF_WIDTH, LNaGCR0_IF_WIDTH_20_BIT), 333 + LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH); 339 334 340 335 /* Find the PLL that works with this interface type */ 341 336 pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_10GBASER); ··· 350 343 lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER); 351 344 352 345 /* Disable the SGMII PCS */ 353 - lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_MSK); 346 + lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN); 354 347 355 348 /* Configure the appropriate equalization parameters for the protocol */ 356 349 iowrite32(0x10808307, priv->base + LNaTECR0(lane->id)); ··· 520 513 if (PLLnRSTCTL_DIS(pll->rstctl)) 521 514 continue; 522 515 523 - switch (PLLnCR1_FRATE_SEL(pll->cr1)) { 516 + switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) { 524 517 case PLLnCR1_FRATE_5G_10GVCO: 525 518 case PLLnCR1_FRATE_5G_25GVCO: 526 519 /* 5GHz clock net */ ··· 577 570 u32 pss, protocol; 578 571 579 572 pss = lynx_28g_lane_read(lane, LNaPSS); 580 - protocol = LNaPSS_TYPE(pss); 573 + protocol = FIELD_GET(LNaPSS_TYPE, pss); 581 574 switch (protocol) { 582 575 case LNaPSS_TYPE_SGMII: 583 576 lane->interface = PHY_INTERFACE_MODE_SGMII;