Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
octeon_ep: reset firmware ready status
Add support to reset firmware ready status
when the driver is removed(either in unload
or unbind)
Signed-off-by: Sathesh Edara <sedara@marvell.com>
Signed-off-by: Shinas Rasheed <srasheed@marvell.com>
Signed-off-by: Vimlesh Kumar <vimleshk@marvell.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20260115092048.870237-1-vimleshk@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
authored by
Vimlesh Kumar
and committed by
Jakub Kicinski
3b85d5f8
3d4375c2
+58
-1
+26
drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
+26
drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
···
637
637
638
638
octep_write_csr64(oct, CN93_SDP_WIN_WR_MASK_REG, 0xFF);
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+
/* Firmware status CSR is supposed to be cleared by
641
+
* core domain reset, but due to a hw bug, it is not.
642
+
* Set it to RUNNING right before reset so that it is not
643
+
* left in READY (1) state after a reset. This is required
644
+
* in addition to the early setting to handle the case where
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+
* the OcteonTX is unexpectedly reset, reboots, and then
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+
* the module is removed.
647
+
*/
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+
OCTEP_PCI_WIN_WRITE(oct,
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+
CN9K_PEMX_PFX_CSX_PFCFGX(0,
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+
0, CN9K_PCIEEP_VSECST_CTL),
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+
FW_STATUS_DOWNING);
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+
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/* Set core domain reset bit */
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OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1S, 1);
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655
/* Wait for 100ms as Octeon resets. */
···
907
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908
895
octep_init_config_cn93_pf(oct);
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octep_configure_ring_mapping_cn93_pf(oct);
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+
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+
if (oct->chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF)
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+
return;
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+
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+
/* Firmware status CSR is supposed to be cleared by
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+
* core domain reset, but due to IPBUPEM-38842, it is not.
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+
* Set it to RUNNING early in boot, so that unexpected resets
904
+
* leave it in a state that is not READY (1).
905
+
*/
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+
OCTEP_PCI_WIN_WRITE(oct,
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+
CN9K_PEMX_PFX_CSX_PFCFGX(0,
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+
0, CN9K_PCIEEP_VSECST_CTL),
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+
FW_STATUS_RUNNING);
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910
}
+1
-1
drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
+1
-1
drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
+30
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
+30
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
···
5
5
*
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6
*/
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7
8
+
#include <linux/bitfield.h>
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+
8
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#ifndef _OCTEP_REGS_CN9K_PF_H_
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#define _OCTEP_REGS_CN9K_PF_H_
10
12
···
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#define CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX BIT_ULL(0)
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/* bit 1 for firmware heartbeat interrupt */
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#define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1)
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+
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+
#define FW_STATUS_DOWNING 0ULL
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+
#define FW_STATUS_RUNNING 2ULL
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+
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+
#define CN9K_PEM_GENMASK BIT_ULL(36)
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+
#define CN9K_PF_GENMASK GENMASK_ULL(21, 18)
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+
#define CN9K_PFX_CSX_PFCFGX_SHADOW_BIT BIT_ULL(16)
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+
#define CN9K_PFX_CSX_PFCFGX_BASE_ADDR (0x8e0000008000ULL)
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+
#define CN9K_4BYTE_ALIGNED_ADDRESS_OFFSET(offset) ((offset) & BIT_ULL(2))
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+
#define CN9K_PEMX_PFX_CSX_PFCFGX cn9k_pemx_pfx_csx_pfcfgx
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+
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+
static inline u64 cn9k_pemx_pfx_csx_pfcfgx(u64 pem, u32 pf, u32 offset)
397
+
{
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+
u32 shadow_addr_bit, pf_addr_bits, aligned_offset;
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+
u64 pem_addr_bits;
400
+
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+
pem_addr_bits = FIELD_PREP(CN9K_PEM_GENMASK, pem);
402
+
pf_addr_bits = FIELD_PREP(CN9K_PF_GENMASK, pf);
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+
shadow_addr_bit = CN9K_PFX_CSX_PFCFGX_SHADOW_BIT & (offset);
404
+
aligned_offset = rounddown((offset), 8);
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+
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+
return (CN9K_PFX_CSX_PFCFGX_BASE_ADDR | pem_addr_bits
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+
| pf_addr_bits | shadow_addr_bit | aligned_offset)
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+
+ CN9K_4BYTE_ALIGNED_ADDRESS_OFFSET(offset);
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+
}
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+
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+
/* Register defines for use with CN9K_PEMX_PFX_CSX_PFCFGX */
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+
#define CN9K_PCIEEP_VSECST_CTL 0x4D0
387
413
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#define CN93_PEM_BAR4_INDEX 7
389
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#define CN93_PEM_BAR4_INDEX_SIZE 0x400000ULL
+1
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
+1
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
···
396
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#define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX BIT_ULL(0)
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/* bit 1 for firmware heartbeat interrupt */
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#define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1)
399
+
#define FW_STATUS_DOWNING 0ULL
399
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#define FW_STATUS_RUNNING 2ULL
400
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#define CNXK_PEMX_PFX_CSX_PFCFGX(pem, pf, offset) ({ typeof(offset) _off = (offset); \
401
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((0x8e0000008000 | \