[PATCH] KVM: Move common msr handling to arch independent code

+2 -3

drivers/kvm/kvm.h

··· 374 374 void set_cr8(struct kvm_vcpu *vcpu, unsigned long cr0); 375 375 void lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 376 376 377 - #ifdef CONFIG_X86_64 378 - void set_efer(struct kvm_vcpu *vcpu, u64 efer); 379 - #endif 377 + int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); 378 + int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data); 380 379 381 380 void fx_init(struct kvm_vcpu *vcpu); 382 381

+69 -2

drivers/kvm/kvm_main.c

··· 1103 1103 } 1104 1104 } 1105 1105 1106 + int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 1107 + { 1108 + u64 data; 1109 + 1110 + switch (msr) { 1111 + case 0xc0010010: /* SYSCFG */ 1112 + case 0xc0010015: /* HWCR */ 1113 + case MSR_IA32_PLATFORM_ID: 1114 + case MSR_IA32_P5_MC_ADDR: 1115 + case MSR_IA32_P5_MC_TYPE: 1116 + case MSR_IA32_MC0_CTL: 1117 + case MSR_IA32_MCG_STATUS: 1118 + case MSR_IA32_MCG_CAP: 1119 + case MSR_IA32_MC0_MISC: 1120 + case MSR_IA32_MC0_MISC+4: 1121 + case MSR_IA32_MC0_MISC+8: 1122 + case MSR_IA32_MC0_MISC+12: 1123 + case MSR_IA32_MC0_MISC+16: 1124 + case MSR_IA32_UCODE_REV: 1125 + /* MTRR registers */ 1126 + case 0xfe: 1127 + case 0x200 ... 0x2ff: 1128 + data = 0; 1129 + break; 1130 + case MSR_IA32_APICBASE: 1131 + data = vcpu->apic_base; 1132 + break; 1133 + #ifdef CONFIG_X86_64 1134 + case MSR_EFER: 1135 + data = vcpu->shadow_efer; 1136 + break; 1137 + #endif 1138 + default: 1139 + printk(KERN_ERR "kvm: unhandled rdmsr: 0x%x\n", msr); 1140 + return 1; 1141 + } 1142 + *pdata = data; 1143 + return 0; 1144 + } 1145 + EXPORT_SYMBOL_GPL(kvm_get_msr_common); 1146 + 1106 1147 /* 1107 1148 * Reads an msr value (of 'msr_index') into 'pdata'. 1108 1149 * Returns 0 on success, non-0 otherwise. ··· 1156 1115 1157 1116 #ifdef CONFIG_X86_64 1158 1117 1159 - void set_efer(struct kvm_vcpu *vcpu, u64 efer) 1118 + static void set_efer(struct kvm_vcpu *vcpu, u64 efer) 1160 1119 { 1161 1120 if (efer & EFER_RESERVED_BITS) { 1162 1121 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n", ··· 1179 1138 1180 1139 vcpu->shadow_efer = efer; 1181 1140 } 1182 - EXPORT_SYMBOL_GPL(set_efer); 1183 1141 1184 1142 #endif 1143 + 1144 + int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1145 + { 1146 + switch (msr) { 1147 + #ifdef CONFIG_X86_64 1148 + case MSR_EFER: 1149 + set_efer(vcpu, data); 1150 + break; 1151 + #endif 1152 + case MSR_IA32_MC0_STATUS: 1153 + printk(KERN_WARNING "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n", 1154 + __FUNCTION__, data); 1155 + break; 1156 + case MSR_IA32_UCODE_REV: 1157 + case MSR_IA32_UCODE_WRITE: 1158 + case 0x200 ... 0x2ff: /* MTRRs */ 1159 + break; 1160 + case MSR_IA32_APICBASE: 1161 + vcpu->apic_base = data; 1162 + break; 1163 + default: 1164 + printk(KERN_ERR "kvm: unhandled wrmsr: 0x%x\n", msr); 1165 + return 1; 1166 + } 1167 + return 0; 1168 + } 1169 + EXPORT_SYMBOL_GPL(kvm_set_msr_common); 1185 1170 1186 1171 /* 1187 1172 * Writes msr value into into the appropriate "register".

+2 -45

drivers/kvm/svm.c

··· 1068 1068 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) 1069 1069 { 1070 1070 switch (ecx) { 1071 - case 0xc0010010: /* SYSCFG */ 1072 - case 0xc0010015: /* HWCR */ 1073 - case MSR_IA32_PLATFORM_ID: 1074 - case MSR_IA32_P5_MC_ADDR: 1075 - case MSR_IA32_P5_MC_TYPE: 1076 - case MSR_IA32_MC0_CTL: 1077 - case MSR_IA32_MCG_STATUS: 1078 - case MSR_IA32_MCG_CAP: 1079 - case MSR_IA32_MC0_MISC: 1080 - case MSR_IA32_MC0_MISC+4: 1081 - case MSR_IA32_MC0_MISC+8: 1082 - case MSR_IA32_MC0_MISC+12: 1083 - case MSR_IA32_MC0_MISC+16: 1084 - case MSR_IA32_UCODE_REV: 1085 - /* MTRR registers */ 1086 - case 0xfe: 1087 - case 0x200 ... 0x2ff: 1088 - *data = 0; 1089 - break; 1090 1071 case MSR_IA32_TIME_STAMP_COUNTER: { 1091 1072 u64 tsc; 1092 1073 ··· 1075 1094 *data = vcpu->svm->vmcb->control.tsc_offset + tsc; 1076 1095 break; 1077 1096 } 1078 - case MSR_EFER: 1079 - *data = vcpu->shadow_efer; 1080 - break; 1081 - case MSR_IA32_APICBASE: 1082 - *data = vcpu->apic_base; 1083 - break; 1084 1097 case MSR_K6_STAR: 1085 1098 *data = vcpu->svm->vmcb->save.star; 1086 1099 break; ··· 1102 1127 *data = vcpu->svm->vmcb->save.sysenter_esp; 1103 1128 break; 1104 1129 default: 1105 - printk(KERN_ERR "kvm: unhandled rdmsr: 0x%x\n", ecx); 1106 - return 1; 1130 + return kvm_get_msr_common(vcpu, ecx, data); 1107 1131 } 1108 1132 return 0; 1109 1133 } ··· 1126 1152 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) 1127 1153 { 1128 1154 switch (ecx) { 1129 - #ifdef CONFIG_X86_64 1130 - case MSR_EFER: 1131 - set_efer(vcpu, data); 1132 - break; 1133 - #endif 1134 - case MSR_IA32_MC0_STATUS: 1135 - printk(KERN_WARNING "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n" 1136 - , __FUNCTION__, data); 1137 - break; 1138 1155 case MSR_IA32_TIME_STAMP_COUNTER: { 1139 1156 u64 tsc; 1140 1157 ··· 1133 1168 vcpu->svm->vmcb->control.tsc_offset = data - tsc; 1134 1169 break; 1135 1170 } 1136 - case MSR_IA32_UCODE_REV: 1137 - case MSR_IA32_UCODE_WRITE: 1138 - case 0x200 ... 0x2ff: /* MTRRs */ 1139 - break; 1140 - case MSR_IA32_APICBASE: 1141 - vcpu->apic_base = data; 1142 - break; 1143 1171 case MSR_K6_STAR: 1144 1172 vcpu->svm->vmcb->save.star = data; 1145 1173 break; ··· 1160 1202 vcpu->svm->vmcb->save.sysenter_esp = data; 1161 1203 break; 1162 1204 default: 1163 - printk(KERN_ERR "kvm: unhandled wrmsr: %x\n", ecx); 1164 - return 1; 1205 + return kvm_set_msr_common(vcpu, ecx, data); 1165 1206 } 1166 1207 return 0; 1167 1208 }

+11 -48

drivers/kvm/vmx.c

··· 344 344 data = vmcs_readl(GUEST_GS_BASE); 345 345 break; 346 346 case MSR_EFER: 347 - data = vcpu->shadow_efer; 348 - break; 347 + return kvm_get_msr_common(vcpu, msr_index, pdata); 349 348 #endif 350 349 case MSR_IA32_TIME_STAMP_COUNTER: 351 350 data = guest_read_tsc(); ··· 358 359 case MSR_IA32_SYSENTER_ESP: 359 360 data = vmcs_read32(GUEST_SYSENTER_ESP); 360 361 break; 361 - case 0xc0010010: /* SYSCFG */ 362 - case 0xc0010015: /* HWCR */ 363 - case MSR_IA32_PLATFORM_ID: 364 - case MSR_IA32_P5_MC_ADDR: 365 - case MSR_IA32_P5_MC_TYPE: 366 - case MSR_IA32_MC0_CTL: 367 - case MSR_IA32_MCG_STATUS: 368 - case MSR_IA32_MCG_CAP: 369 - case MSR_IA32_MC0_MISC: 370 - case MSR_IA32_MC0_MISC+4: 371 - case MSR_IA32_MC0_MISC+8: 372 - case MSR_IA32_MC0_MISC+12: 373 - case MSR_IA32_MC0_MISC+16: 374 - case MSR_IA32_UCODE_REV: 375 - /* MTRR registers */ 376 - case 0xfe: 377 - case 0x200 ... 0x2ff: 378 - data = 0; 379 - break; 380 - case MSR_IA32_APICBASE: 381 - data = vcpu->apic_base; 382 - break; 383 362 default: 384 363 msr = find_msr_entry(vcpu, msr_index); 385 - if (!msr) { 386 - printk(KERN_ERR "kvm: unhandled rdmsr: %x\n", msr_index); 387 - return 1; 364 + if (msr) { 365 + data = msr->data; 366 + break; 388 367 } 389 - data = msr->data; 390 - break; 368 + return kvm_get_msr_common(vcpu, msr_index, pdata); 391 369 } 392 370 393 371 *pdata = data; ··· 381 405 struct vmx_msr_entry *msr; 382 406 switch (msr_index) { 383 407 #ifdef CONFIG_X86_64 408 + case MSR_EFER: 409 + return kvm_set_msr_common(vcpu, msr_index, data); 384 410 case MSR_FS_BASE: 385 411 vmcs_writel(GUEST_FS_BASE, data); 386 412 break; ··· 399 421 case MSR_IA32_SYSENTER_ESP: 400 422 vmcs_write32(GUEST_SYSENTER_ESP, data); 401 423 break; 402 - #ifdef __x86_64 403 - case MSR_EFER: 404 - set_efer(vcpu, data); 405 - break; 406 - case MSR_IA32_MC0_STATUS: 407 - printk(KERN_WARNING "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n" 408 - , __FUNCTION__, data); 409 - break; 410 - #endif 411 424 case MSR_IA32_TIME_STAMP_COUNTER: { 412 425 guest_write_tsc(data); 413 426 break; 414 427 } 415 - case MSR_IA32_UCODE_REV: 416 - case MSR_IA32_UCODE_WRITE: 417 - case 0x200 ... 0x2ff: /* MTRRs */ 418 - break; 419 - case MSR_IA32_APICBASE: 420 - vcpu->apic_base = data; 421 - break; 422 428 default: 423 429 msr = find_msr_entry(vcpu, msr_index); 424 - if (!msr) { 425 - printk(KERN_ERR "kvm: unhandled wrmsr: 0x%x\n", msr_index); 426 - return 1; 430 + if (msr) { 431 + msr->data = data; 432 + break; 427 433 } 434 + return kvm_set_msr_common(vcpu, msr_index, data); 428 435 msr->data = data; 429 436 break; 430 437 }

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