Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/ast: Move Gen6+ POST code to separate source file
Move POST code for Gen6+ to separate source file and hide it in
ast_2500_post(). With P2A configuration, it performs a full board
POST; otherwise it enables the transmitter chip. No changes to the
overall logic.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://lore.kernel.org/r/20250706162816.211552-4-tzimmermann@suse.de
+576
-522
+1
drivers/gpu/drm/ast/Makefile
+1
drivers/gpu/drm/ast/Makefile
+567
drivers/gpu/drm/ast/ast_2500.c
+567
drivers/gpu/drm/ast/ast_2500.c
···
1
+
// SPDX-License-Identifier: MIT
2
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
25
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/*
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* Authors: Dave Airlie <airlied@redhat.com>
27
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*/
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+
29
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#include <linux/delay.h>
30
+
31
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#include <drm/drm_print.h>
32
+
33
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#include "ast_drv.h"
34
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#include "ast_post.h"
35
+
36
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/*
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* POST
38
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*/
39
+
40
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/*
41
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* AST2500 DRAM settings modules
42
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*/
43
+
44
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#define REGTBL_NUM 17
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#define REGIDX_010 0
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#define REGIDX_014 1
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#define REGIDX_018 2
48
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#define REGIDX_020 3
49
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#define REGIDX_024 4
50
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#define REGIDX_02C 5
51
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#define REGIDX_030 6
52
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#define REGIDX_214 7
53
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#define REGIDX_2E0 8
54
+
#define REGIDX_2E4 9
55
+
#define REGIDX_2E8 10
56
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#define REGIDX_2EC 11
57
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#define REGIDX_2F0 12
58
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#define REGIDX_2F4 13
59
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#define REGIDX_2F8 14
60
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#define REGIDX_RFC 15
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#define REGIDX_PLL 16
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+
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static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
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0x64604D38, /* 0x010 */
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0x29690599, /* 0x014 */
66
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0x00000300, /* 0x018 */
67
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0x00000000, /* 0x020 */
68
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0x00000000, /* 0x024 */
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0x02181E70, /* 0x02C */
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0x00000040, /* 0x030 */
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0x00000024, /* 0x214 */
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0x02001300, /* 0x2E0 */
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0x0E0000A0, /* 0x2E4 */
74
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0x000E001B, /* 0x2E8 */
75
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0x35B8C105, /* 0x2EC */
76
+
0x08090408, /* 0x2F0 */
77
+
0x9B000800, /* 0x2F4 */
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0x0E400A00, /* 0x2F8 */
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0x9971452F, /* tRFC */
80
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0x000071C1 /* PLL */
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+
};
82
+
83
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static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
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0x63604E37, /* 0x010 */
85
+
0xE97AFA99, /* 0x014 */
86
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0x00019000, /* 0x018 */
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0x08000000, /* 0x020 */
88
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0x00000400, /* 0x024 */
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0x00000410, /* 0x02C */
90
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0x00000101, /* 0x030 */
91
+
0x00000024, /* 0x214 */
92
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0x03002900, /* 0x2E0 */
93
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0x0E0000A0, /* 0x2E4 */
94
+
0x000E001C, /* 0x2E8 */
95
+
0x35B8C106, /* 0x2EC */
96
+
0x08080607, /* 0x2F0 */
97
+
0x9B000900, /* 0x2F4 */
98
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0x0E400A00, /* 0x2F8 */
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0x99714545, /* tRFC */
100
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0x000071C1 /* PLL */
101
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};
102
+
103
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#define TIMEOUT 5000000
104
+
105
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void ast_2500_patch_ahb(void __iomem *regs)
106
+
{
107
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u32 data;
108
+
109
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/* Clear bus lock condition */
110
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__ast_moutdwm(regs, 0x1e600000, 0xAEED1A03);
111
+
__ast_moutdwm(regs, 0x1e600084, 0x00010000);
112
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__ast_moutdwm(regs, 0x1e600088, 0x00000000);
113
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__ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
114
+
115
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data = __ast_mindwm(regs, 0x1e6e2070);
116
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if (data & 0x08000000) { /* check fast reset */
117
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/*
118
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* If "Fast restet" is enabled for ARM-ICE debugger,
119
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* then WDT needs to enable, that
120
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* WDT04 is WDT#1 Reload reg.
121
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* WDT08 is WDT#1 counter restart reg to avoid system deadlock
122
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* WDT0C is WDT#1 control reg
123
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* [6:5]:= 01:Full chip
124
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* [4]:= 1:1MHz clock source
125
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* [1]:= 1:WDT will be cleeared and disabled after timeout occurs
126
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* [0]:= 1:WDT enable
127
+
*/
128
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__ast_moutdwm(regs, 0x1E785004, 0x00000010);
129
+
__ast_moutdwm(regs, 0x1E785008, 0x00004755);
130
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__ast_moutdwm(regs, 0x1E78500c, 0x00000033);
131
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udelay(1000);
132
+
}
133
+
134
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do {
135
+
__ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
136
+
data = __ast_mindwm(regs, 0x1e6e2000);
137
+
} while (data != 1);
138
+
139
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__ast_moutdwm(regs, 0x1e6e207c, 0x08000000); /* clear fast reset */
140
+
}
141
+
142
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static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen)
143
+
{
144
+
return mmc_test(ast, datagen, 0x85);
145
+
}
146
+
147
+
static bool cbr_test_2500(struct ast_device *ast)
148
+
{
149
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ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
150
+
ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
151
+
if (!mmc_test_burst(ast, 0))
152
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return false;
153
+
if (!mmc_test_single_2500(ast, 0))
154
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return false;
155
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return true;
156
+
}
157
+
158
+
static bool ddr_test_2500(struct ast_device *ast)
159
+
{
160
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ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
161
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ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
162
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if (!mmc_test_burst(ast, 0))
163
+
return false;
164
+
if (!mmc_test_burst(ast, 1))
165
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return false;
166
+
if (!mmc_test_burst(ast, 2))
167
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return false;
168
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if (!mmc_test_burst(ast, 3))
169
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return false;
170
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if (!mmc_test_single_2500(ast, 0))
171
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return false;
172
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return true;
173
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}
174
+
175
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static void ddr_init_common_2500(struct ast_device *ast)
176
+
{
177
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ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
178
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ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
179
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ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
180
+
ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
181
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ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
182
+
ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
183
+
ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
184
+
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
185
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ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
186
+
ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
187
+
ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
188
+
ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
189
+
ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
190
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ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
191
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ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
192
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ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
193
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ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
194
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ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
195
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ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
196
+
}
197
+
198
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static void ddr_phy_init_2500(struct ast_device *ast)
199
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{
200
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u32 data, pass, timecnt;
201
+
202
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pass = 0;
203
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ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
204
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while (!pass) {
205
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for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
206
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data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
207
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if (!data)
208
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break;
209
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}
210
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if (timecnt != TIMEOUT) {
211
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data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
212
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if (!data)
213
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pass = 1;
214
+
}
215
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if (!pass) {
216
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ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
217
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udelay(10); /* delay 10 us */
218
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ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
219
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}
220
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}
221
+
222
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ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
223
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}
224
+
225
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/*
226
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* Check DRAM Size
227
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* 1Gb : 0x80000000 ~ 0x87FFFFFF
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* 2Gb : 0x80000000 ~ 0x8FFFFFFF
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* 4Gb : 0x80000000 ~ 0x9FFFFFFF
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* 8Gb : 0x80000000 ~ 0xBFFFFFFF
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*/
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static void check_dram_size_2500(struct ast_device *ast, u32 tRFC)
233
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{
234
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u32 reg_04, reg_14;
235
+
236
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reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
237
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reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
238
+
239
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ast_moutdwm(ast, 0xA0100000, 0x41424344);
240
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ast_moutdwm(ast, 0x90100000, 0x35363738);
241
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ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
242
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ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
243
+
244
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/* Check 8Gbit */
245
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if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
246
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reg_04 |= 0x03;
247
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reg_14 |= (tRFC >> 24) & 0xFF;
248
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/* Check 4Gbit */
249
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} else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
250
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reg_04 |= 0x02;
251
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reg_14 |= (tRFC >> 16) & 0xFF;
252
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/* Check 2Gbit */
253
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} else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
254
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reg_04 |= 0x01;
255
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reg_14 |= (tRFC >> 8) & 0xFF;
256
+
} else {
257
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reg_14 |= tRFC & 0xFF;
258
+
}
259
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ast_moutdwm(ast, 0x1E6E0004, reg_04);
260
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ast_moutdwm(ast, 0x1E6E0014, reg_14);
261
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}
262
+
263
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static void enable_cache_2500(struct ast_device *ast)
264
+
{
265
+
u32 reg_04, data;
266
+
267
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reg_04 = ast_mindwm(ast, 0x1E6E0004);
268
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ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
269
+
270
+
do
271
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data = ast_mindwm(ast, 0x1E6E0004);
272
+
while (!(data & 0x80000));
273
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ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
274
+
}
275
+
276
+
static void set_mpll_2500(struct ast_device *ast)
277
+
{
278
+
u32 addr, data, param;
279
+
280
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/* Reset MMC */
281
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ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
282
+
ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
283
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for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
284
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ast_moutdwm(ast, addr, 0x0);
285
+
addr += 4;
286
+
}
287
+
ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
288
+
289
+
ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
290
+
data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
291
+
if (data) {
292
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/* CLKIN = 25MHz */
293
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param = 0x930023E0;
294
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ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
295
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} else {
296
+
/* CLKIN = 24MHz */
297
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param = 0x93002400;
298
+
}
299
+
ast_moutdwm(ast, 0x1E6E2020, param);
300
+
udelay(100);
301
+
}
302
+
303
+
static void reset_mmc_2500(struct ast_device *ast)
304
+
{
305
+
ast_moutdwm(ast, 0x1E78505C, 0x00000004);
306
+
ast_moutdwm(ast, 0x1E785044, 0x00000001);
307
+
ast_moutdwm(ast, 0x1E785048, 0x00004755);
308
+
ast_moutdwm(ast, 0x1E78504C, 0x00000013);
309
+
mdelay(100);
310
+
ast_moutdwm(ast, 0x1E785054, 0x00000077);
311
+
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
312
+
}
313
+
314
+
static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table)
315
+
{
316
+
ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
317
+
ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
318
+
ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
319
+
ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
320
+
ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
321
+
ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
322
+
ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
323
+
ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
324
+
325
+
/* DDR PHY Setting */
326
+
ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
327
+
ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
328
+
ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
329
+
ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
330
+
ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
331
+
ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
332
+
ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
333
+
ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
334
+
ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
335
+
ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
336
+
ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
337
+
ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
338
+
ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
339
+
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
340
+
341
+
/* Controller Setting */
342
+
ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
343
+
344
+
/* Wait DDR PHY init done */
345
+
ddr_phy_init_2500(ast);
346
+
347
+
ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
348
+
ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
349
+
ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
350
+
351
+
check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
352
+
enable_cache_2500(ast);
353
+
ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
354
+
ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
355
+
}
356
+
357
+
static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table)
358
+
{
359
+
u32 data, data2, pass, retrycnt;
360
+
u32 ddr_vref, phy_vref;
361
+
u32 min_ddr_vref = 0, min_phy_vref = 0;
362
+
u32 max_ddr_vref = 0, max_phy_vref = 0;
363
+
364
+
ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
365
+
ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
366
+
ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
367
+
ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
368
+
ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
369
+
ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
370
+
ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
371
+
ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
372
+
373
+
/* DDR PHY Setting */
374
+
ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
375
+
ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
376
+
ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
377
+
ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
378
+
ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
379
+
ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
380
+
ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
381
+
ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
382
+
ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
383
+
ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
384
+
ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
385
+
ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
386
+
ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
387
+
ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
388
+
ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
389
+
390
+
/* Controller Setting */
391
+
ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
392
+
393
+
/* Train PHY Vref first */
394
+
pass = 0;
395
+
396
+
for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
397
+
max_phy_vref = 0x0;
398
+
pass = 0;
399
+
ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
400
+
for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
401
+
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
402
+
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
403
+
ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
404
+
/* Fire DFI Init */
405
+
ddr_phy_init_2500(ast);
406
+
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
407
+
if (cbr_test_2500(ast)) {
408
+
pass++;
409
+
data = ast_mindwm(ast, 0x1E6E03D0);
410
+
data2 = data >> 8;
411
+
data = data & 0xff;
412
+
if (data > data2)
413
+
data = data2;
414
+
if (max_phy_vref < data) {
415
+
max_phy_vref = data;
416
+
min_phy_vref = phy_vref;
417
+
}
418
+
} else if (pass > 0) {
419
+
break;
420
+
}
421
+
}
422
+
}
423
+
ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
424
+
425
+
/* Train DDR Vref next */
426
+
pass = 0;
427
+
428
+
for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
429
+
min_ddr_vref = 0xFF;
430
+
max_ddr_vref = 0x0;
431
+
pass = 0;
432
+
for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
433
+
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
434
+
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
435
+
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
436
+
/* Fire DFI Init */
437
+
ddr_phy_init_2500(ast);
438
+
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
439
+
if (cbr_test_2500(ast)) {
440
+
pass++;
441
+
if (min_ddr_vref > ddr_vref)
442
+
min_ddr_vref = ddr_vref;
443
+
if (max_ddr_vref < ddr_vref)
444
+
max_ddr_vref = ddr_vref;
445
+
} else if (pass != 0) {
446
+
break;
447
+
}
448
+
}
449
+
}
450
+
451
+
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
452
+
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
453
+
ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
454
+
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
455
+
456
+
/* Wait DDR PHY init done */
457
+
ddr_phy_init_2500(ast);
458
+
459
+
ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
460
+
ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
461
+
ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
462
+
463
+
check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
464
+
enable_cache_2500(ast);
465
+
ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
466
+
ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
467
+
}
468
+
469
+
static bool ast_dram_init_2500(struct ast_device *ast)
470
+
{
471
+
u32 data;
472
+
u32 max_tries = 5;
473
+
474
+
do {
475
+
if (max_tries-- == 0)
476
+
return false;
477
+
set_mpll_2500(ast);
478
+
reset_mmc_2500(ast);
479
+
ddr_init_common_2500(ast);
480
+
481
+
data = ast_mindwm(ast, 0x1E6E2070);
482
+
if (data & 0x01000000)
483
+
ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
484
+
else
485
+
ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
486
+
} while (!ddr_test_2500(ast));
487
+
488
+
ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
489
+
490
+
/* Patch code */
491
+
data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
492
+
ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
493
+
494
+
return true;
495
+
}
496
+
497
+
static void ast_post_chip_2500(struct ast_device *ast)
498
+
{
499
+
struct drm_device *dev = &ast->base;
500
+
u32 temp;
501
+
u8 reg;
502
+
503
+
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
504
+
if ((reg & AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */
505
+
/* Clear bus lock condition */
506
+
ast_2500_patch_ahb(ast->regs);
507
+
508
+
/* Disable watchdog */
509
+
ast_moutdwm(ast, 0x1E78502C, 0x00000000);
510
+
ast_moutdwm(ast, 0x1E78504C, 0x00000000);
511
+
512
+
/*
513
+
* Reset USB port to patch USB unknown device issue
514
+
* SCU90 is Multi-function Pin Control #5
515
+
* [29]:= 1:Enable USB2.0 Host port#1 (that the mutually shared USB2.0 Hub
516
+
* port).
517
+
* SCU94 is Multi-function Pin Control #6
518
+
* [14:13]:= 1x:USB2.0 Host2 controller
519
+
* SCU70 is Hardware Strap reg
520
+
* [23]:= 1:CLKIN is 25MHz and USBCK1 = 24/48 MHz (determined by
521
+
* [18]: 0(24)/1(48) MHz)
522
+
* SCU7C is Write clear reg to SCU70
523
+
* [23]:= write 1 and then SCU70[23] will be clear as 0b.
524
+
*/
525
+
ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
526
+
ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
527
+
if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
528
+
ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
529
+
mdelay(100);
530
+
ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
531
+
}
532
+
/* Modify eSPI reset pin */
533
+
temp = ast_mindwm(ast, 0x1E6E2070);
534
+
if (temp & 0x02000000)
535
+
ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
536
+
537
+
/* Slow down CPU/AHB CLK in VGA only mode */
538
+
temp = ast_read32(ast, 0x12008);
539
+
temp |= 0x73;
540
+
ast_write32(ast, 0x12008, temp);
541
+
542
+
if (!ast_dram_init_2500(ast))
543
+
drm_err(dev, "DRAM init failed !\n");
544
+
545
+
temp = ast_mindwm(ast, 0x1e6e2040);
546
+
ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
547
+
}
548
+
549
+
/* wait ready */
550
+
do {
551
+
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
552
+
} while ((reg & 0x40) == 0);
553
+
}
554
+
555
+
int ast_2500_post(struct ast_device *ast)
556
+
{
557
+
if (ast->config_mode == ast_use_p2a) {
558
+
ast_post_chip_2500(ast);
559
+
} else {
560
+
if (ast->tx_chip == AST_TX_SIL164) {
561
+
/* Enable DVO */
562
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
563
+
}
564
+
}
565
+
566
+
return 0;
567
+
}
-62
drivers/gpu/drm/ast/ast_dram_tables.h
-62
drivers/gpu/drm/ast/ast_dram_tables.h
···
142
142
{ 0xffff, 0xffffffff },
143
143
};
144
144
145
-
/*
146
-
* AST2500 DRAM settings modules
147
-
*/
148
-
#define REGTBL_NUM 17
149
-
#define REGIDX_010 0
150
-
#define REGIDX_014 1
151
-
#define REGIDX_018 2
152
-
#define REGIDX_020 3
153
-
#define REGIDX_024 4
154
-
#define REGIDX_02C 5
155
-
#define REGIDX_030 6
156
-
#define REGIDX_214 7
157
-
#define REGIDX_2E0 8
158
-
#define REGIDX_2E4 9
159
-
#define REGIDX_2E8 10
160
-
#define REGIDX_2EC 11
161
-
#define REGIDX_2F0 12
162
-
#define REGIDX_2F4 13
163
-
#define REGIDX_2F8 14
164
-
#define REGIDX_RFC 15
165
-
#define REGIDX_PLL 16
166
-
167
-
static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
168
-
0x64604D38, /* 0x010 */
169
-
0x29690599, /* 0x014 */
170
-
0x00000300, /* 0x018 */
171
-
0x00000000, /* 0x020 */
172
-
0x00000000, /* 0x024 */
173
-
0x02181E70, /* 0x02C */
174
-
0x00000040, /* 0x030 */
175
-
0x00000024, /* 0x214 */
176
-
0x02001300, /* 0x2E0 */
177
-
0x0E0000A0, /* 0x2E4 */
178
-
0x000E001B, /* 0x2E8 */
179
-
0x35B8C105, /* 0x2EC */
180
-
0x08090408, /* 0x2F0 */
181
-
0x9B000800, /* 0x2F4 */
182
-
0x0E400A00, /* 0x2F8 */
183
-
0x9971452F, /* tRFC */
184
-
0x000071C1 /* PLL */
185
-
};
186
-
187
-
static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
188
-
0x63604E37, /* 0x010 */
189
-
0xE97AFA99, /* 0x014 */
190
-
0x00019000, /* 0x018 */
191
-
0x08000000, /* 0x020 */
192
-
0x00000400, /* 0x024 */
193
-
0x00000410, /* 0x02C */
194
-
0x00000101, /* 0x030 */
195
-
0x00000024, /* 0x214 */
196
-
0x03002900, /* 0x2E0 */
197
-
0x0E0000A0, /* 0x2E4 */
198
-
0x000E001C, /* 0x2E8 */
199
-
0x35B8C106, /* 0x2EC */
200
-
0x08080607, /* 0x2F0 */
201
-
0x9B000900, /* 0x2F4 */
202
-
0x0E400A00, /* 0x2F8 */
203
-
0x99714545, /* tRFC */
204
-
0x000071C1 /* PLL */
205
-
};
206
-
207
145
#endif
+1
-1
drivers/gpu/drm/ast/ast_drv.c
+1
-1
drivers/gpu/drm/ast/ast_drv.c
+4
-1
drivers/gpu/drm/ast/ast_drv.h
+4
-1
drivers/gpu/drm/ast/ast_drv.h
···
417
417
418
418
int ast_mm_init(struct ast_device *ast);
419
419
420
+
/* ast_2500.c */
421
+
void ast_2500_patch_ahb(void __iomem *regs);
422
+
int ast_2500_post(struct ast_device *ast);
423
+
420
424
/* ast_2600.c */
421
425
int ast_2600_post(struct ast_device *ast);
422
426
···
428
424
int ast_post_gpu(struct ast_device *ast);
429
425
u32 ast_mindwm(struct ast_device *ast, u32 r);
430
426
void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
431
-
void ast_patch_ahb_2500(void __iomem *regs);
432
427
433
428
int ast_vga_output_init(struct ast_device *ast);
434
429
int ast_sil164_output_init(struct ast_device *ast);
+3
-458
drivers/gpu/drm/ast/ast_post.c
+3
-458
drivers/gpu/drm/ast/ast_post.c
···
36
36
#include "ast_post.h"
37
37
38
38
static void ast_post_chip_2300(struct ast_device *ast);
39
-
static void ast_post_chip_2500(struct ast_device *ast);
40
39
41
40
static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
42
41
static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
···
351
352
if (ret)
352
353
return ret;
353
354
} else if (AST_GEN(ast) >= 6) {
354
-
if (ast->config_mode == ast_use_p2a) {
355
-
ast_post_chip_2500(ast);
356
-
} else {
357
-
if (ast->tx_chip == AST_TX_SIL164) {
358
-
/* Enable DVO */
359
-
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
360
-
}
361
-
}
355
+
ret = ast_2500_post(ast);
356
+
if (ret)
357
+
return ret;
362
358
} else if (AST_GEN(ast) >= 4) {
363
359
if (ast->config_mode == ast_use_p2a) {
364
360
ast_post_chip_2300(ast);
···
489
495
static u32 mmc_test_single2(struct ast_device *ast, u32 datagen)
490
496
{
491
497
return mmc_test2(ast, datagen, 0x05);
492
-
}
493
-
494
-
static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen)
495
-
{
496
-
return mmc_test(ast, datagen, 0x85);
497
498
}
498
499
499
500
static int cbr_test(struct ast_device *ast)
···
1645
1656
get_ddr2_info(ast, ¶m);
1646
1657
ddr2_init(ast, ¶m);
1647
1658
}
1648
-
1649
-
temp = ast_mindwm(ast, 0x1e6e2040);
1650
-
ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1651
-
}
1652
-
1653
-
/* wait ready */
1654
-
do {
1655
-
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1656
-
} while ((reg & 0x40) == 0);
1657
-
}
1658
-
1659
-
static bool cbr_test_2500(struct ast_device *ast)
1660
-
{
1661
-
ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1662
-
ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1663
-
if (!mmc_test_burst(ast, 0))
1664
-
return false;
1665
-
if (!mmc_test_single_2500(ast, 0))
1666
-
return false;
1667
-
return true;
1668
-
}
1669
-
1670
-
static bool ddr_test_2500(struct ast_device *ast)
1671
-
{
1672
-
ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1673
-
ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1674
-
if (!mmc_test_burst(ast, 0))
1675
-
return false;
1676
-
if (!mmc_test_burst(ast, 1))
1677
-
return false;
1678
-
if (!mmc_test_burst(ast, 2))
1679
-
return false;
1680
-
if (!mmc_test_burst(ast, 3))
1681
-
return false;
1682
-
if (!mmc_test_single_2500(ast, 0))
1683
-
return false;
1684
-
return true;
1685
-
}
1686
-
1687
-
static void ddr_init_common_2500(struct ast_device *ast)
1688
-
{
1689
-
ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1690
-
ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1691
-
ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1692
-
ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1693
-
ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1694
-
ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1695
-
ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1696
-
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1697
-
ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1698
-
ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1699
-
ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1700
-
ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1701
-
ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1702
-
ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1703
-
ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1704
-
ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1705
-
ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1706
-
ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1707
-
ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1708
-
}
1709
-
1710
-
static void ddr_phy_init_2500(struct ast_device *ast)
1711
-
{
1712
-
u32 data, pass, timecnt;
1713
-
1714
-
pass = 0;
1715
-
ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1716
-
while (!pass) {
1717
-
for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
1718
-
data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1719
-
if (!data)
1720
-
break;
1721
-
}
1722
-
if (timecnt != TIMEOUT) {
1723
-
data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1724
-
if (!data)
1725
-
pass = 1;
1726
-
}
1727
-
if (!pass) {
1728
-
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1729
-
udelay(10); /* delay 10 us */
1730
-
ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1731
-
}
1732
-
}
1733
-
1734
-
ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1735
-
}
1736
-
1737
-
/*
1738
-
* Check DRAM Size
1739
-
* 1Gb : 0x80000000 ~ 0x87FFFFFF
1740
-
* 2Gb : 0x80000000 ~ 0x8FFFFFFF
1741
-
* 4Gb : 0x80000000 ~ 0x9FFFFFFF
1742
-
* 8Gb : 0x80000000 ~ 0xBFFFFFFF
1743
-
*/
1744
-
static void check_dram_size_2500(struct ast_device *ast, u32 tRFC)
1745
-
{
1746
-
u32 reg_04, reg_14;
1747
-
1748
-
reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1749
-
reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1750
-
1751
-
ast_moutdwm(ast, 0xA0100000, 0x41424344);
1752
-
ast_moutdwm(ast, 0x90100000, 0x35363738);
1753
-
ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1754
-
ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1755
-
1756
-
/* Check 8Gbit */
1757
-
if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1758
-
reg_04 |= 0x03;
1759
-
reg_14 |= (tRFC >> 24) & 0xFF;
1760
-
/* Check 4Gbit */
1761
-
} else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1762
-
reg_04 |= 0x02;
1763
-
reg_14 |= (tRFC >> 16) & 0xFF;
1764
-
/* Check 2Gbit */
1765
-
} else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1766
-
reg_04 |= 0x01;
1767
-
reg_14 |= (tRFC >> 8) & 0xFF;
1768
-
} else {
1769
-
reg_14 |= tRFC & 0xFF;
1770
-
}
1771
-
ast_moutdwm(ast, 0x1E6E0004, reg_04);
1772
-
ast_moutdwm(ast, 0x1E6E0014, reg_14);
1773
-
}
1774
-
1775
-
static void enable_cache_2500(struct ast_device *ast)
1776
-
{
1777
-
u32 reg_04, data;
1778
-
1779
-
reg_04 = ast_mindwm(ast, 0x1E6E0004);
1780
-
ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1781
-
1782
-
do
1783
-
data = ast_mindwm(ast, 0x1E6E0004);
1784
-
while (!(data & 0x80000));
1785
-
ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1786
-
}
1787
-
1788
-
static void set_mpll_2500(struct ast_device *ast)
1789
-
{
1790
-
u32 addr, data, param;
1791
-
1792
-
/* Reset MMC */
1793
-
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1794
-
ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1795
-
for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
1796
-
ast_moutdwm(ast, addr, 0x0);
1797
-
addr += 4;
1798
-
}
1799
-
ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1800
-
1801
-
ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1802
-
data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1803
-
if (data) {
1804
-
/* CLKIN = 25MHz */
1805
-
param = 0x930023E0;
1806
-
ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1807
-
} else {
1808
-
/* CLKIN = 24MHz */
1809
-
param = 0x93002400;
1810
-
}
1811
-
ast_moutdwm(ast, 0x1E6E2020, param);
1812
-
udelay(100);
1813
-
}
1814
-
1815
-
static void reset_mmc_2500(struct ast_device *ast)
1816
-
{
1817
-
ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1818
-
ast_moutdwm(ast, 0x1E785044, 0x00000001);
1819
-
ast_moutdwm(ast, 0x1E785048, 0x00004755);
1820
-
ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1821
-
mdelay(100);
1822
-
ast_moutdwm(ast, 0x1E785054, 0x00000077);
1823
-
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1824
-
}
1825
-
1826
-
static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table)
1827
-
{
1828
-
1829
-
ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1830
-
ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1831
-
ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1832
-
ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1833
-
ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1834
-
ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1835
-
ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1836
-
ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1837
-
1838
-
/* DDR PHY Setting */
1839
-
ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1840
-
ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1841
-
ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1842
-
ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1843
-
ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1844
-
ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1845
-
ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1846
-
ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1847
-
ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1848
-
ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1849
-
ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1850
-
ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1851
-
ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1852
-
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1853
-
1854
-
/* Controller Setting */
1855
-
ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1856
-
1857
-
/* Wait DDR PHY init done */
1858
-
ddr_phy_init_2500(ast);
1859
-
1860
-
ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1861
-
ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1862
-
ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1863
-
1864
-
check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1865
-
enable_cache_2500(ast);
1866
-
ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1867
-
ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1868
-
}
1869
-
1870
-
static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table)
1871
-
{
1872
-
u32 data, data2, pass, retrycnt;
1873
-
u32 ddr_vref, phy_vref;
1874
-
u32 min_ddr_vref = 0, min_phy_vref = 0;
1875
-
u32 max_ddr_vref = 0, max_phy_vref = 0;
1876
-
1877
-
ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1878
-
ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1879
-
ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1880
-
ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1881
-
ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1882
-
ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1883
-
ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1884
-
ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1885
-
1886
-
/* DDR PHY Setting */
1887
-
ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1888
-
ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1889
-
ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1890
-
ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1891
-
ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1892
-
ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1893
-
ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1894
-
ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1895
-
ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1896
-
ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1897
-
ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1898
-
ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1899
-
ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1900
-
ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1901
-
ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1902
-
1903
-
/* Controller Setting */
1904
-
ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1905
-
1906
-
/* Train PHY Vref first */
1907
-
pass = 0;
1908
-
1909
-
for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1910
-
max_phy_vref = 0x0;
1911
-
pass = 0;
1912
-
ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1913
-
for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
1914
-
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1915
-
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1916
-
ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1917
-
/* Fire DFI Init */
1918
-
ddr_phy_init_2500(ast);
1919
-
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1920
-
if (cbr_test_2500(ast)) {
1921
-
pass++;
1922
-
data = ast_mindwm(ast, 0x1E6E03D0);
1923
-
data2 = data >> 8;
1924
-
data = data & 0xff;
1925
-
if (data > data2)
1926
-
data = data2;
1927
-
if (max_phy_vref < data) {
1928
-
max_phy_vref = data;
1929
-
min_phy_vref = phy_vref;
1930
-
}
1931
-
} else if (pass > 0)
1932
-
break;
1933
-
}
1934
-
}
1935
-
ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1936
-
1937
-
/* Train DDR Vref next */
1938
-
pass = 0;
1939
-
1940
-
for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1941
-
min_ddr_vref = 0xFF;
1942
-
max_ddr_vref = 0x0;
1943
-
pass = 0;
1944
-
for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
1945
-
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1946
-
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1947
-
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1948
-
/* Fire DFI Init */
1949
-
ddr_phy_init_2500(ast);
1950
-
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1951
-
if (cbr_test_2500(ast)) {
1952
-
pass++;
1953
-
if (min_ddr_vref > ddr_vref)
1954
-
min_ddr_vref = ddr_vref;
1955
-
if (max_ddr_vref < ddr_vref)
1956
-
max_ddr_vref = ddr_vref;
1957
-
} else if (pass != 0)
1958
-
break;
1959
-
}
1960
-
}
1961
-
1962
-
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1963
-
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1964
-
ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
1965
-
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1966
-
1967
-
/* Wait DDR PHY init done */
1968
-
ddr_phy_init_2500(ast);
1969
-
1970
-
ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1971
-
ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1972
-
ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1973
-
1974
-
check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1975
-
enable_cache_2500(ast);
1976
-
ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1977
-
ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1978
-
}
1979
-
1980
-
static bool ast_dram_init_2500(struct ast_device *ast)
1981
-
{
1982
-
u32 data;
1983
-
u32 max_tries = 5;
1984
-
1985
-
do {
1986
-
if (max_tries-- == 0)
1987
-
return false;
1988
-
set_mpll_2500(ast);
1989
-
reset_mmc_2500(ast);
1990
-
ddr_init_common_2500(ast);
1991
-
1992
-
data = ast_mindwm(ast, 0x1E6E2070);
1993
-
if (data & 0x01000000)
1994
-
ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
1995
-
else
1996
-
ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
1997
-
} while (!ddr_test_2500(ast));
1998
-
1999
-
ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
2000
-
2001
-
/* Patch code */
2002
-
data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
2003
-
ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
2004
-
2005
-
return true;
2006
-
}
2007
-
2008
-
void ast_patch_ahb_2500(void __iomem *regs)
2009
-
{
2010
-
u32 data;
2011
-
2012
-
/* Clear bus lock condition */
2013
-
__ast_moutdwm(regs, 0x1e600000, 0xAEED1A03);
2014
-
__ast_moutdwm(regs, 0x1e600084, 0x00010000);
2015
-
__ast_moutdwm(regs, 0x1e600088, 0x00000000);
2016
-
__ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
2017
-
2018
-
data = __ast_mindwm(regs, 0x1e6e2070);
2019
-
if (data & 0x08000000) { /* check fast reset */
2020
-
/*
2021
-
* If "Fast restet" is enabled for ARM-ICE debugger,
2022
-
* then WDT needs to enable, that
2023
-
* WDT04 is WDT#1 Reload reg.
2024
-
* WDT08 is WDT#1 counter restart reg to avoid system deadlock
2025
-
* WDT0C is WDT#1 control reg
2026
-
* [6:5]:= 01:Full chip
2027
-
* [4]:= 1:1MHz clock source
2028
-
* [1]:= 1:WDT will be cleeared and disabled after timeout occurs
2029
-
* [0]:= 1:WDT enable
2030
-
*/
2031
-
__ast_moutdwm(regs, 0x1E785004, 0x00000010);
2032
-
__ast_moutdwm(regs, 0x1E785008, 0x00004755);
2033
-
__ast_moutdwm(regs, 0x1E78500c, 0x00000033);
2034
-
udelay(1000);
2035
-
}
2036
-
2037
-
do {
2038
-
__ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
2039
-
data = __ast_mindwm(regs, 0x1e6e2000);
2040
-
} while (data != 1);
2041
-
2042
-
__ast_moutdwm(regs, 0x1e6e207c, 0x08000000); /* clear fast reset */
2043
-
}
2044
-
2045
-
void ast_post_chip_2500(struct ast_device *ast)
2046
-
{
2047
-
struct drm_device *dev = &ast->base;
2048
-
u32 temp;
2049
-
u8 reg;
2050
-
2051
-
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2052
-
if ((reg & AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */
2053
-
/* Clear bus lock condition */
2054
-
ast_patch_ahb_2500(ast->regs);
2055
-
2056
-
/* Disable watchdog */
2057
-
ast_moutdwm(ast, 0x1E78502C, 0x00000000);
2058
-
ast_moutdwm(ast, 0x1E78504C, 0x00000000);
2059
-
2060
-
/*
2061
-
* Reset USB port to patch USB unknown device issue
2062
-
* SCU90 is Multi-function Pin Control #5
2063
-
* [29]:= 1:Enable USB2.0 Host port#1 (that the mutually shared USB2.0 Hub
2064
-
* port).
2065
-
* SCU94 is Multi-function Pin Control #6
2066
-
* [14:13]:= 1x:USB2.0 Host2 controller
2067
-
* SCU70 is Hardware Strap reg
2068
-
* [23]:= 1:CLKIN is 25MHz and USBCK1 = 24/48 MHz (determined by
2069
-
* [18]: 0(24)/1(48) MHz)
2070
-
* SCU7C is Write clear reg to SCU70
2071
-
* [23]:= write 1 and then SCU70[23] will be clear as 0b.
2072
-
*/
2073
-
ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
2074
-
ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
2075
-
if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
2076
-
ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
2077
-
mdelay(100);
2078
-
ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
2079
-
}
2080
-
/* Modify eSPI reset pin */
2081
-
temp = ast_mindwm(ast, 0x1E6E2070);
2082
-
if (temp & 0x02000000)
2083
-
ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
2084
-
2085
-
/* Slow down CPU/AHB CLK in VGA only mode */
2086
-
temp = ast_read32(ast, 0x12008);
2087
-
temp |= 0x73;
2088
-
ast_write32(ast, 0x12008, temp);
2089
-
2090
-
if (!ast_dram_init_2500(ast))
2091
-
drm_err(dev, "DRAM init failed !\n");
2092
1659
2093
1660
temp = ast_mindwm(ast, 0x1e6e2040);
2094
1661
ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);