Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ALSA: sparc/dbri: Use guard() for spin locks
Clean up the code using guard() for spin locks.
Merely code refactoring, and no behavior change.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
+107
-121
+107
-121
sound/sparc/dbri.c
+107
-121
sound/sparc/dbri.c
···
758
758
u32 dvma_addr = (u32)dbri->dma_dvma;
759
759
s32 *cmd;
760
760
u32 dma_addr;
761
-
unsigned long flags;
762
761
int n;
763
762
764
-
spin_lock_irqsave(&dbri->lock, flags);
763
+
scoped_guard(spinlock_irqsave, &dbri->lock) {
764
+
dbri_reset(dbri);
765
765
766
-
dbri_reset(dbri);
766
+
/* Initialize pipes */
767
+
for (n = 0; n < DBRI_NO_PIPES; n++)
768
+
dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
767
769
768
-
/* Initialize pipes */
769
-
for (n = 0; n < DBRI_NO_PIPES; n++)
770
-
dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
770
+
spin_lock_init(&dbri->cmdlock);
771
+
/*
772
+
* Initialize the interrupt ring buffer.
773
+
*/
774
+
dma_addr = dvma_addr + dbri_dma_off(intr, 0);
775
+
dbri->dma->intr[0] = dma_addr;
776
+
dbri->dbri_irqp = 1;
777
+
/*
778
+
* Set up the interrupt queue
779
+
*/
780
+
scoped_guard(spinlock, &dbri->cmdlock) {
781
+
cmd = dbri->cmdptr = dbri->dma->cmd;
782
+
*(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
783
+
*(cmd++) = dma_addr;
784
+
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
785
+
dbri->cmdptr = cmd;
786
+
*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
787
+
*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
788
+
dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
789
+
sbus_writel(dma_addr, dbri->regs + REG8);
790
+
}
791
+
}
771
792
772
-
spin_lock_init(&dbri->cmdlock);
773
-
/*
774
-
* Initialize the interrupt ring buffer.
775
-
*/
776
-
dma_addr = dvma_addr + dbri_dma_off(intr, 0);
777
-
dbri->dma->intr[0] = dma_addr;
778
-
dbri->dbri_irqp = 1;
779
-
/*
780
-
* Set up the interrupt queue
781
-
*/
782
-
spin_lock(&dbri->cmdlock);
783
-
cmd = dbri->cmdptr = dbri->dma->cmd;
784
-
*(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
785
-
*(cmd++) = dma_addr;
786
-
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
787
-
dbri->cmdptr = cmd;
788
-
*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
789
-
*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
790
-
dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
791
-
sbus_writel(dma_addr, dbri->regs + REG8);
792
-
spin_unlock(&dbri->cmdlock);
793
-
794
-
spin_unlock_irqrestore(&dbri->lock, flags);
795
793
dbri_cmdwait(dbri);
796
794
}
797
795
···
1000
1002
static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
1001
1003
{
1002
1004
s32 *cmd;
1003
-
unsigned long flags;
1004
1005
1005
1006
if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1006
1007
printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
···
1034
1037
*(cmd++) = data;
1035
1038
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1036
1039
1037
-
spin_lock_irqsave(&dbri->lock, flags);
1038
-
dbri_cmdsend(dbri, cmd, 3);
1039
-
spin_unlock_irqrestore(&dbri->lock, flags);
1040
+
scoped_guard(spinlock_irqsave, &dbri->lock) {
1041
+
dbri_cmdsend(dbri, cmd, 3);
1042
+
}
1043
+
1040
1044
dbri_cmdwait(dbri);
1041
1045
1042
1046
}
···
1315
1317
*/
1316
1318
static void cs4215_setup_pipes(struct snd_dbri *dbri)
1317
1319
{
1318
-
unsigned long flags;
1320
+
scoped_guard(spinlock_irqsave, &dbri->lock) {
1321
+
/*
1322
+
* Data mode:
1323
+
* Pipe 4: Send timeslots 1-4 (audio data)
1324
+
* Pipe 20: Send timeslots 5-8 (part of ctrl data)
1325
+
* Pipe 6: Receive timeslots 1-4 (audio data)
1326
+
* Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1327
+
* interrupt, and the rest of the data (slot 5 and 8) is
1328
+
* not relevant for us (only for doublechecking).
1329
+
*
1330
+
* Control mode:
1331
+
* Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1332
+
* Pipe 18: Receive timeslot 1 (clb).
1333
+
* Pipe 19: Receive timeslot 7 (version).
1334
+
*/
1319
1335
1320
-
spin_lock_irqsave(&dbri->lock, flags);
1321
-
/*
1322
-
* Data mode:
1323
-
* Pipe 4: Send timeslots 1-4 (audio data)
1324
-
* Pipe 20: Send timeslots 5-8 (part of ctrl data)
1325
-
* Pipe 6: Receive timeslots 1-4 (audio data)
1326
-
* Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1327
-
* interrupt, and the rest of the data (slot 5 and 8) is
1328
-
* not relevant for us (only for doublechecking).
1329
-
*
1330
-
* Control mode:
1331
-
* Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1332
-
* Pipe 18: Receive timeslot 1 (clb).
1333
-
* Pipe 19: Receive timeslot 7 (version).
1334
-
*/
1336
+
setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1337
+
setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1338
+
setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1339
+
setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1335
1340
1336
-
setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1337
-
setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1338
-
setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1339
-
setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1340
-
1341
-
setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1342
-
setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1343
-
setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1344
-
spin_unlock_irqrestore(&dbri->lock, flags);
1341
+
setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1342
+
setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1343
+
setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1344
+
}
1345
1345
1346
1346
dbri_cmdwait(dbri);
1347
1347
}
···
1414
1418
{
1415
1419
int data_width;
1416
1420
u32 tmp;
1417
-
unsigned long flags;
1418
1421
1419
1422
dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1420
1423
dbri->mm.channels, dbri->mm.precision);
···
1438
1443
* bits. The CS4215, it seems, observes TSIN (the delayed signal)
1439
1444
* even if it's the CHI master. Don't ask me...
1440
1445
*/
1441
-
spin_lock_irqsave(&dbri->lock, flags);
1442
-
tmp = sbus_readl(dbri->regs + REG0);
1443
-
tmp &= ~(D_C); /* Disable CHI */
1444
-
sbus_writel(tmp, dbri->regs + REG0);
1446
+
scoped_guard(spinlock_irqsave, &dbri->lock) {
1447
+
tmp = sbus_readl(dbri->regs + REG0);
1448
+
tmp &= ~(D_C); /* Disable CHI */
1449
+
sbus_writel(tmp, dbri->regs + REG0);
1445
1450
1446
-
/* Switch CS4215 to data mode - set PIO3 to 1 */
1447
-
sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1448
-
(dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1451
+
/* Switch CS4215 to data mode - set PIO3 to 1 */
1452
+
sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1453
+
(dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1449
1454
1450
-
reset_chi(dbri, CHIslave, 128);
1455
+
reset_chi(dbri, CHIslave, 128);
1451
1456
1452
-
/* Note: this next doesn't work for 8-bit stereo, because the two
1453
-
* channels would be on timeslots 1 and 3, with 2 and 4 idle.
1454
-
* (See CS4215 datasheet Fig 15)
1455
-
*
1456
-
* DBRI non-contiguous mode would be required to make this work.
1457
-
*/
1458
-
data_width = dbri->mm.channels * dbri->mm.precision;
1457
+
/* Note: this next doesn't work for 8-bit stereo, because the two
1458
+
* channels would be on timeslots 1 and 3, with 2 and 4 idle.
1459
+
* (See CS4215 datasheet Fig 15)
1460
+
*
1461
+
* DBRI non-contiguous mode would be required to make this work.
1462
+
*/
1463
+
data_width = dbri->mm.channels * dbri->mm.precision;
1459
1464
1460
-
link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1461
-
link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1462
-
link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1463
-
link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1465
+
link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1466
+
link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1467
+
link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1468
+
link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1464
1469
1465
-
/* FIXME: enable CHI after _setdata? */
1466
-
tmp = sbus_readl(dbri->regs + REG0);
1467
-
tmp |= D_C; /* Enable CHI */
1468
-
sbus_writel(tmp, dbri->regs + REG0);
1469
-
spin_unlock_irqrestore(&dbri->lock, flags);
1470
+
/* FIXME: enable CHI after _setdata? */
1471
+
tmp = sbus_readl(dbri->regs + REG0);
1472
+
tmp |= D_C; /* Enable CHI */
1473
+
sbus_writel(tmp, dbri->regs + REG0);
1474
+
}
1470
1475
1471
1476
cs4215_setdata(dbri, 0);
1472
1477
}
···
1478
1483
{
1479
1484
int i, val;
1480
1485
u32 tmp;
1481
-
unsigned long flags;
1482
1486
1483
1487
/* FIXME - let the CPU do something useful during these delays */
1484
1488
···
1514
1520
* done in hardware by a TI 248 that delays the DBRI->4215
1515
1521
* frame sync signal by eight clock cycles. Anybody know why?
1516
1522
*/
1517
-
spin_lock_irqsave(&dbri->lock, flags);
1518
-
tmp = sbus_readl(dbri->regs + REG0);
1519
-
tmp &= ~D_C; /* Disable CHI */
1520
-
sbus_writel(tmp, dbri->regs + REG0);
1523
+
scoped_guard(spinlock_irqsave, &dbri->lock) {
1524
+
tmp = sbus_readl(dbri->regs + REG0);
1525
+
tmp &= ~D_C; /* Disable CHI */
1526
+
sbus_writel(tmp, dbri->regs + REG0);
1521
1527
1522
-
reset_chi(dbri, CHImaster, 128);
1528
+
reset_chi(dbri, CHImaster, 128);
1523
1529
1524
-
/*
1525
-
* Control mode:
1526
-
* Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1527
-
* Pipe 18: Receive timeslot 1 (clb).
1528
-
* Pipe 19: Receive timeslot 7 (version).
1529
-
*/
1530
+
/*
1531
+
* Control mode:
1532
+
* Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1533
+
* Pipe 18: Receive timeslot 1 (clb).
1534
+
* Pipe 19: Receive timeslot 7 (version).
1535
+
*/
1530
1536
1531
-
link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1532
-
link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1533
-
link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1534
-
spin_unlock_irqrestore(&dbri->lock, flags);
1537
+
link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1538
+
link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1539
+
link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1540
+
}
1535
1541
1536
1542
/* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1537
1543
dbri->mm.ctrl[0] &= ~CS4215_CLB;
1538
1544
xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1539
1545
1540
-
spin_lock_irqsave(&dbri->lock, flags);
1541
-
tmp = sbus_readl(dbri->regs + REG0);
1542
-
tmp |= D_C; /* Enable CHI */
1543
-
sbus_writel(tmp, dbri->regs + REG0);
1544
-
spin_unlock_irqrestore(&dbri->lock, flags);
1546
+
scoped_guard(spinlock_irqsave, &dbri->lock) {
1547
+
tmp = sbus_readl(dbri->regs + REG0);
1548
+
tmp |= D_C; /* Enable CHI */
1549
+
sbus_writel(tmp, dbri->regs + REG0);
1550
+
}
1545
1551
1546
1552
for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1547
1553
msleep_interruptible(1);
···
1703
1709
struct dbri_streaminfo *info;
1704
1710
u32 dvma_addr;
1705
1711
s32 *cmd;
1706
-
unsigned long flags;
1707
1712
int first_td;
1708
1713
1709
1714
if (dbri == NULL)
···
1710
1717
1711
1718
dvma_addr = (u32)dbri->dma_dvma;
1712
1719
info = &dbri->stream_info[DBRI_REC];
1713
-
spin_lock_irqsave(&dbri->lock, flags);
1720
+
guard(spinlock_irqsave)(&dbri->lock);
1714
1721
1715
1722
if (info->pipe >= 0) {
1716
1723
first_td = dbri->pipes[info->pipe].first_desc;
···
1753
1760
dbri->pipes[info->pipe].desc = first_td;
1754
1761
}
1755
1762
}
1756
-
1757
-
spin_unlock_irqrestore(&dbri->lock, flags);
1758
1763
}
1759
1764
1760
1765
/* transmission_complete_intr()
···
1923
1932
1924
1933
if (dbri == NULL)
1925
1934
return IRQ_NONE;
1926
-
spin_lock(&dbri->lock);
1935
+
guard(spinlock)(&dbri->lock);
1927
1936
1928
1937
/*
1929
1938
* Read it, so the interrupt goes away.
···
1967
1976
}
1968
1977
1969
1978
dbri_process_interrupt_buffer(dbri);
1970
-
1971
-
spin_unlock(&dbri->lock);
1972
1979
1973
1980
return IRQ_HANDLED;
1974
1981
}
···
2035
2046
struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2036
2047
struct snd_pcm_runtime *runtime = substream->runtime;
2037
2048
struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2038
-
unsigned long flags;
2039
2049
2040
2050
dprintk(D_USR, "open audio output.\n");
2041
2051
runtime->hw = snd_dbri_pcm_hw;
2042
2052
2043
-
spin_lock_irqsave(&dbri->lock, flags);
2044
-
info->substream = substream;
2045
-
info->offset = 0;
2046
-
info->dvma_buffer = 0;
2047
-
info->pipe = -1;
2048
-
spin_unlock_irqrestore(&dbri->lock, flags);
2053
+
scoped_guard(spinlock_irqsave, &dbri->lock) {
2054
+
info->substream = substream;
2055
+
info->offset = 0;
2056
+
info->dvma_buffer = 0;
2057
+
info->pipe = -1;
2058
+
}
2049
2059
2050
2060
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2051
2061
snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
···
2148
2160
else
2149
2161
info->pipe = 6; /* Receive pipe */
2150
2162
2151
-
spin_lock_irq(&dbri->lock);
2163
+
guard(spinlock_irq)(&dbri->lock);
2152
2164
info->offset = 0;
2153
2165
2154
2166
/* Setup the all the transmit/receive descriptors to cover the
···
2156
2168
*/
2157
2169
ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2158
2170
snd_pcm_lib_period_bytes(substream));
2159
-
2160
-
spin_unlock_irq(&dbri->lock);
2161
2171
2162
2172
dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2163
2173
return ret;