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iio/adc/pac1934: fix channel disable configuration

There are two problems with the chip configuration in this driver:
- First, is that writing 12 bytes (ARRAY_SIZE(regs)) would anyhow
lead to a config overflow due to HW auto increment implementation
in the chip.
- Second, the i2c_smbus_write_block_data write ends up in writing
unexpected value to the channel_dis register, this is because
the smbus size that is 0x03 in this case gets written to the
register. The PAC1931/2/3/4 data sheet does not really specify
that block write is indeed supported.

This problem is probably not visible on PAC1934 version where all
channels are used as the chip is properly configured by luck,
but in our case whenusing PAC1931 this leads to nonfunctional device.

Fixes: 0fb528c8255b (iio: adc: adding support for PAC193x)
Suggested-by: Rene Straub <mailto:rene.straub@belden.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@belden.com>
Reviewed-by: Marius Cristea <marius.cristea@microchip.com>
Link: https://patch.msgid.link/20250811130904.2481790-1-aleksandar.gerasimovski@belden.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Aleksandar Gerasimovski and committed by
Jonathan Cameron 3c63ba1c 1b237f19

+18 -2
+18 -2
drivers/iio/adc/pac1934.c
··· 88 88 #define PAC1934_VPOWER_3_ADDR 0x19 89 89 #define PAC1934_VPOWER_4_ADDR 0x1A 90 90 #define PAC1934_REFRESH_V_REG_ADDR 0x1F 91 + #define PAC1934_SLOW_REG_ADDR 0x20 91 92 #define PAC1934_CTRL_STAT_REGS_ADDR 0x1C 92 93 #define PAC1934_PID_REG_ADDR 0xFD 93 94 #define PAC1934_MID_REG_ADDR 0xFE ··· 1266 1265 /* no SLOW triggered REFRESH, clear POR */ 1267 1266 regs[PAC1934_SLOW_REG_OFF] = 0; 1268 1267 1269 - ret = i2c_smbus_write_block_data(client, PAC1934_CTRL_STAT_REGS_ADDR, 1270 - ARRAY_SIZE(regs), (u8 *)regs); 1268 + /* 1269 + * Write the three bytes sequentially, as the device does not support 1270 + * block write. 1271 + */ 1272 + ret = i2c_smbus_write_byte_data(client, PAC1934_CTRL_STAT_REGS_ADDR, 1273 + regs[PAC1934_CHANNEL_DIS_REG_OFF]); 1274 + if (ret) 1275 + return ret; 1276 + 1277 + ret = i2c_smbus_write_byte_data(client, 1278 + PAC1934_CTRL_STAT_REGS_ADDR + PAC1934_NEG_PWR_REG_OFF, 1279 + regs[PAC1934_NEG_PWR_REG_OFF]); 1280 + if (ret) 1281 + return ret; 1282 + 1283 + ret = i2c_smbus_write_byte_data(client, PAC1934_SLOW_REG_ADDR, 1284 + regs[PAC1934_SLOW_REG_OFF]); 1271 1285 if (ret) 1272 1286 return ret; 1273 1287