Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"Patching up across the field. The reversion of the two ASID patches
is particularly important as it was breaking many platforms."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: ralink: use the dwc2 driver for the rt305x USB controller
MIPS: Extract schedule_mfi info from __schedule
MIPS: Fix sibling call handling in get_frame_info
MIPS: MSP71xx: remove inline marking of EXPORT_SYMBOL functions
MIPS: Make virt_to_phys() work for all unmapped addresses.
MIPS: Fix build error for crash_dump.c in 3.10-rc1
MIPS: Xway: Fix clk leak
Revert "MIPS: Allow ASID size to be determined at boot time."
Revert "MIPS: microMIPS: Support dynamic ASID sizing."
+149
-199
+1
-1
arch/mips/include/asm/io.h
+1
-1
arch/mips/include/asm/io.h
+1
-1
arch/mips/include/asm/kvm_host.h
+1
-1
arch/mips/include/asm/kvm_host.h
···
336
336
#define VPN2_MASK 0xffffe000
337
337
#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G))
338
338
#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
339
-
#define TLB_ASID(x) (ASID_MASK((x).tlb_hi))
339
+
#define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
340
340
#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V))
341
341
342
342
struct kvm_mips_tlb {
+35
-58
arch/mips/include/asm/mmu_context.h
+35
-58
arch/mips/include/asm/mmu_context.h
···
67
67
TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
68
68
#endif
69
69
#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
70
+
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
70
71
71
-
#define ASID_INC(asid) \
72
-
({ \
73
-
unsigned long __asid = asid; \
74
-
__asm__("1:\taddiu\t%0,1\t\t\t\t# patched\n\t" \
75
-
".section\t__asid_inc,\"a\"\n\t" \
76
-
".word\t1b\n\t" \
77
-
".previous" \
78
-
:"=r" (__asid) \
79
-
:"0" (__asid)); \
80
-
__asid; \
81
-
})
82
-
#define ASID_MASK(asid) \
83
-
({ \
84
-
unsigned long __asid = asid; \
85
-
__asm__("1:\tandi\t%0,%1,0xfc0\t\t\t# patched\n\t" \
86
-
".section\t__asid_mask,\"a\"\n\t" \
87
-
".word\t1b\n\t" \
88
-
".previous" \
89
-
:"=r" (__asid) \
90
-
:"r" (__asid)); \
91
-
__asid; \
92
-
})
93
-
#define ASID_VERSION_MASK \
94
-
({ \
95
-
unsigned long __asid; \
96
-
__asm__("1:\taddiu\t%0,$0,0xff00\t\t\t\t# patched\n\t" \
97
-
".section\t__asid_version_mask,\"a\"\n\t" \
98
-
".word\t1b\n\t" \
99
-
".previous" \
100
-
:"=r" (__asid)); \
101
-
__asid; \
102
-
})
103
-
#define ASID_FIRST_VERSION \
104
-
({ \
105
-
unsigned long __asid = asid; \
106
-
__asm__("1:\tli\t%0,0x100\t\t\t\t# patched\n\t" \
107
-
".section\t__asid_first_version,\"a\"\n\t" \
108
-
".word\t1b\n\t" \
109
-
".previous" \
110
-
:"=r" (__asid)); \
111
-
__asid; \
112
-
})
72
+
#define ASID_INC 0x40
73
+
#define ASID_MASK 0xfc0
113
74
114
-
#define ASID_FIRST_VERSION_R3000 0x1000
115
-
#define ASID_FIRST_VERSION_R4000 0x100
116
-
#define ASID_FIRST_VERSION_R8000 0x1000
117
-
#define ASID_FIRST_VERSION_RM9000 0x1000
75
+
#elif defined(CONFIG_CPU_R8000)
118
76
119
-
#ifdef CONFIG_MIPS_MT_SMTC
120
-
#define SMTC_HW_ASID_MASK 0xff
121
-
extern unsigned int smtc_asid_mask;
77
+
#define ASID_INC 0x10
78
+
#define ASID_MASK 0xff0
79
+
80
+
#elif defined(CONFIG_MIPS_MT_SMTC)
81
+
82
+
#define ASID_INC 0x1
83
+
extern unsigned long smtc_asid_mask;
84
+
#define ASID_MASK (smtc_asid_mask)
85
+
#define HW_ASID_MASK 0xff
86
+
/* End SMTC/34K debug hack */
87
+
#else /* FIXME: not correct for R6000 */
88
+
89
+
#define ASID_INC 0x1
90
+
#define ASID_MASK 0xff
91
+
122
92
#endif
123
93
124
94
#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
125
-
#define cpu_asid(cpu, mm) ASID_MASK(cpu_context((cpu), (mm)))
95
+
#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
126
96
#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
127
97
128
98
static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
129
99
{
130
100
}
101
+
102
+
/*
103
+
* All unused by hardware upper bits will be considered
104
+
* as a software asid extension.
105
+
*/
106
+
#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
107
+
#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
131
108
132
109
#ifndef CONFIG_MIPS_MT_SMTC
133
110
/* Normal, classic MIPS get_new_mmu_context */
···
114
137
extern void kvm_local_flush_tlb_all(void);
115
138
unsigned long asid = asid_cache(cpu);
116
139
117
-
if (!ASID_MASK((asid = ASID_INC(asid)))) {
140
+
if (! ((asid += ASID_INC) & ASID_MASK) ) {
118
141
if (cpu_has_vtag_icache)
119
142
flush_icache_all();
120
143
#ifdef CONFIG_VIRTUALIZATION
···
177
200
* free up the ASID value for use and flush any old
178
201
* instances of it from the TLB.
179
202
*/
180
-
oldasid = ASID_MASK(read_c0_entryhi());
203
+
oldasid = (read_c0_entryhi() & ASID_MASK);
181
204
if(smtc_live_asid[mytlb][oldasid]) {
182
205
smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
183
206
if(smtc_live_asid[mytlb][oldasid] == 0)
···
188
211
* having ASID_MASK smaller than the hardware maximum,
189
212
* make sure no "soft" bits become "hard"...
190
213
*/
191
-
write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) |
214
+
write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
192
215
cpu_asid(cpu, next));
193
216
ehb(); /* Make sure it propagates to TCStatus */
194
217
evpe(mtflags);
···
241
264
#ifdef CONFIG_MIPS_MT_SMTC
242
265
/* See comments for similar code above */
243
266
mtflags = dvpe();
244
-
oldasid = ASID_MASK(read_c0_entryhi());
267
+
oldasid = read_c0_entryhi() & ASID_MASK;
245
268
if(smtc_live_asid[mytlb][oldasid]) {
246
269
smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
247
270
if(smtc_live_asid[mytlb][oldasid] == 0)
248
271
smtc_flush_tlb_asid(oldasid);
249
272
}
250
273
/* See comments for similar code above */
251
-
write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) |
252
-
cpu_asid(cpu, next));
274
+
write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
275
+
cpu_asid(cpu, next));
253
276
ehb(); /* Make sure it propagates to TCStatus */
254
277
evpe(mtflags);
255
278
#else
···
286
309
#ifdef CONFIG_MIPS_MT_SMTC
287
310
/* See comments for similar code above */
288
311
prevvpe = dvpe();
289
-
oldasid = ASID_MASK(read_c0_entryhi());
312
+
oldasid = (read_c0_entryhi() & ASID_MASK);
290
313
if (smtc_live_asid[mytlb][oldasid]) {
291
314
smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
292
315
if(smtc_live_asid[mytlb][oldasid] == 0)
293
316
smtc_flush_tlb_asid(oldasid);
294
317
}
295
318
/* See comments for similar code above */
296
-
write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK)
319
+
write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
297
320
| cpu_asid(cpu, mm));
298
321
ehb(); /* Make sure it propagates to TCStatus */
299
322
evpe(prevvpe);
+1
-1
arch/mips/include/asm/page.h
+1
-1
arch/mips/include/asm/page.h
···
46
46
#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
47
47
48
48
#include <linux/pfn.h>
49
-
#include <asm/io.h>
50
49
51
50
extern void build_clear_page(void);
52
51
extern void build_copy_page(void);
···
150
151
((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
151
152
#endif
152
153
#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
154
+
#include <asm/io.h>
153
155
154
156
/*
155
157
* RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad
+1
arch/mips/kernel/crash_dump.c
+1
arch/mips/kernel/crash_dump.c
+1
-1
arch/mips/kernel/genex.S
+1
-1
arch/mips/kernel/genex.S
+37
-5
arch/mips/kernel/process.c
+37
-5
arch/mips/kernel/process.c
···
224
224
int pc_offset;
225
225
};
226
226
227
+
#define J_TARGET(pc,target) \
228
+
(((unsigned long)(pc) & 0xf0000000) | ((target) << 2))
229
+
227
230
static inline int is_ra_save_ins(union mips_instruction *ip)
228
231
{
229
232
#ifdef CONFIG_CPU_MICROMIPS
···
267
264
#endif
268
265
}
269
266
270
-
static inline int is_jal_jalr_jr_ins(union mips_instruction *ip)
267
+
static inline int is_jump_ins(union mips_instruction *ip)
271
268
{
272
269
#ifdef CONFIG_CPU_MICROMIPS
273
270
/*
···
291
288
return 0;
292
289
return (((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op);
293
290
#else
291
+
if (ip->j_format.opcode == j_op)
292
+
return 1;
294
293
if (ip->j_format.opcode == jal_op)
295
294
return 1;
296
295
if (ip->r_format.opcode != spec_op)
···
355
350
356
351
for (i = 0; i < max_insns; i++, ip++) {
357
352
358
-
if (is_jal_jalr_jr_ins(ip))
353
+
if (is_jump_ins(ip))
359
354
break;
360
355
if (!info->frame_size) {
361
356
if (is_sp_move_ins(ip))
···
398
393
399
394
static struct mips_frame_info schedule_mfi __read_mostly;
400
395
396
+
#ifdef CONFIG_KALLSYMS
397
+
static unsigned long get___schedule_addr(void)
398
+
{
399
+
return kallsyms_lookup_name("__schedule");
400
+
}
401
+
#else
402
+
static unsigned long get___schedule_addr(void)
403
+
{
404
+
union mips_instruction *ip = (void *)schedule;
405
+
int max_insns = 8;
406
+
int i;
407
+
408
+
for (i = 0; i < max_insns; i++, ip++) {
409
+
if (ip->j_format.opcode == j_op)
410
+
return J_TARGET(ip, ip->j_format.target);
411
+
}
412
+
return 0;
413
+
}
414
+
#endif
415
+
401
416
static int __init frame_info_init(void)
402
417
{
403
418
unsigned long size = 0;
404
419
#ifdef CONFIG_KALLSYMS
405
420
unsigned long ofs;
406
-
407
-
kallsyms_lookup_size_offset((unsigned long)schedule, &size, &ofs);
408
421
#endif
409
-
schedule_mfi.func = schedule;
422
+
unsigned long addr;
423
+
424
+
addr = get___schedule_addr();
425
+
if (!addr)
426
+
addr = (unsigned long)schedule;
427
+
428
+
#ifdef CONFIG_KALLSYMS
429
+
kallsyms_lookup_size_offset(addr, &size, &ofs);
430
+
#endif
431
+
schedule_mfi.func = (void *)addr;
410
432
schedule_mfi.func_size = size;
411
433
412
434
get_frame_info(&schedule_mfi);
+5
-5
arch/mips/kernel/smtc.c
+5
-5
arch/mips/kernel/smtc.c
···
111
111
static int ipibuffers;
112
112
static int nostlb;
113
113
static int asidmask;
114
-
unsigned int smtc_asid_mask = 0xff;
114
+
unsigned long smtc_asid_mask = 0xff;
115
115
116
116
static int __init vpe0tcs(char *str)
117
117
{
···
1395
1395
asid = asid_cache(cpu);
1396
1396
1397
1397
do {
1398
-
if (!ASID_MASK(ASID_INC(asid))) {
1398
+
if (!((asid += ASID_INC) & ASID_MASK) ) {
1399
1399
if (cpu_has_vtag_icache)
1400
1400
flush_icache_all();
1401
1401
/* Traverse all online CPUs (hack requires contiguous range) */
···
1414
1414
mips_ihb();
1415
1415
}
1416
1416
tcstat = read_tc_c0_tcstatus();
1417
-
smtc_live_asid[tlb][ASID_MASK(tcstat)] |= (asiduse)(0x1 << i);
1417
+
smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);
1418
1418
if (!prevhalt)
1419
1419
write_tc_c0_tchalt(0);
1420
1420
}
···
1423
1423
asid = ASID_FIRST_VERSION;
1424
1424
local_flush_tlb_all(); /* start new asid cycle */
1425
1425
}
1426
-
} while (smtc_live_asid[tlb][ASID_MASK(asid)]);
1426
+
} while (smtc_live_asid[tlb][(asid & ASID_MASK)]);
1427
1427
1428
1428
/*
1429
1429
* SMTC shares the TLB within VPEs and possibly across all VPEs.
···
1461
1461
tlb_read();
1462
1462
ehb();
1463
1463
ehi = read_c0_entryhi();
1464
-
if (ASID_MASK(ehi) == asid) {
1464
+
if ((ehi & ASID_MASK) == asid) {
1465
1465
/*
1466
1466
* Invalidate only entries with specified ASID,
1467
1467
* makiing sure all entries differ.
+2
-4
arch/mips/kernel/traps.c
+2
-4
arch/mips/kernel/traps.c
···
1656
1656
unsigned int cpu = smp_processor_id();
1657
1657
unsigned int status_set = ST0_CU0;
1658
1658
unsigned int hwrena = cpu_hwrena_impl_bits;
1659
-
unsigned long asid = 0;
1660
1659
#ifdef CONFIG_MIPS_MT_SMTC
1661
1660
int secondaryTC = 0;
1662
1661
int bootTC = (cpu == 0);
···
1739
1740
}
1740
1741
#endif /* CONFIG_MIPS_MT_SMTC */
1741
1742
1742
-
asid = ASID_FIRST_VERSION;
1743
-
cpu_data[cpu].asid_cache = asid;
1744
-
TLBMISS_HANDLER_SETUP();
1743
+
if (!cpu_data[cpu].asid_cache)
1744
+
cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1745
1745
1746
1746
atomic_inc(&init_mm.mm_count);
1747
1747
current->active_mm = &init_mm;
+16
-13
arch/mips/kvm/kvm_mips_emul.c
+16
-13
arch/mips/kvm/kvm_mips_emul.c
···
525
525
printk("MTCz, cop0->reg[EBASE]: %#lx\n",
526
526
kvm_read_c0_guest_ebase(cop0));
527
527
} else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
528
-
uint32_t nasid = ASID_MASK(vcpu->arch.gprs[rt]);
528
+
uint32_t nasid =
529
+
vcpu->arch.gprs[rt] & ASID_MASK;
529
530
if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0)
530
531
&&
531
-
(ASID_MASK(kvm_read_c0_guest_entryhi(cop0))
532
-
!= nasid)) {
532
+
((kvm_read_c0_guest_entryhi(cop0) &
533
+
ASID_MASK) != nasid)) {
533
534
534
535
kvm_debug
535
536
("MTCz, change ASID from %#lx to %#lx\n",
536
-
ASID_MASK(kvm_read_c0_guest_entryhi(cop0)),
537
-
ASID_MASK(vcpu->arch.gprs[rt]));
537
+
kvm_read_c0_guest_entryhi(cop0) &
538
+
ASID_MASK,
539
+
vcpu->arch.gprs[rt] & ASID_MASK);
538
540
539
541
/* Blow away the shadow host TLBs */
540
542
kvm_mips_flush_host_tlb(1);
···
988
986
* resulting handler will do the right thing
989
987
*/
990
988
index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) |
991
-
ASID_MASK(kvm_read_c0_guest_entryhi(cop0)));
989
+
(kvm_read_c0_guest_entryhi
990
+
(cop0) & ASID_MASK));
992
991
993
992
if (index < 0) {
994
993
vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK);
···
1154
1151
struct kvm_vcpu_arch *arch = &vcpu->arch;
1155
1152
enum emulation_result er = EMULATE_DONE;
1156
1153
unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) |
1157
-
ASID_MASK(kvm_read_c0_guest_entryhi(cop0));
1154
+
(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1158
1155
1159
1156
if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1160
1157
/* save old pc */
···
1201
1198
enum emulation_result er = EMULATE_DONE;
1202
1199
unsigned long entryhi =
1203
1200
(vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1204
-
ASID_MASK(kvm_read_c0_guest_entryhi(cop0));
1201
+
(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1205
1202
1206
1203
if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1207
1204
/* save old pc */
···
1246
1243
struct kvm_vcpu_arch *arch = &vcpu->arch;
1247
1244
enum emulation_result er = EMULATE_DONE;
1248
1245
unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1249
-
ASID_MASK(kvm_read_c0_guest_entryhi(cop0));
1246
+
(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1250
1247
1251
1248
if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1252
1249
/* save old pc */
···
1290
1287
struct kvm_vcpu_arch *arch = &vcpu->arch;
1291
1288
enum emulation_result er = EMULATE_DONE;
1292
1289
unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1293
-
ASID_MASK(kvm_read_c0_guest_entryhi(cop0));
1290
+
(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1294
1291
1295
1292
if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1296
1293
/* save old pc */
···
1359
1356
{
1360
1357
struct mips_coproc *cop0 = vcpu->arch.cop0;
1361
1358
unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1362
-
ASID_MASK(kvm_read_c0_guest_entryhi(cop0));
1359
+
(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1363
1360
struct kvm_vcpu_arch *arch = &vcpu->arch;
1364
1361
enum emulation_result er = EMULATE_DONE;
1365
1362
···
1786
1783
*/
1787
1784
index = kvm_mips_guest_tlb_lookup(vcpu,
1788
1785
(va & VPN2_MASK) |
1789
-
ASID_MASK(kvm_read_c0_guest_entryhi
1790
-
(vcpu->arch.cop0)));
1786
+
(kvm_read_c0_guest_entryhi
1787
+
(vcpu->arch.cop0) & ASID_MASK));
1791
1788
if (index < 0) {
1792
1789
if (exccode == T_TLB_LD_MISS) {
1793
1790
er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu);
+15
-11
arch/mips/kvm/kvm_tlb.c
+15
-11
arch/mips/kvm/kvm_tlb.c
···
51
51
52
52
uint32_t kvm_mips_get_kernel_asid(struct kvm_vcpu *vcpu)
53
53
{
54
-
return ASID_MASK(vcpu->arch.guest_kernel_asid[smp_processor_id()]);
54
+
return vcpu->arch.guest_kernel_asid[smp_processor_id()] & ASID_MASK;
55
55
}
56
56
57
57
58
58
uint32_t kvm_mips_get_user_asid(struct kvm_vcpu *vcpu)
59
59
{
60
-
return ASID_MASK(vcpu->arch.guest_user_asid[smp_processor_id()]);
60
+
return vcpu->arch.guest_user_asid[smp_processor_id()] & ASID_MASK;
61
61
}
62
62
63
63
inline uint32_t kvm_mips_get_commpage_asid (struct kvm_vcpu *vcpu)
···
84
84
old_pagemask = read_c0_pagemask();
85
85
86
86
printk("HOST TLBs:\n");
87
-
printk("ASID: %#lx\n", ASID_MASK(read_c0_entryhi()));
87
+
printk("ASID: %#lx\n", read_c0_entryhi() & ASID_MASK);
88
88
89
89
for (i = 0; i < current_cpu_data.tlbsize; i++) {
90
90
write_c0_index(i);
···
428
428
429
429
for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
430
430
if (((TLB_VPN2(tlb[i]) & ~tlb[i].tlb_mask) == ((entryhi & VPN2_MASK) & ~tlb[i].tlb_mask)) &&
431
-
(TLB_IS_GLOBAL(tlb[i]) || (TLB_ASID(tlb[i]) == ASID_MASK(entryhi)))) {
431
+
(TLB_IS_GLOBAL(tlb[i]) || (TLB_ASID(tlb[i]) == (entryhi & ASID_MASK)))) {
432
432
index = i;
433
433
break;
434
434
}
···
626
626
{
627
627
unsigned long asid = asid_cache(cpu);
628
628
629
-
if (!(ASID_MASK(ASID_INC(asid)))) {
629
+
if (!((asid += ASID_INC) & ASID_MASK)) {
630
630
if (cpu_has_vtag_icache) {
631
631
flush_icache_all();
632
632
}
···
804
804
if (!newasid) {
805
805
/* If we preempted while the guest was executing, then reload the pre-empted ASID */
806
806
if (current->flags & PF_VCPU) {
807
-
write_c0_entryhi(ASID_MASK(vcpu->arch.preempt_entryhi));
807
+
write_c0_entryhi(vcpu->arch.
808
+
preempt_entryhi & ASID_MASK);
808
809
ehb();
809
810
}
810
811
} else {
···
817
816
*/
818
817
if (current->flags & PF_VCPU) {
819
818
if (KVM_GUEST_KERNEL_MODE(vcpu))
820
-
write_c0_entryhi(ASID_MASK(vcpu->arch.
821
-
guest_kernel_asid[cpu]));
819
+
write_c0_entryhi(vcpu->arch.
820
+
guest_kernel_asid[cpu] &
821
+
ASID_MASK);
822
822
else
823
-
write_c0_entryhi(ASID_MASK(vcpu->arch.
824
-
guest_user_asid[cpu]));
823
+
write_c0_entryhi(vcpu->arch.
824
+
guest_user_asid[cpu] &
825
+
ASID_MASK);
825
826
ehb();
826
827
}
827
828
}
···
882
879
kvm_mips_guest_tlb_lookup(vcpu,
883
880
((unsigned long) opc & VPN2_MASK)
884
881
|
885
-
ASID_MASK(kvm_read_c0_guest_entryhi(cop0)));
882
+
(kvm_read_c0_guest_entryhi
883
+
(cop0) & ASID_MASK));
886
884
if (index < 0) {
887
885
kvm_err
888
886
("%s: get_user_failed for %p, vcpu: %p, ASID: %#lx\n",
+2
arch/mips/lantiq/xway/gptu.c
+2
arch/mips/lantiq/xway/gptu.c
+2
-3
arch/mips/lib/dump_tlb.c
+2
-3
arch/mips/lib/dump_tlb.c
···
11
11
#include <asm/page.h>
12
12
#include <asm/pgtable.h>
13
13
#include <asm/tlbdebug.h>
14
-
#include <asm/mmu_context.h>
15
14
16
15
static inline const char *msk2str(unsigned int mask)
17
16
{
···
55
56
s_pagemask = read_c0_pagemask();
56
57
s_entryhi = read_c0_entryhi();
57
58
s_index = read_c0_index();
58
-
asid = ASID_MASK(s_entryhi);
59
+
asid = s_entryhi & 0xff;
59
60
60
61
for (i = first; i <= last; i++) {
61
62
write_c0_index(i);
···
85
86
86
87
printk("va=%0*lx asid=%02lx\n",
87
88
width, (entryhi & ~0x1fffUL),
88
-
ASID_MASK(entryhi));
89
+
entryhi & 0xff);
89
90
printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
90
91
width,
91
92
(entrylo0 << 6) & PAGE_MASK, c0,
+3
-4
arch/mips/lib/r3k_dump_tlb.c
+3
-4
arch/mips/lib/r3k_dump_tlb.c
···
9
9
#include <linux/mm.h>
10
10
11
11
#include <asm/mipsregs.h>
12
-
#include <asm/mmu_context.h>
13
12
#include <asm/page.h>
14
13
#include <asm/pgtable.h>
15
14
#include <asm/tlbdebug.h>
···
21
22
unsigned int asid;
22
23
unsigned long entryhi, entrylo0;
23
24
24
-
asid = ASID_MASK(read_c0_entryhi());
25
+
asid = read_c0_entryhi() & 0xfc0;
25
26
26
27
for (i = first; i <= last; i++) {
27
28
write_c0_index(i<<8);
···
35
36
36
37
/* Unused entries have a virtual address of KSEG0. */
37
38
if ((entryhi & 0xffffe000) != 0x80000000
38
-
&& (ASID_MASK(entryhi) == asid)) {
39
+
&& (entryhi & 0xfc0) == asid) {
39
40
/*
40
41
* Only print entries in use
41
42
*/
···
44
45
printk("va=%08lx asid=%08lx"
45
46
" [pa=%06lx n=%d d=%d v=%d g=%d]",
46
47
(entryhi & 0xffffe000),
47
-
ASID_MASK(entryhi),
48
+
entryhi & 0xfc0,
48
49
entrylo0 & PAGE_MASK,
49
50
(entrylo0 & (1 << 11)) ? 1 : 0,
50
51
(entrylo0 & (1 << 10)) ? 1 : 0,
+10
-10
arch/mips/mm/tlb-r3k.c
+10
-10
arch/mips/mm/tlb-r3k.c
···
51
51
#endif
52
52
53
53
local_irq_save(flags);
54
-
old_ctx = ASID_MASK(read_c0_entryhi());
54
+
old_ctx = read_c0_entryhi() & ASID_MASK;
55
55
write_c0_entrylo0(0);
56
56
entry = r3k_have_wired_reg ? read_c0_wired() : 8;
57
57
for (; entry < current_cpu_data.tlbsize; entry++) {
···
87
87
88
88
#ifdef DEBUG_TLB
89
89
printk("[tlbrange<%lu,0x%08lx,0x%08lx>]",
90
-
ASID_MASK(cpu_context(cpu, mm)), start, end);
90
+
cpu_context(cpu, mm) & ASID_MASK, start, end);
91
91
#endif
92
92
local_irq_save(flags);
93
93
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
94
94
if (size <= current_cpu_data.tlbsize) {
95
-
int oldpid = ASID_MASK(read_c0_entryhi());
96
-
int newpid = ASID_MASK(cpu_context(cpu, mm));
95
+
int oldpid = read_c0_entryhi() & ASID_MASK;
96
+
int newpid = cpu_context(cpu, mm) & ASID_MASK;
97
97
98
98
start &= PAGE_MASK;
99
99
end += PAGE_SIZE - 1;
···
166
166
#ifdef DEBUG_TLB
167
167
printk("[tlbpage<%lu,0x%08lx>]", cpu_context(cpu, vma->vm_mm), page);
168
168
#endif
169
-
newpid = ASID_MASK(cpu_context(cpu, vma->vm_mm));
169
+
newpid = cpu_context(cpu, vma->vm_mm) & ASID_MASK;
170
170
page &= PAGE_MASK;
171
171
local_irq_save(flags);
172
-
oldpid = ASID_MASK(read_c0_entryhi());
172
+
oldpid = read_c0_entryhi() & ASID_MASK;
173
173
write_c0_entryhi(page | newpid);
174
174
BARRIER;
175
175
tlb_probe();
···
197
197
if (current->active_mm != vma->vm_mm)
198
198
return;
199
199
200
-
pid = ASID_MASK(read_c0_entryhi());
200
+
pid = read_c0_entryhi() & ASID_MASK;
201
201
202
202
#ifdef DEBUG_TLB
203
-
if ((pid != ASID_MASK(cpu_context(cpu, vma->vm_mm))) || (cpu_context(cpu, vma->vm_mm) == 0)) {
203
+
if ((pid != (cpu_context(cpu, vma->vm_mm) & ASID_MASK)) || (cpu_context(cpu, vma->vm_mm) == 0)) {
204
204
printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n",
205
205
(cpu_context(cpu, vma->vm_mm)), pid);
206
206
}
···
241
241
242
242
local_irq_save(flags);
243
243
/* Save old context and create impossible VPN2 value */
244
-
old_ctx = ASID_MASK(read_c0_entryhi());
244
+
old_ctx = read_c0_entryhi() & ASID_MASK;
245
245
old_pagemask = read_c0_pagemask();
246
246
w = read_c0_wired();
247
247
write_c0_wired(w + 1);
···
264
264
#endif
265
265
266
266
local_irq_save(flags);
267
-
old_ctx = ASID_MASK(read_c0_entryhi());
267
+
old_ctx = read_c0_entryhi() & ASID_MASK;
268
268
write_c0_entrylo0(entrylo0);
269
269
write_c0_entryhi(entryhi);
270
270
write_c0_index(wired);
+1
-1
arch/mips/mm/tlb-r4k.c
+1
-1
arch/mips/mm/tlb-r4k.c
+1
-1
arch/mips/mm/tlb-r8k.c
+1
-1
arch/mips/mm/tlb-r8k.c
-79
arch/mips/mm/tlbex.c
-79
arch/mips/mm/tlbex.c
···
29
29
#include <linux/init.h>
30
30
#include <linux/cache.h>
31
31
32
-
#include <asm/mmu_context.h>
33
32
#include <asm/cacheflush.h>
34
33
#include <asm/pgtable.h>
35
34
#include <asm/war.h>
···
304
305
#ifdef CONFIG_64BIT
305
306
static int check_for_high_segbits __cpuinitdata;
306
307
#endif
307
-
308
-
static void __cpuinit insn_fixup(unsigned int **start, unsigned int **stop,
309
-
unsigned int i_const)
310
-
{
311
-
unsigned int **p;
312
-
313
-
for (p = start; p < stop; p++) {
314
-
#ifndef CONFIG_CPU_MICROMIPS
315
-
unsigned int *ip;
316
-
317
-
ip = *p;
318
-
*ip = (*ip & 0xffff0000) | i_const;
319
-
#else
320
-
unsigned short *ip;
321
-
322
-
ip = ((unsigned short *)((unsigned int)*p - 1));
323
-
if ((*ip & 0xf000) == 0x4000) {
324
-
*ip &= 0xfff1;
325
-
*ip |= (i_const << 1);
326
-
} else if ((*ip & 0xf000) == 0x6000) {
327
-
*ip &= 0xfff1;
328
-
*ip |= ((i_const >> 2) << 1);
329
-
} else {
330
-
ip++;
331
-
*ip = i_const;
332
-
}
333
-
#endif
334
-
local_flush_icache_range((unsigned long)ip,
335
-
(unsigned long)ip + sizeof(*ip));
336
-
}
337
-
}
338
-
339
-
#define asid_insn_fixup(section, const) \
340
-
do { \
341
-
extern unsigned int *__start_ ## section; \
342
-
extern unsigned int *__stop_ ## section; \
343
-
insn_fixup(&__start_ ## section, &__stop_ ## section, const); \
344
-
} while(0)
345
-
346
-
/*
347
-
* Caller is assumed to flush the caches before the first context switch.
348
-
*/
349
-
static void __cpuinit setup_asid(unsigned int inc, unsigned int mask,
350
-
unsigned int version_mask,
351
-
unsigned int first_version)
352
-
{
353
-
extern asmlinkage void handle_ri_rdhwr_vivt(void);
354
-
unsigned long *vivt_exc;
355
-
356
-
#ifdef CONFIG_CPU_MICROMIPS
357
-
/*
358
-
* Worst case optimised microMIPS addiu instructions support
359
-
* only a 3-bit immediate value.
360
-
*/
361
-
if(inc > 7)
362
-
panic("Invalid ASID increment value!");
363
-
#endif
364
-
asid_insn_fixup(__asid_inc, inc);
365
-
asid_insn_fixup(__asid_mask, mask);
366
-
asid_insn_fixup(__asid_version_mask, version_mask);
367
-
asid_insn_fixup(__asid_first_version, first_version);
368
-
369
-
/* Patch up the 'handle_ri_rdhwr_vivt' handler. */
370
-
vivt_exc = (unsigned long *) &handle_ri_rdhwr_vivt;
371
-
#ifdef CONFIG_CPU_MICROMIPS
372
-
vivt_exc = (unsigned long *)((unsigned long) vivt_exc - 1);
373
-
#endif
374
-
vivt_exc++;
375
-
*vivt_exc = (*vivt_exc & ~mask) | mask;
376
-
377
-
current_cpu_data.asid_cache = first_version;
378
-
}
379
308
380
309
static int check_for_high_segbits __cpuinitdata;
381
310
···
2183
2256
case CPU_TX3922:
2184
2257
case CPU_TX3927:
2185
2258
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2186
-
setup_asid(0x40, 0xfc0, 0xf000, ASID_FIRST_VERSION_R3000);
2187
2259
if (cpu_has_local_ebase)
2188
2260
build_r3000_tlb_refill_handler();
2189
2261
if (!run_once) {
···
2208
2282
break;
2209
2283
2210
2284
default:
2211
-
#ifndef CONFIG_MIPS_MT_SMTC
2212
-
setup_asid(0x1, 0xff, 0xff00, ASID_FIRST_VERSION_R4000);
2213
-
#else
2214
-
setup_asid(0x1, smtc_asid_mask, 0xff00, ASID_FIRST_VERSION_R4000);
2215
-
#endif
2216
2285
if (!run_once) {
2217
2286
scratch_reg = allocate_kscratch();
2218
2287
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
+1
-1
arch/mips/pmcs-msp71xx/msp_prom.c
+1
-1
arch/mips/pmcs-msp71xx/msp_prom.c
+10
arch/mips/ralink/dts/rt3050.dtsi
+10
arch/mips/ralink/dts/rt3050.dtsi