Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-misc-fixes-2026-03-12' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes
A pixel byte swap fix for st7586, a null pointer dereference fix for
gud, two timings fixes for ti-sn65dsi83, an initialization fix for ivpu,
and a runtime suspend deadlock fix for amdxdna.
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Maxime Ripard <mripard@redhat.com>
Link: https://patch.msgid.link/20260312-accurate-ambrosial-trout-bfabf8@houat
+74
-55
+1
-2
MAINTAINERS
+1
-2
MAINTAINERS
···
8626
8626
F: include/uapi/drm/lima_drm.h
8627
8627
8628
8628
DRM DRIVERS FOR LOONGSON
8629
-
M: Sui Jingfeng <suijingfeng@loongson.cn>
8630
8629
L: dri-devel@lists.freedesktop.org
8631
-
S: Supported
8630
+
S: Orphan
8632
8631
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
8633
8632
F: drivers/gpu/drm/loongson/
8634
8633
+2
-12
drivers/accel/amdxdna/aie2_ctx.c
+2
-12
drivers/accel/amdxdna/aie2_ctx.c
···
165
165
166
166
trace_xdna_job(&job->base, job->hwctx->name, "signaled fence", job->seq);
167
167
168
-
amdxdna_pm_suspend_put(job->hwctx->client->xdna);
169
168
job->hwctx->priv->completed++;
170
169
dma_fence_signal(fence);
171
170
···
289
290
struct dma_fence *fence;
290
291
int ret;
291
292
292
-
ret = amdxdna_pm_resume_get(hwctx->client->xdna);
293
-
if (ret)
293
+
if (!hwctx->priv->mbox_chann)
294
294
return NULL;
295
295
296
-
if (!hwctx->priv->mbox_chann) {
297
-
amdxdna_pm_suspend_put(hwctx->client->xdna);
298
-
return NULL;
299
-
}
300
-
301
-
if (!mmget_not_zero(job->mm)) {
302
-
amdxdna_pm_suspend_put(hwctx->client->xdna);
296
+
if (!mmget_not_zero(job->mm))
303
297
return ERR_PTR(-ESRCH);
304
-
}
305
298
306
299
kref_get(&job->refcnt);
307
300
fence = dma_fence_get(job->fence);
···
324
333
325
334
out:
326
335
if (ret) {
327
-
amdxdna_pm_suspend_put(hwctx->client->xdna);
328
336
dma_fence_put(job->fence);
329
337
aie2_job_put(job);
330
338
mmput(job->mm);
+10
drivers/accel/amdxdna/amdxdna_ctx.c
+10
drivers/accel/amdxdna/amdxdna_ctx.c
···
17
17
#include "amdxdna_ctx.h"
18
18
#include "amdxdna_gem.h"
19
19
#include "amdxdna_pci_drv.h"
20
+
#include "amdxdna_pm.h"
20
21
21
22
#define MAX_HWCTX_ID 255
22
23
#define MAX_ARG_COUNT 4095
···
446
445
void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job)
447
446
{
448
447
trace_amdxdna_debug_point(job->hwctx->name, job->seq, "job release");
448
+
amdxdna_pm_suspend_put(job->hwctx->client->xdna);
449
449
amdxdna_arg_bos_put(job);
450
450
amdxdna_gem_put_obj(job->cmd_bo);
451
451
dma_fence_put(job->fence);
···
482
480
if (ret) {
483
481
XDNA_ERR(xdna, "Argument BOs lookup failed, ret %d", ret);
484
482
goto cmd_put;
483
+
}
484
+
485
+
ret = amdxdna_pm_resume_get(xdna);
486
+
if (ret) {
487
+
XDNA_ERR(xdna, "Resume failed, ret %d", ret);
488
+
goto put_bos;
485
489
}
486
490
487
491
idx = srcu_read_lock(&client->hwctx_srcu);
···
530
522
dma_fence_put(job->fence);
531
523
unlock_srcu:
532
524
srcu_read_unlock(&client->hwctx_srcu, idx);
525
+
amdxdna_pm_suspend_put(xdna);
526
+
put_bos:
533
527
amdxdna_arg_bos_put(job);
534
528
cmd_put:
535
529
amdxdna_gem_put_obj(job->cmd_bo);
-6
drivers/accel/ivpu/ivpu_hw_40xx_reg.h
-6
drivers/accel/ivpu/ivpu_hw_40xx_reg.h
···
121
121
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY 0x0003006cu
122
122
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0)
123
123
124
-
#define VPU_40XX_HOST_SS_AON_RETENTION0 0x0003000cu
125
-
#define VPU_40XX_HOST_SS_AON_RETENTION1 0x00030010u
126
-
#define VPU_40XX_HOST_SS_AON_RETENTION2 0x00030014u
127
-
#define VPU_40XX_HOST_SS_AON_RETENTION3 0x00030018u
128
-
#define VPU_40XX_HOST_SS_AON_RETENTION4 0x0003001cu
129
-
130
124
#define VPU_40XX_HOST_SS_AON_IDLE_GEN 0x00030200u
131
125
#define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK BIT_MASK(0)
132
126
#define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK BIT_MASK(1)
-1
drivers/accel/ivpu/ivpu_hw_ip.c
-1
drivers/accel/ivpu/ivpu_hw_ip.c
+7
-6
drivers/gpu/drm/bridge/ti-sn65dsi83.c
+7
-6
drivers/gpu/drm/bridge/ti-sn65dsi83.c
···
351
351
* DSI_CLK = mode clock * bpp / dsi_data_lanes / 2
352
352
* the 2 is there because the bus is DDR.
353
353
*/
354
-
return DIV_ROUND_UP(clamp((unsigned int)mode->clock *
355
-
mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
356
-
ctx->dsi->lanes / 2, 40000U, 500000U), 5000U);
354
+
return clamp((unsigned int)mode->clock *
355
+
mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
356
+
ctx->dsi->lanes / 2, 40000U, 500000U) / 5000U;
357
357
}
358
358
359
359
static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)
···
517
517
struct drm_atomic_state *state)
518
518
{
519
519
struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
520
+
const unsigned int dual_factor = ctx->lvds_dual_link ? 2 : 1;
520
521
const struct drm_bridge_state *bridge_state;
521
522
const struct drm_crtc_state *crtc_state;
522
523
const struct drm_display_mode *mode;
···
654
653
/* 32 + 1 pixel clock to ensure proper operation */
655
654
le16val = cpu_to_le16(32 + 1);
656
655
regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2);
657
-
le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start);
656
+
le16val = cpu_to_le16((mode->hsync_end - mode->hsync_start) / dual_factor);
658
657
regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
659
658
&le16val, 2);
660
659
le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start);
661
660
regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
662
661
&le16val, 2);
663
662
regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
664
-
mode->htotal - mode->hsync_end);
663
+
(mode->htotal - mode->hsync_end) / dual_factor);
665
664
regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
666
665
mode->vtotal - mode->vsync_end);
667
666
regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
668
-
mode->hsync_start - mode->hdisplay);
667
+
(mode->hsync_start - mode->hdisplay) / dual_factor);
669
668
regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
670
669
mode->vsync_start - mode->vdisplay);
671
670
regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
+8
-1
drivers/gpu/drm/gud/gud_drv.c
+8
-1
drivers/gpu/drm/gud/gud_drv.c
···
339
339
}
340
340
341
341
static const struct drm_crtc_helper_funcs gud_crtc_helper_funcs = {
342
-
.atomic_check = drm_crtc_helper_atomic_check
342
+
.atomic_check = drm_crtc_helper_atomic_check,
343
+
.atomic_enable = gud_crtc_atomic_enable,
344
+
.atomic_disable = gud_crtc_atomic_disable,
343
345
};
344
346
345
347
static const struct drm_crtc_funcs gud_crtc_funcs = {
···
364
362
.disable_plane = drm_atomic_helper_disable_plane,
365
363
.destroy = drm_plane_cleanup,
366
364
DRM_GEM_SHADOW_PLANE_FUNCS,
365
+
};
366
+
367
+
static const struct drm_mode_config_helper_funcs gud_mode_config_helpers = {
368
+
.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
367
369
};
368
370
369
371
static const struct drm_mode_config_funcs gud_mode_config_funcs = {
···
505
499
drm->mode_config.min_height = le32_to_cpu(desc.min_height);
506
500
drm->mode_config.max_height = le32_to_cpu(desc.max_height);
507
501
drm->mode_config.funcs = &gud_mode_config_funcs;
502
+
drm->mode_config.helper_private = &gud_mode_config_helpers;
508
503
509
504
/* Format init */
510
505
formats_dev = devm_kmalloc(dev, GUD_FORMATS_MAX_NUM, GFP_KERNEL);
+4
drivers/gpu/drm/gud/gud_internal.h
+4
drivers/gpu/drm/gud/gud_internal.h
···
62
62
63
63
void gud_clear_damage(struct gud_device *gdrm);
64
64
void gud_flush_work(struct work_struct *work);
65
+
void gud_crtc_atomic_enable(struct drm_crtc *crtc,
66
+
struct drm_atomic_state *state);
67
+
void gud_crtc_atomic_disable(struct drm_crtc *crtc,
68
+
struct drm_atomic_state *state);
65
69
int gud_plane_atomic_check(struct drm_plane *plane,
66
70
struct drm_atomic_state *state);
67
71
void gud_plane_atomic_update(struct drm_plane *plane,
+36
-18
drivers/gpu/drm/gud/gud_pipe.c
+36
-18
drivers/gpu/drm/gud/gud_pipe.c
···
580
580
return ret;
581
581
}
582
582
583
+
void gud_crtc_atomic_enable(struct drm_crtc *crtc,
584
+
struct drm_atomic_state *state)
585
+
{
586
+
struct drm_device *drm = crtc->dev;
587
+
struct gud_device *gdrm = to_gud_device(drm);
588
+
int idx;
589
+
590
+
if (!drm_dev_enter(drm, &idx))
591
+
return;
592
+
593
+
gud_usb_set_u8(gdrm, GUD_REQ_SET_CONTROLLER_ENABLE, 1);
594
+
gud_usb_set(gdrm, GUD_REQ_SET_STATE_COMMIT, 0, NULL, 0);
595
+
gud_usb_set_u8(gdrm, GUD_REQ_SET_DISPLAY_ENABLE, 1);
596
+
597
+
drm_dev_exit(idx);
598
+
}
599
+
600
+
void gud_crtc_atomic_disable(struct drm_crtc *crtc,
601
+
struct drm_atomic_state *state)
602
+
{
603
+
struct drm_device *drm = crtc->dev;
604
+
struct gud_device *gdrm = to_gud_device(drm);
605
+
int idx;
606
+
607
+
if (!drm_dev_enter(drm, &idx))
608
+
return;
609
+
610
+
gud_usb_set_u8(gdrm, GUD_REQ_SET_DISPLAY_ENABLE, 0);
611
+
gud_usb_set_u8(gdrm, GUD_REQ_SET_CONTROLLER_ENABLE, 0);
612
+
613
+
drm_dev_exit(idx);
614
+
}
615
+
583
616
void gud_plane_atomic_update(struct drm_plane *plane,
584
617
struct drm_atomic_state *atomic_state)
585
618
{
···
640
607
mutex_unlock(&gdrm->damage_lock);
641
608
}
642
609
643
-
if (!drm_dev_enter(drm, &idx))
610
+
if (!crtc || !drm_dev_enter(drm, &idx))
644
611
return;
645
-
646
-
if (!old_state->fb)
647
-
gud_usb_set_u8(gdrm, GUD_REQ_SET_CONTROLLER_ENABLE, 1);
648
-
649
-
if (fb && (crtc->state->mode_changed || crtc->state->connectors_changed))
650
-
gud_usb_set(gdrm, GUD_REQ_SET_STATE_COMMIT, 0, NULL, 0);
651
-
652
-
if (crtc->state->active_changed)
653
-
gud_usb_set_u8(gdrm, GUD_REQ_SET_DISPLAY_ENABLE, crtc->state->active);
654
-
655
-
if (!fb)
656
-
goto ctrl_disable;
657
612
658
613
ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
659
614
if (ret)
660
-
goto ctrl_disable;
615
+
goto out;
661
616
662
617
drm_atomic_helper_damage_iter_init(&iter, old_state, new_state);
663
618
drm_atomic_for_each_plane_damage(&iter, &damage)
···
653
632
654
633
drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
655
634
656
-
ctrl_disable:
657
-
if (!crtc->state->enable)
658
-
gud_usb_set_u8(gdrm, GUD_REQ_SET_CONTROLLER_ENABLE, 0);
659
-
635
+
out:
660
636
drm_dev_exit(idx);
661
637
}
+6
-9
drivers/gpu/drm/sitronix/st7586.c
+6
-9
drivers/gpu/drm/sitronix/st7586.c
···
347
347
if (ret)
348
348
return ret;
349
349
350
+
/*
351
+
* Override value set by mipi_dbi_spi_init(). This driver is a bit
352
+
* non-standard, so best to set it explicitly here.
353
+
*/
354
+
dbi->write_memory_bpw = 8;
355
+
350
356
/* Cannot read from this controller via SPI */
351
357
dbi->read_commands = NULL;
352
358
···
361
355
&st7586_mode, rotation, bufsize);
362
356
if (ret)
363
357
return ret;
364
-
365
-
/*
366
-
* we are using 8-bit data, so we are not actually swapping anything,
367
-
* but setting mipi->swap_bytes makes mipi_dbi_typec3_command() do the
368
-
* right thing and not use 16-bit transfers (which results in swapped
369
-
* bytes on little-endian systems and causes out of order data to be
370
-
* sent to the display).
371
-
*/
372
-
dbi->swap_bytes = true;
373
358
374
359
drm_mode_config_reset(drm);
375
360