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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM fixes from Paolo Bonzini:
"PPC:
- fix bug leading to lost IPIs and smp_call_function_many() lockups
on POWER9

ARM:
- locking fix
- reset fix
- GICv2 multi-source SGI injection fix
- GICv2-on-v3 MMIO synchronization fix
- make the console less verbose.

x86:
- fix device passthrough on AMD SME"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: x86: Fix device passthrough when SME is active
kvm: arm/arm64: vgic-v3: Tighten synchronization for guests using v2 on v3
KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid
KVM: arm/arm64: Reduce verbosity of KVM init log
KVM: arm/arm64: Reset mapped IRQs on VM reset
KVM: arm/arm64: Avoid vcpu_load for other vcpu ioctls than KVM_RUN
KVM: arm/arm64: vgic: Add missing irq_lock to vgic_mmio_read_pending
KVM: PPC: Book3S HV: Fix trap number return from __kvmppc_vcore_entry

+118 -41
-3
arch/arm64/kvm/guest.c
··· 363 363 { 364 364 int ret = 0; 365 365 366 - vcpu_load(vcpu); 367 - 368 366 trace_kvm_set_guest_debug(vcpu, dbg->control); 369 367 370 368 if (dbg->control & ~KVM_GUESTDBG_VALID_MASK) { ··· 384 386 } 385 387 386 388 out: 387 - vcpu_put(vcpu); 388 389 return ret; 389 390 } 390 391
+5 -5
arch/powerpc/kvm/book3s_hv_rmhandlers.S
··· 320 320 stw r12, STACK_SLOT_TRAP(r1) 321 321 bl kvmhv_commence_exit 322 322 nop 323 - lwz r12, STACK_SLOT_TRAP(r1) 324 323 b kvmhv_switch_to_host 325 324 326 325 /* ··· 1219 1220 1220 1221 secondary_too_late: 1221 1222 li r12, 0 1223 + stw r12, STACK_SLOT_TRAP(r1) 1222 1224 cmpdi r4, 0 1223 1225 beq 11f 1224 1226 stw r12, VCPU_TRAP(r4) ··· 1558 1558 3: stw r5,VCPU_SLB_MAX(r9) 1559 1559 1560 1560 guest_bypass: 1561 + stw r12, STACK_SLOT_TRAP(r1) 1561 1562 mr r3, r12 1562 1563 /* Increment exit count, poke other threads to exit */ 1563 1564 bl kvmhv_commence_exit 1564 1565 nop 1565 1566 ld r9, HSTATE_KVM_VCPU(r13) 1566 - lwz r12, VCPU_TRAP(r9) 1567 1567 1568 1568 /* Stop others sending VCPU interrupts to this physical CPU */ 1569 1569 li r0, -1 ··· 1898 1898 * POWER7/POWER8 guest -> host partition switch code. 1899 1899 * We don't have to lock against tlbies but we do 1900 1900 * have to coordinate the hardware threads. 1901 + * Here STACK_SLOT_TRAP(r1) contains the trap number. 1901 1902 */ 1902 1903 kvmhv_switch_to_host: 1903 1904 /* Secondary threads wait for primary to do partition switch */ ··· 1951 1950 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 1952 1951 1953 1952 /* If HMI, call kvmppc_realmode_hmi_handler() */ 1953 + lwz r12, STACK_SLOT_TRAP(r1) 1954 1954 cmpwi r12, BOOK3S_INTERRUPT_HMI 1955 1955 bne 27f 1956 1956 bl kvmppc_realmode_hmi_handler 1957 1957 nop 1958 1958 cmpdi r3, 0 1959 - li r12, BOOK3S_INTERRUPT_HMI 1960 1959 /* 1961 1960 * At this point kvmppc_realmode_hmi_handler may have resync-ed 1962 1961 * the TB, and if it has, we must not subtract the guest timebase ··· 2009 2008 lwz r8, KVM_SPLIT_DO_RESTORE(r3) 2010 2009 cmpwi r8, 0 2011 2010 beq 47f 2012 - stw r12, STACK_SLOT_TRAP(r1) 2013 2011 bl kvmhv_p9_restore_lpcr 2014 2012 nop 2015 - lwz r12, STACK_SLOT_TRAP(r1) 2016 2013 b 48f 2017 2014 47: 2018 2015 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) ··· 2048 2049 li r0, KVM_GUEST_MODE_NONE 2049 2050 stb r0, HSTATE_IN_GUEST(r13) 2050 2051 2052 + lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */ 2051 2053 ld r0, SFS+PPC_LR_STKOFF(r1) 2052 2054 addi r1, r1, SFS 2053 2055 mtlr r0
+3 -1
arch/x86/kvm/mmu.c
··· 2770 2770 else 2771 2771 pte_access &= ~ACC_WRITE_MASK; 2772 2772 2773 + if (!kvm_is_mmio_pfn(pfn)) 2774 + spte |= shadow_me_mask; 2775 + 2773 2776 spte |= (u64)pfn << PAGE_SHIFT; 2774 - spte |= shadow_me_mask; 2775 2777 2776 2778 if (pte_access & ACC_WRITE_MASK) { 2777 2779
+1
include/kvm/arm_vgic.h
··· 360 360 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu); 361 361 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 362 362 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 363 + void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid); 363 364 364 365 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); 365 366
+1
include/linux/irqchip/arm-gic-v3.h
··· 503 503 504 504 #define ICH_HCR_EN (1 << 0) 505 505 #define ICH_HCR_UIE (1 << 1) 506 + #define ICH_HCR_NPIE (1 << 3) 506 507 #define ICH_HCR_TC (1 << 10) 507 508 #define ICH_HCR_TALL0 (1 << 11) 508 509 #define ICH_HCR_TALL1 (1 << 12)
+1
include/linux/irqchip/arm-gic.h
··· 84 84 85 85 #define GICH_HCR_EN (1 << 0) 86 86 #define GICH_HCR_UIE (1 << 1) 87 + #define GICH_HCR_NPIE (1 << 3) 87 88 88 89 #define GICH_LR_VIRTUALID (0x3ff << 0) 89 90 #define GICH_LR_PHYSID_CPUID_SHIFT (10)
+5 -1
virt/kvm/arm/arch_timer.c
··· 581 581 582 582 int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu) 583 583 { 584 + struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; 584 585 struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); 585 586 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); 586 587 ··· 594 593 vtimer->cnt_ctl = 0; 595 594 ptimer->cnt_ctl = 0; 596 595 kvm_timer_update_state(vcpu); 596 + 597 + if (timer->enabled && irqchip_in_kernel(vcpu->kvm)) 598 + kvm_vgic_reset_mapped_irq(vcpu, vtimer->irq.irq); 597 599 598 600 return 0; 599 601 } ··· 771 767 static_branch_enable(&has_gic_active_state); 772 768 } 773 769 774 - kvm_info("virtual timer IRQ%d\n", host_vtimer_irq); 770 + kvm_debug("virtual timer IRQ%d\n", host_vtimer_irq); 775 771 776 772 cpuhp_setup_state(CPUHP_AP_KVM_ARM_TIMER_STARTING, 777 773 "kvm/arm/timer:starting", kvm_timer_starting_cpu,
-9
virt/kvm/arm/arm.c
··· 384 384 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 385 385 struct kvm_mp_state *mp_state) 386 386 { 387 - vcpu_load(vcpu); 388 - 389 387 if (vcpu->arch.power_off) 390 388 mp_state->mp_state = KVM_MP_STATE_STOPPED; 391 389 else 392 390 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 393 391 394 - vcpu_put(vcpu); 395 392 return 0; 396 393 } 397 394 ··· 396 399 struct kvm_mp_state *mp_state) 397 400 { 398 401 int ret = 0; 399 - 400 - vcpu_load(vcpu); 401 402 402 403 switch (mp_state->mp_state) { 403 404 case KVM_MP_STATE_RUNNABLE: ··· 408 413 ret = -EINVAL; 409 414 } 410 415 411 - vcpu_put(vcpu); 412 416 return ret; 413 417 } 414 418 ··· 1030 1036 struct kvm_device_attr attr; 1031 1037 long r; 1032 1038 1033 - vcpu_load(vcpu); 1034 - 1035 1039 switch (ioctl) { 1036 1040 case KVM_ARM_VCPU_INIT: { 1037 1041 struct kvm_vcpu_init init; ··· 1106 1114 r = -EINVAL; 1107 1115 } 1108 1116 1109 - vcpu_put(vcpu); 1110 1117 return r; 1111 1118 } 1112 1119
+2 -1
virt/kvm/arm/hyp/vgic-v3-sr.c
··· 215 215 * are now visible to the system register interface. 216 216 */ 217 217 if (!cpu_if->vgic_sre) { 218 - dsb(st); 218 + dsb(sy); 219 + isb(); 219 220 cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2); 220 221 } 221 222
+3 -3
virt/kvm/arm/mmu.c
··· 1810 1810 */ 1811 1811 BUG_ON((hyp_idmap_start ^ (hyp_idmap_end - 1)) & PAGE_MASK); 1812 1812 1813 - kvm_info("IDMAP page: %lx\n", hyp_idmap_start); 1814 - kvm_info("HYP VA range: %lx:%lx\n", 1815 - kern_hyp_va(PAGE_OFFSET), kern_hyp_va(~0UL)); 1813 + kvm_debug("IDMAP page: %lx\n", hyp_idmap_start); 1814 + kvm_debug("HYP VA range: %lx:%lx\n", 1815 + kern_hyp_va(PAGE_OFFSET), kern_hyp_va(~0UL)); 1816 1816 1817 1817 if (hyp_idmap_start >= kern_hyp_va(PAGE_OFFSET) && 1818 1818 hyp_idmap_start < kern_hyp_va(~0UL) &&
+3
virt/kvm/arm/vgic/vgic-mmio.c
··· 113 113 /* Loop over all IRQs affected by this read */ 114 114 for (i = 0; i < len * 8; i++) { 115 115 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); 116 + unsigned long flags; 116 117 118 + spin_lock_irqsave(&irq->irq_lock, flags); 117 119 if (irq_is_pending(irq)) 118 120 value |= (1U << i); 121 + spin_unlock_irqrestore(&irq->irq_lock, flags); 119 122 120 123 vgic_put_irq(vcpu->kvm, irq); 121 124 }
+9 -2
virt/kvm/arm/vgic/vgic-v2.c
··· 37 37 vgic_v2_write_lr(i, 0); 38 38 } 39 39 40 + void vgic_v2_set_npie(struct kvm_vcpu *vcpu) 41 + { 42 + struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2; 43 + 44 + cpuif->vgic_hcr |= GICH_HCR_NPIE; 45 + } 46 + 40 47 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu) 41 48 { 42 49 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2; ··· 71 64 int lr; 72 65 unsigned long flags; 73 66 74 - cpuif->vgic_hcr &= ~GICH_HCR_UIE; 67 + cpuif->vgic_hcr &= ~(GICH_HCR_UIE | GICH_HCR_NPIE); 75 68 76 69 for (lr = 0; lr < vgic_cpu->used_lrs; lr++) { 77 70 u32 val = cpuif->vgic_lr[lr]; ··· 417 410 kvm_vgic_global_state.type = VGIC_V2; 418 411 kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS; 419 412 420 - kvm_info("vgic-v2@%llx\n", info->vctrl.start); 413 + kvm_debug("vgic-v2@%llx\n", info->vctrl.start); 421 414 422 415 return 0; 423 416 out:
+8 -1
virt/kvm/arm/vgic/vgic-v3.c
··· 26 26 static bool common_trap; 27 27 static bool gicv4_enable; 28 28 29 + void vgic_v3_set_npie(struct kvm_vcpu *vcpu) 30 + { 31 + struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; 32 + 33 + cpuif->vgic_hcr |= ICH_HCR_NPIE; 34 + } 35 + 29 36 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu) 30 37 { 31 38 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; ··· 54 47 int lr; 55 48 unsigned long flags; 56 49 57 - cpuif->vgic_hcr &= ~ICH_HCR_UIE; 50 + cpuif->vgic_hcr &= ~(ICH_HCR_UIE | ICH_HCR_NPIE); 58 51 59 52 for (lr = 0; lr < vgic_cpu->used_lrs; lr++) { 60 53 u64 val = cpuif->vgic_lr[lr];
+74 -15
virt/kvm/arm/vgic/vgic.c
··· 495 495 return ret; 496 496 } 497 497 498 + /** 499 + * kvm_vgic_reset_mapped_irq - Reset a mapped IRQ 500 + * @vcpu: The VCPU pointer 501 + * @vintid: The INTID of the interrupt 502 + * 503 + * Reset the active and pending states of a mapped interrupt. Kernel 504 + * subsystems injecting mapped interrupts should reset their interrupt lines 505 + * when we are doing a reset of the VM. 506 + */ 507 + void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid) 508 + { 509 + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, vintid); 510 + unsigned long flags; 511 + 512 + if (!irq->hw) 513 + goto out; 514 + 515 + spin_lock_irqsave(&irq->irq_lock, flags); 516 + irq->active = false; 517 + irq->pending_latch = false; 518 + irq->line_level = false; 519 + spin_unlock_irqrestore(&irq->irq_lock, flags); 520 + out: 521 + vgic_put_irq(vcpu->kvm, irq); 522 + } 523 + 498 524 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid) 499 525 { 500 526 struct vgic_irq *irq; ··· 710 684 vgic_v3_set_underflow(vcpu); 711 685 } 712 686 687 + static inline void vgic_set_npie(struct kvm_vcpu *vcpu) 688 + { 689 + if (kvm_vgic_global_state.type == VGIC_V2) 690 + vgic_v2_set_npie(vcpu); 691 + else 692 + vgic_v3_set_npie(vcpu); 693 + } 694 + 713 695 /* Requires the ap_list_lock to be held. */ 714 - static int compute_ap_list_depth(struct kvm_vcpu *vcpu) 696 + static int compute_ap_list_depth(struct kvm_vcpu *vcpu, 697 + bool *multi_sgi) 715 698 { 716 699 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 717 700 struct vgic_irq *irq; 718 701 int count = 0; 702 + 703 + *multi_sgi = false; 719 704 720 705 DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vgic_cpu->ap_list_lock)); 721 706 722 707 list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) { 723 708 spin_lock(&irq->irq_lock); 724 709 /* GICv2 SGIs can count for more than one... */ 725 - if (vgic_irq_is_sgi(irq->intid) && irq->source) 726 - count += hweight8(irq->source); 727 - else 710 + if (vgic_irq_is_sgi(irq->intid) && irq->source) { 711 + int w = hweight8(irq->source); 712 + 713 + count += w; 714 + *multi_sgi |= (w > 1); 715 + } else { 728 716 count++; 717 + } 729 718 spin_unlock(&irq->irq_lock); 730 719 } 731 720 return count; ··· 751 710 { 752 711 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 753 712 struct vgic_irq *irq; 754 - int count = 0; 713 + int count; 714 + bool npie = false; 715 + bool multi_sgi; 716 + u8 prio = 0xff; 755 717 756 718 DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vgic_cpu->ap_list_lock)); 757 719 758 - if (compute_ap_list_depth(vcpu) > kvm_vgic_global_state.nr_lr) 720 + count = compute_ap_list_depth(vcpu, &multi_sgi); 721 + if (count > kvm_vgic_global_state.nr_lr || multi_sgi) 759 722 vgic_sort_ap_list(vcpu); 723 + 724 + count = 0; 760 725 761 726 list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) { 762 727 spin_lock(&irq->irq_lock); 763 728 764 - if (unlikely(vgic_target_oracle(irq) != vcpu)) 765 - goto next; 766 - 767 729 /* 768 - * If we get an SGI with multiple sources, try to get 769 - * them in all at once. 730 + * If we have multi-SGIs in the pipeline, we need to 731 + * guarantee that they are all seen before any IRQ of 732 + * lower priority. In that case, we need to filter out 733 + * these interrupts by exiting early. This is easy as 734 + * the AP list has been sorted already. 770 735 */ 771 - do { 772 - vgic_populate_lr(vcpu, irq, count++); 773 - } while (irq->source && count < kvm_vgic_global_state.nr_lr); 736 + if (multi_sgi && irq->priority > prio) { 737 + spin_unlock(&irq->irq_lock); 738 + break; 739 + } 774 740 775 - next: 741 + if (likely(vgic_target_oracle(irq) == vcpu)) { 742 + vgic_populate_lr(vcpu, irq, count++); 743 + 744 + if (irq->source) { 745 + npie = true; 746 + prio = irq->priority; 747 + } 748 + } 749 + 776 750 spin_unlock(&irq->irq_lock); 777 751 778 752 if (count == kvm_vgic_global_state.nr_lr) { ··· 797 741 break; 798 742 } 799 743 } 744 + 745 + if (npie) 746 + vgic_set_npie(vcpu); 800 747 801 748 vcpu->arch.vgic_cpu.used_lrs = count; 802 749
+3
virt/kvm/arm/vgic/vgic.h
··· 96 96 /* we only support 64 kB translation table page size */ 97 97 #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16) 98 98 99 + /* Requires the irq_lock to be held by the caller. */ 99 100 static inline bool irq_is_pending(struct vgic_irq *irq) 100 101 { 101 102 if (irq->config == VGIC_CONFIG_EDGE) ··· 160 159 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr); 161 160 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr); 162 161 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu); 162 + void vgic_v2_set_npie(struct kvm_vcpu *vcpu); 163 163 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr); 164 164 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 165 165 int offset, u32 *val); ··· 190 188 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr); 191 189 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr); 192 190 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu); 191 + void vgic_v3_set_npie(struct kvm_vcpu *vcpu); 193 192 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 194 193 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 195 194 void vgic_v3_enable(struct kvm_vcpu *vcpu);