Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma
Pull rdma updates from Jason Gunthorpe:
"Usual collection of small improvements and fixes:
- Bug fixes and minor improvments in efa, irdma, mlx4, mlx5, rxe,
hf1, qib, ocrdma
- bnxt_re support for MSN, which is a new retransmit logic
- Initial mana support for RC qps
- Use after free bug and cleanups in iwcm
- Reduce resource usage in mlx5 when RDMA verbs features are not used
- New verb to drain shared recieve queues, similar to normal recieve
queues. This is necessary to allow ULPs a clean shutdown. Used in
the iscsi rdma target
- mlx5 support for more than 16 bits of doorbell indexes
- Doorbell moderation support for bnxt_re
- IB multi-plane support for mlx5
- New EFA adaptor PCI IDs
- RDMA_NAME_ASSIGN_TYPE_USER to hint to userspace that it shouldn't
rename the device
- A collection of hns bugs
- Fix long standing bug in bnxt_re with incorrect endian handling of
immediate data"
* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (65 commits)
IB/hfi1: Constify struct flag_table
RDMA/mana_ib: Set correct device into ib
bnxt_re: Fix imm_data endianness
RDMA: Fix netdev tracker in ib_device_set_netdev
RDMA/hns: Fix mbx timing out before CMD execution is completed
RDMA/hns: Fix insufficient extend DB for VFs.
RDMA/hns: Fix undifined behavior caused by invalid max_sge
RDMA/hns: Fix shift-out-bounds when max_inline_data is 0
RDMA/hns: Fix missing pagesize and alignment check in FRMR
RDMA/hns: Fix unmatch exception handling when init eq table fails
RDMA/hns: Fix soft lockup under heavy CEQE load
RDMA/hns: Check atomic wr length
RDMA/ocrdma: Don't inline statistics functions
RDMA/core: Introduce "name_assign_type" for an IB device
RDMA/qib: Fix truncation compilation warnings in qib_verbs.c
RDMA/qib: Fix truncation compilation warnings in qib_init.c
RDMA/efa: Add EFA 0xefa3 PCI ID
RDMA/mlx5: Support per-plane port IB counters by querying PPCNT register
net/mlx5: mlx5_ifc update for accessing ppcnt register of plane ports
RDMA/mlx5: Add plane index support when querying PTYS registers
...
+1787
-416
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
11207
11207
11208
11208
INTEL ETHERNET PROTOCOL DRIVER FOR RDMA
11209
11209
M: Mustafa Ismail <mustafa.ismail@intel.com>
11210
-
M: Shiraz Saleem <shiraz.saleem@intel.com>
11210
+
M: Tatyana Nikolova <tatyana.e.nikolova@intel.com>
11211
11211
L: linux-rdma@vger.kernel.org
11212
11212
S: Supported
11213
11213
F: drivers/infiniband/hw/irdma/
+22
-10
drivers/infiniband/core/agent.c
+22
-10
drivers/infiniband/core/agent.c
···
59
59
struct ib_agent_port_private *entry;
60
60
61
61
list_for_each_entry(entry, &ib_agent_port_list, port_list) {
62
-
if (entry->agent[1]->device == device &&
62
+
/* Need to check both agent[0] and agent[1], as an agent port
63
+
* may only have one of them
64
+
*/
65
+
if (entry->agent[0] &&
66
+
entry->agent[0]->device == device &&
67
+
entry->agent[0]->port_num == port_num)
68
+
return entry;
69
+
70
+
if (entry->agent[1] &&
71
+
entry->agent[1]->device == device &&
63
72
entry->agent[1]->port_num == port_num)
64
73
return entry;
65
74
}
···
181
172
}
182
173
}
183
174
184
-
/* Obtain send only MAD agent for GSI QP */
185
-
port_priv->agent[1] = ib_register_mad_agent(device, port_num,
186
-
IB_QPT_GSI, NULL, 0,
187
-
&agent_send_handler,
188
-
NULL, NULL, 0);
189
-
if (IS_ERR(port_priv->agent[1])) {
190
-
ret = PTR_ERR(port_priv->agent[1]);
191
-
goto error3;
175
+
if (rdma_cap_ib_cm(device, port_num)) {
176
+
/* Obtain send only MAD agent for GSI QP */
177
+
port_priv->agent[1] = ib_register_mad_agent(device, port_num,
178
+
IB_QPT_GSI, NULL, 0,
179
+
&agent_send_handler,
180
+
NULL, NULL, 0);
181
+
if (IS_ERR(port_priv->agent[1])) {
182
+
ret = PTR_ERR(port_priv->agent[1]);
183
+
goto error3;
184
+
}
192
185
}
193
186
194
187
spin_lock_irqsave(&ib_agent_port_list_lock, flags);
···
223
212
list_del(&port_priv->port_list);
224
213
spin_unlock_irqrestore(&ib_agent_port_list_lock, flags);
225
214
226
-
ib_unregister_mad_agent(port_priv->agent[1]);
215
+
if (port_priv->agent[1])
216
+
ib_unregister_mad_agent(port_priv->agent[1]);
227
217
if (port_priv->agent[0])
228
218
ib_unregister_mad_agent(port_priv->agent[0]);
229
219
+5
-9
drivers/infiniband/core/cache.c
+5
-9
drivers/infiniband/core/cache.c
···
794
794
static void release_gid_table(struct ib_device *device,
795
795
struct ib_gid_table *table)
796
796
{
797
-
bool leak = false;
798
797
int i;
799
798
800
799
if (!table)
···
802
803
for (i = 0; i < table->sz; i++) {
803
804
if (is_gid_entry_free(table->data_vec[i]))
804
805
continue;
805
-
if (kref_read(&table->data_vec[i]->kref) > 1) {
806
-
dev_err(&device->dev,
807
-
"GID entry ref leak for index %d ref=%u\n", i,
808
-
kref_read(&table->data_vec[i]->kref));
809
-
leak = true;
810
-
}
806
+
807
+
WARN_ONCE(true,
808
+
"GID entry ref leak for dev %s index %d ref=%u\n",
809
+
dev_name(&device->dev), i,
810
+
kref_read(&table->data_vec[i]->kref));
811
811
}
812
-
if (leak)
813
-
return;
814
812
815
813
mutex_destroy(&table->lock);
816
814
kfree(table->data_vec);
+74
-9
drivers/infiniband/core/device.c
+74
-9
drivers/infiniband/core/device.c
···
503
503
rcu_head);
504
504
}
505
505
506
+
mutex_destroy(&dev->subdev_lock);
506
507
mutex_destroy(&dev->unregistration_lock);
507
508
mutex_destroy(&dev->compat_devs_mutex);
508
509
···
642
641
BIT_ULL(IB_USER_VERBS_CMD_REG_MR) |
643
642
BIT_ULL(IB_USER_VERBS_CMD_REREG_MR) |
644
643
BIT_ULL(IB_USER_VERBS_CMD_RESIZE_CQ);
644
+
645
+
mutex_init(&device->subdev_lock);
646
+
INIT_LIST_HEAD(&device->subdev_list_head);
647
+
INIT_LIST_HEAD(&device->subdev_list);
648
+
645
649
return device;
646
650
}
647
651
EXPORT_SYMBOL(_ib_alloc_device);
···
1467
1461
/* Callers must hold a get on the device. */
1468
1462
static void __ib_unregister_device(struct ib_device *ib_dev)
1469
1463
{
1464
+
struct ib_device *sub, *tmp;
1465
+
1466
+
mutex_lock(&ib_dev->subdev_lock);
1467
+
list_for_each_entry_safe_reverse(sub, tmp,
1468
+
&ib_dev->subdev_list_head,
1469
+
subdev_list) {
1470
+
list_del(&sub->subdev_list);
1471
+
ib_dev->ops.del_sub_dev(sub);
1472
+
ib_device_put(ib_dev);
1473
+
}
1474
+
mutex_unlock(&ib_dev->subdev_lock);
1475
+
1470
1476
/*
1471
1477
* We have a registration lock so that all the calls to unregister are
1472
1478
* fully fenced, once any unregister returns the device is truely
···
2164
2146
unsigned long flags;
2165
2147
int ret;
2166
2148
2149
+
if (!rdma_is_port_valid(ib_dev, port))
2150
+
return -EINVAL;
2151
+
2167
2152
/*
2168
2153
* Drivers wish to call this before ib_register_driver, so we have to
2169
2154
* setup the port data early.
···
2174
2153
ret = alloc_port_data(ib_dev);
2175
2154
if (ret)
2176
2155
return ret;
2177
-
2178
-
if (!rdma_is_port_valid(ib_dev, port))
2179
-
return -EINVAL;
2180
2156
2181
2157
pdata = &ib_dev->port_data[port];
2182
2158
spin_lock_irqsave(&pdata->netdev_lock, flags);
···
2184
2166
return 0;
2185
2167
}
2186
2168
2187
-
if (old_ndev)
2188
-
netdev_tracker_free(ndev, &pdata->netdev_tracker);
2189
-
if (ndev)
2190
-
netdev_hold(ndev, &pdata->netdev_tracker, GFP_ATOMIC);
2191
2169
rcu_assign_pointer(pdata->netdev, ndev);
2170
+
netdev_put(old_ndev, &pdata->netdev_tracker);
2171
+
netdev_hold(ndev, &pdata->netdev_tracker, GFP_ATOMIC);
2192
2172
spin_unlock_irqrestore(&pdata->netdev_lock, flags);
2193
2173
2194
2174
add_ndev_hash(pdata);
2195
-
__dev_put(old_ndev);
2196
-
2197
2175
return 0;
2198
2176
}
2199
2177
EXPORT_SYMBOL(ib_device_set_netdev);
···
2611
2597
ops->uverbs_no_driver_id_binding;
2612
2598
2613
2599
SET_DEVICE_OP(dev_ops, add_gid);
2600
+
SET_DEVICE_OP(dev_ops, add_sub_dev);
2614
2601
SET_DEVICE_OP(dev_ops, advise_mr);
2615
2602
SET_DEVICE_OP(dev_ops, alloc_dm);
2616
2603
SET_DEVICE_OP(dev_ops, alloc_hw_device_stats);
···
2646
2631
SET_DEVICE_OP(dev_ops, dealloc_ucontext);
2647
2632
SET_DEVICE_OP(dev_ops, dealloc_xrcd);
2648
2633
SET_DEVICE_OP(dev_ops, del_gid);
2634
+
SET_DEVICE_OP(dev_ops, del_sub_dev);
2649
2635
SET_DEVICE_OP(dev_ops, dereg_mr);
2650
2636
SET_DEVICE_OP(dev_ops, destroy_ah);
2651
2637
SET_DEVICE_OP(dev_ops, destroy_counters);
···
2742
2726
SET_OBJ_SIZE(dev_ops, ib_xrcd);
2743
2727
}
2744
2728
EXPORT_SYMBOL(ib_set_device_ops);
2729
+
2730
+
int ib_add_sub_device(struct ib_device *parent,
2731
+
enum rdma_nl_dev_type type,
2732
+
const char *name)
2733
+
{
2734
+
struct ib_device *sub;
2735
+
int ret = 0;
2736
+
2737
+
if (!parent->ops.add_sub_dev || !parent->ops.del_sub_dev)
2738
+
return -EOPNOTSUPP;
2739
+
2740
+
if (!ib_device_try_get(parent))
2741
+
return -EINVAL;
2742
+
2743
+
sub = parent->ops.add_sub_dev(parent, type, name);
2744
+
if (IS_ERR(sub)) {
2745
+
ib_device_put(parent);
2746
+
return PTR_ERR(sub);
2747
+
}
2748
+
2749
+
sub->type = type;
2750
+
sub->parent = parent;
2751
+
2752
+
mutex_lock(&parent->subdev_lock);
2753
+
list_add_tail(&parent->subdev_list_head, &sub->subdev_list);
2754
+
mutex_unlock(&parent->subdev_lock);
2755
+
2756
+
return ret;
2757
+
}
2758
+
EXPORT_SYMBOL(ib_add_sub_device);
2759
+
2760
+
int ib_del_sub_device_and_put(struct ib_device *sub)
2761
+
{
2762
+
struct ib_device *parent = sub->parent;
2763
+
2764
+
if (!parent)
2765
+
return -EOPNOTSUPP;
2766
+
2767
+
mutex_lock(&parent->subdev_lock);
2768
+
list_del(&sub->subdev_list);
2769
+
mutex_unlock(&parent->subdev_lock);
2770
+
2771
+
ib_device_put(sub);
2772
+
parent->ops.del_sub_dev(sub);
2773
+
ib_device_put(parent);
2774
+
2775
+
return 0;
2776
+
}
2777
+
EXPORT_SYMBOL(ib_del_sub_device_and_put);
2745
2778
2746
2779
#ifdef CONFIG_INFINIBAND_VIRT_DMA
2747
2780
int ib_dma_virt_map_sg(struct ib_device *dev, struct scatterlist *sg, int nents)
+18
-23
drivers/infiniband/core/iwcm.c
+18
-23
drivers/infiniband/core/iwcm.c
···
143
143
144
144
if (list_empty(&cm_id_priv->work_free_list))
145
145
return NULL;
146
-
work = list_entry(cm_id_priv->work_free_list.next, struct iwcm_work,
147
-
free_list);
146
+
work = list_first_entry(&cm_id_priv->work_free_list, struct iwcm_work,
147
+
free_list);
148
148
list_del_init(&work->free_list);
149
149
return work;
150
150
}
···
206
206
207
207
/*
208
208
* Release a reference on cm_id. If the last reference is being
209
-
* released, free the cm_id and return 1.
209
+
* released, free the cm_id and return 'true'.
210
210
*/
211
-
static int iwcm_deref_id(struct iwcm_id_private *cm_id_priv)
211
+
static bool iwcm_deref_id(struct iwcm_id_private *cm_id_priv)
212
212
{
213
213
if (refcount_dec_and_test(&cm_id_priv->refcount)) {
214
214
BUG_ON(!list_empty(&cm_id_priv->work_list));
215
215
free_cm_id(cm_id_priv);
216
-
return 1;
216
+
return true;
217
217
}
218
218
219
-
return 0;
219
+
return false;
220
220
}
221
221
222
222
static void add_ref(struct iw_cm_id *cm_id)
···
368
368
*
369
369
* Clean up all resources associated with the connection and release
370
370
* the initial reference taken by iw_create_cm_id.
371
+
*
372
+
* Returns true if and only if the last cm_id_priv reference has been dropped.
371
373
*/
372
-
static void destroy_cm_id(struct iw_cm_id *cm_id)
374
+
static bool destroy_cm_id(struct iw_cm_id *cm_id)
373
375
{
374
376
struct iwcm_id_private *cm_id_priv;
375
377
struct ib_qp *qp;
···
441
439
iwpm_remove_mapping(&cm_id->local_addr, RDMA_NL_IWCM);
442
440
}
443
441
444
-
(void)iwcm_deref_id(cm_id_priv);
442
+
return iwcm_deref_id(cm_id_priv);
445
443
}
446
444
447
445
/*
···
452
450
*/
453
451
void iw_destroy_cm_id(struct iw_cm_id *cm_id)
454
452
{
455
-
destroy_cm_id(cm_id);
453
+
if (!destroy_cm_id(cm_id))
454
+
flush_workqueue(iwcm_wq);
456
455
}
457
456
EXPORT_SYMBOL(iw_destroy_cm_id);
458
457
···
1020
1017
struct iw_cm_event levent;
1021
1018
struct iwcm_id_private *cm_id_priv = work->cm_id;
1022
1019
unsigned long flags;
1023
-
int empty;
1024
1020
int ret = 0;
1025
1021
1026
1022
spin_lock_irqsave(&cm_id_priv->lock, flags);
1027
-
empty = list_empty(&cm_id_priv->work_list);
1028
-
while (!empty) {
1029
-
work = list_entry(cm_id_priv->work_list.next,
1030
-
struct iwcm_work, list);
1023
+
while (!list_empty(&cm_id_priv->work_list)) {
1024
+
work = list_first_entry(&cm_id_priv->work_list,
1025
+
struct iwcm_work, list);
1031
1026
list_del_init(&work->list);
1032
-
empty = list_empty(&cm_id_priv->work_list);
1033
1027
levent = work->event;
1034
1028
put_work(work);
1035
1029
spin_unlock_irqrestore(&cm_id_priv->lock, flags);
···
1034
1034
if (!test_bit(IWCM_F_DROP_EVENTS, &cm_id_priv->flags)) {
1035
1035
ret = process_event(cm_id_priv, &levent);
1036
1036
if (ret)
1037
-
destroy_cm_id(&cm_id_priv->id);
1037
+
WARN_ON_ONCE(destroy_cm_id(&cm_id_priv->id));
1038
1038
} else
1039
1039
pr_debug("dropping event %d\n", levent.event);
1040
1040
if (iwcm_deref_id(cm_id_priv))
1041
-
return;
1042
-
if (empty)
1043
1041
return;
1044
1042
spin_lock_irqsave(&cm_id_priv->lock, flags);
1045
1043
}
···
1091
1093
}
1092
1094
1093
1095
refcount_inc(&cm_id_priv->refcount);
1094
-
if (list_empty(&cm_id_priv->work_list)) {
1095
-
list_add_tail(&work->list, &cm_id_priv->work_list);
1096
-
queue_work(iwcm_wq, &work->work);
1097
-
} else
1098
-
list_add_tail(&work->list, &cm_id_priv->work_list);
1096
+
list_add_tail(&work->list, &cm_id_priv->work_list);
1097
+
queue_work(iwcm_wq, &work->work);
1099
1098
out:
1100
1099
spin_unlock_irqrestore(&cm_id_priv->lock, flags);
1101
1100
return ret;
+6
-3
drivers/infiniband/core/mad.c
+6
-3
drivers/infiniband/core/mad.c
···
2983
2983
if (ret)
2984
2984
goto error6;
2985
2985
}
2986
-
ret = create_mad_qp(&port_priv->qp_info[1], IB_QPT_GSI);
2987
-
if (ret)
2988
-
goto error7;
2986
+
2987
+
if (rdma_cap_ib_cm(device, port_num)) {
2988
+
ret = create_mad_qp(&port_priv->qp_info[1], IB_QPT_GSI);
2989
+
if (ret)
2990
+
goto error7;
2991
+
}
2989
2992
2990
2993
snprintf(name, sizeof(name), "ib_mad%u", port_num);
2991
2994
port_priv->wq = alloc_ordered_workqueue(name, WQ_MEM_RECLAIM);
+74
drivers/infiniband/core/nldev.c
+74
drivers/infiniband/core/nldev.c
···
167
167
[RDMA_NLDEV_ATTR_STAT_HWCOUNTER_DYNAMIC] = { .type = NLA_U8 },
168
168
[RDMA_NLDEV_SYS_ATTR_PRIVILEGED_QKEY_MODE] = { .type = NLA_U8 },
169
169
[RDMA_NLDEV_ATTR_DRIVER_DETAILS] = { .type = NLA_U8 },
170
+
[RDMA_NLDEV_ATTR_DEV_TYPE] = { .type = NLA_U8 },
171
+
[RDMA_NLDEV_ATTR_PARENT_NAME] = { .type = NLA_NUL_STRING },
172
+
[RDMA_NLDEV_ATTR_NAME_ASSIGN_TYPE] = { .type = NLA_U8 },
170
173
};
171
174
172
175
static int put_driver_name_print_type(struct sk_buff *msg, const char *name,
···
302
299
if (nla_put_u8(msg, RDMA_NLDEV_ATTR_DEV_NODE_TYPE, device->node_type))
303
300
return -EMSGSIZE;
304
301
if (nla_put_u8(msg, RDMA_NLDEV_ATTR_DEV_DIM, device->use_cq_dim))
302
+
return -EMSGSIZE;
303
+
304
+
if (device->type &&
305
+
nla_put_u8(msg, RDMA_NLDEV_ATTR_DEV_TYPE, device->type))
306
+
return -EMSGSIZE;
307
+
308
+
if (device->parent &&
309
+
nla_put_string(msg, RDMA_NLDEV_ATTR_PARENT_NAME,
310
+
dev_name(&device->parent->dev)))
311
+
return -EMSGSIZE;
312
+
313
+
if (nla_put_u8(msg, RDMA_NLDEV_ATTR_NAME_ASSIGN_TYPE,
314
+
device->name_assign_type))
305
315
return -EMSGSIZE;
306
316
307
317
/*
···
2564
2548
return ret;
2565
2549
}
2566
2550
2551
+
static int nldev_newdev(struct sk_buff *skb, struct nlmsghdr *nlh,
2552
+
struct netlink_ext_ack *extack)
2553
+
{
2554
+
struct nlattr *tb[RDMA_NLDEV_ATTR_MAX];
2555
+
enum rdma_nl_dev_type type;
2556
+
struct ib_device *parent;
2557
+
char name[IFNAMSIZ] = {};
2558
+
u32 parentid;
2559
+
int ret;
2560
+
2561
+
ret = nlmsg_parse(nlh, 0, tb, RDMA_NLDEV_ATTR_MAX - 1,
2562
+
nldev_policy, extack);
2563
+
if (ret || !tb[RDMA_NLDEV_ATTR_DEV_INDEX] ||
2564
+
!tb[RDMA_NLDEV_ATTR_DEV_NAME] || !tb[RDMA_NLDEV_ATTR_DEV_TYPE])
2565
+
return -EINVAL;
2566
+
2567
+
nla_strscpy(name, tb[RDMA_NLDEV_ATTR_DEV_NAME], sizeof(name));
2568
+
type = nla_get_u8(tb[RDMA_NLDEV_ATTR_DEV_TYPE]);
2569
+
parentid = nla_get_u32(tb[RDMA_NLDEV_ATTR_DEV_INDEX]);
2570
+
parent = ib_device_get_by_index(sock_net(skb->sk), parentid);
2571
+
if (!parent)
2572
+
return -EINVAL;
2573
+
2574
+
ret = ib_add_sub_device(parent, type, name);
2575
+
ib_device_put(parent);
2576
+
2577
+
return ret;
2578
+
}
2579
+
2580
+
static int nldev_deldev(struct sk_buff *skb, struct nlmsghdr *nlh,
2581
+
struct netlink_ext_ack *extack)
2582
+
{
2583
+
struct nlattr *tb[RDMA_NLDEV_ATTR_MAX];
2584
+
struct ib_device *device;
2585
+
u32 devid;
2586
+
int ret;
2587
+
2588
+
ret = nlmsg_parse(nlh, 0, tb, RDMA_NLDEV_ATTR_MAX - 1,
2589
+
nldev_policy, extack);
2590
+
if (ret || !tb[RDMA_NLDEV_ATTR_DEV_INDEX])
2591
+
return -EINVAL;
2592
+
2593
+
devid = nla_get_u32(tb[RDMA_NLDEV_ATTR_DEV_INDEX]);
2594
+
device = ib_device_get_by_index(sock_net(skb->sk), devid);
2595
+
if (!device)
2596
+
return -EINVAL;
2597
+
2598
+
return ib_del_sub_device_and_put(device);
2599
+
}
2600
+
2567
2601
static const struct rdma_nl_cbs nldev_cb_table[RDMA_NLDEV_NUM_OPS] = {
2568
2602
[RDMA_NLDEV_CMD_GET] = {
2569
2603
.doit = nldev_get_doit,
···
2711
2645
},
2712
2646
[RDMA_NLDEV_CMD_STAT_GET_STATUS] = {
2713
2647
.doit = nldev_stat_get_counter_status_doit,
2648
+
},
2649
+
[RDMA_NLDEV_CMD_NEWDEV] = {
2650
+
.doit = nldev_newdev,
2651
+
.flags = RDMA_NL_ADMIN_PERM,
2652
+
},
2653
+
[RDMA_NLDEV_CMD_DELDEV] = {
2654
+
.doit = nldev_deldev,
2655
+
.flags = RDMA_NL_ADMIN_PERM,
2714
2656
},
2715
2657
};
2716
2658
+17
-10
drivers/infiniband/core/user_mad.c
+17
-10
drivers/infiniband/core/user_mad.c
···
1321
1321
if (ret)
1322
1322
goto err_cdev;
1323
1323
1324
-
ib_umad_init_port_dev(&port->sm_dev, port, device);
1325
-
port->sm_dev.devt = base_issm;
1326
-
dev_set_name(&port->sm_dev, "issm%d", port->dev_num);
1327
-
cdev_init(&port->sm_cdev, &umad_sm_fops);
1328
-
port->sm_cdev.owner = THIS_MODULE;
1324
+
if (rdma_cap_ib_smi(device, port_num)) {
1325
+
ib_umad_init_port_dev(&port->sm_dev, port, device);
1326
+
port->sm_dev.devt = base_issm;
1327
+
dev_set_name(&port->sm_dev, "issm%d", port->dev_num);
1328
+
cdev_init(&port->sm_cdev, &umad_sm_fops);
1329
+
port->sm_cdev.owner = THIS_MODULE;
1329
1330
1330
-
ret = cdev_device_add(&port->sm_cdev, &port->sm_dev);
1331
-
if (ret)
1332
-
goto err_dev;
1331
+
ret = cdev_device_add(&port->sm_cdev, &port->sm_dev);
1332
+
if (ret)
1333
+
goto err_dev;
1334
+
}
1333
1335
1334
1336
return 0;
1335
1337
···
1347
1345
static void ib_umad_kill_port(struct ib_umad_port *port)
1348
1346
{
1349
1347
struct ib_umad_file *file;
1348
+
bool has_smi = false;
1350
1349
int id;
1351
1350
1352
-
cdev_device_del(&port->sm_cdev, &port->sm_dev);
1351
+
if (rdma_cap_ib_smi(port->ib_dev, port->port_num)) {
1352
+
cdev_device_del(&port->sm_cdev, &port->sm_dev);
1353
+
has_smi = true;
1354
+
}
1353
1355
cdev_device_del(&port->cdev, &port->dev);
1354
1356
1355
1357
mutex_lock(&port->file_mutex);
···
1379
1373
ida_free(&umad_ida, port->dev_num);
1380
1374
1381
1375
/* balances device_initialize() */
1382
-
put_device(&port->sm_dev);
1376
+
if (has_smi)
1377
+
put_device(&port->sm_dev);
1383
1378
put_device(&port->dev);
1384
1379
}
1385
1380
+1
-1
drivers/infiniband/core/uverbs_cmd.c
+1
-1
drivers/infiniband/core/uverbs_cmd.c
···
1051
1051
rdma_restrack_new(&cq->res, RDMA_RESTRACK_CQ);
1052
1052
rdma_restrack_set_name(&cq->res, NULL);
1053
1053
1054
-
ret = ib_dev->ops.create_cq(cq, &attr, &attrs->driver_udata);
1054
+
ret = ib_dev->ops.create_cq(cq, &attr, attrs);
1055
1055
if (ret)
1056
1056
goto err_free;
1057
1057
rdma_restrack_add(&cq->res);
+2
-1
drivers/infiniband/core/uverbs_main.c
+2
-1
drivers/infiniband/core/uverbs_main.c
···
1114
1114
struct ib_uverbs_device *uverbs_dev;
1115
1115
int ret;
1116
1116
1117
-
if (!device->ops.alloc_ucontext)
1117
+
if (!device->ops.alloc_ucontext ||
1118
+
device->type == RDMA_DEVICE_TYPE_SMI)
1118
1119
return -EOPNOTSUPP;
1119
1120
1120
1121
uverbs_dev = kzalloc(sizeof(*uverbs_dev), GFP_KERNEL);
+1
-1
drivers/infiniband/core/uverbs_std_types_cq.c
+1
-1
drivers/infiniband/core/uverbs_std_types_cq.c
+81
-1
drivers/infiniband/core/verbs.c
+81
-1
drivers/infiniband/core/verbs.c
···
1101
1101
1102
1102
/* Queue pairs */
1103
1103
1104
+
static void __ib_qp_event_handler(struct ib_event *event, void *context)
1105
+
{
1106
+
struct ib_qp *qp = event->element.qp;
1107
+
1108
+
if (event->event == IB_EVENT_QP_LAST_WQE_REACHED)
1109
+
complete(&qp->srq_completion);
1110
+
if (qp->registered_event_handler)
1111
+
qp->registered_event_handler(event, qp->qp_context);
1112
+
}
1113
+
1104
1114
static void __ib_shared_qp_event_handler(struct ib_event *event, void *context)
1105
1115
{
1106
1116
struct ib_qp *qp = context;
···
1231
1221
qp->qp_type = attr->qp_type;
1232
1222
qp->rwq_ind_tbl = attr->rwq_ind_tbl;
1233
1223
qp->srq = attr->srq;
1234
-
qp->event_handler = attr->event_handler;
1224
+
qp->event_handler = __ib_qp_event_handler;
1225
+
qp->registered_event_handler = attr->event_handler;
1235
1226
qp->port = attr->port_num;
1236
1227
qp->qp_context = attr->qp_context;
1237
1228
1238
1229
spin_lock_init(&qp->mr_lock);
1239
1230
INIT_LIST_HEAD(&qp->rdma_mrs);
1240
1231
INIT_LIST_HEAD(&qp->sig_mrs);
1232
+
init_completion(&qp->srq_completion);
1241
1233
1242
1234
qp->send_cq = attr->send_cq;
1243
1235
qp->recv_cq = attr->recv_cq;
···
2896
2884
wait_for_completion(&rdrain.done);
2897
2885
}
2898
2886
2887
+
/*
2888
+
* __ib_drain_srq() - Block until Last WQE Reached event arrives, or timeout
2889
+
* expires.
2890
+
* @qp: queue pair associated with SRQ to drain
2891
+
*
2892
+
* Quoting 10.3.1 Queue Pair and EE Context States:
2893
+
*
2894
+
* Note, for QPs that are associated with an SRQ, the Consumer should take the
2895
+
* QP through the Error State before invoking a Destroy QP or a Modify QP to the
2896
+
* Reset State. The Consumer may invoke the Destroy QP without first performing
2897
+
* a Modify QP to the Error State and waiting for the Affiliated Asynchronous
2898
+
* Last WQE Reached Event. However, if the Consumer does not wait for the
2899
+
* Affiliated Asynchronous Last WQE Reached Event, then WQE and Data Segment
2900
+
* leakage may occur. Therefore, it is good programming practice to tear down a
2901
+
* QP that is associated with an SRQ by using the following process:
2902
+
*
2903
+
* - Put the QP in the Error State
2904
+
* - Wait for the Affiliated Asynchronous Last WQE Reached Event;
2905
+
* - either:
2906
+
* drain the CQ by invoking the Poll CQ verb and either wait for CQ
2907
+
* to be empty or the number of Poll CQ operations has exceeded
2908
+
* CQ capacity size;
2909
+
* - or
2910
+
* post another WR that completes on the same CQ and wait for this
2911
+
* WR to return as a WC;
2912
+
* - and then invoke a Destroy QP or Reset QP.
2913
+
*
2914
+
* We use the first option.
2915
+
*/
2916
+
static void __ib_drain_srq(struct ib_qp *qp)
2917
+
{
2918
+
struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
2919
+
struct ib_cq *cq;
2920
+
int n, polled = 0;
2921
+
int ret;
2922
+
2923
+
if (!qp->srq) {
2924
+
WARN_ONCE(1, "QP 0x%p is not associated with SRQ\n", qp);
2925
+
return;
2926
+
}
2927
+
2928
+
ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
2929
+
if (ret) {
2930
+
WARN_ONCE(ret, "failed to drain shared recv queue: %d\n", ret);
2931
+
return;
2932
+
}
2933
+
2934
+
if (ib_srq_has_cq(qp->srq->srq_type)) {
2935
+
cq = qp->srq->ext.cq;
2936
+
} else if (qp->recv_cq) {
2937
+
cq = qp->recv_cq;
2938
+
} else {
2939
+
WARN_ONCE(1, "QP 0x%p has no CQ associated with SRQ\n", qp);
2940
+
return;
2941
+
}
2942
+
2943
+
if (wait_for_completion_timeout(&qp->srq_completion, 60 * HZ) > 0) {
2944
+
while (polled != cq->cqe) {
2945
+
n = ib_process_cq_direct(cq, cq->cqe - polled);
2946
+
if (!n)
2947
+
return;
2948
+
polled += n;
2949
+
}
2950
+
}
2951
+
}
2952
+
2899
2953
/**
2900
2954
* ib_drain_sq() - Block until all SQ CQEs have been consumed by the
2901
2955
* application.
···
3040
2962
ib_drain_sq(qp);
3041
2963
if (!qp->srq)
3042
2964
ib_drain_rq(qp);
2965
+
else
2966
+
__ib_drain_srq(qp);
3043
2967
}
3044
2968
EXPORT_SYMBOL(ib_drain_qp);
3045
2969
+9
-3
drivers/infiniband/hw/bnxt_re/bnxt_re.h
+9
-3
drivers/infiniband/hw/bnxt_re/bnxt_re.h
···
129
129
#define BNXT_RE_PACING_ALARM_TH_MULTIPLE 2 /* Multiple of pacing algo threshold */
130
130
/* Default do_pacing value when there is no congestion */
131
131
#define BNXT_RE_DBR_DO_PACING_NO_CONGESTION 0x7F /* 1 in 512 probability */
132
-
#define BNXT_RE_DB_FIFO_ROOM_MASK 0x1FFF8000
133
-
#define BNXT_RE_MAX_FIFO_DEPTH 0x2c00
134
-
#define BNXT_RE_DB_FIFO_ROOM_SHIFT 15
132
+
133
+
#define BNXT_RE_MAX_FIFO_DEPTH_P5 0x2c00
134
+
#define BNXT_RE_MAX_FIFO_DEPTH_P7 0x8000
135
+
136
+
#define BNXT_RE_MAX_FIFO_DEPTH(ctx) \
137
+
(bnxt_qplib_is_chip_gen_p7((ctx)) ? \
138
+
BNXT_RE_MAX_FIFO_DEPTH_P7 :\
139
+
BNXT_RE_MAX_FIFO_DEPTH_P5)
140
+
135
141
#define BNXT_RE_GRC_FIFO_REG_BASE 0x2000
136
142
137
143
#define MAX_CQ_HASH_BITS (16)
+9
-5
drivers/infiniband/hw/bnxt_re/ib_verbs.c
+9
-5
drivers/infiniband/hw/bnxt_re/ib_verbs.c
···
2479
2479
break;
2480
2480
case IB_WR_SEND_WITH_IMM:
2481
2481
wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2482
-
wqe->send.imm_data = wr->ex.imm_data;
2482
+
wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data);
2483
2483
break;
2484
2484
case IB_WR_SEND_WITH_INV:
2485
2485
wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
···
2509
2509
break;
2510
2510
case IB_WR_RDMA_WRITE_WITH_IMM:
2511
2511
wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2512
-
wqe->rdma.imm_data = wr->ex.imm_data;
2512
+
wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data);
2513
2513
break;
2514
2514
case IB_WR_RDMA_READ:
2515
2515
wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
···
2948
2948
}
2949
2949
2950
2950
int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
2951
-
struct ib_udata *udata)
2951
+
struct uverbs_attr_bundle *attrs)
2952
2952
{
2953
2953
struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
2954
2954
struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
2955
+
struct ib_udata *udata = &attrs->driver_udata;
2955
2956
struct bnxt_re_ucontext *uctx =
2956
2957
rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
2957
2958
struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
···
3582
3581
wc->byte_len = orig_cqe->length;
3583
3582
wc->qp = &gsi_qp->ib_qp;
3584
3583
3585
-
wc->ex.imm_data = orig_cqe->immdata;
3584
+
wc->ex.imm_data = cpu_to_be32(le32_to_cpu(orig_cqe->immdata));
3586
3585
wc->src_qp = orig_cqe->src_qp;
3587
3586
memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3588
3587
if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
···
3727
3726
(unsigned long)(cqe->qp_handle),
3728
3727
struct bnxt_re_qp, qplib_qp);
3729
3728
wc->qp = &qp->ib_qp;
3730
-
wc->ex.imm_data = cqe->immdata;
3729
+
wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immdata));
3731
3730
wc->src_qp = cqe->src_qp;
3732
3731
memcpy(wc->smac, cqe->smac, ETH_ALEN);
3733
3732
wc->port_num = 1;
···
4201
4200
uctx->shpage_mmap = &entry->rdma_entry;
4202
4201
if (rdev->pacing.dbr_pacing)
4203
4202
resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED;
4203
+
4204
+
if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2))
4205
+
resp.comp_mask |= BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED;
4204
4206
4205
4207
if (udata->inlen >= sizeof(ureq)) {
4206
4208
rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq)));
+1
-1
drivers/infiniband/hw/bnxt_re/ib_verbs.h
+1
-1
drivers/infiniband/hw/bnxt_re/ib_verbs.h
···
221
221
int bnxt_re_post_recv(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
222
222
const struct ib_recv_wr **bad_recv_wr);
223
223
int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
224
-
struct ib_udata *udata);
224
+
struct uverbs_attr_bundle *attrs);
225
225
int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata);
226
226
int bnxt_re_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
227
227
int bnxt_re_poll_cq(struct ib_cq *cq, int num_entries, struct ib_wc *wc);
+56
-22
drivers/infiniband/hw/bnxt_re/main.c
+56
-22
drivers/infiniband/hw/bnxt_re/main.c
···
423
423
struct hwrm_func_qcaps_input req = {};
424
424
struct bnxt_qplib_chip_ctx *cctx;
425
425
struct bnxt_fw_msg fw_msg = {};
426
+
u32 flags_ext2;
426
427
int rc;
427
428
428
429
cctx = rdev->chip_ctx;
···
437
436
return rc;
438
437
cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE;
439
438
440
-
cctx->modes.dbr_pacing =
441
-
le32_to_cpu(resp.flags_ext2) &
442
-
FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED;
439
+
flags_ext2 = le32_to_cpu(resp.flags_ext2);
440
+
cctx->modes.dbr_pacing = flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED ||
441
+
flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED;
443
442
return 0;
444
443
}
445
444
446
445
static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev)
447
446
{
447
+
struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
448
448
struct hwrm_func_dbr_pacing_qcfg_output resp = {};
449
449
struct hwrm_func_dbr_pacing_qcfg_input req = {};
450
450
struct bnxt_en_dev *en_dev = rdev->en_dev;
···
467
465
cctx->dbr_stat_db_fifo =
468
466
le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
469
467
~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK;
468
+
469
+
pacing_data->fifo_max_depth = le32_to_cpu(resp.dbr_stat_db_max_fifo_depth);
470
+
if (!pacing_data->fifo_max_depth)
471
+
pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH(cctx);
472
+
pacing_data->fifo_room_mask = le32_to_cpu(resp.dbr_stat_db_fifo_reg_fifo_room_mask);
473
+
pacing_data->fifo_room_shift = resp.dbr_stat_db_fifo_reg_fifo_room_shift;
474
+
470
475
return 0;
471
476
}
472
477
···
488
479
pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
489
480
}
490
481
482
+
static u32 __get_fifo_occupancy(struct bnxt_re_dev *rdev)
483
+
{
484
+
struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
485
+
u32 read_val, fifo_occup;
486
+
487
+
read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
488
+
fifo_occup = pacing_data->fifo_max_depth -
489
+
((read_val & pacing_data->fifo_room_mask) >>
490
+
pacing_data->fifo_room_shift);
491
+
return fifo_occup;
492
+
}
493
+
494
+
static bool is_dbr_fifo_full(struct bnxt_re_dev *rdev)
495
+
{
496
+
u32 max_occup, fifo_occup;
497
+
498
+
fifo_occup = __get_fifo_occupancy(rdev);
499
+
max_occup = BNXT_RE_MAX_FIFO_DEPTH(rdev->chip_ctx) - 1;
500
+
if (fifo_occup == max_occup)
501
+
return true;
502
+
503
+
return false;
504
+
}
505
+
491
506
static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev)
492
507
{
493
-
u32 read_val, fifo_occup;
508
+
struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
509
+
u32 fifo_occup;
494
510
495
511
/* loop shouldn't run infintely as the occupancy usually goes
496
512
* below pacing algo threshold as soon as pacing kicks in.
497
513
*/
498
514
while (1) {
499
-
read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
500
-
fifo_occup = BNXT_RE_MAX_FIFO_DEPTH -
501
-
((read_val & BNXT_RE_DB_FIFO_ROOM_MASK) >>
502
-
BNXT_RE_DB_FIFO_ROOM_SHIFT);
515
+
fifo_occup = __get_fifo_occupancy(rdev);
503
516
/* Fifo occupancy cannot be greater the MAX FIFO depth */
504
-
if (fifo_occup > BNXT_RE_MAX_FIFO_DEPTH)
517
+
if (fifo_occup > pacing_data->fifo_max_depth)
505
518
break;
506
519
507
-
if (fifo_occup < rdev->qplib_res.pacing_data->pacing_th)
520
+
if (fifo_occup < pacing_data->pacing_th)
508
521
break;
509
522
}
510
523
}
···
577
546
struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
578
547
dbq_pacing_work.work);
579
548
struct bnxt_qplib_db_pacing_data *pacing_data;
580
-
u32 read_val, fifo_occup;
549
+
u32 fifo_occup;
581
550
582
551
if (!mutex_trylock(&rdev->pacing.dbq_lock))
583
552
return;
584
553
585
554
pacing_data = rdev->qplib_res.pacing_data;
586
-
read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
587
-
fifo_occup = BNXT_RE_MAX_FIFO_DEPTH -
588
-
((read_val & BNXT_RE_DB_FIFO_ROOM_MASK) >>
589
-
BNXT_RE_DB_FIFO_ROOM_SHIFT);
555
+
fifo_occup = __get_fifo_occupancy(rdev);
590
556
591
557
if (fifo_occup > pacing_data->pacing_th)
592
558
goto restart_timer;
···
622
594
* Increase the alarm_th to max so that other user lib instances do not
623
595
* keep alerting the driver.
624
596
*/
625
-
pacing_data->alarm_th = BNXT_RE_MAX_FIFO_DEPTH;
597
+
pacing_data->alarm_th = pacing_data->fifo_max_depth;
626
598
pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING;
627
599
cancel_work_sync(&rdev->dbq_fifo_check_work);
628
600
schedule_work(&rdev->dbq_fifo_check_work);
···
631
603
632
604
static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev)
633
605
{
634
-
if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev))
635
-
return -EIO;
636
-
637
606
/* Allocate a page for app use */
638
607
rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL);
639
608
if (!rdev->pacing.dbr_page)
···
638
613
639
614
memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE);
640
615
rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page;
616
+
617
+
if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) {
618
+
free_page((u64)rdev->pacing.dbr_page);
619
+
rdev->pacing.dbr_page = NULL;
620
+
return -EIO;
621
+
}
641
622
642
623
/* MAP HW window 2 for reading db fifo depth */
643
624
writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK,
···
654
623
rdev->pacing.dbr_bar_addr =
655
624
pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off;
656
625
626
+
if (is_dbr_fifo_full(rdev)) {
627
+
free_page((u64)rdev->pacing.dbr_page);
628
+
rdev->pacing.dbr_page = NULL;
629
+
return -EIO;
630
+
}
631
+
657
632
rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD;
658
633
rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME;
659
634
rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION;
660
635
rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing;
661
-
rdev->qplib_res.pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH;
662
-
rdev->qplib_res.pacing_data->fifo_room_mask = BNXT_RE_DB_FIFO_ROOM_MASK;
663
-
rdev->qplib_res.pacing_data->fifo_room_shift = BNXT_RE_DB_FIFO_ROOM_SHIFT;
664
636
rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off;
665
637
bnxt_re_set_default_pacing_data(rdev);
666
638
/* Initialize worker for DBR Pacing */
+6
-6
drivers/infiniband/hw/bnxt_re/qplib_fp.c
+6
-6
drivers/infiniband/hw/bnxt_re/qplib_fp.c
···
984
984
u16 nsge;
985
985
986
986
if (res->dattr)
987
-
qp->dev_cap_flags = res->dattr->dev_cap_flags;
987
+
qp->is_host_msn_tbl = _is_host_msn_table(res->dattr->dev_cap_flags2);
988
988
989
989
sq->dbinfo.flags = 0;
990
990
bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
···
1002
1002
sizeof(struct sq_psn_search_ext) :
1003
1003
sizeof(struct sq_psn_search);
1004
1004
1005
-
if (BNXT_RE_HW_RETX(qp->dev_cap_flags)) {
1005
+
if (qp->is_host_msn_tbl) {
1006
1006
psn_sz = sizeof(struct sq_msn_search);
1007
1007
qp->msn = 0;
1008
1008
}
···
1016
1016
hwq_attr.aux_depth = psn_sz ? bnxt_qplib_set_sq_size(sq, qp->wqe_mode)
1017
1017
: 0;
1018
1018
/* Update msn tbl size */
1019
-
if (BNXT_RE_HW_RETX(qp->dev_cap_flags) && psn_sz) {
1019
+
if (qp->is_host_msn_tbl && psn_sz) {
1020
1020
hwq_attr.aux_depth = roundup_pow_of_two(bnxt_qplib_set_sq_size(sq, qp->wqe_mode));
1021
1021
qp->msn_tbl_sz = hwq_attr.aux_depth;
1022
1022
qp->msn = 0;
···
1637
1637
if (!swq->psn_search)
1638
1638
return;
1639
1639
/* Handle MSN differently on cap flags */
1640
-
if (BNXT_RE_HW_RETX(qp->dev_cap_flags)) {
1640
+
if (qp->is_host_msn_tbl) {
1641
1641
bnxt_qplib_fill_msn_search(qp, wqe, swq);
1642
1642
return;
1643
1643
}
···
1819
1819
}
1820
1820
1821
1821
swq = bnxt_qplib_get_swqe(sq, &wqe_idx);
1822
-
bnxt_qplib_pull_psn_buff(qp, sq, swq, BNXT_RE_HW_RETX(qp->dev_cap_flags));
1822
+
bnxt_qplib_pull_psn_buff(qp, sq, swq, qp->is_host_msn_tbl);
1823
1823
1824
1824
idx = 0;
1825
1825
swq->slot_idx = hwq->prod;
···
2009
2009
rc = -EINVAL;
2010
2010
goto done;
2011
2011
}
2012
-
if (!BNXT_RE_HW_RETX(qp->dev_cap_flags) || msn_update) {
2012
+
if (!qp->is_host_msn_tbl || msn_update) {
2013
2013
swq->next_psn = sq->psn & BTH_PSN_MASK;
2014
2014
bnxt_qplib_fill_psn_search(qp, wqe, swq);
2015
2015
}
+4
-4
drivers/infiniband/hw/bnxt_re/qplib_fp.h
+4
-4
drivers/infiniband/hw/bnxt_re/qplib_fp.h
···
164
164
/* Send, with imm, inval key */
165
165
struct {
166
166
union {
167
-
__be32 imm_data;
167
+
u32 imm_data;
168
168
u32 inv_key;
169
169
};
170
170
u32 q_key;
···
182
182
/* RDMA write, with imm, read */
183
183
struct {
184
184
union {
185
-
__be32 imm_data;
185
+
u32 imm_data;
186
186
u32 inv_key;
187
187
};
188
188
u64 remote_va;
···
340
340
struct list_head rq_flush;
341
341
u32 msn;
342
342
u32 msn_tbl_sz;
343
-
u16 dev_cap_flags;
343
+
bool is_host_msn_tbl;
344
344
};
345
345
346
346
#define BNXT_QPLIB_MAX_CQE_ENTRY_SIZE sizeof(struct cq_base)
···
389
389
u16 cfa_meta;
390
390
u64 wr_id;
391
391
union {
392
-
__be32 immdata;
392
+
__le32 immdata;
393
393
u32 invrkey;
394
394
};
395
395
u64 qp_handle;
+6
drivers/infiniband/hw/bnxt_re/qplib_res.h
+6
drivers/infiniband/hw/bnxt_re/qplib_res.h
···
554
554
555
555
#define BNXT_RE_HW_RETX(a) _is_hw_retx_supported((a))
556
556
557
+
static inline bool _is_host_msn_table(u16 dev_cap_ext_flags2)
558
+
{
559
+
return (dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK) ==
560
+
CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE;
561
+
}
562
+
557
563
static inline u8 bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx *cctx)
558
564
{
559
565
return cctx->modes.dbr_pacing;
+1
drivers/infiniband/hw/bnxt_re/qplib_sp.c
+1
drivers/infiniband/hw/bnxt_re/qplib_sp.c
···
156
156
(0x01 << RCFW_DBR_BASE_PAGE_SHIFT);
157
157
attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED;
158
158
attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags);
159
+
attr->dev_cap_flags2 = le16_to_cpu(sb->dev_cap_ext_flags_2);
159
160
160
161
bnxt_qplib_query_version(rcfw, attr->fw_ver);
161
162
+1
drivers/infiniband/hw/bnxt_re/qplib_sp.h
+1
drivers/infiniband/hw/bnxt_re/qplib_sp.h
+29
-1
drivers/infiniband/hw/bnxt_re/roce_hsi.h
+29
-1
drivers/infiniband/hw/bnxt_re/roce_hsi.h
···
2157
2157
__le32 tqm_alloc_reqs[12];
2158
2158
__le32 max_dpi;
2159
2159
u8 max_sge_var_wqe;
2160
-
u8 reserved_8;
2160
+
u8 dev_cap_ext_flags;
2161
+
#define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED 0x1UL
2162
+
#define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED 0x2UL
2163
+
#define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED 0x4UL
2164
+
#define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED 0x8UL
2165
+
#define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED 0x10UL
2166
+
#define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED 0x20UL
2167
+
#define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED 0x40UL
2168
+
#define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED 0x80UL
2161
2169
__le16 max_inline_data_var_wqe;
2170
+
__le32 start_qid;
2171
+
u8 max_msn_table_size;
2172
+
u8 reserved8_1;
2173
+
__le16 dev_cap_ext_flags_2;
2174
+
#define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED 0x1UL
2175
+
#define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED 0x2UL
2176
+
#define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED 0x4UL
2177
+
#define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED 0x8UL
2178
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK 0x30UL
2179
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_SFT 4
2180
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (0x0UL << 4)
2181
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (0x1UL << 4)
2182
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (0x2UL << 4)
2183
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST \
2184
+
CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE
2185
+
__le16 max_xp_qp_size;
2186
+
__le16 create_qp_batch_size;
2187
+
__le16 destroy_qp_batch_size;
2188
+
__le16 reserved16;
2189
+
__le64 reserved64;
2162
2190
};
2163
2191
2164
2192
/* cmdq_set_func_resources (size:448b/56B) */
+2
-1
drivers/infiniband/hw/cxgb4/cq.c
+2
-1
drivers/infiniband/hw/cxgb4/cq.c
···
995
995
}
996
996
997
997
int c4iw_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
998
-
struct ib_udata *udata)
998
+
struct uverbs_attr_bundle *attrs)
999
999
{
1000
+
struct ib_udata *udata = &attrs->driver_udata;
1000
1001
struct ib_device *ibdev = ibcq->device;
1001
1002
int entries = attr->cqe;
1002
1003
int vector = attr->comp_vector;
+1
-1
drivers/infiniband/hw/cxgb4/iw_cxgb4.h
+1
-1
drivers/infiniband/hw/cxgb4/iw_cxgb4.h
···
978
978
int c4iw_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
979
979
void c4iw_cq_rem_ref(struct c4iw_cq *chp);
980
980
int c4iw_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
981
-
struct ib_udata *udata);
981
+
struct uverbs_attr_bundle *attrs);
982
982
int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
983
983
int c4iw_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *attr,
984
984
enum ib_srq_attr_mask srq_attr_mask,
+1
-1
drivers/infiniband/hw/efa/efa.h
+1
-1
drivers/infiniband/hw/efa/efa.h
···
161
161
struct ib_udata *udata);
162
162
int efa_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata);
163
163
int efa_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
164
-
struct ib_udata *udata);
164
+
struct uverbs_attr_bundle *attrs);
165
165
struct ib_mr *efa_reg_mr(struct ib_pd *ibpd, u64 start, u64 length,
166
166
u64 virt_addr, int access_flags,
167
167
struct ib_udata *udata);
+17
-13
drivers/infiniband/hw/efa/efa_com.c
+17
-13
drivers/infiniband/hw/efa/efa_com.c
···
1
1
// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
2
/*
3
-
* Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved.
3
+
* Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved.
4
4
*/
5
5
6
6
#include "efa_com.h"
···
406
406
return comp_ctx;
407
407
}
408
408
409
-
static void efa_com_handle_single_admin_completion(struct efa_com_admin_queue *aq,
410
-
struct efa_admin_acq_entry *cqe)
409
+
static int efa_com_handle_single_admin_completion(struct efa_com_admin_queue *aq,
410
+
struct efa_admin_acq_entry *cqe)
411
411
{
412
412
struct efa_comp_ctx *comp_ctx;
413
413
u16 cmd_id;
···
416
416
EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID);
417
417
418
418
comp_ctx = efa_com_get_comp_ctx(aq, cmd_id, false);
419
-
if (!comp_ctx) {
419
+
if (comp_ctx->status != EFA_CMD_SUBMITTED) {
420
420
ibdev_err(aq->efa_dev,
421
-
"comp_ctx is NULL. Changing the admin queue running state\n");
422
-
clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
423
-
return;
421
+
"Received completion with unexpected command id[%d], sq producer: %d, sq consumer: %d, cq consumer: %d\n",
422
+
cmd_id, aq->sq.pc, aq->sq.cc, aq->cq.cc);
423
+
return -EINVAL;
424
424
}
425
425
426
426
comp_ctx->status = EFA_CMD_COMPLETED;
···
428
428
429
429
if (!test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state))
430
430
complete(&comp_ctx->wait_event);
431
+
432
+
return 0;
431
433
}
432
434
433
435
static void efa_com_handle_admin_completion(struct efa_com_admin_queue *aq)
434
436
{
435
437
struct efa_admin_acq_entry *cqe;
436
438
u16 queue_size_mask;
437
-
u16 comp_num = 0;
439
+
u16 comp_cmds = 0;
438
440
u8 phase;
441
+
int err;
439
442
u16 ci;
440
443
441
444
queue_size_mask = aq->depth - 1;
···
456
453
* phase bit was validated
457
454
*/
458
455
dma_rmb();
459
-
efa_com_handle_single_admin_completion(aq, cqe);
456
+
err = efa_com_handle_single_admin_completion(aq, cqe);
457
+
if (!err)
458
+
comp_cmds++;
460
459
460
+
aq->cq.cc++;
461
461
ci++;
462
-
comp_num++;
463
462
if (ci == aq->depth) {
464
463
ci = 0;
465
464
phase = !phase;
···
470
465
cqe = &aq->cq.entries[ci];
471
466
}
472
467
473
-
aq->cq.cc += comp_num;
474
468
aq->cq.phase = phase;
475
-
aq->sq.cc += comp_num;
476
-
atomic64_add(comp_num, &aq->stats.completed_cmd);
469
+
aq->sq.cc += comp_cmds;
470
+
atomic64_add(comp_cmds, &aq->stats.completed_cmd);
477
471
}
478
472
479
473
static int efa_com_comp_status_to_errno(u8 comp_status)
+24
-8
drivers/infiniband/hw/efa/efa_main.c
+24
-8
drivers/infiniband/hw/efa/efa_main.c
···
16
16
#define PCI_DEV_ID_EFA0_VF 0xefa0
17
17
#define PCI_DEV_ID_EFA1_VF 0xefa1
18
18
#define PCI_DEV_ID_EFA2_VF 0xefa2
19
+
#define PCI_DEV_ID_EFA3_VF 0xefa3
19
20
20
21
static const struct pci_device_id efa_pci_tbl[] = {
21
22
{ PCI_VDEVICE(AMAZON, PCI_DEV_ID_EFA0_VF) },
22
23
{ PCI_VDEVICE(AMAZON, PCI_DEV_ID_EFA1_VF) },
23
24
{ PCI_VDEVICE(AMAZON, PCI_DEV_ID_EFA2_VF) },
25
+
{ PCI_VDEVICE(AMAZON, PCI_DEV_ID_EFA3_VF) },
24
26
{ }
25
27
};
26
28
···
192
190
{
193
191
u8 db_bar_idx = dev->dev_attr.db_bar;
194
192
struct pci_dev *pdev = dev->pdev;
195
-
int bars;
193
+
int pci_mem_bars;
194
+
int db_bar;
196
195
int err;
197
196
198
-
if (!(BIT(db_bar_idx) & EFA_BASE_BAR_MASK)) {
199
-
bars = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(db_bar_idx);
197
+
db_bar = BIT(db_bar_idx);
198
+
if (!(db_bar & EFA_BASE_BAR_MASK)) {
199
+
pci_mem_bars = pci_select_bars(pdev, IORESOURCE_MEM);
200
+
if (db_bar & ~pci_mem_bars) {
201
+
dev_err(&pdev->dev,
202
+
"Doorbells BAR unavailable. Requested %#x, available %#x\n",
203
+
db_bar, pci_mem_bars);
204
+
return -ENODEV;
205
+
}
200
206
201
-
err = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME);
207
+
err = pci_request_selected_regions(pdev, db_bar, DRV_MODULE_NAME);
202
208
if (err) {
203
-
dev_err(&dev->pdev->dev,
209
+
dev_err(&pdev->dev,
204
210
"pci_request_selected_regions for bar %d failed %d\n",
205
211
db_bar_idx, err);
206
212
return err;
···
541
531
{
542
532
struct efa_com_dev *edev;
543
533
struct efa_dev *dev;
544
-
int bars;
534
+
int pci_mem_bars;
545
535
int err;
546
536
547
537
err = pci_enable_device_mem(pdev);
···
566
556
dev->pdev = pdev;
567
557
xa_init(&dev->cqs_xa);
568
558
569
-
bars = pci_select_bars(pdev, IORESOURCE_MEM) & EFA_BASE_BAR_MASK;
570
-
err = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME);
559
+
pci_mem_bars = pci_select_bars(pdev, IORESOURCE_MEM);
560
+
if (EFA_BASE_BAR_MASK & ~pci_mem_bars) {
561
+
dev_err(&pdev->dev, "BARs unavailable. Requested %#x, available %#x\n",
562
+
(int)EFA_BASE_BAR_MASK, pci_mem_bars);
563
+
err = -ENODEV;
564
+
goto err_ibdev_destroy;
565
+
}
566
+
err = pci_request_selected_regions(pdev, EFA_BASE_BAR_MASK, DRV_MODULE_NAME);
571
567
if (err) {
572
568
dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n",
573
569
err);
+3
-6
drivers/infiniband/hw/efa/efa_verbs.c
+3
-6
drivers/infiniband/hw/efa/efa_verbs.c
···
26
26
EFA_MMAP_IO_NC,
27
27
};
28
28
29
-
#define EFA_AENQ_ENABLED_GROUPS \
30
-
(BIT(EFA_ADMIN_FATAL_ERROR) | BIT(EFA_ADMIN_WARNING) | \
31
-
BIT(EFA_ADMIN_NOTIFICATION) | BIT(EFA_ADMIN_KEEP_ALIVE))
32
-
33
29
struct efa_user_mmap_entry {
34
30
struct rdma_user_mmap_entry rdma_entry;
35
31
u64 address;
···
520
524
521
525
address = dev->mem_bar_addr + resp->llq_desc_offset;
522
526
length = PAGE_ALIGN(params->sq_ring_size_in_bytes +
523
-
(resp->llq_desc_offset & ~PAGE_MASK));
527
+
offset_in_page(resp->llq_desc_offset));
524
528
525
529
qp->llq_desc_mmap_entry =
526
530
efa_user_mmap_entry_insert(&ucontext->ibucontext,
···
1080
1084
}
1081
1085
1082
1086
int efa_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1083
-
struct ib_udata *udata)
1087
+
struct uverbs_attr_bundle *attrs)
1084
1088
{
1089
+
struct ib_udata *udata = &attrs->driver_udata;
1085
1090
struct efa_ucontext *ucontext = rdma_udata_to_drv_context(
1086
1091
udata, struct efa_ucontext, ibucontext);
1087
1092
struct efa_com_create_cq_params params = {};
+2
-1
drivers/infiniband/hw/erdma/erdma_verbs.c
+2
-1
drivers/infiniband/hw/erdma/erdma_verbs.c
···
1628
1628
}
1629
1629
1630
1630
int erdma_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1631
-
struct ib_udata *udata)
1631
+
struct uverbs_attr_bundle *attrs)
1632
1632
{
1633
+
struct ib_udata *udata = &attrs->driver_udata;
1633
1634
struct erdma_cq *cq = to_ecq(ibcq);
1634
1635
struct erdma_dev *dev = to_edev(ibcq->device);
1635
1636
unsigned int depth = attr->cqe;
+1
-1
drivers/infiniband/hw/erdma/erdma_verbs.h
+1
-1
drivers/infiniband/hw/erdma/erdma_verbs.h
···
329
329
int erdma_get_port_immutable(struct ib_device *dev, u32 port,
330
330
struct ib_port_immutable *ib_port_immutable);
331
331
int erdma_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
332
-
struct ib_udata *data);
332
+
struct uverbs_attr_bundle *attrs);
333
333
int erdma_query_port(struct ib_device *dev, u32 port,
334
334
struct ib_port_attr *attr);
335
335
int erdma_query_gid(struct ib_device *dev, u32 port, int idx,
+15
-15
drivers/infiniband/hw/hfi1/chip.c
+15
-15
drivers/infiniband/hw/hfi1/chip.c
···
251
251
/*
252
252
* CCE Error flags.
253
253
*/
254
-
static struct flag_table cce_err_status_flags[] = {
254
+
static const struct flag_table cce_err_status_flags[] = {
255
255
/* 0*/ FLAG_ENTRY0("CceCsrParityErr",
256
256
CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
257
257
/* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr",
···
341
341
* Misc Error flags
342
342
*/
343
343
#define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
344
-
static struct flag_table misc_err_status_flags[] = {
344
+
static const struct flag_table misc_err_status_flags[] = {
345
345
/* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
346
346
/* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
347
347
/* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
···
360
360
/*
361
361
* TXE PIO Error flags and consequences
362
362
*/
363
-
static struct flag_table pio_err_status_flags[] = {
363
+
static const struct flag_table pio_err_status_flags[] = {
364
364
/* 0*/ FLAG_ENTRY("PioWriteBadCtxt",
365
365
SEC_WRITE_DROPPED,
366
366
SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
···
502
502
/*
503
503
* TXE SDMA Error flags
504
504
*/
505
-
static struct flag_table sdma_err_status_flags[] = {
505
+
static const struct flag_table sdma_err_status_flags[] = {
506
506
/* 0*/ FLAG_ENTRY0("SDmaRpyTagErr",
507
507
SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
508
508
/* 1*/ FLAG_ENTRY0("SDmaCsrParityErr",
···
530
530
* TXE Egress Error flags
531
531
*/
532
532
#define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
533
-
static struct flag_table egress_err_status_flags[] = {
533
+
static const struct flag_table egress_err_status_flags[] = {
534
534
/* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
535
535
/* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
536
536
/* 2 reserved */
···
631
631
* TXE Egress Error Info flags
632
632
*/
633
633
#define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
634
-
static struct flag_table egress_err_info_flags[] = {
634
+
static const struct flag_table egress_err_info_flags[] = {
635
635
/* 0*/ FLAG_ENTRY0("Reserved", 0ull),
636
636
/* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)),
637
637
/* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
···
680
680
* TXE Send error flags
681
681
*/
682
682
#define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
683
-
static struct flag_table send_err_status_flags[] = {
683
+
static const struct flag_table send_err_status_flags[] = {
684
684
/* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
685
685
/* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
686
686
/* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
···
689
689
/*
690
690
* TXE Send Context Error flags and consequences
691
691
*/
692
-
static struct flag_table sc_err_status_flags[] = {
692
+
static const struct flag_table sc_err_status_flags[] = {
693
693
/* 0*/ FLAG_ENTRY("InconsistentSop",
694
694
SEC_PACKET_DROPPED | SEC_SC_HALTED,
695
695
SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
···
712
712
* RXE Receive Error flags
713
713
*/
714
714
#define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
715
-
static struct flag_table rxe_err_status_flags[] = {
715
+
static const struct flag_table rxe_err_status_flags[] = {
716
716
/* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
717
717
/* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
718
718
/* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
···
847
847
* DCC Error Flags
848
848
*/
849
849
#define DCCE(name) DCC_ERR_FLG_##name##_SMASK
850
-
static struct flag_table dcc_err_flags[] = {
850
+
static const struct flag_table dcc_err_flags[] = {
851
851
FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
852
852
FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
853
853
FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
···
900
900
* LCB error flags
901
901
*/
902
902
#define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
903
-
static struct flag_table lcb_err_flags[] = {
903
+
static const struct flag_table lcb_err_flags[] = {
904
904
/* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
905
905
/* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
906
906
/* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
···
943
943
* DC8051 Error Flags
944
944
*/
945
945
#define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
946
-
static struct flag_table dc8051_err_flags[] = {
946
+
static const struct flag_table dc8051_err_flags[] = {
947
947
FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
948
948
FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
949
949
FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
···
962
962
*
963
963
* Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
964
964
*/
965
-
static struct flag_table dc8051_info_err_flags[] = {
965
+
static const struct flag_table dc8051_info_err_flags[] = {
966
966
FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED),
967
967
FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME),
968
968
FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET),
···
986
986
*
987
987
* Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
988
988
*/
989
-
static struct flag_table dc8051_info_host_msg_flags[] = {
989
+
static const struct flag_table dc8051_info_host_msg_flags[] = {
990
990
FLAG_ENTRY0("Host request done", 0x0001),
991
991
FLAG_ENTRY0("BC PWR_MGM message", 0x0002),
992
992
FLAG_ENTRY0("BC SMA message", 0x0004),
···
5275
5275
* the buffer. End in '*' if the buffer is too short.
5276
5276
*/
5277
5277
static char *flag_string(char *buf, int buf_len, u64 flags,
5278
-
struct flag_table *table, int table_size)
5278
+
const struct flag_table *table, int table_size)
5279
5279
{
5280
5280
char extra[32];
5281
5281
char *p = buf;
+1
-1
drivers/infiniband/hw/hfi1/mmu_rb.c
+1
-1
drivers/infiniband/hw/hfi1/mmu_rb.c
+2
-2
drivers/infiniband/hw/hfi1/mmu_rb.h
+2
-2
drivers/infiniband/hw/hfi1/mmu_rb.h
···
42
42
/* Begin on a new cachline boundary here */
43
43
struct rb_root_cached root ____cacheline_aligned_in_smp;
44
44
void *ops_arg;
45
-
struct mmu_rb_ops *ops;
45
+
const struct mmu_rb_ops *ops;
46
46
struct list_head lru_list;
47
47
struct work_struct del_work;
48
48
struct list_head del_list;
···
51
51
};
52
52
53
53
int hfi1_mmu_rb_register(void *ops_arg,
54
-
struct mmu_rb_ops *ops,
54
+
const struct mmu_rb_ops *ops,
55
55
struct workqueue_struct *wq,
56
56
struct mmu_rb_handler **handler);
57
57
void hfi1_mmu_rb_unregister(struct mmu_rb_handler *handler);
+1
-1
drivers/infiniband/hw/hfi1/pin_system.c
+1
-1
drivers/infiniband/hw/hfi1/pin_system.c
+2
-1
drivers/infiniband/hw/hns/hns_roce_cq.c
+2
-1
drivers/infiniband/hw/hns/hns_roce_cq.c
···
353
353
}
354
354
355
355
int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
356
-
struct ib_udata *udata)
356
+
struct uverbs_attr_bundle *attrs)
357
357
{
358
358
struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device);
359
+
struct ib_udata *udata = &attrs->driver_udata;
359
360
struct hns_roce_ib_create_cq_resp resp = {};
360
361
struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq);
361
362
struct ib_device *ibdev = &hr_dev->ib_dev;
+8
-1
drivers/infiniband/hw/hns/hns_roce_device.h
+8
-1
drivers/infiniband/hw/hns/hns_roce_device.h
···
83
83
#define MR_TYPE_DMA 0x03
84
84
85
85
#define HNS_ROCE_FRMR_MAX_PA 512
86
+
#define HNS_ROCE_FRMR_ALIGN_SIZE 128
86
87
87
88
#define PKEY_ID 0xffff
88
89
#define NODE_DESC_SIZE 64
···
91
90
92
91
/* Configure to HW for PAGE_SIZE larger than 4KB */
93
92
#define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
93
+
94
+
#define ATOMIC_WR_LEN 8
94
95
95
96
#define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
96
97
#define SRQ_DB_REG 0x230
···
189
186
/* The minimum page size is 4K for hardware */
190
187
#define HNS_HW_PAGE_SHIFT 12
191
188
#define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
189
+
190
+
#define HNS_HW_MAX_PAGE_SHIFT 27
191
+
#define HNS_HW_MAX_PAGE_SIZE (1 << HNS_HW_MAX_PAGE_SHIFT)
192
192
193
193
struct hns_roce_uar {
194
194
u64 pfn;
···
721
715
int shift;
722
716
int event_type;
723
717
int sub_type;
718
+
struct work_struct work;
724
719
};
725
720
726
721
struct hns_roce_eq_table {
···
1274
1267
int to_hr_qp_type(int qp_type);
1275
1268
1276
1269
int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1277
-
struct ib_udata *udata);
1270
+
struct uverbs_attr_bundle *attrs);
1278
1271
1279
1272
int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1280
1273
int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
+105
-59
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+105
-59
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
···
36
36
#include <linux/iopoll.h>
37
37
#include <linux/kernel.h>
38
38
#include <linux/types.h>
39
+
#include <linux/workqueue.h>
39
40
#include <net/addrconf.h>
40
41
#include <rdma/ib_addr.h>
41
42
#include <rdma/ib_cache.h>
···
592
591
(wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
593
592
594
593
if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
595
-
wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
594
+
wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
595
+
if (msg_len != ATOMIC_WR_LEN)
596
+
return -EINVAL;
596
597
set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
597
-
else if (wr->opcode != IB_WR_REG_MR)
598
+
} else if (wr->opcode != IB_WR_REG_MR) {
598
599
ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
599
600
&curr_idx, valid_num_sge);
601
+
if (ret)
602
+
return ret;
603
+
}
600
604
601
605
/*
602
606
* The pipeline can sequentially post all valid WQEs into WQ buffer,
···
1275
1269
return -EIO;
1276
1270
}
1277
1271
1272
+
static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout)
1273
+
{
1274
+
static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = {
1275
+
{HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT},
1276
+
};
1277
+
int i;
1278
+
1279
+
for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++)
1280
+
if (cmdq_tx_timeout[i].opcode == opcode)
1281
+
return cmdq_tx_timeout[i].tx_timeout;
1282
+
1283
+
return tx_timeout;
1284
+
}
1285
+
1286
+
static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u16 opcode)
1287
+
{
1288
+
struct hns_roce_v2_priv *priv = hr_dev->priv;
1289
+
u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout);
1290
+
u32 timeout = 0;
1291
+
1292
+
do {
1293
+
if (hns_roce_cmq_csq_done(hr_dev))
1294
+
break;
1295
+
udelay(1);
1296
+
} while (++timeout < tx_timeout);
1297
+
}
1298
+
1278
1299
static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1279
1300
struct hns_roce_cmq_desc *desc, int num)
1280
1301
{
1281
1302
struct hns_roce_v2_priv *priv = hr_dev->priv;
1282
1303
struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1283
-
u32 timeout = 0;
1284
1304
u16 desc_ret;
1285
1305
u32 tail;
1286
1306
int ret;
···
1327
1295
1328
1296
atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]);
1329
1297
1330
-
do {
1331
-
if (hns_roce_cmq_csq_done(hr_dev))
1332
-
break;
1333
-
udelay(1);
1334
-
} while (++timeout < priv->cmq.tx_timeout);
1335
-
1298
+
hns_roce_wait_csq_done(hr_dev, le16_to_cpu(desc->opcode));
1336
1299
if (hns_roce_cmq_csq_done(hr_dev)) {
1337
1300
ret = 0;
1338
1301
for (i = 0; i < num; i++) {
···
2484
2457
static struct hns_roce_link_table *
2485
2458
alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2486
2459
{
2460
+
u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num;
2487
2461
struct hns_roce_v2_priv *priv = hr_dev->priv;
2488
2462
struct hns_roce_link_table *link_tbl;
2489
2463
u32 pg_shift, size, min_size;
2490
2464
2491
2465
link_tbl = &priv->ext_llm;
2492
2466
pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2493
-
size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2494
-
min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift;
2467
+
size = hr_dev->caps.num_qps * hr_dev->func_num *
2468
+
HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2469
+
min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift;
2495
2470
2496
2471
/* Alloc data table */
2497
2472
size = max(size, min_size);
···
6164
6135
!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
6165
6136
}
6166
6137
6167
-
static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
6168
-
struct hns_roce_eq *eq)
6138
+
static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq)
6169
6139
{
6170
-
struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6171
-
irqreturn_t ceqe_found = IRQ_NONE;
6172
-
u32 cqn;
6140
+
queue_work(system_bh_wq, &eq->work);
6173
6141
6174
-
while (ceqe) {
6175
-
/* Make sure we read CEQ entry after we have checked the
6176
-
* ownership bit
6177
-
*/
6178
-
dma_rmb();
6179
-
6180
-
cqn = hr_reg_read(ceqe, CEQE_CQN);
6181
-
6182
-
hns_roce_cq_completion(hr_dev, cqn);
6183
-
6184
-
++eq->cons_index;
6185
-
ceqe_found = IRQ_HANDLED;
6186
-
atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]);
6187
-
6188
-
ceqe = next_ceqe_sw_v2(eq);
6189
-
}
6190
-
6191
-
update_eq_db(eq);
6192
-
6193
-
return IRQ_RETVAL(ceqe_found);
6142
+
return IRQ_HANDLED;
6194
6143
}
6195
6144
6196
6145
static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
···
6179
6172
6180
6173
if (eq->type_flag == HNS_ROCE_CEQ)
6181
6174
/* Completion event interrupt */
6182
-
int_work = hns_roce_v2_ceq_int(hr_dev, eq);
6175
+
int_work = hns_roce_v2_ceq_int(eq);
6183
6176
else
6184
6177
/* Asynchronous event interrupt */
6185
6178
int_work = hns_roce_v2_aeq_int(hr_dev, eq);
···
6391
6384
roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
6392
6385
}
6393
6386
6394
-
static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn)
6387
+
static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6388
+
{
6389
+
hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6390
+
}
6391
+
6392
+
static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev,
6393
+
struct hns_roce_eq *eq)
6395
6394
{
6396
6395
struct device *dev = hr_dev->dev;
6396
+
int eqn = eq->eqn;
6397
6397
int ret;
6398
6398
u8 cmd;
6399
6399
···
6411
6397
6412
6398
ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
6413
6399
if (ret)
6414
-
dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn);
6415
-
}
6400
+
dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
6416
6401
6417
-
static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6418
-
{
6419
-
hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6402
+
free_eq_buf(hr_dev, eq);
6420
6403
}
6421
6404
6422
6405
static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
···
6551
6540
return ret;
6552
6541
}
6553
6542
6543
+
static void hns_roce_ceq_work(struct work_struct *work)
6544
+
{
6545
+
struct hns_roce_eq *eq = from_work(eq, work, work);
6546
+
struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6547
+
struct hns_roce_dev *hr_dev = eq->hr_dev;
6548
+
int ceqe_num = 0;
6549
+
u32 cqn;
6550
+
6551
+
while (ceqe && ceqe_num < hr_dev->caps.ceqe_depth) {
6552
+
/* Make sure we read CEQ entry after we have checked the
6553
+
* ownership bit
6554
+
*/
6555
+
dma_rmb();
6556
+
6557
+
cqn = hr_reg_read(ceqe, CEQE_CQN);
6558
+
6559
+
hns_roce_cq_completion(hr_dev, cqn);
6560
+
6561
+
++eq->cons_index;
6562
+
++ceqe_num;
6563
+
atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]);
6564
+
6565
+
ceqe = next_ceqe_sw_v2(eq);
6566
+
}
6567
+
6568
+
update_eq_db(eq);
6569
+
}
6570
+
6554
6571
static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6555
6572
int comp_num, int aeq_num, int other_num)
6556
6573
{
···
6610
6571
j - other_num - aeq_num);
6611
6572
6612
6573
for (j = 0; j < irq_num; j++) {
6613
-
if (j < other_num)
6574
+
if (j < other_num) {
6614
6575
ret = request_irq(hr_dev->irq[j],
6615
6576
hns_roce_v2_msix_interrupt_abn,
6616
6577
0, hr_dev->irq_names[j], hr_dev);
6617
-
6618
-
else if (j < (other_num + comp_num))
6578
+
} else if (j < (other_num + comp_num)) {
6579
+
INIT_WORK(&eq_table->eq[j - other_num].work,
6580
+
hns_roce_ceq_work);
6619
6581
ret = request_irq(eq_table->eq[j - other_num].irq,
6620
6582
hns_roce_v2_msix_interrupt_eq,
6621
6583
0, hr_dev->irq_names[j + aeq_num],
6622
6584
&eq_table->eq[j - other_num]);
6623
-
else
6585
+
} else {
6624
6586
ret = request_irq(eq_table->eq[j - other_num].irq,
6625
6587
hns_roce_v2_msix_interrupt_eq,
6626
6588
0, hr_dev->irq_names[j - comp_num],
6627
6589
&eq_table->eq[j - other_num]);
6590
+
}
6591
+
6628
6592
if (ret) {
6629
6593
dev_err(hr_dev->dev, "request irq error!\n");
6630
6594
goto err_request_failed;
···
6637
6595
return 0;
6638
6596
6639
6597
err_request_failed:
6640
-
for (j -= 1; j >= 0; j--)
6641
-
if (j < other_num)
6598
+
for (j -= 1; j >= 0; j--) {
6599
+
if (j < other_num) {
6642
6600
free_irq(hr_dev->irq[j], hr_dev);
6643
-
else
6644
-
free_irq(eq_table->eq[j - other_num].irq,
6645
-
&eq_table->eq[j - other_num]);
6601
+
continue;
6602
+
}
6603
+
free_irq(eq_table->eq[j - other_num].irq,
6604
+
&eq_table->eq[j - other_num]);
6605
+
if (j < other_num + comp_num)
6606
+
cancel_work_sync(&eq_table->eq[j - other_num].work);
6607
+
}
6646
6608
6647
6609
err_kzalloc_failed:
6648
6610
for (i -= 1; i >= 0; i--)
···
6667
6621
for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6668
6622
free_irq(hr_dev->irq[i], hr_dev);
6669
6623
6670
-
for (i = 0; i < eq_num; i++)
6624
+
for (i = 0; i < eq_num; i++) {
6671
6625
free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6626
+
if (i < hr_dev->caps.num_comp_vectors)
6627
+
cancel_work_sync(&hr_dev->eq_table.eq[i].work);
6628
+
}
6672
6629
6673
6630
for (i = 0; i < irq_num; i++)
6674
6631
kfree(hr_dev->irq_names[i]);
···
6760
6711
6761
6712
err_create_eq_fail:
6762
6713
for (i -= 1; i >= 0; i--)
6763
-
free_eq_buf(hr_dev, &eq_table->eq[i]);
6714
+
hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6764
6715
kfree(eq_table->eq);
6765
6716
6766
6717
return ret;
···
6780
6731
__hns_roce_free_irq(hr_dev);
6781
6732
destroy_workqueue(hr_dev->irq_workq);
6782
6733
6783
-
for (i = 0; i < eq_num; i++) {
6784
-
hns_roce_v2_destroy_eqc(hr_dev, i);
6785
-
6786
-
free_eq_buf(hr_dev, &eq_table->eq[i]);
6787
-
}
6734
+
for (i = 0; i < eq_num; i++)
6735
+
hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6788
6736
6789
6737
kfree(eq_table->eq);
6790
6738
}
+6
drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+6
drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+5
drivers/infiniband/hw/hns/hns_roce_mr.c
+5
drivers/infiniband/hw/hns/hns_roce_mr.c
···
443
443
struct hns_roce_mtr *mtr = &mr->pbl_mtr;
444
444
int ret, sg_num = 0;
445
445
446
+
if (!IS_ALIGNED(*sg_offset, HNS_ROCE_FRMR_ALIGN_SIZE) ||
447
+
ibmr->page_size < HNS_HW_PAGE_SIZE ||
448
+
ibmr->page_size > HNS_HW_MAX_PAGE_SIZE)
449
+
return sg_num;
450
+
446
451
mr->npages = 0;
447
452
mr->page_list = kvcalloc(mr->pbl_mtr.hem_cfg.buf_pg_count,
448
453
sizeof(dma_addr_t), GFP_KERNEL);
+3
-1
drivers/infiniband/hw/hns/hns_roce_qp.c
+3
-1
drivers/infiniband/hw/hns/hns_roce_qp.c
···
532
532
{
533
533
unsigned int inline_sge;
534
534
535
-
inline_sge = roundup_pow_of_two(max_inline_data) / HNS_ROCE_SGE_SIZE;
535
+
if (!max_inline_data)
536
+
return 0;
536
537
537
538
/*
538
539
* if max_inline_data less than
539
540
* HNS_ROCE_SGE_IN_WQE * HNS_ROCE_SGE_SIZE,
540
541
* In addition to ud's mode, no need to extend sge.
541
542
*/
543
+
inline_sge = roundup_pow_of_two(max_inline_data) / HNS_ROCE_SGE_SIZE;
542
544
if (!is_ud_or_gsi && inline_sge <= HNS_ROCE_SGE_IN_WQE)
543
545
inline_sge = 0;
544
546
+1
-1
drivers/infiniband/hw/hns/hns_roce_srq.c
+1
-1
drivers/infiniband/hw/hns/hns_roce_srq.c
···
297
297
298
298
max_sge = proc_srq_sge(hr_dev, srq, !!udata);
299
299
if (attr->max_wr > hr_dev->caps.max_srq_wrs ||
300
-
attr->max_sge > max_sge) {
300
+
attr->max_sge > max_sge || !attr->max_sge) {
301
301
ibdev_err(&hr_dev->ib_dev,
302
302
"invalid SRQ attr, depth = %u, sge = %u.\n",
303
303
attr->max_wr, attr->max_sge);
+1
-1
drivers/infiniband/hw/irdma/main.h
+1
-1
drivers/infiniband/hw/irdma/main.h
+3
-2
drivers/infiniband/hw/irdma/verbs.c
+3
-2
drivers/infiniband/hw/irdma/verbs.c
···
2035
2035
* irdma_create_cq - create cq
2036
2036
* @ibcq: CQ allocated
2037
2037
* @attr: attributes for cq
2038
-
* @udata: user data
2038
+
* @attrs: uverbs attribute bundle
2039
2039
*/
2040
2040
static int irdma_create_cq(struct ib_cq *ibcq,
2041
2041
const struct ib_cq_init_attr *attr,
2042
-
struct ib_udata *udata)
2042
+
struct uverbs_attr_bundle *attrs)
2043
2043
{
2044
2044
#define IRDMA_CREATE_CQ_MIN_REQ_LEN offsetofend(struct irdma_create_cq_req, user_cq_buf)
2045
2045
#define IRDMA_CREATE_CQ_MIN_RESP_LEN offsetofend(struct irdma_create_cq_resp, cq_size)
2046
+
struct ib_udata *udata = &attrs->driver_udata;
2046
2047
struct ib_device *ibdev = ibcq->device;
2047
2048
struct irdma_device *iwdev = to_iwdev(ibdev);
2048
2049
struct irdma_pci_f *rf = iwdev->rf;
+2
-1
drivers/infiniband/hw/mana/cq.c
+2
-1
drivers/infiniband/hw/mana/cq.c
···
6
6
#include "mana_ib.h"
7
7
8
8
int mana_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
9
-
struct ib_udata *udata)
9
+
struct uverbs_attr_bundle *attrs)
10
10
{
11
+
struct ib_udata *udata = &attrs->driver_udata;
11
12
struct mana_ib_cq *cq = container_of(ibcq, struct mana_ib_cq, ibcq);
12
13
struct mana_ib_create_cq_resp resp = {};
13
14
struct mana_ib_ucontext *mana_ucontext;
+12
-7
drivers/infiniband/hw/mana/device.c
+12
-7
drivers/infiniband/hw/mana/device.c
···
5
5
6
6
#include "mana_ib.h"
7
7
#include <net/mana/mana_auxiliary.h>
8
+
#include <net/addrconf.h>
8
9
9
10
MODULE_DESCRIPTION("Microsoft Azure Network Adapter IB driver");
10
11
MODULE_LICENSE("GPL");
···
56
55
{
57
56
struct mana_adev *madev = container_of(adev, struct mana_adev, adev);
58
57
struct gdma_dev *mdev = madev->mdev;
59
-
struct net_device *upper_ndev;
58
+
struct net_device *ndev;
60
59
struct mana_context *mc;
61
60
struct mana_ib_dev *dev;
62
61
u8 mac_addr[ETH_ALEN];
···
84
83
dev->ib_dev.num_comp_vectors = mdev->gdma_context->max_num_queues;
85
84
dev->ib_dev.dev.parent = mdev->gdma_context->dev;
86
85
87
-
rcu_read_lock(); /* required to get upper dev */
88
-
upper_ndev = netdev_master_upper_dev_get_rcu(mc->ports[0]);
89
-
if (!upper_ndev) {
86
+
rcu_read_lock(); /* required to get primary netdev */
87
+
ndev = mana_get_primary_netdev_rcu(mc, 0);
88
+
if (!ndev) {
90
89
rcu_read_unlock();
91
90
ret = -ENODEV;
92
-
ibdev_err(&dev->ib_dev, "Failed to get master netdev");
91
+
ibdev_err(&dev->ib_dev, "Failed to get netdev for IB port 1");
93
92
goto free_ib_device;
94
93
}
95
-
ether_addr_copy(mac_addr, upper_ndev->dev_addr);
96
-
ret = ib_device_set_netdev(&dev->ib_dev, upper_ndev, 1);
94
+
ether_addr_copy(mac_addr, ndev->dev_addr);
95
+
addrconf_addr_eui48((u8 *)&dev->ib_dev.node_guid, ndev->dev_addr);
96
+
ret = ib_device_set_netdev(&dev->ib_dev, ndev, 1);
97
97
rcu_read_unlock();
98
98
if (ret) {
99
99
ibdev_err(&dev->ib_dev, "Failed to set ib netdev, ret %d", ret);
···
126
124
if (ret)
127
125
goto destroy_eqs;
128
126
127
+
xa_init_flags(&dev->qp_table_wq, XA_FLAGS_LOCK_IRQ);
129
128
ret = mana_ib_gd_config_mac(dev, ADDR_OP_ADD, mac_addr);
130
129
if (ret) {
131
130
ibdev_err(&dev->ib_dev, "Failed to add Mac address, ret %d",
···
144
141
return 0;
145
142
146
143
destroy_rnic:
144
+
xa_destroy(&dev->qp_table_wq);
147
145
mana_ib_gd_destroy_rnic_adapter(dev);
148
146
destroy_eqs:
149
147
mana_ib_destroy_eqs(dev);
···
160
156
struct mana_ib_dev *dev = dev_get_drvdata(&adev->dev);
161
157
162
158
ib_unregister_device(&dev->ib_dev);
159
+
xa_destroy(&dev->qp_table_wq);
163
160
mana_ib_gd_destroy_rnic_adapter(dev);
164
161
mana_ib_destroy_eqs(dev);
165
162
mana_gd_deregister_device(dev->gdma_dev);
+104
-5
drivers/infiniband/hw/mana/main.c
+104
-5
drivers/infiniband/hw/mana/main.c
···
547
547
struct mana_ib_dev *dev = container_of(ibdev,
548
548
struct mana_ib_dev, ib_dev);
549
549
550
+
memset(props, 0, sizeof(*props));
551
+
props->max_mr_size = MANA_IB_MAX_MR_SIZE;
552
+
props->page_size_cap = PAGE_SZ_BM;
550
553
props->max_qp = dev->adapter_caps.max_qp_count;
551
554
props->max_qp_wr = dev->adapter_caps.max_qp_wr;
555
+
props->device_cap_flags = IB_DEVICE_RC_RNR_NAK_GEN;
556
+
props->max_send_sge = dev->adapter_caps.max_send_sge_count;
557
+
props->max_recv_sge = dev->adapter_caps.max_recv_sge_count;
558
+
props->max_sge_rd = dev->adapter_caps.max_recv_sge_count;
552
559
props->max_cq = dev->adapter_caps.max_cq_count;
553
560
props->max_cqe = dev->adapter_caps.max_qp_wr;
554
561
props->max_mr = dev->adapter_caps.max_mr_count;
555
-
props->max_mr_size = MANA_IB_MAX_MR_SIZE;
556
-
props->max_send_sge = dev->adapter_caps.max_send_sge_count;
557
-
props->max_recv_sge = dev->adapter_caps.max_recv_sge_count;
562
+
props->max_pd = dev->adapter_caps.max_pd_count;
563
+
props->max_qp_rd_atom = dev->adapter_caps.max_inbound_read_limit;
564
+
props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
565
+
props->max_qp_init_rd_atom = dev->adapter_caps.max_outbound_read_limit;
566
+
props->atomic_cap = IB_ATOMIC_NONE;
567
+
props->masked_atomic_cap = IB_ATOMIC_NONE;
568
+
props->max_ah = INT_MAX;
569
+
props->max_pkeys = 1;
570
+
props->local_ca_ack_delay = MANA_CA_ACK_DELAY;
558
571
559
572
return 0;
560
573
}
···
667
654
return 0;
668
655
}
669
656
657
+
static void
658
+
mana_ib_event_handler(void *ctx, struct gdma_queue *q, struct gdma_event *event)
659
+
{
660
+
struct mana_ib_dev *mdev = (struct mana_ib_dev *)ctx;
661
+
struct mana_ib_qp *qp;
662
+
struct ib_event ev;
663
+
u32 qpn;
664
+
665
+
switch (event->type) {
666
+
case GDMA_EQE_RNIC_QP_FATAL:
667
+
qpn = event->details[0];
668
+
qp = mana_get_qp_ref(mdev, qpn);
669
+
if (!qp)
670
+
break;
671
+
if (qp->ibqp.event_handler) {
672
+
ev.device = qp->ibqp.device;
673
+
ev.element.qp = &qp->ibqp;
674
+
ev.event = IB_EVENT_QP_FATAL;
675
+
qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
676
+
}
677
+
mana_put_qp_ref(qp);
678
+
break;
679
+
default:
680
+
break;
681
+
}
682
+
}
683
+
670
684
int mana_ib_create_eqs(struct mana_ib_dev *mdev)
671
685
{
672
686
struct gdma_context *gc = mdev_to_gc(mdev);
···
703
663
spec.type = GDMA_EQ;
704
664
spec.monitor_avl_buf = false;
705
665
spec.queue_size = EQ_SIZE;
706
-
spec.eq.callback = NULL;
666
+
spec.eq.callback = mana_ib_event_handler;
707
667
spec.eq.context = mdev;
708
668
spec.eq.log2_throttle_limit = LOG2_EQ_THROTTLE;
709
669
spec.eq.msix_index = 0;
···
718
678
err = -ENOMEM;
719
679
goto destroy_fatal_eq;
720
680
}
721
-
681
+
spec.eq.callback = NULL;
722
682
for (i = 0; i < mdev->ib_dev.num_comp_vectors; i++) {
723
683
spec.eq.msix_index = (i + 1) % gc->num_msix_usable;
724
684
err = mana_gd_create_mana_eq(mdev->gdma_dev, &spec, &mdev->eqs[i]);
···
926
886
return err;
927
887
}
928
888
889
+
return 0;
890
+
}
891
+
892
+
int mana_ib_gd_create_rc_qp(struct mana_ib_dev *mdev, struct mana_ib_qp *qp,
893
+
struct ib_qp_init_attr *attr, u32 doorbell, u64 flags)
894
+
{
895
+
struct mana_ib_cq *send_cq = container_of(qp->ibqp.send_cq, struct mana_ib_cq, ibcq);
896
+
struct mana_ib_cq *recv_cq = container_of(qp->ibqp.recv_cq, struct mana_ib_cq, ibcq);
897
+
struct mana_ib_pd *pd = container_of(qp->ibqp.pd, struct mana_ib_pd, ibpd);
898
+
struct gdma_context *gc = mdev_to_gc(mdev);
899
+
struct mana_rnic_create_qp_resp resp = {};
900
+
struct mana_rnic_create_qp_req req = {};
901
+
int err, i;
902
+
903
+
mana_gd_init_req_hdr(&req.hdr, MANA_IB_CREATE_RC_QP, sizeof(req), sizeof(resp));
904
+
req.hdr.dev_id = gc->mana_ib.dev_id;
905
+
req.adapter = mdev->adapter_handle;
906
+
req.pd_handle = pd->pd_handle;
907
+
req.send_cq_handle = send_cq->cq_handle;
908
+
req.recv_cq_handle = recv_cq->cq_handle;
909
+
for (i = 0; i < MANA_RC_QUEUE_TYPE_MAX; i++)
910
+
req.dma_region[i] = qp->rc_qp.queues[i].gdma_region;
911
+
req.doorbell_page = doorbell;
912
+
req.max_send_wr = attr->cap.max_send_wr;
913
+
req.max_recv_wr = attr->cap.max_recv_wr;
914
+
req.max_send_sge = attr->cap.max_send_sge;
915
+
req.max_recv_sge = attr->cap.max_recv_sge;
916
+
req.flags = flags;
917
+
918
+
err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
919
+
if (err) {
920
+
ibdev_err(&mdev->ib_dev, "Failed to create rc qp err %d", err);
921
+
return err;
922
+
}
923
+
qp->qp_handle = resp.rc_qp_handle;
924
+
for (i = 0; i < MANA_RC_QUEUE_TYPE_MAX; i++) {
925
+
qp->rc_qp.queues[i].id = resp.queue_ids[i];
926
+
/* The GDMA regions are now owned by the RNIC QP handle */
927
+
qp->rc_qp.queues[i].gdma_region = GDMA_INVALID_DMA_REGION;
928
+
}
929
+
return 0;
930
+
}
931
+
932
+
int mana_ib_gd_destroy_rc_qp(struct mana_ib_dev *mdev, struct mana_ib_qp *qp)
933
+
{
934
+
struct mana_rnic_destroy_rc_qp_resp resp = {0};
935
+
struct mana_rnic_destroy_rc_qp_req req = {0};
936
+
struct gdma_context *gc = mdev_to_gc(mdev);
937
+
int err;
938
+
939
+
mana_gd_init_req_hdr(&req.hdr, MANA_IB_DESTROY_RC_QP, sizeof(req), sizeof(resp));
940
+
req.hdr.dev_id = gc->mana_ib.dev_id;
941
+
req.adapter = mdev->adapter_handle;
942
+
req.rc_qp_handle = qp->qp_handle;
943
+
err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
944
+
if (err) {
945
+
ibdev_err(&mdev->ib_dev, "Failed to destroy rc qp err %d", err);
946
+
return err;
947
+
}
929
948
return 0;
930
949
}
+128
-2
drivers/infiniband/hw/mana/mana_ib.h
+128
-2
drivers/infiniband/hw/mana/mana_ib.h
···
27
27
*/
28
28
#define MANA_IB_MAX_MR 0xFFFFFFu
29
29
30
+
/*
31
+
* The CA timeout is approx. 260ms (4us * 2^(DELAY))
32
+
*/
33
+
#define MANA_CA_ACK_DELAY 16
34
+
30
35
struct mana_ib_adapter_caps {
31
36
u32 max_sq_id;
32
37
u32 max_rq_id;
···
62
57
mana_handle_t adapter_handle;
63
58
struct gdma_queue *fatal_err_eq;
64
59
struct gdma_queue **eqs;
60
+
struct xarray qp_table_wq;
65
61
struct mana_ib_adapter_caps adapter_caps;
66
62
};
67
63
···
101
95
mana_handle_t cq_handle;
102
96
};
103
97
98
+
enum mana_rc_queue_type {
99
+
MANA_RC_SEND_QUEUE_REQUESTER = 0,
100
+
MANA_RC_SEND_QUEUE_RESPONDER,
101
+
MANA_RC_SEND_QUEUE_FMR,
102
+
MANA_RC_RECV_QUEUE_REQUESTER,
103
+
MANA_RC_RECV_QUEUE_RESPONDER,
104
+
MANA_RC_QUEUE_TYPE_MAX,
105
+
};
106
+
107
+
struct mana_ib_rc_qp {
108
+
struct mana_ib_queue queues[MANA_RC_QUEUE_TYPE_MAX];
109
+
};
110
+
104
111
struct mana_ib_qp {
105
112
struct ib_qp ibqp;
106
113
107
114
mana_handle_t qp_handle;
108
-
struct mana_ib_queue raw_sq;
115
+
union {
116
+
struct mana_ib_queue raw_sq;
117
+
struct mana_ib_rc_qp rc_qp;
118
+
};
109
119
110
120
/* The port on the IB device, starting with 1 */
111
121
u32 port;
122
+
123
+
refcount_t refcount;
124
+
struct completion free;
112
125
};
113
126
114
127
struct mana_ib_ucontext {
···
147
122
MANA_IB_CONFIG_MAC_ADDR = 0x30005,
148
123
MANA_IB_CREATE_CQ = 0x30008,
149
124
MANA_IB_DESTROY_CQ = 0x30009,
125
+
MANA_IB_CREATE_RC_QP = 0x3000a,
126
+
MANA_IB_DESTROY_RC_QP = 0x3000b,
127
+
MANA_IB_SET_QP_STATE = 0x3000d,
150
128
};
151
129
152
130
struct mana_ib_query_adapter_caps_req {
···
258
230
struct gdma_resp_hdr hdr;
259
231
}; /* HW Data */
260
232
233
+
enum mana_rnic_create_rc_flags {
234
+
MANA_RC_FLAG_NO_FMR = 2,
235
+
};
236
+
237
+
struct mana_rnic_create_qp_req {
238
+
struct gdma_req_hdr hdr;
239
+
mana_handle_t adapter;
240
+
mana_handle_t pd_handle;
241
+
mana_handle_t send_cq_handle;
242
+
mana_handle_t recv_cq_handle;
243
+
u64 dma_region[MANA_RC_QUEUE_TYPE_MAX];
244
+
u64 deprecated[2];
245
+
u64 flags;
246
+
u32 doorbell_page;
247
+
u32 max_send_wr;
248
+
u32 max_recv_wr;
249
+
u32 max_send_sge;
250
+
u32 max_recv_sge;
251
+
u32 reserved;
252
+
}; /* HW Data */
253
+
254
+
struct mana_rnic_create_qp_resp {
255
+
struct gdma_resp_hdr hdr;
256
+
mana_handle_t rc_qp_handle;
257
+
u32 queue_ids[MANA_RC_QUEUE_TYPE_MAX];
258
+
u32 reserved;
259
+
}; /* HW Data*/
260
+
261
+
struct mana_rnic_destroy_rc_qp_req {
262
+
struct gdma_req_hdr hdr;
263
+
mana_handle_t adapter;
264
+
mana_handle_t rc_qp_handle;
265
+
}; /* HW Data */
266
+
267
+
struct mana_rnic_destroy_rc_qp_resp {
268
+
struct gdma_resp_hdr hdr;
269
+
}; /* HW Data */
270
+
271
+
struct mana_ib_ah_attr {
272
+
u8 src_addr[16];
273
+
u8 dest_addr[16];
274
+
u8 src_mac[ETH_ALEN];
275
+
u8 dest_mac[ETH_ALEN];
276
+
u8 src_addr_type;
277
+
u8 dest_addr_type;
278
+
u8 hop_limit;
279
+
u8 traffic_class;
280
+
u16 src_port;
281
+
u16 dest_port;
282
+
u32 reserved;
283
+
};
284
+
285
+
struct mana_rnic_set_qp_state_req {
286
+
struct gdma_req_hdr hdr;
287
+
mana_handle_t adapter;
288
+
mana_handle_t qp_handle;
289
+
u64 attr_mask;
290
+
u32 qp_state;
291
+
u32 path_mtu;
292
+
u32 rq_psn;
293
+
u32 sq_psn;
294
+
u32 dest_qpn;
295
+
u32 max_dest_rd_atomic;
296
+
u32 retry_cnt;
297
+
u32 rnr_retry;
298
+
u32 min_rnr_timer;
299
+
u32 reserved;
300
+
struct mana_ib_ah_attr ah_attr;
301
+
}; /* HW Data */
302
+
303
+
struct mana_rnic_set_qp_state_resp {
304
+
struct gdma_resp_hdr hdr;
305
+
}; /* HW Data */
306
+
261
307
static inline struct gdma_context *mdev_to_gc(struct mana_ib_dev *mdev)
262
308
{
263
309
return mdev->gdma_dev->gdma_context;
310
+
}
311
+
312
+
static inline struct mana_ib_qp *mana_get_qp_ref(struct mana_ib_dev *mdev,
313
+
uint32_t qid)
314
+
{
315
+
struct mana_ib_qp *qp;
316
+
unsigned long flag;
317
+
318
+
xa_lock_irqsave(&mdev->qp_table_wq, flag);
319
+
qp = xa_load(&mdev->qp_table_wq, qid);
320
+
if (qp)
321
+
refcount_inc(&qp->refcount);
322
+
xa_unlock_irqrestore(&mdev->qp_table_wq, flag);
323
+
return qp;
324
+
}
325
+
326
+
static inline void mana_put_qp_ref(struct mana_ib_qp *qp)
327
+
{
328
+
if (refcount_dec_and_test(&qp->refcount))
329
+
complete(&qp->free);
264
330
}
265
331
266
332
static inline struct net_device *mana_ib_get_netdev(struct ib_device *ibdev, u32 port)
···
429
307
u32 port);
430
308
431
309
int mana_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
432
-
struct ib_udata *udata);
310
+
struct uverbs_attr_bundle *attrs);
433
311
434
312
int mana_ib_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata);
435
313
···
476
354
int mana_ib_gd_create_cq(struct mana_ib_dev *mdev, struct mana_ib_cq *cq, u32 doorbell);
477
355
478
356
int mana_ib_gd_destroy_cq(struct mana_ib_dev *mdev, struct mana_ib_cq *cq);
357
+
358
+
int mana_ib_gd_create_rc_qp(struct mana_ib_dev *mdev, struct mana_ib_qp *qp,
359
+
struct ib_qp_init_attr *attr, u32 doorbell, u64 flags);
360
+
int mana_ib_gd_destroy_rc_qp(struct mana_ib_dev *mdev, struct mana_ib_qp *qp);
479
361
#endif
+184
-4
drivers/infiniband/hw/mana/qp.c
+184
-4
drivers/infiniband/hw/mana/qp.c
···
398
398
return err;
399
399
}
400
400
401
+
static int mana_table_store_qp(struct mana_ib_dev *mdev, struct mana_ib_qp *qp)
402
+
{
403
+
refcount_set(&qp->refcount, 1);
404
+
init_completion(&qp->free);
405
+
return xa_insert_irq(&mdev->qp_table_wq, qp->ibqp.qp_num, qp,
406
+
GFP_KERNEL);
407
+
}
408
+
409
+
static void mana_table_remove_qp(struct mana_ib_dev *mdev,
410
+
struct mana_ib_qp *qp)
411
+
{
412
+
xa_erase_irq(&mdev->qp_table_wq, qp->ibqp.qp_num);
413
+
mana_put_qp_ref(qp);
414
+
wait_for_completion(&qp->free);
415
+
}
416
+
417
+
static int mana_ib_create_rc_qp(struct ib_qp *ibqp, struct ib_pd *ibpd,
418
+
struct ib_qp_init_attr *attr, struct ib_udata *udata)
419
+
{
420
+
struct mana_ib_dev *mdev = container_of(ibpd->device, struct mana_ib_dev, ib_dev);
421
+
struct mana_ib_qp *qp = container_of(ibqp, struct mana_ib_qp, ibqp);
422
+
struct mana_ib_create_rc_qp_resp resp = {};
423
+
struct mana_ib_ucontext *mana_ucontext;
424
+
struct mana_ib_create_rc_qp ucmd = {};
425
+
int i, err, j;
426
+
u64 flags = 0;
427
+
u32 doorbell;
428
+
429
+
if (!udata || udata->inlen < sizeof(ucmd))
430
+
return -EINVAL;
431
+
432
+
mana_ucontext = rdma_udata_to_drv_context(udata, struct mana_ib_ucontext, ibucontext);
433
+
doorbell = mana_ucontext->doorbell;
434
+
flags = MANA_RC_FLAG_NO_FMR;
435
+
err = ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen));
436
+
if (err) {
437
+
ibdev_dbg(&mdev->ib_dev, "Failed to copy from udata, %d\n", err);
438
+
return err;
439
+
}
440
+
441
+
for (i = 0, j = 0; i < MANA_RC_QUEUE_TYPE_MAX; ++i) {
442
+
/* skip FMR for user-level RC QPs */
443
+
if (i == MANA_RC_SEND_QUEUE_FMR) {
444
+
qp->rc_qp.queues[i].id = INVALID_QUEUE_ID;
445
+
qp->rc_qp.queues[i].gdma_region = GDMA_INVALID_DMA_REGION;
446
+
continue;
447
+
}
448
+
err = mana_ib_create_queue(mdev, ucmd.queue_buf[j], ucmd.queue_size[j],
449
+
&qp->rc_qp.queues[i]);
450
+
if (err) {
451
+
ibdev_err(&mdev->ib_dev, "Failed to create queue %d, err %d\n", i, err);
452
+
goto destroy_queues;
453
+
}
454
+
j++;
455
+
}
456
+
457
+
err = mana_ib_gd_create_rc_qp(mdev, qp, attr, doorbell, flags);
458
+
if (err) {
459
+
ibdev_err(&mdev->ib_dev, "Failed to create rc qp %d\n", err);
460
+
goto destroy_queues;
461
+
}
462
+
qp->ibqp.qp_num = qp->rc_qp.queues[MANA_RC_RECV_QUEUE_RESPONDER].id;
463
+
qp->port = attr->port_num;
464
+
465
+
if (udata) {
466
+
for (i = 0, j = 0; i < MANA_RC_QUEUE_TYPE_MAX; ++i) {
467
+
if (i == MANA_RC_SEND_QUEUE_FMR)
468
+
continue;
469
+
resp.queue_id[j] = qp->rc_qp.queues[i].id;
470
+
j++;
471
+
}
472
+
err = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
473
+
if (err) {
474
+
ibdev_dbg(&mdev->ib_dev, "Failed to copy to udata, %d\n", err);
475
+
goto destroy_qp;
476
+
}
477
+
}
478
+
479
+
err = mana_table_store_qp(mdev, qp);
480
+
if (err)
481
+
goto destroy_qp;
482
+
483
+
return 0;
484
+
485
+
destroy_qp:
486
+
mana_ib_gd_destroy_rc_qp(mdev, qp);
487
+
destroy_queues:
488
+
while (i-- > 0)
489
+
mana_ib_destroy_queue(mdev, &qp->rc_qp.queues[i]);
490
+
return err;
491
+
}
492
+
401
493
int mana_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attr,
402
494
struct ib_udata *udata)
403
495
{
···
501
409
udata);
502
410
503
411
return mana_ib_create_qp_raw(ibqp, ibqp->pd, attr, udata);
412
+
case IB_QPT_RC:
413
+
return mana_ib_create_rc_qp(ibqp, ibqp->pd, attr, udata);
504
414
default:
505
-
/* Creating QP other than IB_QPT_RAW_PACKET is not supported */
506
415
ibdev_dbg(ibqp->device, "Creating QP type %u not supported\n",
507
416
attr->qp_type);
508
417
}
···
511
418
return -EINVAL;
512
419
}
513
420
421
+
static int mana_ib_gd_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
422
+
int attr_mask, struct ib_udata *udata)
423
+
{
424
+
struct mana_ib_dev *mdev = container_of(ibqp->device, struct mana_ib_dev, ib_dev);
425
+
struct mana_ib_qp *qp = container_of(ibqp, struct mana_ib_qp, ibqp);
426
+
struct mana_rnic_set_qp_state_resp resp = {};
427
+
struct mana_rnic_set_qp_state_req req = {};
428
+
struct gdma_context *gc = mdev_to_gc(mdev);
429
+
struct mana_port_context *mpc;
430
+
struct net_device *ndev;
431
+
int err;
432
+
433
+
mana_gd_init_req_hdr(&req.hdr, MANA_IB_SET_QP_STATE, sizeof(req), sizeof(resp));
434
+
req.hdr.dev_id = gc->mana_ib.dev_id;
435
+
req.adapter = mdev->adapter_handle;
436
+
req.qp_handle = qp->qp_handle;
437
+
req.qp_state = attr->qp_state;
438
+
req.attr_mask = attr_mask;
439
+
req.path_mtu = attr->path_mtu;
440
+
req.rq_psn = attr->rq_psn;
441
+
req.sq_psn = attr->sq_psn;
442
+
req.dest_qpn = attr->dest_qp_num;
443
+
req.max_dest_rd_atomic = attr->max_dest_rd_atomic;
444
+
req.retry_cnt = attr->retry_cnt;
445
+
req.rnr_retry = attr->rnr_retry;
446
+
req.min_rnr_timer = attr->min_rnr_timer;
447
+
if (attr_mask & IB_QP_AV) {
448
+
ndev = mana_ib_get_netdev(&mdev->ib_dev, ibqp->port);
449
+
if (!ndev) {
450
+
ibdev_dbg(&mdev->ib_dev, "Invalid port %u in QP %u\n",
451
+
ibqp->port, ibqp->qp_num);
452
+
return -EINVAL;
453
+
}
454
+
mpc = netdev_priv(ndev);
455
+
copy_in_reverse(req.ah_attr.src_mac, mpc->mac_addr, ETH_ALEN);
456
+
copy_in_reverse(req.ah_attr.dest_mac, attr->ah_attr.roce.dmac, ETH_ALEN);
457
+
copy_in_reverse(req.ah_attr.src_addr, attr->ah_attr.grh.sgid_attr->gid.raw,
458
+
sizeof(union ib_gid));
459
+
copy_in_reverse(req.ah_attr.dest_addr, attr->ah_attr.grh.dgid.raw,
460
+
sizeof(union ib_gid));
461
+
if (rdma_gid_attr_network_type(attr->ah_attr.grh.sgid_attr) == RDMA_NETWORK_IPV4) {
462
+
req.ah_attr.src_addr_type = SGID_TYPE_IPV4;
463
+
req.ah_attr.dest_addr_type = SGID_TYPE_IPV4;
464
+
} else {
465
+
req.ah_attr.src_addr_type = SGID_TYPE_IPV6;
466
+
req.ah_attr.dest_addr_type = SGID_TYPE_IPV6;
467
+
}
468
+
req.ah_attr.dest_port = ROCE_V2_UDP_DPORT;
469
+
req.ah_attr.src_port = rdma_get_udp_sport(attr->ah_attr.grh.flow_label,
470
+
ibqp->qp_num, attr->dest_qp_num);
471
+
req.ah_attr.traffic_class = attr->ah_attr.grh.traffic_class;
472
+
req.ah_attr.hop_limit = attr->ah_attr.grh.hop_limit;
473
+
}
474
+
475
+
err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
476
+
if (err) {
477
+
ibdev_err(&mdev->ib_dev, "Failed modify qp err %d", err);
478
+
return err;
479
+
}
480
+
481
+
return 0;
482
+
}
483
+
514
484
int mana_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
515
485
int attr_mask, struct ib_udata *udata)
516
486
{
517
-
/* modify_qp is not supported by this version of the driver */
518
-
return -EOPNOTSUPP;
487
+
switch (ibqp->qp_type) {
488
+
case IB_QPT_RC:
489
+
return mana_ib_gd_modify_qp(ibqp, attr, attr_mask, udata);
490
+
default:
491
+
ibdev_dbg(ibqp->device, "Modify QP type %u not supported", ibqp->qp_type);
492
+
return -EOPNOTSUPP;
493
+
}
519
494
}
520
495
521
496
static int mana_ib_destroy_qp_rss(struct mana_ib_qp *qp,
···
634
473
return 0;
635
474
}
636
475
476
+
static int mana_ib_destroy_rc_qp(struct mana_ib_qp *qp, struct ib_udata *udata)
477
+
{
478
+
struct mana_ib_dev *mdev =
479
+
container_of(qp->ibqp.device, struct mana_ib_dev, ib_dev);
480
+
int i;
481
+
482
+
mana_table_remove_qp(mdev, qp);
483
+
484
+
/* Ignore return code as there is not much we can do about it.
485
+
* The error message is printed inside.
486
+
*/
487
+
mana_ib_gd_destroy_rc_qp(mdev, qp);
488
+
for (i = 0; i < MANA_RC_QUEUE_TYPE_MAX; ++i)
489
+
mana_ib_destroy_queue(mdev, &qp->rc_qp.queues[i]);
490
+
491
+
return 0;
492
+
}
493
+
637
494
int mana_ib_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
638
495
{
639
496
struct mana_ib_qp *qp = container_of(ibqp, struct mana_ib_qp, ibqp);
···
663
484
udata);
664
485
665
486
return mana_ib_destroy_qp_raw(qp, udata);
666
-
487
+
case IB_QPT_RC:
488
+
return mana_ib_destroy_rc_qp(qp, udata);
667
489
default:
668
490
ibdev_dbg(ibqp->device, "Unexpected QP type %u\n",
669
491
ibqp->qp_type);
+1
-1
drivers/infiniband/hw/mlx4/alias_GUID.c
+1
-1
drivers/infiniband/hw/mlx4/alias_GUID.c
+2
-1
drivers/infiniband/hw/mlx4/cq.c
+2
-1
drivers/infiniband/hw/mlx4/cq.c
···
172
172
173
173
#define CQ_CREATE_FLAGS_SUPPORTED IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION
174
174
int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
175
-
struct ib_udata *udata)
175
+
struct uverbs_attr_bundle *attrs)
176
176
{
177
+
struct ib_udata *udata = &attrs->driver_udata;
177
178
struct ib_device *ibdev = ibcq->device;
178
179
int entries = attr->cqe;
179
180
int vector = attr->comp_vector;
+1
-1
drivers/infiniband/hw/mlx4/mad.c
+1
-1
drivers/infiniband/hw/mlx4/mad.c
+1
-1
drivers/infiniband/hw/mlx4/mlx4_ib.h
+1
-1
drivers/infiniband/hw/mlx4/mlx4_ib.h
···
767
767
int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
768
768
int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
769
769
int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
770
-
struct ib_udata *udata);
770
+
struct uverbs_attr_bundle *attrs);
771
771
int mlx4_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
772
772
int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
773
773
int mlx4_ib_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
+9
-3
drivers/infiniband/hw/mlx5/cmd.c
+9
-3
drivers/infiniband/hw/mlx5/cmd.c
···
177
177
return mlx5_cmd_exec_in(dev, dealloc_xrcd, in);
178
178
}
179
179
180
-
int mlx5_cmd_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
180
+
int mlx5_cmd_mad_ifc(struct mlx5_ib_dev *dev, const void *inb, void *outb,
181
181
u16 opmod, u8 port)
182
182
{
183
183
int outlen = MLX5_ST_SZ_BYTES(mad_ifc_out);
···
195
195
196
196
MLX5_SET(mad_ifc_in, in, opcode, MLX5_CMD_OP_MAD_IFC);
197
197
MLX5_SET(mad_ifc_in, in, op_mod, opmod);
198
-
MLX5_SET(mad_ifc_in, in, port, port);
198
+
if (dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) {
199
+
MLX5_SET(mad_ifc_in, in, plane_index, port);
200
+
MLX5_SET(mad_ifc_in, in, port,
201
+
smi_to_native_portnum(dev, port));
202
+
} else {
203
+
MLX5_SET(mad_ifc_in, in, port, port);
204
+
}
199
205
200
206
data = MLX5_ADDR_OF(mad_ifc_in, in, mad);
201
207
memcpy(data, inb, MLX5_FLD_SZ_BYTES(mad_ifc_in, mad));
202
208
203
-
err = mlx5_cmd_exec_inout(dev, mad_ifc, in, out);
209
+
err = mlx5_cmd_exec_inout(dev->mdev, mad_ifc, in, out);
204
210
if (err)
205
211
goto out;
206
212
+1
-1
drivers/infiniband/hw/mlx5/cmd.h
+1
-1
drivers/infiniband/hw/mlx5/cmd.h
···
54
54
u32 qpn, u16 uid);
55
55
int mlx5_cmd_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn, u16 uid);
56
56
int mlx5_cmd_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn, u16 uid);
57
-
int mlx5_cmd_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
57
+
int mlx5_cmd_mad_ifc(struct mlx5_ib_dev *dev, const void *inb, void *outb,
58
58
u16 opmod, u8 port);
59
59
int mlx5_cmd_uar_alloc(struct mlx5_core_dev *dev, u32 *uarn, u16 uid);
60
60
int mlx5_cmd_uar_dealloc(struct mlx5_core_dev *dev, u32 uarn, u16 uid);
+27
-4
drivers/infiniband/hw/mlx5/cq.c
+27
-4
drivers/infiniband/hw/mlx5/cq.c
···
38
38
#include "srq.h"
39
39
#include "qp.h"
40
40
41
+
#define UVERBS_MODULE_NAME mlx5_ib
42
+
#include <rdma/uverbs_named_ioctl.h>
43
+
41
44
static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe)
42
45
{
43
46
struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
···
717
714
718
715
static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
719
716
struct mlx5_ib_cq *cq, int entries, u32 **cqb,
720
-
int *cqe_size, int *index, int *inlen)
717
+
int *cqe_size, int *index, int *inlen,
718
+
struct uverbs_attr_bundle *attrs)
721
719
{
722
720
struct mlx5_ib_create_cq ucmd = {};
723
721
unsigned long page_size;
···
792
788
order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT);
793
789
MLX5_SET(cqc, cqc, page_offset, page_offset_quantized);
794
790
795
-
if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX) {
791
+
if (uverbs_attr_is_valid(attrs, MLX5_IB_ATTR_CREATE_CQ_UAR_INDEX)) {
792
+
err = uverbs_copy_from(index, attrs, MLX5_IB_ATTR_CREATE_CQ_UAR_INDEX);
793
+
if (err)
794
+
goto err_cqb;
795
+
} else if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX) {
796
796
*index = ucmd.uar_page_index;
797
797
} else if (context->bfregi.lib_uar_dyn) {
798
798
err = -EINVAL;
···
950
942
}
951
943
952
944
int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
953
-
struct ib_udata *udata)
945
+
struct uverbs_attr_bundle *attrs)
954
946
{
947
+
struct ib_udata *udata = &attrs->driver_udata;
955
948
struct ib_device *ibdev = ibcq->device;
956
949
int entries = attr->cqe;
957
950
int vector = attr->comp_vector;
···
989
980
990
981
if (udata) {
991
982
err = create_cq_user(dev, udata, cq, entries, &cqb, &cqe_size,
992
-
&index, &inlen);
983
+
&index, &inlen, attrs);
993
984
if (err)
994
985
return err;
995
986
} else {
···
1451
1442
1452
1443
return 0;
1453
1444
}
1445
+
1446
+
ADD_UVERBS_ATTRIBUTES_SIMPLE(
1447
+
mlx5_ib_cq_create,
1448
+
UVERBS_OBJECT_CQ,
1449
+
UVERBS_METHOD_CQ_CREATE,
1450
+
UVERBS_ATTR_PTR_IN(
1451
+
MLX5_IB_ATTR_CREATE_CQ_UAR_INDEX,
1452
+
UVERBS_ATTR_TYPE(u32),
1453
+
UA_OPTIONAL));
1454
+
1455
+
const struct uapi_definition mlx5_ib_create_cq_defs[] = {
1456
+
UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_CQ, &mlx5_ib_cq_create),
1457
+
{},
1458
+
};
+58
-11
drivers/infiniband/hw/mlx5/mad.c
+58
-11
drivers/infiniband/hw/mlx5/mad.c
···
69
69
if (ignore_bkey || !in_wc)
70
70
op_modifier |= 0x2;
71
71
72
-
return mlx5_cmd_mad_ifc(dev->mdev, in_mad, response_mad, op_modifier,
72
+
return mlx5_cmd_mad_ifc(dev, in_mad, response_mad, op_modifier,
73
73
port);
74
74
}
75
75
···
147
147
vl_15_dropped);
148
148
}
149
149
150
-
static int query_ib_ppcnt(struct mlx5_core_dev *dev, u8 port_num, void *out,
151
-
size_t sz)
150
+
static void pma_cnt_ext_assign_ppcnt(struct ib_pma_portcounters_ext *cnt_ext,
151
+
void *out)
152
+
{
153
+
void *out_pma = MLX5_ADDR_OF(ppcnt_reg, out,
154
+
counter_set);
155
+
156
+
#define MLX5_GET_EXT_CNTR(counter_name) \
157
+
MLX5_GET64(ib_ext_port_cntrs_grp_data_layout, \
158
+
out_pma, counter_name##_high)
159
+
160
+
cnt_ext->port_xmit_data =
161
+
cpu_to_be64(MLX5_GET_EXT_CNTR(port_xmit_data) >> 2);
162
+
cnt_ext->port_rcv_data =
163
+
cpu_to_be64(MLX5_GET_EXT_CNTR(port_rcv_data) >> 2);
164
+
165
+
cnt_ext->port_xmit_packets =
166
+
cpu_to_be64(MLX5_GET_EXT_CNTR(port_xmit_pkts));
167
+
cnt_ext->port_rcv_packets =
168
+
cpu_to_be64(MLX5_GET_EXT_CNTR(port_rcv_pkts));
169
+
170
+
cnt_ext->port_unicast_xmit_packets =
171
+
cpu_to_be64(MLX5_GET_EXT_CNTR(port_unicast_xmit_pkts));
172
+
cnt_ext->port_unicast_rcv_packets =
173
+
cpu_to_be64(MLX5_GET_EXT_CNTR(port_unicast_rcv_pkts));
174
+
175
+
cnt_ext->port_multicast_xmit_packets =
176
+
cpu_to_be64(MLX5_GET_EXT_CNTR(port_multicast_xmit_pkts));
177
+
cnt_ext->port_multicast_rcv_packets =
178
+
cpu_to_be64(MLX5_GET_EXT_CNTR(port_multicast_rcv_pkts));
179
+
}
180
+
181
+
static int query_ib_ppcnt(struct mlx5_core_dev *dev, u8 port_num, u8 plane_num,
182
+
void *out, size_t sz, bool ext)
152
183
{
153
184
u32 *in;
154
185
int err;
···
191
160
}
192
161
193
162
MLX5_SET(ppcnt_reg, in, local_port, port_num);
163
+
MLX5_SET(ppcnt_reg, in, plane_ind, plane_num);
194
164
195
-
MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
165
+
if (ext)
166
+
MLX5_SET(ppcnt_reg, in, grp,
167
+
MLX5_INFINIBAND_EXTENDED_PORT_COUNTERS_GROUP);
168
+
else
169
+
MLX5_SET(ppcnt_reg, in, grp,
170
+
MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
196
171
err = mlx5_core_access_reg(dev, in, sz, out,
197
172
sz, MLX5_REG_PPCNT, 0, 0);
198
173
···
226
189
mdev_port_num = 1;
227
190
}
228
191
if (MLX5_CAP_GEN(dev->mdev, num_ports) == 1 &&
229
-
!mlx5_core_mp_enabled(mdev)) {
192
+
!mlx5_core_mp_enabled(mdev) &&
193
+
dev->ib_dev.type != RDMA_DEVICE_TYPE_SMI) {
230
194
/* set local port to one for Function-Per-Port HCA. */
231
195
mdev = dev->mdev;
232
196
mdev_port_num = 1;
···
246
208
if (in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS_EXT) {
247
209
struct ib_pma_portcounters_ext *pma_cnt_ext =
248
210
(struct ib_pma_portcounters_ext *)(out_mad->data + 40);
249
-
int sz = MLX5_ST_SZ_BYTES(query_vport_counter_out);
211
+
int sz = max(MLX5_ST_SZ_BYTES(query_vport_counter_out),
212
+
MLX5_ST_SZ_BYTES(ppcnt_reg));
250
213
251
214
out_cnt = kvzalloc(sz, GFP_KERNEL);
252
215
if (!out_cnt) {
···
255
216
goto done;
256
217
}
257
218
258
-
err = mlx5_core_query_vport_counter(mdev, 0, 0, mdev_port_num,
259
-
out_cnt);
260
-
if (!err)
261
-
pma_cnt_ext_assign(pma_cnt_ext, out_cnt);
219
+
if (dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) {
220
+
err = query_ib_ppcnt(mdev, mdev_port_num,
221
+
port_num, out_cnt, sz, 1);
222
+
if (!err)
223
+
pma_cnt_ext_assign_ppcnt(pma_cnt_ext, out_cnt);
224
+
} else {
225
+
err = mlx5_core_query_vport_counter(mdev, 0, 0,
226
+
mdev_port_num,
227
+
out_cnt);
228
+
if (!err)
229
+
pma_cnt_ext_assign(pma_cnt_ext, out_cnt);
230
+
}
262
231
} else {
263
232
struct ib_pma_portcounters *pma_cnt =
264
233
(struct ib_pma_portcounters *)(out_mad->data + 40);
···
278
231
goto done;
279
232
}
280
233
281
-
err = query_ib_ppcnt(mdev, mdev_port_num, out_cnt, sz);
234
+
err = query_ib_ppcnt(mdev, mdev_port_num, 0, out_cnt, sz, 0);
282
235
if (!err)
283
236
pma_cnt_assign(pma_cnt, out_cnt);
284
237
}
+282
-62
drivers/infiniband/hw/mlx5/main.c
+282
-62
drivers/infiniband/hw/mlx5/main.c
···
282
282
struct mlx5_ib_multiport_info *mpi;
283
283
struct mlx5_ib_port *port;
284
284
285
+
if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) {
286
+
if (native_port_num)
287
+
*native_port_num = smi_to_native_portnum(ibdev,
288
+
ib_port_num);
289
+
return ibdev->mdev;
290
+
291
+
}
292
+
285
293
if (!mlx5_core_mp_enabled(ibdev->mdev) ||
286
294
ll != IB_LINK_LAYER_ETHERNET) {
287
295
if (native_port_num)
···
511
503
*/
512
504
if (dev->is_rep)
513
505
err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
514
-
1);
506
+
1, 0);
515
507
else
516
508
err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
517
-
mdev_port_num);
509
+
mdev_port_num, 0);
518
510
if (err)
519
511
goto out;
520
512
ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
···
1341
1333
struct mlx5_ib_dev *dev = to_mdev(ibdev);
1342
1334
struct mlx5_core_dev *mdev = dev->mdev;
1343
1335
struct mlx5_hca_vport_context *rep;
1336
+
u8 vl_hw_cap, plane_index = 0;
1344
1337
u16 max_mtu;
1345
1338
u16 oper_mtu;
1346
1339
int err;
1347
1340
u16 ib_link_width_oper;
1348
-
u8 vl_hw_cap;
1349
1341
1350
1342
rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1351
1343
if (!rep) {
···
1354
1346
}
1355
1347
1356
1348
/* props being zeroed by the caller, avoid zeroing it here */
1349
+
1350
+
if (ibdev->type == RDMA_DEVICE_TYPE_SMI) {
1351
+
plane_index = port;
1352
+
port = smi_to_native_portnum(dev, port);
1353
+
}
1357
1354
1358
1355
err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1359
1356
if (err)
···
1370
1357
props->sm_sl = rep->sm_sl;
1371
1358
props->state = rep->vport_state;
1372
1359
props->phys_state = rep->port_physical_state;
1373
-
props->port_cap_flags = rep->cap_mask1;
1360
+
1361
+
props->port_cap_flags = rep->cap_mask1;
1362
+
if (dev->num_plane) {
1363
+
props->port_cap_flags |= IB_PORT_SM_DISABLED;
1364
+
props->port_cap_flags &= ~IB_PORT_SM;
1365
+
} else if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
1366
+
props->port_cap_flags &= ~IB_PORT_CM_SUP;
1367
+
1374
1368
props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1375
1369
props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1376
1370
props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
···
1390
1370
props->port_cap_flags2 = rep->cap_mask2;
1391
1371
1392
1372
err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1393
-
&props->active_speed, port);
1373
+
&props->active_speed, port, plane_index);
1394
1374
if (err)
1395
1375
goto out;
1396
1376
···
2796
2776
return NOTIFY_OK;
2797
2777
}
2798
2778
2779
+
static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane)
2780
+
{
2781
+
struct mlx5_hca_vport_context vport_ctx;
2782
+
int err;
2783
+
2784
+
*num_plane = 0;
2785
+
if (!MLX5_CAP_GEN(mdev, ib_virt))
2786
+
return 0;
2787
+
2788
+
err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx);
2789
+
if (err)
2790
+
return err;
2791
+
2792
+
*num_plane = vport_ctx.num_plane;
2793
+
return 0;
2794
+
}
2795
+
2799
2796
static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2800
2797
{
2801
2798
struct mlx5_hca_vport_context vport_ctx;
···
2823
2786
return 0;
2824
2787
2825
2788
for (port = 1; port <= dev->num_ports; port++) {
2826
-
if (!MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2789
+
if (dev->num_plane) {
2790
+
dev->port_caps[port - 1].has_smi = false;
2791
+
continue;
2792
+
} else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) ||
2793
+
dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) {
2827
2794
dev->port_caps[port - 1].has_smi = true;
2828
2795
continue;
2829
2796
}
2797
+
2830
2798
err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0,
2831
2799
&vport_ctx);
2832
2800
if (err) {
···
2865
2823
}
2866
2824
}
2867
2825
2868
-
static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2826
+
int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev)
2827
+
{
2828
+
struct mlx5_ib_resources *devr = &dev->devr;
2829
+
struct ib_cq_init_attr cq_attr = {.cqe = 1};
2830
+
struct ib_device *ibdev;
2831
+
struct ib_pd *pd;
2832
+
struct ib_cq *cq;
2833
+
int ret = 0;
2834
+
2835
+
2836
+
/*
2837
+
* devr->c0 is set once, never changed until device unload.
2838
+
* Avoid taking the mutex if initialization is already done.
2839
+
*/
2840
+
if (devr->c0)
2841
+
return 0;
2842
+
2843
+
mutex_lock(&devr->cq_lock);
2844
+
if (devr->c0)
2845
+
goto unlock;
2846
+
2847
+
ibdev = &dev->ib_dev;
2848
+
pd = ib_alloc_pd(ibdev, 0);
2849
+
if (IS_ERR(pd)) {
2850
+
ret = PTR_ERR(pd);
2851
+
mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%d\n", ret);
2852
+
goto unlock;
2853
+
}
2854
+
2855
+
cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr);
2856
+
if (IS_ERR(cq)) {
2857
+
ret = PTR_ERR(cq);
2858
+
mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%d\n", ret);
2859
+
ib_dealloc_pd(pd);
2860
+
goto unlock;
2861
+
}
2862
+
2863
+
devr->p0 = pd;
2864
+
devr->c0 = cq;
2865
+
2866
+
unlock:
2867
+
mutex_unlock(&devr->cq_lock);
2868
+
return ret;
2869
+
}
2870
+
2871
+
int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev)
2869
2872
{
2870
2873
struct mlx5_ib_resources *devr = &dev->devr;
2871
2874
struct ib_srq_init_attr attr;
2872
-
struct ib_device *ibdev;
2873
-
struct ib_cq_init_attr cq_attr = {.cqe = 1};
2874
-
int port;
2875
+
struct ib_srq *s0, *s1;
2875
2876
int ret = 0;
2876
2877
2877
-
ibdev = &dev->ib_dev;
2878
+
/*
2879
+
* devr->s1 is set once, never changed until device unload.
2880
+
* Avoid taking the mutex if initialization is already done.
2881
+
*/
2882
+
if (devr->s1)
2883
+
return 0;
2878
2884
2879
-
if (!MLX5_CAP_GEN(dev->mdev, xrc))
2880
-
return -EOPNOTSUPP;
2885
+
mutex_lock(&devr->srq_lock);
2886
+
if (devr->s1)
2887
+
goto unlock;
2881
2888
2882
-
devr->p0 = ib_alloc_pd(ibdev, 0);
2883
-
if (IS_ERR(devr->p0))
2884
-
return PTR_ERR(devr->p0);
2885
-
2886
-
devr->c0 = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr);
2887
-
if (IS_ERR(devr->c0)) {
2888
-
ret = PTR_ERR(devr->c0);
2889
-
goto error1;
2890
-
}
2891
-
2892
-
ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2889
+
ret = mlx5_ib_dev_res_cq_init(dev);
2893
2890
if (ret)
2894
-
goto error2;
2895
-
2896
-
ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2897
-
if (ret)
2898
-
goto error3;
2891
+
goto unlock;
2899
2892
2900
2893
memset(&attr, 0, sizeof(attr));
2901
2894
attr.attr.max_sge = 1;
···
2938
2861
attr.srq_type = IB_SRQT_XRC;
2939
2862
attr.ext.cq = devr->c0;
2940
2863
2941
-
devr->s0 = ib_create_srq(devr->p0, &attr);
2942
-
if (IS_ERR(devr->s0)) {
2943
-
ret = PTR_ERR(devr->s0);
2944
-
goto err_create;
2864
+
s0 = ib_create_srq(devr->p0, &attr);
2865
+
if (IS_ERR(s0)) {
2866
+
ret = PTR_ERR(s0);
2867
+
mlx5_ib_err(dev, "Couldn't create SRQ 0 for res init, err=%d\n", ret);
2868
+
goto unlock;
2945
2869
}
2946
2870
2947
2871
memset(&attr, 0, sizeof(attr));
···
2950
2872
attr.attr.max_wr = 1;
2951
2873
attr.srq_type = IB_SRQT_BASIC;
2952
2874
2953
-
devr->s1 = ib_create_srq(devr->p0, &attr);
2954
-
if (IS_ERR(devr->s1)) {
2955
-
ret = PTR_ERR(devr->s1);
2956
-
goto error6;
2875
+
s1 = ib_create_srq(devr->p0, &attr);
2876
+
if (IS_ERR(s1)) {
2877
+
ret = PTR_ERR(s1);
2878
+
mlx5_ib_err(dev, "Couldn't create SRQ 1 for res init, err=%d\n", ret);
2879
+
ib_destroy_srq(s0);
2880
+
}
2881
+
2882
+
devr->s0 = s0;
2883
+
devr->s1 = s1;
2884
+
2885
+
unlock:
2886
+
mutex_unlock(&devr->srq_lock);
2887
+
return ret;
2888
+
}
2889
+
2890
+
static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2891
+
{
2892
+
struct mlx5_ib_resources *devr = &dev->devr;
2893
+
int port;
2894
+
int ret;
2895
+
2896
+
if (!MLX5_CAP_GEN(dev->mdev, xrc))
2897
+
return -EOPNOTSUPP;
2898
+
2899
+
ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2900
+
if (ret)
2901
+
return ret;
2902
+
2903
+
ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2904
+
if (ret) {
2905
+
mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2906
+
return ret;
2957
2907
}
2958
2908
2959
2909
for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2960
2910
INIT_WORK(&devr->ports[port].pkey_change_work,
2961
2911
pkey_change_handler);
2962
2912
2963
-
return 0;
2913
+
mutex_init(&devr->cq_lock);
2914
+
mutex_init(&devr->srq_lock);
2964
2915
2965
-
error6:
2966
-
ib_destroy_srq(devr->s0);
2967
-
err_create:
2968
-
mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2969
-
error3:
2970
-
mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2971
-
error2:
2972
-
ib_destroy_cq(devr->c0);
2973
-
error1:
2974
-
ib_dealloc_pd(devr->p0);
2975
-
return ret;
2916
+
return 0;
2976
2917
}
2977
2918
2978
2919
static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
···
3008
2911
for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
3009
2912
cancel_work_sync(&devr->ports[port].pkey_change_work);
3010
2913
3011
-
ib_destroy_srq(devr->s1);
3012
-
ib_destroy_srq(devr->s0);
2914
+
/* After s0/s1 init, they are not unset during the device lifetime. */
2915
+
if (devr->s1) {
2916
+
ib_destroy_srq(devr->s1);
2917
+
ib_destroy_srq(devr->s0);
2918
+
}
3013
2919
mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
3014
2920
mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3015
-
ib_destroy_cq(devr->c0);
3016
-
ib_dealloc_pd(devr->p0);
2921
+
/* After p0/c0 init, they are not unset during the device lifetime. */
2922
+
if (devr->c0) {
2923
+
ib_destroy_cq(devr->c0);
2924
+
ib_dealloc_pd(devr->p0);
2925
+
}
2926
+
mutex_destroy(&devr->cq_lock);
2927
+
mutex_destroy(&devr->srq_lock);
3017
2928
}
3018
2929
3019
2930
static u32 get_core_cap_flags(struct ib_device *ibdev,
···
3036
2931
3037
2932
if (rep->grh_required)
3038
2933
ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
2934
+
2935
+
if (dev->num_plane)
2936
+
return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD |
2937
+
RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA |
2938
+
RDMA_CORE_CAP_AF_IB;
2939
+
else if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
2940
+
return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI;
3039
2941
3040
2942
if (ll == IB_LINK_LAYER_INFINIBAND)
3041
2943
return ret | RDMA_CORE_PORT_IBA_IB;
···
3079
2967
return err;
3080
2968
3081
2969
if (ll == IB_LINK_LAYER_INFINIBAND) {
2970
+
if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
2971
+
port_num = smi_to_native_portnum(dev, port_num);
2972
+
3082
2973
err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
3083
2974
&rep);
3084
2975
if (err)
···
3802
3687
UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3803
3688
UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3804
3689
UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
3690
+
UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs),
3805
3691
3806
3692
UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3807
3693
UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
···
3882
3766
return err;
3883
3767
}
3884
3768
3769
+
static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent,
3770
+
enum rdma_nl_dev_type type,
3771
+
const char *name);
3772
+
static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev);
3773
+
3885
3774
static const struct ib_device_ops mlx5_ib_dev_ops = {
3886
3775
.owner = THIS_MODULE,
3887
3776
.driver_id = RDMA_DRIVER_MLX5,
3888
3777
.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
3889
3778
3890
3779
.add_gid = mlx5_ib_add_gid,
3780
+
.add_sub_dev = mlx5_ib_add_sub_dev,
3891
3781
.alloc_mr = mlx5_ib_alloc_mr,
3892
3782
.alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
3893
3783
.alloc_pd = mlx5_ib_alloc_pd,
···
3908
3786
.dealloc_pd = mlx5_ib_dealloc_pd,
3909
3787
.dealloc_ucontext = mlx5_ib_dealloc_ucontext,
3910
3788
.del_gid = mlx5_ib_del_gid,
3789
+
.del_sub_dev = mlx5_ib_del_sub_dev,
3911
3790
.dereg_mr = mlx5_ib_dereg_mr,
3912
3791
.destroy_ah = mlx5_ib_destroy_ah,
3913
3792
.destroy_cq = mlx5_ib_destroy_cq,
···
4198
4075
{
4199
4076
const char *name;
4200
4077
4201
-
if (!mlx5_lag_is_active(dev->mdev))
4078
+
if (dev->sub_dev_name) {
4079
+
name = dev->sub_dev_name;
4080
+
ib_mark_name_assigned_by_user(&dev->ib_dev);
4081
+
} else if (!mlx5_lag_is_active(dev->mdev))
4202
4082
name = "mlx5_%d";
4203
4083
else
4204
4084
name = "mlx5_bond_%d";
···
4212
4086
{
4213
4087
mlx5_mkey_cache_cleanup(dev);
4214
4088
mlx5r_umr_resource_cleanup(dev);
4089
+
mlx5r_umr_cleanup(dev);
4215
4090
}
4216
4091
4217
4092
static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
···
4224
4097
{
4225
4098
int ret;
4226
4099
4227
-
ret = mlx5r_umr_resource_init(dev);
4100
+
ret = mlx5r_umr_init(dev);
4228
4101
if (ret)
4229
4102
return ret;
4230
4103
···
4462
4335
NULL),
4463
4336
};
4464
4337
4338
+
static const struct mlx5_ib_profile plane_profile = {
4339
+
STAGE_CREATE(MLX5_IB_STAGE_INIT,
4340
+
mlx5_ib_stage_init_init,
4341
+
mlx5_ib_stage_init_cleanup),
4342
+
STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4343
+
mlx5_ib_stage_caps_init,
4344
+
mlx5_ib_stage_caps_cleanup),
4345
+
STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4346
+
mlx5_ib_stage_non_default_cb,
4347
+
NULL),
4348
+
STAGE_CREATE(MLX5_IB_STAGE_QP,
4349
+
mlx5_init_qp_table,
4350
+
mlx5_cleanup_qp_table),
4351
+
STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4352
+
mlx5_init_srq_table,
4353
+
mlx5_cleanup_srq_table),
4354
+
STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4355
+
mlx5_ib_dev_res_init,
4356
+
mlx5_ib_dev_res_cleanup),
4357
+
STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4358
+
mlx5_ib_stage_bfrag_init,
4359
+
mlx5_ib_stage_bfrag_cleanup),
4360
+
STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4361
+
mlx5_ib_stage_ib_reg_init,
4362
+
mlx5_ib_stage_ib_reg_cleanup),
4363
+
};
4364
+
4365
+
static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent,
4366
+
enum rdma_nl_dev_type type,
4367
+
const char *name)
4368
+
{
4369
+
struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane;
4370
+
enum rdma_link_layer ll;
4371
+
int ret;
4372
+
4373
+
if (mparent->smi_dev)
4374
+
return ERR_PTR(-EEXIST);
4375
+
4376
+
ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev,
4377
+
port_type));
4378
+
if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane ||
4379
+
ll != IB_LINK_LAYER_INFINIBAND ||
4380
+
!MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud))
4381
+
return ERR_PTR(-EOPNOTSUPP);
4382
+
4383
+
mplane = ib_alloc_device(mlx5_ib_dev, ib_dev);
4384
+
if (!mplane)
4385
+
return ERR_PTR(-ENOMEM);
4386
+
4387
+
mplane->port = kcalloc(mparent->num_plane * mparent->num_ports,
4388
+
sizeof(*mplane->port), GFP_KERNEL);
4389
+
if (!mplane->port) {
4390
+
ret = -ENOMEM;
4391
+
goto fail_kcalloc;
4392
+
}
4393
+
4394
+
mplane->ib_dev.type = type;
4395
+
mplane->mdev = mparent->mdev;
4396
+
mplane->num_ports = mparent->num_plane;
4397
+
mplane->sub_dev_name = name;
4398
+
4399
+
ret = __mlx5_ib_add(mplane, &plane_profile);
4400
+
if (ret)
4401
+
goto fail_ib_add;
4402
+
4403
+
mparent->smi_dev = mplane;
4404
+
return &mplane->ib_dev;
4405
+
4406
+
fail_ib_add:
4407
+
kfree(mplane->port);
4408
+
fail_kcalloc:
4409
+
ib_dealloc_device(&mplane->ib_dev);
4410
+
return ERR_PTR(ret);
4411
+
}
4412
+
4413
+
static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev)
4414
+
{
4415
+
struct mlx5_ib_dev *mdev = to_mdev(sub_dev);
4416
+
4417
+
to_mdev(sub_dev->parent)->smi_dev = NULL;
4418
+
__mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX);
4419
+
}
4420
+
4465
4421
static int mlx5r_mp_probe(struct auxiliary_device *adev,
4466
4422
const struct auxiliary_device_id *id)
4467
4423
{
···
4622
4412
dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4623
4413
if (!dev)
4624
4414
return -ENOMEM;
4415
+
4416
+
if (ll == IB_LINK_LAYER_INFINIBAND) {
4417
+
ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane);
4418
+
if (ret)
4419
+
goto fail;
4420
+
}
4421
+
4625
4422
dev->port = kcalloc(num_ports, sizeof(*dev->port),
4626
4423
GFP_KERNEL);
4627
4424
if (!dev->port) {
4628
-
ib_dealloc_device(&dev->ib_dev);
4629
-
return -ENOMEM;
4425
+
ret = -ENOMEM;
4426
+
goto fail;
4630
4427
}
4631
4428
4632
4429
dev->mdev = mdev;
···
4645
4428
profile = &pf_profile;
4646
4429
4647
4430
ret = __mlx5_ib_add(dev, profile);
4648
-
if (ret) {
4649
-
kfree(dev->port);
4650
-
ib_dealloc_device(&dev->ib_dev);
4651
-
return ret;
4652
-
}
4431
+
if (ret)
4432
+
goto fail_ib_add;
4653
4433
4654
4434
auxiliary_set_drvdata(adev, dev);
4655
4435
return 0;
4436
+
4437
+
fail_ib_add:
4438
+
kfree(dev->port);
4439
+
fail:
4440
+
ib_dealloc_device(&dev->ib_dev);
4441
+
return ret;
4656
4442
}
4657
4443
4658
4444
static void mlx5r_remove(struct auxiliary_device *adev)
+31
-1
drivers/infiniband/hw/mlx5/mlx5_ib.h
+31
-1
drivers/infiniband/hw/mlx5/mlx5_ib.h
···
115
115
__mlx5_bit_sz(typ, page_offset_fld), 0, scale, \
116
116
page_offset_quantized)
117
117
118
+
static inline unsigned long
119
+
mlx5_umem_dmabuf_find_best_pgsz(struct ib_umem_dmabuf *umem_dmabuf)
120
+
{
121
+
/*
122
+
* mkeys used for dmabuf are fixed at PAGE_SIZE because we must be able
123
+
* to hold any sgl after a move operation. Ideally the mkc page size
124
+
* could be changed at runtime to be optimal, but right now the driver
125
+
* cannot do that.
126
+
*/
127
+
return ib_umem_find_best_pgsz(&umem_dmabuf->umem, PAGE_SIZE,
128
+
umem_dmabuf->umem.iova);
129
+
}
130
+
118
131
enum {
119
132
MLX5_IB_MMAP_OFFSET_START = 9,
120
133
MLX5_IB_MMAP_OFFSET_END = 255,
···
764
751
*/
765
752
struct mutex lock;
766
753
unsigned int state;
754
+
/* Protects from repeat UMR QP creation */
755
+
struct mutex init_lock;
767
756
};
768
757
769
758
#define NUM_MKEYS_PER_PAGE \
···
837
822
838
823
struct mlx5_ib_resources {
839
824
struct ib_cq *c0;
825
+
struct mutex cq_lock;
840
826
u32 xrcdn0;
841
827
u32 xrcdn1;
842
828
struct ib_pd *p0;
843
829
struct ib_srq *s0;
844
830
struct ib_srq *s1;
831
+
struct mutex srq_lock;
845
832
struct mlx5_ib_port_resources ports[2];
846
833
};
847
834
···
1189
1172
#ifdef CONFIG_MLX5_MACSEC
1190
1173
struct mlx5_macsec macsec;
1191
1174
#endif
1175
+
1176
+
u8 num_plane;
1177
+
struct mlx5_ib_dev *smi_dev;
1178
+
const char *sub_dev_name;
1192
1179
};
1193
1180
1194
1181
static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
···
1291
1270
struct mlx5_user_mmap_entry, rdma_entry);
1292
1271
}
1293
1272
1273
+
int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev);
1274
+
int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev);
1294
1275
int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
1295
1276
struct mlx5_db *db);
1296
1277
void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
···
1332
1309
int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
1333
1310
size_t buflen, size_t *bc);
1334
1311
int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1335
-
struct ib_udata *udata);
1312
+
struct uverbs_attr_bundle *attrs);
1336
1313
int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1337
1314
int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1338
1315
int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
···
1532
1509
extern const struct uapi_definition mlx5_ib_flow_defs[];
1533
1510
extern const struct uapi_definition mlx5_ib_qos_defs[];
1534
1511
extern const struct uapi_definition mlx5_ib_std_types_defs[];
1512
+
extern const struct uapi_definition mlx5_ib_create_cq_defs[];
1535
1513
1536
1514
static inline int is_qp1(enum ib_qp_type qp_type)
1537
1515
{
···
1701
1677
int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
1702
1678
unsigned int index, const union ib_gid *gid,
1703
1679
const struct ib_gid_attr *attr);
1680
+
1681
+
static inline u32 smi_to_native_portnum(struct mlx5_ib_dev *dev, u32 port)
1682
+
{
1683
+
return (port - 1) / dev->num_ports + 1;
1684
+
}
1685
+
1704
1686
#endif /* MLX5_IB_H */
+9
drivers/infiniband/hw/mlx5/mr.c
+9
drivers/infiniband/hw/mlx5/mr.c
···
1470
1470
{
1471
1471
struct mlx5_ib_dev *dev = to_mdev(pd->device);
1472
1472
struct ib_umem *umem;
1473
+
int err;
1473
1474
1474
1475
if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM))
1475
1476
return ERR_PTR(-EOPNOTSUPP);
1476
1477
1477
1478
mlx5_ib_dbg(dev, "start 0x%llx, iova 0x%llx, length 0x%llx, access_flags 0x%x\n",
1478
1479
start, iova, length, access_flags);
1480
+
1481
+
err = mlx5r_umr_resource_init(dev);
1482
+
if (err)
1483
+
return ERR_PTR(err);
1479
1484
1480
1485
if (access_flags & IB_ACCESS_ON_DEMAND)
1481
1486
return create_user_odp_mr(pd, start, length, iova, access_flags,
···
1527
1522
mlx5_ib_dbg(dev,
1528
1523
"offset 0x%llx, virt_addr 0x%llx, length 0x%llx, fd %d, access_flags 0x%x\n",
1529
1524
offset, virt_addr, length, fd, access_flags);
1525
+
1526
+
err = mlx5r_umr_resource_init(dev);
1527
+
if (err)
1528
+
return ERR_PTR(err);
1530
1529
1531
1530
/* dmabuf requires xlt update via umr to work. */
1532
1531
if (!mlx5r_umr_can_load_pas(dev, length))
+2
-4
drivers/infiniband/hw/mlx5/odp.c
+2
-4
drivers/infiniband/hw/mlx5/odp.c
···
705
705
return err;
706
706
}
707
707
708
-
page_size = mlx5_umem_find_best_pgsz(&umem_dmabuf->umem, mkc,
709
-
log_page_size, 0,
710
-
umem_dmabuf->umem.iova);
711
-
if (unlikely(page_size < PAGE_SIZE)) {
708
+
page_size = mlx5_umem_dmabuf_find_best_pgsz(umem_dmabuf);
709
+
if (!page_size) {
712
710
ib_umem_dmabuf_unmap_pages(umem_dmabuf);
713
711
err = -EINVAL;
714
712
} else {
+10
-1
drivers/infiniband/hw/mlx5/qp.c
+10
-1
drivers/infiniband/hw/mlx5/qp.c
···
3234
3234
enum ib_qp_type type;
3235
3235
int err;
3236
3236
3237
+
err = mlx5_ib_dev_res_srq_init(dev);
3238
+
if (err)
3239
+
return err;
3240
+
3237
3241
err = check_qp_type(dev, attr, &type);
3238
3242
if (err)
3239
3243
return err;
···
4217
4213
4218
4214
/* todo implement counter_index functionality */
4219
4215
4220
-
if (is_sqp(qp->type))
4216
+
if (dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI && is_qp0(qp->type)) {
4217
+
MLX5_SET(ads, pri_path, vhca_port_num,
4218
+
smi_to_native_portnum(dev, qp->port));
4219
+
if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)
4220
+
MLX5_SET(ads, pri_path, plane_index, qp->port);
4221
+
} else if (is_sqp(qp->type))
4221
4222
MLX5_SET(ads, pri_path, vhca_port_num, qp->port);
4222
4223
4223
4224
if (attr_mask & IB_QP_PORT)
+9
-4
drivers/infiniband/hw/mlx5/qpc.c
+9
-4
drivers/infiniband/hw/mlx5/qpc.c
···
249
249
if (err)
250
250
goto err_cmd;
251
251
252
-
mlx5_debug_qp_add(dev->mdev, qp);
252
+
if (dev->ib_dev.type != RDMA_DEVICE_TYPE_SMI)
253
+
mlx5_debug_qp_add(dev->mdev, qp);
253
254
254
255
return 0;
255
256
···
308
307
{
309
308
u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
310
309
311
-
mlx5_debug_qp_remove(dev->mdev, qp);
310
+
if (dev->ib_dev.type != RDMA_DEVICE_TYPE_SMI)
311
+
mlx5_debug_qp_remove(dev->mdev, qp);
312
312
313
313
destroy_resource_common(dev, qp);
314
314
···
506
504
spin_lock_init(&table->lock);
507
505
INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
508
506
xa_init(&table->dct_xa);
509
-
mlx5_qp_debugfs_init(dev->mdev);
507
+
508
+
if (dev->ib_dev.type != RDMA_DEVICE_TYPE_SMI)
509
+
mlx5_qp_debugfs_init(dev->mdev);
510
510
511
511
table->nb.notifier_call = rsc_event_notifier;
512
512
mlx5_notifier_register(dev->mdev, &table->nb);
···
521
517
struct mlx5_qp_table *table = &dev->qp_table;
522
518
523
519
mlx5_notifier_unregister(dev->mdev, &table->nb);
524
-
mlx5_qp_debugfs_cleanup(dev->mdev);
520
+
if (dev->ib_dev.type != RDMA_DEVICE_TYPE_SMI)
521
+
mlx5_qp_debugfs_cleanup(dev->mdev);
525
522
}
526
523
527
524
int mlx5_core_qp_query(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp,
+4
drivers/infiniband/hw/mlx5/srq.c
+4
drivers/infiniband/hw/mlx5/srq.c
+42
-13
drivers/infiniband/hw/mlx5/umr.c
+42
-13
drivers/infiniband/hw/mlx5/umr.c
···
135
135
int mlx5r_umr_resource_init(struct mlx5_ib_dev *dev)
136
136
{
137
137
struct ib_qp_init_attr init_attr = {};
138
-
struct ib_pd *pd;
139
138
struct ib_cq *cq;
140
139
struct ib_qp *qp;
141
-
int ret;
140
+
int ret = 0;
142
141
143
-
pd = ib_alloc_pd(&dev->ib_dev, 0);
144
-
if (IS_ERR(pd)) {
145
-
mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
146
-
return PTR_ERR(pd);
147
-
}
142
+
143
+
/*
144
+
* UMR qp is set once, never changed until device unload.
145
+
* Avoid taking the mutex if initialization is already done.
146
+
*/
147
+
if (dev->umrc.qp)
148
+
return 0;
149
+
150
+
mutex_lock(&dev->umrc.init_lock);
151
+
/* First user allocates the UMR resources. Skip if already allocated. */
152
+
if (dev->umrc.qp)
153
+
goto unlock;
148
154
149
155
cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
150
156
if (IS_ERR(cq)) {
151
157
mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
152
158
ret = PTR_ERR(cq);
153
-
goto destroy_pd;
159
+
goto unlock;
154
160
}
155
161
156
162
init_attr.send_cq = cq;
···
166
160
init_attr.cap.max_send_sge = 1;
167
161
init_attr.qp_type = MLX5_IB_QPT_REG_UMR;
168
162
init_attr.port_num = 1;
169
-
qp = ib_create_qp(pd, &init_attr);
163
+
qp = ib_create_qp(dev->umrc.pd, &init_attr);
170
164
if (IS_ERR(qp)) {
171
165
mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
172
166
ret = PTR_ERR(qp);
···
177
171
if (ret)
178
172
goto destroy_qp;
179
173
180
-
dev->umrc.qp = qp;
181
174
dev->umrc.cq = cq;
182
-
dev->umrc.pd = pd;
183
175
184
176
sema_init(&dev->umrc.sem, MAX_UMR_WR);
185
177
mutex_init(&dev->umrc.lock);
186
178
dev->umrc.state = MLX5_UMR_STATE_ACTIVE;
179
+
dev->umrc.qp = qp;
187
180
181
+
mutex_unlock(&dev->umrc.init_lock);
188
182
return 0;
189
183
190
184
destroy_qp:
191
185
ib_destroy_qp(qp);
192
186
destroy_cq:
193
187
ib_free_cq(cq);
194
-
destroy_pd:
195
-
ib_dealloc_pd(pd);
188
+
unlock:
189
+
mutex_unlock(&dev->umrc.init_lock);
196
190
return ret;
197
191
}
198
192
···
200
194
{
201
195
if (dev->umrc.state == MLX5_UMR_STATE_UNINIT)
202
196
return;
197
+
mutex_destroy(&dev->umrc.lock);
198
+
/* After device init, UMR cp/qp are not unset during the lifetime. */
203
199
ib_destroy_qp(dev->umrc.qp);
204
200
ib_free_cq(dev->umrc.cq);
201
+
}
202
+
203
+
int mlx5r_umr_init(struct mlx5_ib_dev *dev)
204
+
{
205
+
struct ib_pd *pd;
206
+
207
+
pd = ib_alloc_pd(&dev->ib_dev, 0);
208
+
if (IS_ERR(pd)) {
209
+
mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
210
+
return PTR_ERR(pd);
211
+
}
212
+
dev->umrc.pd = pd;
213
+
214
+
mutex_init(&dev->umrc.init_lock);
215
+
216
+
return 0;
217
+
}
218
+
219
+
void mlx5r_umr_cleanup(struct mlx5_ib_dev *dev)
220
+
{
221
+
mutex_destroy(&dev->umrc.init_lock);
205
222
ib_dealloc_pd(dev->umrc.pd);
206
223
}
207
224
+3
drivers/infiniband/hw/mlx5/umr.h
+3
drivers/infiniband/hw/mlx5/umr.h
···
16
16
int mlx5r_umr_resource_init(struct mlx5_ib_dev *dev);
17
17
void mlx5r_umr_resource_cleanup(struct mlx5_ib_dev *dev);
18
18
19
+
int mlx5r_umr_init(struct mlx5_ib_dev *dev);
20
+
void mlx5r_umr_cleanup(struct mlx5_ib_dev *dev);
21
+
19
22
static inline bool mlx5r_umr_can_load_pas(struct mlx5_ib_dev *dev,
20
23
size_t length)
21
24
{
+2
-1
drivers/infiniband/hw/mthca/mthca_provider.c
+2
-1
drivers/infiniband/hw/mthca/mthca_provider.c
···
574
574
575
575
static int mthca_create_cq(struct ib_cq *ibcq,
576
576
const struct ib_cq_init_attr *attr,
577
-
struct ib_udata *udata)
577
+
struct uverbs_attr_bundle *attrs)
578
578
{
579
+
struct ib_udata *udata = &attrs->driver_udata;
579
580
struct ib_device *ibdev = ibcq->device;
580
581
int entries = attr->cqe;
581
582
struct mthca_create_cq ucmd;
+11
-11
drivers/infiniband/hw/ocrdma/ocrdma_stats.c
+11
-11
drivers/infiniband/hw/ocrdma/ocrdma_stats.c
···
46
46
47
47
static struct dentry *ocrdma_dbgfs_dir;
48
48
49
-
static int ocrdma_add_stat(char *start, char *pcur,
49
+
static noinline_for_stack int ocrdma_add_stat(char *start, char *pcur,
50
50
char *name, u64 count)
51
51
{
52
52
char buff[128] = {0};
···
99
99
kfree(mem->debugfs_mem);
100
100
}
101
101
102
-
static char *ocrdma_resource_stats(struct ocrdma_dev *dev)
102
+
static noinline_for_stack char *ocrdma_resource_stats(struct ocrdma_dev *dev)
103
103
{
104
104
char *stats = dev->stats_mem.debugfs_mem, *pcur;
105
105
struct ocrdma_rdma_stats_resp *rdma_stats =
···
216
216
return stats;
217
217
}
218
218
219
-
static char *ocrdma_rx_stats(struct ocrdma_dev *dev)
219
+
static noinline_for_stack char *ocrdma_rx_stats(struct ocrdma_dev *dev)
220
220
{
221
221
char *stats = dev->stats_mem.debugfs_mem, *pcur;
222
222
struct ocrdma_rdma_stats_resp *rdma_stats =
···
284
284
rx_stats->roce_frame_bytes_hi))/4;
285
285
}
286
286
287
-
static char *ocrdma_tx_stats(struct ocrdma_dev *dev)
287
+
static noinline_for_stack char *ocrdma_tx_stats(struct ocrdma_dev *dev)
288
288
{
289
289
char *stats = dev->stats_mem.debugfs_mem, *pcur;
290
290
struct ocrdma_rdma_stats_resp *rdma_stats =
···
358
358
tx_stats->read_rsp_bytes_hi))/4;
359
359
}
360
360
361
-
static char *ocrdma_wqe_stats(struct ocrdma_dev *dev)
361
+
static noinline_for_stack char *ocrdma_wqe_stats(struct ocrdma_dev *dev)
362
362
{
363
363
char *stats = dev->stats_mem.debugfs_mem, *pcur;
364
364
struct ocrdma_rdma_stats_resp *rdma_stats =
···
391
391
return stats;
392
392
}
393
393
394
-
static char *ocrdma_db_errstats(struct ocrdma_dev *dev)
394
+
static noinline_for_stack char *ocrdma_db_errstats(struct ocrdma_dev *dev)
395
395
{
396
396
char *stats = dev->stats_mem.debugfs_mem, *pcur;
397
397
struct ocrdma_rdma_stats_resp *rdma_stats =
···
412
412
return stats;
413
413
}
414
414
415
-
static char *ocrdma_rxqp_errstats(struct ocrdma_dev *dev)
415
+
static noinline_for_stack char *ocrdma_rxqp_errstats(struct ocrdma_dev *dev)
416
416
{
417
417
char *stats = dev->stats_mem.debugfs_mem, *pcur;
418
418
struct ocrdma_rdma_stats_resp *rdma_stats =
···
438
438
return stats;
439
439
}
440
440
441
-
static char *ocrdma_txqp_errstats(struct ocrdma_dev *dev)
441
+
static noinline_for_stack char *ocrdma_txqp_errstats(struct ocrdma_dev *dev)
442
442
{
443
443
char *stats = dev->stats_mem.debugfs_mem, *pcur;
444
444
struct ocrdma_rdma_stats_resp *rdma_stats =
···
462
462
return stats;
463
463
}
464
464
465
-
static char *ocrdma_tx_dbg_stats(struct ocrdma_dev *dev)
465
+
static noinline_for_stack char *ocrdma_tx_dbg_stats(struct ocrdma_dev *dev)
466
466
{
467
467
int i;
468
468
char *pstats = dev->stats_mem.debugfs_mem;
···
480
480
return dev->stats_mem.debugfs_mem;
481
481
}
482
482
483
-
static char *ocrdma_rx_dbg_stats(struct ocrdma_dev *dev)
483
+
static noinline_for_stack char *ocrdma_rx_dbg_stats(struct ocrdma_dev *dev)
484
484
{
485
485
int i;
486
486
char *pstats = dev->stats_mem.debugfs_mem;
···
498
498
return dev->stats_mem.debugfs_mem;
499
499
}
500
500
501
-
static char *ocrdma_driver_dbg_stats(struct ocrdma_dev *dev)
501
+
static noinline_for_stack char *ocrdma_driver_dbg_stats(struct ocrdma_dev *dev)
502
502
{
503
503
char *stats = dev->stats_mem.debugfs_mem, *pcur;
504
504
+2
-1
drivers/infiniband/hw/ocrdma/ocrdma_verbs.c
+2
-1
drivers/infiniband/hw/ocrdma/ocrdma_verbs.c
···
963
963
}
964
964
965
965
int ocrdma_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
966
-
struct ib_udata *udata)
966
+
struct uverbs_attr_bundle *attrs)
967
967
{
968
+
struct ib_udata *udata = &attrs->driver_udata;
968
969
struct ib_device *ibdev = ibcq->device;
969
970
int entries = attr->cqe;
970
971
struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
+1
-1
drivers/infiniband/hw/ocrdma/ocrdma_verbs.h
+1
-1
drivers/infiniband/hw/ocrdma/ocrdma_verbs.h
···
70
70
int ocrdma_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
71
71
72
72
int ocrdma_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
73
-
struct ib_udata *udata);
73
+
struct uverbs_attr_bundle *attrs);
74
74
int ocrdma_resize_cq(struct ib_cq *, int cqe, struct ib_udata *);
75
75
int ocrdma_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata);
76
76
+2
-1
drivers/infiniband/hw/qedr/verbs.c
+2
-1
drivers/infiniband/hw/qedr/verbs.c
···
900
900
}
901
901
902
902
int qedr_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
903
-
struct ib_udata *udata)
903
+
struct uverbs_attr_bundle *attrs)
904
904
{
905
+
struct ib_udata *udata = &attrs->driver_udata;
905
906
struct ib_device *ibdev = ibcq->device;
906
907
struct qedr_ucontext *ctx = rdma_udata_to_drv_context(
907
908
udata, struct qedr_ucontext, ibucontext);
+1
-1
drivers/infiniband/hw/qedr/verbs.h
+1
-1
drivers/infiniband/hw/qedr/verbs.h
···
52
52
int qedr_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata);
53
53
int qedr_dealloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata);
54
54
int qedr_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
55
-
struct ib_udata *udata);
55
+
struct uverbs_attr_bundle *attrs);
56
56
int qedr_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata);
57
57
int qedr_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
58
58
int qedr_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *attrs,
+1
-1
drivers/infiniband/hw/qib/qib_init.c
+1
-1
drivers/infiniband/hw/qib/qib_init.c
+1
-1
drivers/infiniband/hw/qib/qib_verbs.c
+1
-1
drivers/infiniband/hw/qib/qib_verbs.c
···
1551
1551
ibdev->dev.parent = &dd->pcidev->dev;
1552
1552
1553
1553
snprintf(ibdev->node_desc, sizeof(ibdev->node_desc),
1554
-
"Intel Infiniband HCA %s", init_utsname()->nodename);
1554
+
"Intel Infiniband HCA %.42s", init_utsname()->nodename);
1555
1555
1556
1556
/*
1557
1557
* Fill in rvt info object.
+1
-1
drivers/infiniband/hw/usnic/usnic_ib_verbs.c
+1
-1
drivers/infiniband/hw/usnic/usnic_ib_verbs.c
+1
-1
drivers/infiniband/hw/usnic/usnic_ib_verbs.h
+1
-1
drivers/infiniband/hw/usnic/usnic_ib_verbs.h
···
56
56
int usnic_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
57
57
int attr_mask, struct ib_udata *udata);
58
58
int usnic_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
59
-
struct ib_udata *udata);
59
+
struct uverbs_attr_bundle *attrs);
60
60
int usnic_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
61
61
struct ib_mr *usnic_ib_reg_mr(struct ib_pd *pd, u64 start, u64 length,
62
62
u64 virt_addr, int access_flags,
+3
-2
drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c
+3
-2
drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c
···
94
94
* pvrdma_create_cq - create completion queue
95
95
* @ibcq: Allocated CQ
96
96
* @attr: completion queue attributes
97
-
* @udata: user data
97
+
* @attrs: bundle
98
98
*
99
99
* @return: 0 on success
100
100
*/
101
101
int pvrdma_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
102
-
struct ib_udata *udata)
102
+
struct uverbs_attr_bundle *attrs)
103
103
{
104
+
struct ib_udata *udata = &attrs->driver_udata;
104
105
struct ib_device *ibdev = ibcq->device;
105
106
int entries = attr->cqe;
106
107
struct pvrdma_dev *dev = to_vdev(ibdev);
+1
-1
drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h
+1
-1
drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h
···
375
375
int pvrdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
376
376
int sg_nents, unsigned int *sg_offset);
377
377
int pvrdma_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
378
-
struct ib_udata *udata);
378
+
struct uverbs_attr_bundle *attrs);
379
379
int pvrdma_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
380
380
int pvrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
381
381
int pvrdma_req_notify_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
+4
-2
drivers/infiniband/sw/rdmavt/cq.c
+4
-2
drivers/infiniband/sw/rdmavt/cq.c
···
5
5
6
6
#include <linux/slab.h>
7
7
#include <linux/vmalloc.h>
8
+
#include <rdma/uverbs_ioctl.h>
8
9
#include "cq.h"
9
10
#include "vt.h"
10
11
#include "trace.h"
···
150
149
* rvt_create_cq - create a completion queue
151
150
* @ibcq: Allocated CQ
152
151
* @attr: creation attributes
153
-
* @udata: user data for libibverbs.so
152
+
* @attrs: uverbs bundle
154
153
*
155
154
* Called by ib_create_cq() in the generic verbs code.
156
155
*
157
156
* Return: 0 on success
158
157
*/
159
158
int rvt_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
160
-
struct ib_udata *udata)
159
+
struct uverbs_attr_bundle *attrs)
161
160
{
161
+
struct ib_udata *udata = &attrs->driver_udata;
162
162
struct ib_device *ibdev = ibcq->device;
163
163
struct rvt_dev_info *rdi = ib_to_rvt(ibdev);
164
164
struct rvt_cq *cq = ibcq_to_rvtcq(ibcq);
+1
-1
drivers/infiniband/sw/rdmavt/cq.h
+1
-1
drivers/infiniband/sw/rdmavt/cq.h
···
10
10
#include <rdma/rdmavt_cq.h>
11
11
12
12
int rvt_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
13
-
struct ib_udata *udata);
13
+
struct uverbs_attr_bundle *attrs);
14
14
int rvt_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata);
15
15
int rvt_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags notify_flags);
16
16
int rvt_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata);
+1
drivers/infiniband/sw/rxe/rxe_net.c
+1
drivers/infiniband/sw/rxe/rxe_net.c
+4
-3
drivers/infiniband/sw/rxe/rxe_req.c
+4
-3
drivers/infiniband/sw/rxe/rxe_req.c
···
424
424
int paylen;
425
425
int solicited;
426
426
u32 qp_num;
427
-
int ack_req;
427
+
int ack_req = 0;
428
428
429
429
/* length from start of bth to end of icrc */
430
430
paylen = rxe_opcode[opcode].length + payload + pad + RXE_ICRC_SIZE;
···
445
445
qp_num = (pkt->mask & RXE_DETH_MASK) ? ibwr->wr.ud.remote_qpn :
446
446
qp->attr.dest_qp_num;
447
447
448
-
ack_req = ((pkt->mask & RXE_END_MASK) ||
449
-
(qp->req.noack_pkts++ > RXE_MAX_PKT_PER_ACK));
448
+
if (qp_type(qp) != IB_QPT_UD && qp_type(qp) != IB_QPT_UC)
449
+
ack_req = ((pkt->mask & RXE_END_MASK) ||
450
+
(qp->req.noack_pkts++ > RXE_MAX_PKT_PER_ACK));
450
451
if (ack_req)
451
452
qp->req.noack_pkts = 0;
452
453
+2
-1
drivers/infiniband/sw/rxe/rxe_verbs.c
+2
-1
drivers/infiniband/sw/rxe/rxe_verbs.c
···
1053
1053
1054
1054
/* cq */
1055
1055
static int rxe_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1056
-
struct ib_udata *udata)
1056
+
struct uverbs_attr_bundle *attrs)
1057
1057
{
1058
+
struct ib_udata *udata = &attrs->driver_udata;
1058
1059
struct ib_device *dev = ibcq->device;
1059
1060
struct rxe_dev *rxe = to_rdev(dev);
1060
1061
struct rxe_cq *cq = to_rcq(ibcq);
+1
drivers/infiniband/sw/siw/siw_main.c
+1
drivers/infiniband/sw/siw/siw_main.c
+3
-2
drivers/infiniband/sw/siw/siw_verbs.c
+3
-2
drivers/infiniband/sw/siw/siw_verbs.c
···
1124
1124
*
1125
1125
* @base_cq: CQ as allocated by RDMA midlayer
1126
1126
* @attr: Initial CQ attributes
1127
-
* @udata: relates to user context
1127
+
* @attrs: uverbs bundle
1128
1128
*/
1129
1129
1130
1130
int siw_create_cq(struct ib_cq *base_cq, const struct ib_cq_init_attr *attr,
1131
-
struct ib_udata *udata)
1131
+
struct uverbs_attr_bundle *attrs)
1132
1132
{
1133
+
struct ib_udata *udata = &attrs->driver_udata;
1133
1134
struct siw_device *sdev = to_siw_dev(base_cq->device);
1134
1135
struct siw_cq *cq = to_siw_cq(base_cq);
1135
1136
int rv, size = attr->cqe;
+1
-1
drivers/infiniband/sw/siw/siw_verbs.h
+1
-1
drivers/infiniband/sw/siw/siw_verbs.h
···
43
43
int siw_query_device(struct ib_device *base_dev, struct ib_device_attr *attr,
44
44
struct ib_udata *udata);
45
45
int siw_create_cq(struct ib_cq *base_cq, const struct ib_cq_init_attr *attr,
46
-
struct ib_udata *udata);
46
+
struct uverbs_attr_bundle *attrs);
47
47
int siw_query_port(struct ib_device *base_dev, u32 port,
48
48
struct ib_port_attr *attr);
49
49
int siw_query_gid(struct ib_device *base_dev, u32 port, int idx,
-3
drivers/infiniband/ulp/isert/ib_isert.c
-3
drivers/infiniband/ulp/isert/ib_isert.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en/port.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en/port.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
···
1195
1195
bool ext;
1196
1196
int err;
1197
1197
1198
-
err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
1198
+
err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1, 0);
1199
1199
if (err) {
1200
1200
netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
1201
1201
__func__, err);
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c
+6
-4
drivers/net/ethernet/mellanox/mlx5/core/port.c
+6
-4
drivers/net/ethernet/mellanox/mlx5/core/port.c
···
144
144
EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
145
145
146
146
int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
147
-
int ptys_size, int proto_mask, u8 local_port)
147
+
int ptys_size, int proto_mask,
148
+
u8 local_port, u8 plane_index)
148
149
{
149
150
u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
150
151
151
152
MLX5_SET(ptys_reg, in, local_port, local_port);
153
+
MLX5_SET(ptys_reg, in, plane_ind, plane_index);
152
154
MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
153
155
return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
154
156
ptys_size, MLX5_REG_PTYS, 0, 0);
···
169
167
}
170
168
171
169
int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
172
-
u16 *proto_oper, u8 local_port)
170
+
u16 *proto_oper, u8 local_port, u8 plane_index)
173
171
{
174
172
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
175
173
int err;
176
174
177
175
err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB,
178
-
local_port);
176
+
local_port, plane_index);
179
177
if (err)
180
178
return err;
181
179
···
1116
1114
if (!eproto)
1117
1115
return -EINVAL;
1118
1116
1119
-
err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_EN, port);
1117
+
err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_EN, port, 0);
1120
1118
if (err)
1121
1119
return err;
1122
1120
+1
drivers/net/ethernet/mellanox/mlx5/core/vport.c
+1
drivers/net/ethernet/mellanox/mlx5/core/vport.c
+1
drivers/net/ethernet/microsoft/mana/gdma_main.c
+1
drivers/net/ethernet/microsoft/mana/gdma_main.c
+19
drivers/net/ethernet/microsoft/mana/mana_en.c
+19
drivers/net/ethernet/microsoft/mana/mana_en.c
···
3007
3007
gd->gdma_context = NULL;
3008
3008
kfree(ac);
3009
3009
}
3010
+
3011
+
struct net_device *mana_get_primary_netdev_rcu(struct mana_context *ac, u32 port_index)
3012
+
{
3013
+
struct net_device *ndev;
3014
+
3015
+
RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
3016
+
"Taking primary netdev without holding the RCU read lock");
3017
+
if (port_index >= ac->num_ports)
3018
+
return NULL;
3019
+
3020
+
/* When mana is used in netvsc, the upper netdevice should be returned. */
3021
+
if (ac->ports[port_index]->flags & IFF_SLAVE)
3022
+
ndev = netdev_master_upper_dev_get_rcu(ac->ports[port_index]);
3023
+
else
3024
+
ndev = ac->ports[port_index];
3025
+
3026
+
return ndev;
3027
+
}
3028
+
EXPORT_SYMBOL_NS(mana_get_primary_netdev_rcu, NET_MANA);
+1
include/linux/mlx5/device.h
+1
include/linux/mlx5/device.h
+1
include/linux/mlx5/driver.h
+1
include/linux/mlx5/driver.h
+54
-7
include/linux/mlx5/mlx5_ifc.h
+54
-7
include/linux/mlx5/mlx5_ifc.h
···
793
793
u8 reserved_at_2[0xe];
794
794
u8 pkey_index[0x10];
795
795
796
-
u8 reserved_at_20[0x8];
796
+
u8 plane_index[0x8];
797
797
u8 grh[0x1];
798
798
u8 mlid[0x7];
799
799
u8 rlid[0x10];
···
1992
1992
u8 reserved_at_c0[0x8];
1993
1993
u8 migration_multi_load[0x1];
1994
1994
u8 migration_tracking_state[0x1];
1995
-
u8 reserved_at_ca[0x6];
1995
+
u8 multiplane_qp_ud[0x1];
1996
+
u8 reserved_at_cb[0x5];
1996
1997
u8 migration_in_chunks[0x1];
1997
1998
u8 reserved_at_d1[0x1];
1998
1999
u8 sf_eq_usage[0x1];
···
2662
2661
u8 reserved_at_a0[0x80];
2663
2662
2664
2663
u8 port_xmit_wait[0x20];
2664
+
};
2665
+
2666
+
struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
2667
+
u8 reserved_at_0[0x300];
2668
+
2669
+
u8 port_xmit_data_high[0x20];
2670
+
2671
+
u8 port_xmit_data_low[0x20];
2672
+
2673
+
u8 port_rcv_data_high[0x20];
2674
+
2675
+
u8 port_rcv_data_low[0x20];
2676
+
2677
+
u8 port_xmit_pkts_high[0x20];
2678
+
2679
+
u8 port_xmit_pkts_low[0x20];
2680
+
2681
+
u8 port_rcv_pkts_high[0x20];
2682
+
2683
+
u8 port_rcv_pkts_low[0x20];
2684
+
2685
+
u8 reserved_at_400[0x80];
2686
+
2687
+
u8 port_unicast_xmit_pkts_high[0x20];
2688
+
2689
+
u8 port_unicast_xmit_pkts_low[0x20];
2690
+
2691
+
u8 port_multicast_xmit_pkts_high[0x20];
2692
+
2693
+
u8 port_multicast_xmit_pkts_low[0x20];
2694
+
2695
+
u8 port_unicast_rcv_pkts_high[0x20];
2696
+
2697
+
u8 port_unicast_rcv_pkts_low[0x20];
2698
+
2699
+
u8 port_multicast_rcv_pkts_high[0x20];
2700
+
2701
+
u8 port_multicast_rcv_pkts_low[0x20];
2702
+
2703
+
u8 reserved_at_580[0x240];
2665
2704
};
2666
2705
2667
2706
struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
···
4226
4185
u8 has_smi[0x1];
4227
4186
u8 has_raw[0x1];
4228
4187
u8 grh_required[0x1];
4229
-
u8 reserved_at_104[0xc];
4188
+
u8 reserved_at_104[0x4];
4189
+
u8 num_port_plane[0x8];
4230
4190
u8 port_physical_state[0x4];
4231
4191
u8 vport_state_policy[0x4];
4232
4192
u8 port_state[0x4];
···
4596
4554
struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4597
4555
struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4598
4556
struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4557
+
struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4599
4558
struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4600
4559
struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4601
4560
u8 reserved_at_0[0x7c0];
···
7748
7705
u8 op_mod[0x10];
7749
7706
7750
7707
u8 remote_lid[0x10];
7751
-
u8 reserved_at_50[0x8];
7708
+
u8 plane_index[0x8];
7752
7709
u8 port[0x8];
7753
7710
7754
7711
u8 reserved_at_60[0x20];
···
9677
9634
u8 an_disable_cap[0x1];
9678
9635
u8 reserved_at_3[0x5];
9679
9636
u8 local_port[0x8];
9680
-
u8 reserved_at_10[0xd];
9637
+
u8 reserved_at_10[0x8];
9638
+
u8 plane_ind[0x4];
9639
+
u8 reserved_at_1c[0x1];
9681
9640
u8 proto_mask[0x3];
9682
9641
9683
9642
u8 an_status[0x4];
···
9905
9860
u8 grp[0x6];
9906
9861
9907
9862
u8 clr[0x1];
9908
-
u8 reserved_at_21[0x1c];
9909
-
u8 prio_tc[0x3];
9863
+
u8 reserved_at_21[0x13];
9864
+
u8 plane_ind[0x4];
9865
+
u8 reserved_at_38[0x3];
9866
+
u8 prio_tc[0x5];
9910
9867
9911
9868
union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9912
9869
};
+3
-2
include/linux/mlx5/port.h
+3
-2
include/linux/mlx5/port.h
···
155
155
156
156
int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
157
157
int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
158
-
int ptys_size, int proto_mask, u8 local_port);
158
+
int ptys_size, int proto_mask,
159
+
u8 local_port, u8 plane_index);
159
160
160
161
int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
161
-
u16 *proto_oper, u8 local_port);
162
+
u16 *proto_oper, u8 local_port, u8 plane_index);
162
163
void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
163
164
int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
164
165
enum mlx5_port_status status);
+6
-3
include/linux/mlx5/qp.h
+6
-3
include/linux/mlx5/qp.h
···
576
576
577
577
static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
578
578
{
579
-
return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
580
-
MLX5_TIMESTAMP_FORMAT_FREE_RUNNING :
581
-
MLX5_TIMESTAMP_FORMAT_DEFAULT;
579
+
u8 supported_ts_cap = mlx5_get_roce_state(dev) ?
580
+
MLX5_CAP_ROCE(dev, qp_ts_format) :
581
+
MLX5_CAP_GEN(dev, sq_ts_format);
582
+
583
+
return supported_ts_cap ? MLX5_TIMESTAMP_FORMAT_DEFAULT :
584
+
MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
582
585
}
583
586
584
587
#endif /* MLX5_QP_H */
+1
include/net/mana/gdma.h
+1
include/net/mana/gdma.h
+2
include/net/mana/mana.h
+2
include/net/mana/mana.h
···
798
798
int mana_cfg_vport(struct mana_port_context *apc, u32 protection_dom_id,
799
799
u32 doorbell_pg_id);
800
800
void mana_uncfg_vport(struct mana_port_context *apc);
801
+
802
+
struct net_device *mana_get_primary_netdev_rcu(struct mana_context *ac, u32 port_index);
801
803
#endif /* _MANA_H */
+56
-1
include/rdma/ib_verbs.h
+56
-1
include/rdma/ib_verbs.h
···
1788
1788
struct list_head rdma_mrs;
1789
1789
struct list_head sig_mrs;
1790
1790
struct ib_srq *srq;
1791
+
struct completion srq_completion;
1791
1792
struct ib_xrcd *xrcd; /* XRC TGT QPs only */
1792
1793
struct list_head xrcd_list;
1793
1794
···
1798
1797
struct ib_qp *real_qp;
1799
1798
struct ib_uqp_object *uobject;
1800
1799
void (*event_handler)(struct ib_event *, void *);
1800
+
void (*registered_event_handler)(struct ib_event *, void *);
1801
1801
void *qp_context;
1802
1802
/* sgid_attrs associated with the AV's */
1803
1803
const struct ib_gid_attr *av_sgid_attr;
···
2465
2463
int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
2466
2464
int (*destroy_qp)(struct ib_qp *qp, struct ib_udata *udata);
2467
2465
int (*create_cq)(struct ib_cq *cq, const struct ib_cq_init_attr *attr,
2468
-
struct ib_udata *udata);
2466
+
struct uverbs_attr_bundle *attrs);
2469
2467
int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
2470
2468
int (*destroy_cq)(struct ib_cq *cq, struct ib_udata *udata);
2471
2469
int (*resize_cq)(struct ib_cq *cq, int cqe, struct ib_udata *udata);
···
2663
2661
*/
2664
2662
int (*get_numa_node)(struct ib_device *dev);
2665
2663
2664
+
/**
2665
+
* add_sub_dev - Add a sub IB device
2666
+
*/
2667
+
struct ib_device *(*add_sub_dev)(struct ib_device *parent,
2668
+
enum rdma_nl_dev_type type,
2669
+
const char *name);
2670
+
2671
+
/**
2672
+
* del_sub_dev - Delete a sub IB device
2673
+
*/
2674
+
void (*del_sub_dev)(struct ib_device *sub_dev);
2675
+
2666
2676
DECLARE_RDMA_OBJ_SIZE(ib_ah);
2667
2677
DECLARE_RDMA_OBJ_SIZE(ib_counters);
2668
2678
DECLARE_RDMA_OBJ_SIZE(ib_cq);
···
2785
2771
char iw_ifname[IFNAMSIZ];
2786
2772
u32 iw_driver_flags;
2787
2773
u32 lag_flags;
2774
+
2775
+
/* A parent device has a list of sub-devices */
2776
+
struct mutex subdev_lock;
2777
+
struct list_head subdev_list_head;
2778
+
2779
+
/* A sub device has a type and a parent */
2780
+
enum rdma_nl_dev_type type;
2781
+
struct ib_device *parent;
2782
+
struct list_head subdev_list;
2783
+
2784
+
enum rdma_nl_name_assign_type name_assign_type;
2788
2785
};
2789
2786
2790
2787
static inline void *rdma_zalloc_obj(struct ib_device *dev, size_t size,
···
4664
4639
return RDMA_AH_ATTR_TYPE_OPA;
4665
4640
return RDMA_AH_ATTR_TYPE_IB;
4666
4641
}
4642
+
if (dev->type == RDMA_DEVICE_TYPE_SMI)
4643
+
return RDMA_AH_ATTR_TYPE_IB;
4667
4644
4668
4645
return RDMA_AH_ATTR_TYPE_UNDEFINED;
4669
4646
}
···
4847
4820
4848
4821
const struct ib_port_immutable*
4849
4822
ib_port_immutable_read(struct ib_device *dev, unsigned int port);
4823
+
4824
+
/** ib_add_sub_device - Add a sub IB device on an existing one
4825
+
*
4826
+
* @parent: The IB device that needs to add a sub device
4827
+
* @type: The type of the new sub device
4828
+
* @name: The name of the new sub device
4829
+
*
4830
+
*
4831
+
* Return 0 on success, an error code otherwise
4832
+
*/
4833
+
int ib_add_sub_device(struct ib_device *parent,
4834
+
enum rdma_nl_dev_type type,
4835
+
const char *name);
4836
+
4837
+
4838
+
/** ib_del_sub_device_and_put - Delect an IB sub device while holding a 'get'
4839
+
*
4840
+
* @sub: The sub device that is going to be deleted
4841
+
*
4842
+
* Return 0 on success, an error code otherwise
4843
+
*/
4844
+
int ib_del_sub_device_and_put(struct ib_device *sub);
4845
+
4846
+
static inline void ib_mark_name_assigned_by_user(struct ib_device *ibdev)
4847
+
{
4848
+
ibdev->name_assign_type = RDMA_NAME_ASSIGN_TYPE_USER;
4849
+
}
4850
+
4850
4851
#endif /* IB_VERBS_H */
+1
-1
include/uapi/rdma/bnxt_re-abi.h
+1
-1
include/uapi/rdma/bnxt_re-abi.h
···
55
55
BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED = 0x04ULL,
56
56
BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED = 0x08ULL,
57
57
BNXT_RE_UCNTX_CMASK_POW2_DISABLED = 0x10ULL,
58
-
BNXT_RE_COMP_MASK_UCNTX_HW_RETX_ENABLED = 0x40,
58
+
BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED = 0x40,
59
59
};
60
60
61
61
enum bnxt_re_wqe_mode {
+3
-4
include/uapi/rdma/ib_user_ioctl_cmds.h
+3
-4
include/uapi/rdma/ib_user_ioctl_cmds.h
···
37
37
#define UVERBS_ID_NS_MASK 0xF000
38
38
#define UVERBS_ID_NS_SHIFT 12
39
39
40
-
#define UVERBS_UDATA_DRIVER_DATA_NS 1
41
-
#define UVERBS_UDATA_DRIVER_DATA_FLAG (1UL << UVERBS_ID_NS_SHIFT)
42
-
43
40
enum uverbs_default_objects {
44
41
UVERBS_OBJECT_DEVICE, /* No instances of DEVICE are allowed */
45
42
UVERBS_OBJECT_PD,
···
58
61
};
59
62
60
63
enum {
61
-
UVERBS_ATTR_UHW_IN = UVERBS_UDATA_DRIVER_DATA_FLAG,
64
+
UVERBS_ID_DRIVER_NS = 1UL << UVERBS_ID_NS_SHIFT,
65
+
UVERBS_ATTR_UHW_IN = UVERBS_ID_DRIVER_NS,
62
66
UVERBS_ATTR_UHW_OUT,
67
+
UVERBS_ID_DRIVER_NS_WITH_UHW,
63
68
};
64
69
65
70
enum uverbs_methods_device {
+9
include/uapi/rdma/mana-abi.h
+9
include/uapi/rdma/mana-abi.h
···
45
45
__u32 reserved;
46
46
};
47
47
48
+
struct mana_ib_create_rc_qp {
49
+
__aligned_u64 queue_buf[4];
50
+
__u32 queue_size[4];
51
+
};
52
+
53
+
struct mana_ib_create_rc_qp_resp {
54
+
__u32 queue_id[4];
55
+
};
56
+
48
57
struct mana_ib_create_wq {
49
58
__aligned_u64 wq_buf_addr;
50
59
__u32 wq_buf_size;
+4
include/uapi/rdma/mlx5_user_ioctl_cmds.h
+4
include/uapi/rdma/mlx5_user_ioctl_cmds.h
···
270
270
MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX = (1U << UVERBS_ID_NS_SHIFT),
271
271
};
272
272
273
+
enum mlx5_ib_create_cq_attrs {
274
+
MLX5_IB_ATTR_CREATE_CQ_UAR_INDEX = UVERBS_ID_DRIVER_NS_WITH_UHW,
275
+
};
276
+
273
277
#define MLX5_IB_DW_MATCH_PARAM 0xA0
274
278
275
279
struct mlx5_ib_match_params {
+22
include/uapi/rdma/rdma_netlink.h
+22
include/uapi/rdma/rdma_netlink.h
···
301
301
302
302
RDMA_NLDEV_CMD_RES_SRQ_GET_RAW,
303
303
304
+
RDMA_NLDEV_CMD_NEWDEV,
305
+
306
+
RDMA_NLDEV_CMD_DELDEV,
307
+
304
308
RDMA_NLDEV_NUM_OPS
305
309
};
306
310
···
568
564
*/
569
565
RDMA_NLDEV_ATTR_RES_SUBTYPE, /* string */
570
566
567
+
RDMA_NLDEV_ATTR_DEV_TYPE, /* u8 */
568
+
569
+
RDMA_NLDEV_ATTR_PARENT_NAME, /* string */
570
+
571
+
RDMA_NLDEV_ATTR_NAME_ASSIGN_TYPE, /* u8 */
572
+
571
573
/*
572
574
* Always the end
573
575
*/
···
612
602
RDMA_COUNTER_MASK_QP_TYPE = 1,
613
603
RDMA_COUNTER_MASK_PID = 1 << 1,
614
604
};
605
+
606
+
/* Supported rdma device types. */
607
+
enum rdma_nl_dev_type {
608
+
RDMA_DEVICE_TYPE_SMI = 1,
609
+
};
610
+
611
+
/* RDMA device name assignment types */
612
+
enum rdma_nl_name_assign_type {
613
+
RDMA_NAME_ASSIGN_TYPE_UNKNOWN = 0,
614
+
RDMA_NAME_ASSIGN_TYPE_USER = 1, /* Provided by user-space */
615
+
};
616
+
615
617
#endif /* _UAPI_RDMA_NETLINK_H */