tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'imx-fixes-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into arm/fixes

i.MX fixes for 7.0:

- Revert the NAND property move that broke compatibility across multiple
imx6/imx7 device trees
- Fix imx8mq-librem5 power management by bumping BUCK1 suspend voltage to
0.85V and reverting problematic DVS voltage changes
- Correct eMMC pad configuration for imx93-tqma9352 and imx91-tqma9131
- Change usdhc tuning step for eMMC and SD on imx93-9x9-qsb
- Correct gpu_ahb clock frequency for imx8mq

* tag 'imx-fixes-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux:
arm64: dts: imx8mq-librem5: Bump BUCK1 suspend voltage up to 0.85V
Revert "arm64: dts: imx8mq-librem5: Set the DVS voltages lower"
Revert "ARM: dts: imx: move nand related property under nand@0"
arm64: dts: imx93-tqma9352: improve eMMC pad configuration
arm64: dts: imx91-tqma9131: improve eMMC pad configuration
arm64: dts: imx93-9x9-qsb: change usdhc tuning step for eMMC and SD
arm64: dts: imx8mq: Set the correct gpu_ahb clock frequency

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

Krzysztof Kozlowski 3d53a7a2 df3ef89d

+56 -124
+1 -5
arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi
··· 36 36 &gpmi { 37 37 pinctrl-names = "default"; 38 38 pinctrl-0 = <&pinctrl_gpmi_nand>; 39 + nand-on-flash-bbt; 39 40 status = "okay"; 40 - 41 - nand@0 { 42 - reg = <0>; 43 - nand-on-flash-bbt; 44 - }; 45 41 }; 46 42 47 43 &i2c3 {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi
··· 172 172 &gpmi { 173 173 pinctrl-names = "default"; 174 174 pinctrl-0 = <&pinctrl_gpmi_nand>; 175 + nand-on-flash-bbt; 175 176 status = "okay"; 176 - 177 - nand@0 { 178 - reg = <0>; 179 - nand-on-flash-bbt; 180 - }; 181 177 }; 182 178 183 179 &i2c1 {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi
··· 102 102 &gpmi { 103 103 pinctrl-names = "default"; 104 104 pinctrl-0 = <&pinctrl_gpmi_nand>; 105 + nand-on-flash-bbt; 105 106 status = "okay"; 106 - 107 - nand@0 { 108 - reg = <0>; 109 - nand-on-flash-bbt; 110 - }; 111 107 }; 112 108 113 109 &i2c1 {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
··· 73 73 &gpmi { 74 74 pinctrl-names = "default"; 75 75 pinctrl-0 = <&pinctrl_gpmi_nand>; 76 + nand-on-flash-bbt; 76 77 status = "disabled"; 77 - 78 - nand@0 { 79 - reg = <0>; 80 - nand-on-flash-bbt; 81 - }; 82 78 }; 83 79 84 80 &i2c3 {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi
··· 260 260 &gpmi { 261 261 pinctrl-names = "default"; 262 262 pinctrl-0 = <&pinctrl_gpmi_nand>; 263 + nand-on-flash-bbt; 263 264 #address-cells = <1>; 264 265 #size-cells = <0>; 265 266 status = "okay"; 266 - 267 - nand@0 { 268 - reg = <0>; 269 - nand-on-flash-bbt; 270 - }; 271 267 }; 272 268 273 269 &i2c3 {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi
··· 252 252 &gpmi { 253 253 pinctrl-names = "default"; 254 254 pinctrl-0 = <&pinctrl_gpmi_nand>; 255 + nand-on-flash-bbt; 255 256 fsl,no-blockmark-swap; 256 257 status = "okay"; 257 - 258 - nand@0 { 259 - reg = <0>; 260 - nand-on-flash-bbt; 261 - }; 262 258 }; 263 259 264 260 &i2c1 {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
··· 133 133 &gpmi { 134 134 pinctrl-names = "default"; 135 135 pinctrl-0 = <&pinctrl_gpmi_nand>; 136 + nand-on-flash-bbt; 136 137 status = "okay"; 137 - 138 - nand@0 { 139 - reg = <0>; 140 - nand-on-flash-bbt; 141 - }; 142 138 }; 143 139 144 140 &i2c1 {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
··· 101 101 &gpmi { 102 102 pinctrl-names = "default"; 103 103 pinctrl-0 = <&pinctrl_gpmi_nand>; 104 + nand-on-flash-bbt; 104 105 status = "disabled"; 105 - 106 - nand@0 { 107 - reg = <0>; 108 - nand-on-flash-bbt; 109 - }; 110 106 }; 111 107 112 108 &i2c1 {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi
··· 63 63 &gpmi { 64 64 pinctrl-names = "default"; 65 65 pinctrl-0 = <&pinctrl_gpmi_nand>; 66 + nand-on-flash-bbt; 66 67 status = "disabled"; 67 - 68 - nand@0 { 69 - reg = <0>; 70 - nand-on-flash-bbt; 71 - }; 72 68 }; 73 69 74 70 &i2c1 {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
··· 296 296 &gpmi { 297 297 pinctrl-names = "default"; 298 298 pinctrl-0 = <&pinctrl_gpmi_nand>; 299 + nand-on-flash-bbt; 299 300 fsl,no-blockmark-swap; 300 301 status = "okay"; 301 - 302 - nand@0 { 303 - reg = <0>; 304 - nand-on-flash-bbt; 305 - }; 306 302 }; 307 303 308 304 &i2c2 {
+4 -8
arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi
··· 160 160 pinctrl-names = "default"; 161 161 pinctrl-0 = <&pinctrl_gpmi_nand>; 162 162 fsl,use-minimum-ecc; 163 + nand-on-flash-bbt; 164 + nand-ecc-mode = "hw"; 165 + nand-ecc-strength = <8>; 166 + nand-ecc-step-size = <512>; 163 167 status = "okay"; 164 - 165 - nand@0 { 166 - reg = <0>; 167 - nand-on-flash-bbt; 168 - nand-ecc-mode = "hw"; 169 - nand-ecc-strength = <8>; 170 - nand-ecc-step-size = <512>; 171 - }; 172 168 }; 173 169 174 170 /* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
+4 -8
arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi
··· 43 43 &gpmi { 44 44 pinctrl-names = "default"; 45 45 pinctrl-0 = <&pinctrl_gpmi_nand>; 46 + nand-ecc-mode = "hw"; 47 + nand-ecc-strength = <0>; 48 + nand-ecc-step-size = <0>; 49 + nand-on-flash-bbt; 46 50 status = "okay"; 47 - 48 - nand@0 { 49 - reg = <0>; 50 - nand-ecc-mode = "hw"; 51 - nand-ecc-strength = <0>; 52 - nand-ecc-step-size = <0>; 53 - nand-on-flash-bbt; 54 - }; 55 51 }; 56 52 57 53 &iomuxc {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
··· 60 60 &gpmi { 61 61 pinctrl-names = "default"; 62 62 pinctrl-0 = <&pinctrl_gpmi_nand>; 63 + nand-on-flash-bbt; 63 64 status = "disabled"; 64 - 65 - nand@0 { 66 - reg = <0>; 67 - nand-on-flash-bbt; 68 - }; 69 65 }; 70 66 71 67 &uart1 {
+1 -5
arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
··· 25 25 &gpmi { 26 26 pinctrl-names = "default"; 27 27 pinctrl-0 = <&pinctrl_gpmi_nand>; 28 + nand-on-flash-bbt; 28 29 status = "okay"; 29 - 30 - nand@0 { 31 - reg = <0>; 32 - nand-on-flash-bbt; 33 - }; 34 30 }; 35 31 36 32 &snvs_poweroff {
+2 -6
arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi
··· 375 375 /* NAND on such SKUs */ 376 376 &gpmi { 377 377 fsl,use-minimum-ecc; 378 + nand-ecc-mode = "hw"; 379 + nand-on-flash-bbt; 378 380 pinctrl-names = "default"; 379 381 pinctrl-0 = <&pinctrl_gpmi_nand>; 380 - 381 - nand@0 { 382 - reg = <0>; 383 - nand-ecc-mode = "hw"; 384 - nand-on-flash-bbt; 385 - }; 386 382 }; 387 383 388 384 /* On-module Power I2C */
+1 -1
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
··· 7 7 8 8 &a53_opp_table { 9 9 opp-1000000000 { 10 - opp-microvolt = <950000>; 10 + opp-microvolt = <1000000>; 11 11 }; 12 12 }; 13 13
+7 -17
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
··· 880 880 regulator-max-microvolt = <1300000>; 881 881 regulator-boot-on; 882 882 regulator-ramp-delay = <1250>; 883 - rohm,dvs-run-voltage = <880000>; 884 - rohm,dvs-idle-voltage = <820000>; 885 - rohm,dvs-suspend-voltage = <810000>; 883 + rohm,dvs-run-voltage = <900000>; 884 + rohm,dvs-idle-voltage = <850000>; 885 + rohm,dvs-suspend-voltage = <850000>; 886 886 regulator-always-on; 887 887 }; 888 888 ··· 892 892 regulator-max-microvolt = <1300000>; 893 893 regulator-boot-on; 894 894 regulator-ramp-delay = <1250>; 895 - rohm,dvs-run-voltage = <950000>; 896 - rohm,dvs-idle-voltage = <850000>; 895 + rohm,dvs-run-voltage = <1000000>; 896 + rohm,dvs-idle-voltage = <900000>; 897 897 regulator-always-on; 898 898 }; 899 899 ··· 902 902 regulator-min-microvolt = <700000>; 903 903 regulator-max-microvolt = <1300000>; 904 904 regulator-boot-on; 905 - rohm,dvs-run-voltage = <850000>; 905 + rohm,dvs-run-voltage = <900000>; 906 906 }; 907 907 908 908 buck4_reg: BUCK4 { 909 909 regulator-name = "buck4"; 910 910 regulator-min-microvolt = <700000>; 911 911 regulator-max-microvolt = <1300000>; 912 - rohm,dvs-run-voltage = <930000>; 912 + rohm,dvs-run-voltage = <1000000>; 913 913 }; 914 914 915 915 buck5_reg: BUCK5 { ··· 1447 1447 pinctrl-0 = <&pinctrl_wdog>; 1448 1448 fsl,ext-reset-output; 1449 1449 status = "okay"; 1450 - }; 1451 - 1452 - &a53_opp_table { 1453 - opp-1000000000 { 1454 - opp-microvolt = <850000>; 1455 - }; 1456 - 1457 - opp-1500000000 { 1458 - opp-microvolt = <950000>; 1459 - }; 1460 1450 };
+1 -1
arch/arm64/boot/dts/freescale/imx8mq.dtsi
··· 1632 1632 <&clk IMX8MQ_GPU_PLL_OUT>, 1633 1633 <&clk IMX8MQ_GPU_PLL>; 1634 1634 assigned-clock-rates = <800000000>, <800000000>, 1635 - <800000000>, <800000000>, <0>; 1635 + <800000000>, <400000000>, <0>; 1636 1636 power-domains = <&pgc_gpu>; 1637 1637 }; 1638 1638
+10 -10
arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi
··· 272 272 /* enable SION for data and cmd pad due to ERR052021 */ 273 273 pinctrl_usdhc1: usdhc1grp { 274 274 fsl,pins = /* PD | FSEL 3 | DSE X5 */ 275 - <MX91_PAD_SD1_CLK__USDHC1_CLK 0x5be>, 275 + <MX91_PAD_SD1_CLK__USDHC1_CLK 0x59e>, 276 276 /* HYS | FSEL 0 | no drive */ 277 277 <MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1000>, 278 278 /* HYS | FSEL 3 | X5 */ 279 - <MX91_PAD_SD1_CMD__USDHC1_CMD 0x400011be>, 279 + <MX91_PAD_SD1_CMD__USDHC1_CMD 0x4000139e>, 280 280 /* HYS | FSEL 3 | X4 */ 281 - <MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e>, 282 - <MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e>, 283 - <MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e>, 284 - <MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e>, 285 - <MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e>, 286 - <MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e>, 287 - <MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e>, 288 - <MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e>; 281 + <MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e>, 282 + <MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e>, 283 + <MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e>, 284 + <MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e>, 285 + <MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e>, 286 + <MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e>, 287 + <MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e>, 288 + <MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e>; 289 289 }; 290 290 291 291 pinctrl_wdog: wdoggrp {
+2
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
··· 507 507 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 508 508 bus-width = <8>; 509 509 non-removable; 510 + fsl,tuning-step = <1>; 510 511 status = "okay"; 511 512 }; 512 513 ··· 520 519 vmmc-supply = <&reg_usdhc2_vmmc>; 521 520 bus-width = <4>; 522 521 no-mmc; 522 + fsl,tuning-step = <1>; 523 523 status = "okay"; 524 524 }; 525 525
+13 -13
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
··· 271 271 /* enable SION for data and cmd pad due to ERR052021 */ 272 272 pinctrl_usdhc1: usdhc1grp { 273 273 fsl,pins = < 274 - /* PD | FSEL 3 | DSE X5 */ 275 - MX93_PAD_SD1_CLK__USDHC1_CLK 0x5be 274 + /* PD | FSEL 3 | DSE X4 */ 275 + MX93_PAD_SD1_CLK__USDHC1_CLK 0x59e 276 276 /* HYS | FSEL 0 | no drive */ 277 277 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1000 278 - /* HYS | FSEL 3 | X5 */ 279 - MX93_PAD_SD1_CMD__USDHC1_CMD 0x400011be 280 - /* HYS | FSEL 3 | X4 */ 281 - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e 282 - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e 283 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e 284 - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e 285 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e 286 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e 287 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e 288 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e 278 + /* HYS | PU | FSEL 3 | DSE X4 */ 279 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e 280 + /* HYS | PU | FSEL 3 | DSE X4 */ 281 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e 282 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e 283 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e 284 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e 285 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e 286 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e 287 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e 288 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e 289 289 >; 290 290 }; 291 291