+243 -244

arch/arm/Kconfig

reviewed

··· 1 1 config ARM 2 2 bool 3 3 default y 4 4 - select ARCH_HAVE_CUSTOM_GPIO_H 5 5 - select HAVE_AOUT 6 6 - select HAVE_DMA_API_DEBUG 7 7 - select HAVE_IDE if PCI || ISA || PCMCIA 8 8 - select HAVE_DMA_ATTRS 9 9 - select HAVE_DMA_CONTIGUOUS if MMU 10 10 - select HAVE_MEMBLOCK 11 11 - select RTC_LIB 12 12 - select SYS_SUPPORTS_APM_EMULATION 13 13 - select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 4 4 + select ARCH_BINFMT_ELF_RANDOMIZE_PIE 14 5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 15 15 - select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 6 6 + select ARCH_HAVE_CUSTOM_GPIO_H 7 7 + select ARCH_WANT_IPC_PARSE_VERSION 8 8 + select CPU_PM if (SUSPEND || CPU_IDLE) 9 9 + select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN 10 10 + select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 11 11 + select GENERIC_CLOCKEVENTS_BROADCAST if SMP 12 12 + select GENERIC_IRQ_PROBE 13 13 + select GENERIC_IRQ_SHOW 14 14 + select GENERIC_KERNEL_THREAD 15 15 + select GENERIC_KERNEL_EXECVE 16 16 + select GENERIC_PCI_IOMAP 17 17 + select GENERIC_SMP_IDLE_THREAD 18 18 + select GENERIC_STRNCPY_FROM_USER 19 19 + select GENERIC_STRNLEN_USER 20 20 + select HARDIRQS_SW_RESEND 21 21 + select HAVE_AOUT 16 22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 17 23 select HAVE_ARCH_KGDB 18 24 select HAVE_ARCH_TRACEHOOK 19 19 - select HAVE_SYSCALL_TRACEPOINTS 25 25 + select HAVE_BPF_JIT 26 26 + select HAVE_C_RECORDMCOUNT 27 27 + select HAVE_DEBUG_KMEMLEAK 28 28 + select HAVE_DMA_API_DEBUG 29 29 + select HAVE_DMA_ATTRS 30 30 + select HAVE_DMA_CONTIGUOUS if MMU 31 31 + select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 32 32 + select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 33 33 + select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 34 34 + select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 35 35 + select HAVE_GENERIC_DMA_COHERENT 36 36 + select HAVE_GENERIC_HARDIRQS 37 37 + select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 38 38 + select HAVE_IDE if PCI || ISA || PCMCIA 39 39 + select HAVE_IRQ_WORK 40 40 + select HAVE_KERNEL_GZIP 41 41 + select HAVE_KERNEL_LZMA 42 42 + select HAVE_KERNEL_LZO 43 43 + select HAVE_KERNEL_XZ 20 44 select HAVE_KPROBES if !XIP_KERNEL 21 45 select HAVE_KRETPROBES if (HAVE_KPROBES) 22 22 - select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 23 23 - select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 24 24 - select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 25 25 - select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 26 26 - select ARCH_BINFMT_ELF_RANDOMIZE_PIE 27 27 - select HAVE_GENERIC_DMA_COHERENT 28 28 - select HAVE_DEBUG_KMEMLEAK 29 29 - select HAVE_KERNEL_GZIP 30 30 - select HAVE_KERNEL_LZO 31 31 - select HAVE_KERNEL_LZMA 32 32 - select HAVE_KERNEL_XZ 33 33 - select HAVE_IRQ_WORK 46 46 + select HAVE_MEMBLOCK 47 47 + select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 34 48 select HAVE_PERF_EVENTS 35 35 - select PERF_USE_VMALLOC 36 49 select HAVE_REGS_AND_STACK_ACCESS_API 37 37 - select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 38 38 - select HAVE_C_RECORDMCOUNT 39 39 - select HAVE_GENERIC_HARDIRQS 40 40 - select HARDIRQS_SW_RESEND 41 41 - select GENERIC_IRQ_PROBE 42 42 - select GENERIC_IRQ_SHOW 50 50 + select HAVE_SYSCALL_TRACEPOINTS 43 51 select HAVE_UID16 44 44 - select ARCH_WANT_IPC_PARSE_VERSION 45 45 - select HARDIRQS_SW_RESEND 46 46 - select CPU_PM if (SUSPEND || CPU_IDLE) 47 47 - select GENERIC_PCI_IOMAP 48 48 - select HAVE_BPF_JIT 49 49 - select GENERIC_SMP_IDLE_THREAD 50 52 select KTIME_SCALAR 51 51 - select GENERIC_CLOCKEVENTS_BROADCAST if SMP 52 52 - select GENERIC_STRNCPY_FROM_USER 53 53 - select GENERIC_STRNLEN_USER 54 54 - select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN 55 55 - select GENERIC_KERNEL_THREAD 56 56 - select GENERIC_KERNEL_EXECVE 53 53 + select PERF_USE_VMALLOC 54 54 + select RTC_LIB 55 55 + select SYS_SUPPORTS_APM_EMULATION 57 56 help 58 57 The ARM series is a line of low-power-consumption RISC chip designs 59 58 licensed by ARM Ltd and targeted at embedded applications and ··· 68 69 bool 69 70 70 71 config ARM_DMA_USE_IOMMU 71 71 - select NEED_SG_DMA_LENGTH 72 72 - select ARM_HAS_SG_CHAIN 73 72 bool 73 73 + select ARM_HAS_SG_CHAIN 74 74 + select NEED_SG_DMA_LENGTH 74 75 75 76 config HAVE_PWM 76 77 bool ··· 262 263 263 264 config ARCH_MULTIPLATFORM 264 265 bool "Allow multiple platforms to be selected" 266 266 + depends on MMU 265 267 select ARM_PATCH_PHYS_VIRT 266 268 select AUTO_ZRELADDR 267 269 select COMMON_CLK 268 270 select MULTI_IRQ_HANDLER 269 271 select SPARSE_IRQ 270 272 select USE_OF 271 271 - depends on MMU 272 273 273 274 config ARCH_INTEGRATOR 274 275 bool "ARM Ltd. Integrator family" 275 275 - select ARM_AMBA 276 276 select ARCH_HAS_CPUFREQ 277 277 + select ARM_AMBA 277 278 select COMMON_CLK 278 279 select COMMON_CLK_VERSATILE 280 280 + select GENERIC_CLOCKEVENTS 279 281 select HAVE_TCM 280 282 select ICST 281 281 - select GENERIC_CLOCKEVENTS 283 283 + select MULTI_IRQ_HANDLER 284 284 + select NEED_MACH_MEMORY_H 282 285 select PLAT_VERSATILE 283 286 select PLAT_VERSATILE_FPGA_IRQ 284 284 - select NEED_MACH_MEMORY_H 285 287 select SPARSE_IRQ 286 286 - select MULTI_IRQ_HANDLER 287 288 help 288 289 Support for ARM's Integrator platform. 289 290 290 291 config ARCH_REALVIEW 291 292 bool "ARM Ltd. RealView family" 293 293 + select ARCH_WANT_OPTIONAL_GPIOLIB 292 294 select ARM_AMBA 295 295 + select ARM_TIMER_SP804 293 296 select COMMON_CLK 294 297 select COMMON_CLK_VERSATILE 295 295 - select ICST 296 298 select GENERIC_CLOCKEVENTS 297 297 - select ARCH_WANT_OPTIONAL_GPIOLIB 299 299 + select GPIO_PL061 if GPIOLIB 300 300 + select ICST 301 301 + select NEED_MACH_MEMORY_H 298 302 select PLAT_VERSATILE 299 303 select PLAT_VERSATILE_CLCD 300 300 - select ARM_TIMER_SP804 301 301 - select GPIO_PL061 if GPIOLIB 302 302 - select NEED_MACH_MEMORY_H 303 304 help 304 305 This enables support for ARM Ltd RealView boards. 305 306 306 307 config ARCH_VERSATILE 307 308 bool "ARM Ltd. Versatile family" 309 309 + select ARCH_WANT_OPTIONAL_GPIOLIB 308 310 select ARM_AMBA 311 311 + select ARM_TIMER_SP804 309 312 select ARM_VIC 310 313 select CLKDEV_LOOKUP 314 314 + select GENERIC_CLOCKEVENTS 311 315 select HAVE_MACH_CLKDEV 312 316 select ICST 313 313 - select GENERIC_CLOCKEVENTS 314 314 - select ARCH_WANT_OPTIONAL_GPIOLIB 315 317 select PLAT_VERSATILE 316 316 - select PLAT_VERSATILE_CLOCK 317 318 select PLAT_VERSATILE_CLCD 319 319 + select PLAT_VERSATILE_CLOCK 318 320 select PLAT_VERSATILE_FPGA_IRQ 319 319 - select ARM_TIMER_SP804 320 321 help 321 322 This enables support for ARM Ltd Versatile board. 322 323 323 324 config ARCH_AT91 324 325 bool "Atmel AT91" 325 326 select ARCH_REQUIRE_GPIOLIB 326 326 - select HAVE_CLK 327 327 select CLKDEV_LOOKUP 328 328 + select HAVE_CLK 328 329 select IRQ_DOMAIN 329 330 select NEED_MACH_GPIO_H 330 331 select NEED_MACH_IO_H if PCCARD ··· 349 350 This enables support for the Broadcom BCM2835 SoC. This SoC is 350 351 use in the Raspberry Pi, and Roku 2 devices. 351 352 352 352 - config ARCH_CLPS711X 353 353 - bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 354 354 - select CPU_ARM720T 355 355 - select ARCH_USES_GETTIMEOFFSET 356 356 - select COMMON_CLK 357 357 - select CLKDEV_LOOKUP 358 358 - select NEED_MACH_MEMORY_H 359 359 - help 360 360 - Support for Cirrus Logic 711x/721x/731x based boards. 361 361 - 362 353 config ARCH_CNS3XXX 363 354 bool "Cavium Networks CNS3XXX family" 355 355 + select ARM_GIC 364 356 select CPU_V6K 365 357 select GENERIC_CLOCKEVENTS 366 366 - select ARM_GIC 367 358 select MIGHT_HAVE_CACHE_L2X0 368 359 select MIGHT_HAVE_PCI 369 360 select PCI_DOMAINS if PCI 370 361 help 371 362 Support for Cavium Networks CNS3XXX platform. 372 363 364 364 + config ARCH_CLPS711X 365 365 + bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 366 366 + select ARCH_USES_GETTIMEOFFSET 367 367 + select CLKDEV_LOOKUP 368 368 + select COMMON_CLK 369 369 + select CPU_ARM720T 370 370 + select NEED_MACH_MEMORY_H 371 371 + help 372 372 + Support for Cirrus Logic 711x/721x/731x based boards. 373 373 + 373 374 config ARCH_GEMINI 374 375 bool "Cortina Systems Gemini" 375 375 - select CPU_FA526 376 376 select ARCH_REQUIRE_GPIOLIB 377 377 select ARCH_USES_GETTIMEOFFSET 378 378 + select CPU_FA526 378 379 help 379 380 Support for the Cortina Systems Gemini family SoCs 380 381 381 382 config ARCH_SIRF 382 383 bool "CSR SiRF" 383 383 - select NO_IOPORT 384 384 select ARCH_REQUIRE_GPIOLIB 385 385 - select GENERIC_CLOCKEVENTS 386 385 select COMMON_CLK 386 386 + select GENERIC_CLOCKEVENTS 387 387 select GENERIC_IRQ_CHIP 388 388 select MIGHT_HAVE_CACHE_L2X0 389 389 + select NO_IOPORT 389 390 select PINCTRL 390 391 select PINCTRL_SIRF 391 392 select USE_OF ··· 394 395 395 396 config ARCH_EBSA110 396 397 bool "EBSA-110" 398 398 + select ARCH_USES_GETTIMEOFFSET 397 399 select CPU_SA110 398 400 select ISA 399 399 - select NO_IOPORT 400 400 - select ARCH_USES_GETTIMEOFFSET 401 401 select NEED_MACH_IO_H 402 402 select NEED_MACH_MEMORY_H 403 403 + select NO_IOPORT 403 404 help 404 405 This is an evaluation board for the StrongARM processor available 405 406 from Digital. It has limited hardware on-board, including an ··· 408 409 409 410 config ARCH_EP93XX 410 411 bool "EP93xx-based" 411 411 - select CPU_ARM920T 412 412 + select ARCH_HAS_HOLES_MEMORYMODEL 413 413 + select ARCH_REQUIRE_GPIOLIB 414 414 + select ARCH_USES_GETTIMEOFFSET 412 415 select ARM_AMBA 413 416 select ARM_VIC 414 417 select CLKDEV_LOOKUP 415 415 - select ARCH_REQUIRE_GPIOLIB 416 416 - select ARCH_HAS_HOLES_MEMORYMODEL 417 417 - select ARCH_USES_GETTIMEOFFSET 418 418 + select CPU_ARM920T 418 419 select NEED_MACH_MEMORY_H 419 420 help 420 421 This enables support for the Cirrus EP93xx series of CPUs. ··· 433 434 434 435 config ARCH_MXC 435 436 bool "Freescale MXC/iMX-based" 436 436 - select GENERIC_CLOCKEVENTS 437 437 select ARCH_REQUIRE_GPIOLIB 438 438 select CLKDEV_LOOKUP 439 439 select CLKSRC_MMIO 440 440 + select GENERIC_CLOCKEVENTS 440 441 select GENERIC_IRQ_CHIP 441 442 select MULTI_IRQ_HANDLER 442 443 select SPARSE_IRQ ··· 446 447 447 448 config ARCH_MXS 448 449 bool "Freescale MXS-based" 449 449 - select GENERIC_CLOCKEVENTS 450 450 select ARCH_REQUIRE_GPIOLIB 451 451 select CLKDEV_LOOKUP 452 452 select CLKSRC_MMIO 453 453 select COMMON_CLK 454 454 + select GENERIC_CLOCKEVENTS 454 455 select HAVE_CLK_PREPARE 455 456 select MULTI_IRQ_HANDLER 456 457 select PINCTRL ··· 461 462 462 463 config ARCH_NETX 463 464 bool "Hilscher NetX based" 465 465 + select ARM_VIC 464 466 select CLKSRC_MMIO 465 467 select CPU_ARM926T 466 466 - select ARM_VIC 467 468 select GENERIC_CLOCKEVENTS 468 469 help 469 470 This enables support for systems based on the Hilscher NetX Soc 470 471 471 472 config ARCH_H720X 472 473 bool "Hynix HMS720x-based" 474 474 + select ARCH_USES_GETTIMEOFFSET 473 475 select CPU_ARM720T 474 476 select ISA_DMA_API 475 475 - select ARCH_USES_GETTIMEOFFSET 476 477 help 477 478 This enables support for systems based on the Hynix HMS720x 478 479 479 480 config ARCH_IOP13XX 480 481 bool "IOP13xx-based" 481 482 depends on MMU 482 482 - select CPU_XSC3 483 483 - select PLAT_IOP 484 484 - select PCI 485 483 select ARCH_SUPPORTS_MSI 486 486 - select VMSPLIT_1G 484 484 + select CPU_XSC3 487 485 select NEED_MACH_MEMORY_H 488 486 select NEED_RET_TO_USER 487 487 + select PCI 488 488 + select PLAT_IOP 489 489 + select VMSPLIT_1G 489 490 help 490 491 Support for Intel's IOP13XX (XScale) family of processors. 491 492 492 493 config ARCH_IOP32X 493 494 bool "IOP32x-based" 494 495 depends on MMU 496 496 + select ARCH_REQUIRE_GPIOLIB 495 497 select CPU_XSCALE 496 498 select NEED_MACH_GPIO_H 497 499 select NEED_RET_TO_USER 498 498 - select PLAT_IOP 499 500 select PCI 500 500 - select ARCH_REQUIRE_GPIOLIB 501 501 + select PLAT_IOP 501 502 help 502 503 Support for Intel's 80219 and IOP32X (XScale) family of 503 504 processors. ··· 505 506 config ARCH_IOP33X 506 507 bool "IOP33x-based" 507 508 depends on MMU 509 509 + select ARCH_REQUIRE_GPIOLIB 508 510 select CPU_XSCALE 509 511 select NEED_MACH_GPIO_H 510 512 select NEED_RET_TO_USER 511 511 - select PLAT_IOP 512 513 select PCI 513 513 - select ARCH_REQUIRE_GPIOLIB 514 514 + select PLAT_IOP 514 515 help 515 516 Support for Intel's IOP33X (XScale) family of processors. 516 517 ··· 518 519 bool "IXP4xx-based" 519 520 depends on MMU 520 521 select ARCH_HAS_DMA_SET_COHERENT_MASK 522 522 + select ARCH_REQUIRE_GPIOLIB 521 523 select CLKSRC_MMIO 522 524 select CPU_XSCALE 523 523 - select ARCH_REQUIRE_GPIOLIB 525 525 + select DMABOUNCE if PCI 524 526 select GENERIC_CLOCKEVENTS 525 527 select MIGHT_HAVE_PCI 526 528 select NEED_MACH_IO_H 527 527 - select DMABOUNCE if PCI 528 529 help 529 530 Support for Intel's IXP4XX (XScale) family of processors. 530 531 531 532 config ARCH_DOVE 532 533 bool "Marvell Dove" 533 533 - select CPU_V7 534 534 select ARCH_REQUIRE_GPIOLIB 535 535 + select CPU_V7 535 536 select GENERIC_CLOCKEVENTS 536 537 select MIGHT_HAVE_PCI 537 538 select PLAT_ORION_LEGACY ··· 541 542 542 543 config ARCH_KIRKWOOD 543 544 bool "Marvell Kirkwood" 544 544 - select CPU_FEROCEON 545 545 - select PCI 546 545 select ARCH_REQUIRE_GPIOLIB 546 546 + select CPU_FEROCEON 547 547 select GENERIC_CLOCKEVENTS 548 548 + select PCI 548 549 select PLAT_ORION_LEGACY 549 550 help 550 551 Support for the following Marvell Kirkwood series SoCs: 551 552 88F6180, 88F6192 and 88F6281. 552 553 553 553 - config ARCH_LPC32XX 554 554 - bool "NXP LPC32XX" 555 555 - select CLKSRC_MMIO 556 556 - select CPU_ARM926T 557 557 - select ARCH_REQUIRE_GPIOLIB 558 558 - select HAVE_IDE 559 559 - select ARM_AMBA 560 560 - select USB_ARCH_HAS_OHCI 561 561 - select CLKDEV_LOOKUP 562 562 - select GENERIC_CLOCKEVENTS 563 563 - select USE_OF 564 564 - select HAVE_PWM 565 565 - help 566 566 - Support for the NXP LPC32XX family of processors 567 567 - 568 554 config ARCH_MV78XX0 569 555 bool "Marvell MV78xx0" 570 570 - select CPU_FEROCEON 571 571 - select PCI 572 556 select ARCH_REQUIRE_GPIOLIB 557 557 + select CPU_FEROCEON 573 558 select GENERIC_CLOCKEVENTS 559 559 + select PCI 574 560 select PLAT_ORION_LEGACY 575 561 help 576 562 Support for the following Marvell MV78xx0 series SoCs: ··· 564 580 config ARCH_ORION5X 565 581 bool "Marvell Orion" 566 582 depends on MMU 567 567 - select CPU_FEROCEON 568 568 - select PCI 569 583 select ARCH_REQUIRE_GPIOLIB 584 584 + select CPU_FEROCEON 570 585 select GENERIC_CLOCKEVENTS 586 586 + select PCI 571 587 select PLAT_ORION_LEGACY 572 588 help 573 589 Support for the following Marvell Orion 5x series SoCs: ··· 579 595 depends on MMU 580 596 select ARCH_REQUIRE_GPIOLIB 581 597 select CLKDEV_LOOKUP 598 598 + select GENERIC_ALLOCATOR 582 599 select GENERIC_CLOCKEVENTS 583 600 select GPIO_PXA 584 601 select IRQ_DOMAIN 602 602 + select NEED_MACH_GPIO_H 585 603 select PLAT_PXA 586 604 select SPARSE_IRQ 587 587 - select GENERIC_ALLOCATOR 588 588 - select NEED_MACH_GPIO_H 589 605 help 590 606 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 591 607 592 608 config ARCH_KS8695 593 609 bool "Micrel/Kendin KS8695" 594 594 - select CPU_ARM922T 595 610 select ARCH_REQUIRE_GPIOLIB 596 596 - select NEED_MACH_MEMORY_H 597 611 select CLKSRC_MMIO 612 612 + select CPU_ARM922T 598 613 select GENERIC_CLOCKEVENTS 614 614 + select NEED_MACH_MEMORY_H 599 615 help 600 616 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 601 617 System-on-Chip devices. 602 618 603 619 config ARCH_W90X900 604 620 bool "Nuvoton W90X900 CPU" 605 605 - select CPU_ARM926T 606 621 select ARCH_REQUIRE_GPIOLIB 607 622 select CLKDEV_LOOKUP 608 623 select CLKSRC_MMIO 624 624 + select CPU_ARM926T 609 625 select GENERIC_CLOCKEVENTS 610 626 help 611 627 Support for Nuvoton (Winbond logic dept.) ARM9 processor, ··· 616 632 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 617 633 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 618 634 619 619 - config ARCH_TEGRA 620 620 - bool "NVIDIA Tegra" 635 635 + config ARCH_LPC32XX 636 636 + bool "NXP LPC32XX" 637 637 + select ARCH_REQUIRE_GPIOLIB 638 638 + select ARM_AMBA 621 639 select CLKDEV_LOOKUP 622 640 select CLKSRC_MMIO 641 641 + select CPU_ARM926T 642 642 + select GENERIC_CLOCKEVENTS 643 643 + select HAVE_IDE 644 644 + select HAVE_PWM 645 645 + select USB_ARCH_HAS_OHCI 646 646 + select USE_OF 647 647 + help 648 648 + Support for the NXP LPC32XX family of processors 649 649 + 650 650 + config ARCH_TEGRA 651 651 + bool "NVIDIA Tegra" 652 652 + select ARCH_HAS_CPUFREQ 653 653 + select CLKDEV_LOOKUP 654 654 + select CLKSRC_MMIO 655 655 + select COMMON_CLK 623 656 select GENERIC_CLOCKEVENTS 624 657 select GENERIC_GPIO 625 658 select HAVE_CLK 626 659 select HAVE_SMP 627 660 select MIGHT_HAVE_CACHE_L2X0 628 628 - select ARCH_HAS_CPUFREQ 629 661 select USE_OF 630 630 - select COMMON_CLK 631 662 help 632 663 This enables support for NVIDIA Tegra based systems (Tegra APX, 633 664 Tegra 6xx and Tegra 2 series). ··· 650 651 config ARCH_PXA 651 652 bool "PXA2xx/PXA3xx-based" 652 653 depends on MMU 653 653 - select ARCH_MTD_XIP 654 654 select ARCH_HAS_CPUFREQ 655 655 + select ARCH_MTD_XIP 656 656 + select ARCH_REQUIRE_GPIOLIB 657 657 + select ARM_CPU_SUSPEND if PM 658 658 + select AUTO_ZRELADDR 655 659 select CLKDEV_LOOKUP 656 660 select CLKSRC_MMIO 657 657 - select ARCH_REQUIRE_GPIOLIB 658 661 select GENERIC_CLOCKEVENTS 659 662 select GPIO_PXA 663 663 + select HAVE_IDE 664 664 + select MULTI_IRQ_HANDLER 665 665 + select NEED_MACH_GPIO_H 660 666 select PLAT_PXA 661 667 select SPARSE_IRQ 662 662 - select AUTO_ZRELADDR 663 663 - select MULTI_IRQ_HANDLER 664 664 - select ARM_CPU_SUSPEND if PM 665 665 - select HAVE_IDE 666 666 - select NEED_MACH_GPIO_H 667 668 help 668 669 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 669 670 670 671 config ARCH_MSM 671 672 bool "Qualcomm MSM" 672 672 - select HAVE_CLK 673 673 - select GENERIC_CLOCKEVENTS 674 673 select ARCH_REQUIRE_GPIOLIB 675 674 select CLKDEV_LOOKUP 675 675 + select GENERIC_CLOCKEVENTS 676 676 + select HAVE_CLK 676 677 help 677 678 Support for Qualcomm MSM/QSD based systems. This runs on the 678 679 apps processor of the MSM/QSD and depends on a shared memory ··· 682 683 683 684 config ARCH_SHMOBILE 684 685 bool "Renesas SH-Mobile / R-Mobile" 685 685 - select HAVE_CLK 686 686 select CLKDEV_LOOKUP 687 687 + select GENERIC_CLOCKEVENTS 688 688 + select HAVE_CLK 687 689 select HAVE_MACH_CLKDEV 688 690 select HAVE_SMP 689 689 - select GENERIC_CLOCKEVENTS 690 691 select MIGHT_HAVE_CACHE_L2X0 691 691 - select NO_IOPORT 692 692 - select SPARSE_IRQ 693 692 select MULTI_IRQ_HANDLER 694 694 - select PM_GENERIC_DOMAINS if PM 695 693 select NEED_MACH_MEMORY_H 694 694 + select NO_IOPORT 695 695 + select PM_GENERIC_DOMAINS if PM 696 696 + select SPARSE_IRQ 696 697 help 697 698 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 698 699 699 700 config ARCH_RPC 700 701 bool "RiscPC" 701 702 select ARCH_ACORN 702 702 - select FIQ 703 703 select ARCH_MAY_HAVE_PC_FDC 704 704 - select HAVE_PATA_PLATFORM 705 705 - select ISA_DMA_API 706 706 - select NO_IOPORT 707 704 select ARCH_SPARSEMEM_ENABLE 708 705 select ARCH_USES_GETTIMEOFFSET 706 706 + select FIQ 709 707 select HAVE_IDE 708 708 + select HAVE_PATA_PLATFORM 709 709 + select ISA_DMA_API 710 710 select NEED_MACH_IO_H 711 711 select NEED_MACH_MEMORY_H 712 712 + select NO_IOPORT 712 713 help 713 714 On the Acorn Risc-PC, Linux can support the internal IDE disk and 714 715 CD-ROM interface, serial and parallel port, and the floppy drive. 715 716 716 717 config ARCH_SA1100 717 718 bool "SA1100-based" 718 718 - select CLKSRC_MMIO 719 719 - select CPU_SA1100 720 720 - select ISA 721 721 - select ARCH_SPARSEMEM_ENABLE 722 722 - select ARCH_MTD_XIP 723 719 select ARCH_HAS_CPUFREQ 724 724 - select CPU_FREQ 725 725 - select GENERIC_CLOCKEVENTS 726 726 - select CLKDEV_LOOKUP 720 720 + select ARCH_MTD_XIP 727 721 select ARCH_REQUIRE_GPIOLIB 722 722 + select ARCH_SPARSEMEM_ENABLE 723 723 + select CLKDEV_LOOKUP 724 724 + select CLKSRC_MMIO 725 725 + select CPU_FREQ 726 726 + select CPU_SA1100 727 727 + select GENERIC_CLOCKEVENTS 728 728 select HAVE_IDE 729 729 + select ISA 729 730 select NEED_MACH_GPIO_H 730 731 select NEED_MACH_MEMORY_H 731 732 select SPARSE_IRQ ··· 734 735 735 736 config ARCH_S3C24XX 736 737 bool "Samsung S3C24XX SoCs" 737 737 - select GENERIC_GPIO 738 738 select ARCH_HAS_CPUFREQ 739 739 - select HAVE_CLK 740 740 - select CLKDEV_LOOKUP 741 739 select ARCH_USES_GETTIMEOFFSET 740 740 + select CLKDEV_LOOKUP 741 741 + select GENERIC_GPIO 742 742 + select HAVE_CLK 742 743 select HAVE_S3C2410_I2C if I2C 743 743 - select HAVE_S3C_RTC if RTC_CLASS 744 744 select HAVE_S3C2410_WATCHDOG if WATCHDOG 745 745 + select HAVE_S3C_RTC if RTC_CLASS 745 746 select NEED_MACH_GPIO_H 746 747 select NEED_MACH_IO_H 747 748 help ··· 752 753 753 754 config ARCH_S3C64XX 754 755 bool "Samsung S3C64XX" 755 755 - select PLAT_SAMSUNG 756 756 - select CPU_V6 757 757 - select ARM_VIC 758 758 - select HAVE_CLK 759 759 - select HAVE_TCM 760 760 - select CLKDEV_LOOKUP 761 761 - select NO_IOPORT 762 762 - select ARCH_USES_GETTIMEOFFSET 763 756 select ARCH_HAS_CPUFREQ 764 757 select ARCH_REQUIRE_GPIOLIB 765 765 - select SAMSUNG_CLKSRC 766 766 - select SAMSUNG_IRQ_VIC_TIMER 767 767 - select S3C_GPIO_TRACK 768 768 - select S3C_DEV_NAND 769 769 - select USB_ARCH_HAS_OHCI 770 770 - select SAMSUNG_GPIOLIB_4BIT 758 758 + select ARCH_USES_GETTIMEOFFSET 759 759 + select ARM_VIC 760 760 + select CLKDEV_LOOKUP 761 761 + select CPU_V6 762 762 + select HAVE_CLK 771 763 select HAVE_S3C2410_I2C if I2C 772 764 select HAVE_S3C2410_WATCHDOG if WATCHDOG 765 765 + select HAVE_TCM 773 766 select NEED_MACH_GPIO_H 767 767 + select NO_IOPORT 768 768 + select PLAT_SAMSUNG 769 769 + select S3C_DEV_NAND 770 770 + select S3C_GPIO_TRACK 771 771 + select SAMSUNG_CLKSRC 772 772 + select SAMSUNG_GPIOLIB_4BIT 773 773 + select SAMSUNG_IRQ_VIC_TIMER 774 774 + select USB_ARCH_HAS_OHCI 774 775 help 775 776 Samsung S3C64XX series based systems 776 777 777 778 config ARCH_S5P64X0 778 779 bool "Samsung S5P6440 S5P6450" 779 779 - select CPU_V6 780 780 - select GENERIC_GPIO 781 781 - select HAVE_CLK 782 780 select CLKDEV_LOOKUP 783 781 select CLKSRC_MMIO 784 784 - select HAVE_S3C2410_WATCHDOG if WATCHDOG 782 782 + select CPU_V6 785 783 select GENERIC_CLOCKEVENTS 784 784 + select GENERIC_GPIO 785 785 + select HAVE_CLK 786 786 select HAVE_S3C2410_I2C if I2C 787 787 + select HAVE_S3C2410_WATCHDOG if WATCHDOG 787 788 select HAVE_S3C_RTC if RTC_CLASS 788 789 select NEED_MACH_GPIO_H 789 790 help ··· 792 793 793 794 config ARCH_S5PC100 794 795 bool "Samsung S5PC100" 795 795 - select GENERIC_GPIO 796 796 - select HAVE_CLK 796 796 + select ARCH_USES_GETTIMEOFFSET 797 797 select CLKDEV_LOOKUP 798 798 select CPU_V7 799 799 - select ARCH_USES_GETTIMEOFFSET 799 799 + select GENERIC_GPIO 800 800 + select HAVE_CLK 800 801 select HAVE_S3C2410_I2C if I2C 801 801 - select HAVE_S3C_RTC if RTC_CLASS 802 802 select HAVE_S3C2410_WATCHDOG if WATCHDOG 803 803 + select HAVE_S3C_RTC if RTC_CLASS 803 804 select NEED_MACH_GPIO_H 804 805 help 805 806 Samsung S5PC100 series based systems 806 807 807 808 config ARCH_S5PV210 808 809 bool "Samsung S5PV210/S5PC110" 809 809 - select CPU_V7 810 810 - select ARCH_SPARSEMEM_ENABLE 810 810 + select ARCH_HAS_CPUFREQ 811 811 select ARCH_HAS_HOLES_MEMORYMODEL 812 812 - select GENERIC_GPIO 813 813 - select HAVE_CLK 812 812 + select ARCH_SPARSEMEM_ENABLE 814 813 select CLKDEV_LOOKUP 815 814 select CLKSRC_MMIO 816 816 - select ARCH_HAS_CPUFREQ 815 815 + select CPU_V7 817 816 select GENERIC_CLOCKEVENTS 817 817 + select GENERIC_GPIO 818 818 + select HAVE_CLK 818 819 select HAVE_S3C2410_I2C if I2C 819 819 - select HAVE_S3C_RTC if RTC_CLASS 820 820 select HAVE_S3C2410_WATCHDOG if WATCHDOG 821 821 + select HAVE_S3C_RTC if RTC_CLASS 821 822 select NEED_MACH_GPIO_H 822 823 select NEED_MACH_MEMORY_H 823 824 help 824 825 Samsung S5PV210/S5PC110 series based systems 825 826 826 827 config ARCH_EXYNOS 827 827 - bool "SAMSUNG EXYNOS" 828 828 - select CPU_V7 829 829 - select ARCH_SPARSEMEM_ENABLE 828 828 + bool "Samsung EXYNOS" 829 829 + select ARCH_HAS_CPUFREQ 830 830 select ARCH_HAS_HOLES_MEMORYMODEL 831 831 + select ARCH_SPARSEMEM_ENABLE 832 832 + select CLKDEV_LOOKUP 833 833 + select CPU_V7 834 834 + select GENERIC_CLOCKEVENTS 831 835 select GENERIC_GPIO 832 836 select HAVE_CLK 833 833 - select CLKDEV_LOOKUP 834 834 - select ARCH_HAS_CPUFREQ 835 835 - select GENERIC_CLOCKEVENTS 836 836 - select HAVE_S3C_RTC if RTC_CLASS 837 837 select HAVE_S3C2410_I2C if I2C 838 838 select HAVE_S3C2410_WATCHDOG if WATCHDOG 839 839 + select HAVE_S3C_RTC if RTC_CLASS 839 840 select NEED_MACH_GPIO_H 840 841 select NEED_MACH_MEMORY_H 841 842 help ··· 843 844 844 845 config ARCH_SHARK 845 846 bool "Shark" 847 847 + select ARCH_USES_GETTIMEOFFSET 846 848 select CPU_SA110 847 849 select ISA 848 850 select ISA_DMA 849 849 - select ZONE_DMA 850 850 - select PCI 851 851 - select ARCH_USES_GETTIMEOFFSET 852 851 select NEED_MACH_MEMORY_H 852 852 + select PCI 853 853 + select ZONE_DMA 853 854 help 854 855 Support for the StrongARM based Digital DNARD machine, also known 855 856 as "Shark" (<http://www.shark-linux.de/shark.html>). ··· 857 858 config ARCH_U300 858 859 bool "ST-Ericsson U300 Series" 859 860 depends on MMU 860 860 - select CLKSRC_MMIO 861 861 - select CPU_ARM926T 862 862 - select HAVE_TCM 861 861 + select ARCH_REQUIRE_GPIOLIB 863 862 select ARM_AMBA 864 863 select ARM_PATCH_PHYS_VIRT 865 864 select ARM_VIC 866 866 - select GENERIC_CLOCKEVENTS 867 865 select CLKDEV_LOOKUP 866 866 + select CLKSRC_MMIO 868 867 select COMMON_CLK 868 868 + select CPU_ARM926T 869 869 + select GENERIC_CLOCKEVENTS 869 870 select GENERIC_GPIO 870 870 - select ARCH_REQUIRE_GPIOLIB 871 871 + select HAVE_TCM 871 872 select SPARSE_IRQ 872 873 help 873 874 Support for ST-Ericsson U300 series mobile platforms. ··· 875 876 config ARCH_U8500 876 877 bool "ST-Ericsson U8500 Series" 877 878 depends on MMU 878 878 - select CPU_V7 879 879 - select ARM_AMBA 880 880 - select GENERIC_CLOCKEVENTS 881 881 - select CLKDEV_LOOKUP 882 882 - select ARCH_REQUIRE_GPIOLIB 883 879 select ARCH_HAS_CPUFREQ 880 880 + select ARCH_REQUIRE_GPIOLIB 881 881 + select ARM_AMBA 882 882 + select CLKDEV_LOOKUP 883 883 + select CPU_V7 884 884 + select GENERIC_CLOCKEVENTS 884 885 select HAVE_SMP 885 886 select MIGHT_HAVE_CACHE_L2X0 886 887 help ··· 888 889 889 890 config ARCH_NOMADIK 890 891 bool "STMicroelectronics Nomadik" 892 892 + select ARCH_REQUIRE_GPIOLIB 891 893 select ARM_AMBA 892 894 select ARM_VIC 893 893 - select CPU_ARM926T 894 895 select COMMON_CLK 896 896 + select CPU_ARM926T 895 897 select GENERIC_CLOCKEVENTS 898 898 + select MIGHT_HAVE_CACHE_L2X0 896 899 select PINCTRL 897 900 select PINCTRL_STN8815 898 898 - select MIGHT_HAVE_CACHE_L2X0 899 899 - select ARCH_REQUIRE_GPIOLIB 900 901 help 901 902 Support for the Nomadik platform by ST-Ericsson 902 903 904 904 + config PLAT_SPEAR 905 905 + bool "ST SPEAr" 906 906 + select ARCH_REQUIRE_GPIOLIB 907 907 + select ARM_AMBA 908 908 + select CLKDEV_LOOKUP 909 909 + select CLKSRC_MMIO 910 910 + select COMMON_CLK 911 911 + select GENERIC_CLOCKEVENTS 912 912 + select HAVE_CLK 913 913 + help 914 914 + Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 915 915 + 903 916 config ARCH_DAVINCI 904 917 bool "TI DaVinci" 905 905 - select GENERIC_CLOCKEVENTS 918 918 + select ARCH_HAS_HOLES_MEMORYMODEL 906 919 select ARCH_REQUIRE_GPIOLIB 907 907 - select ZONE_DMA 908 908 - select HAVE_IDE 909 920 select CLKDEV_LOOKUP 910 921 select GENERIC_ALLOCATOR 922 922 + select GENERIC_CLOCKEVENTS 911 923 select GENERIC_IRQ_CHIP 912 912 - select ARCH_HAS_HOLES_MEMORYMODEL 924 924 + select HAVE_IDE 913 925 select NEED_MACH_GPIO_H 926 926 + select ZONE_DMA 914 927 help 915 928 Support for TI's DaVinci platform. 916 929 917 930 config ARCH_OMAP 918 931 bool "TI OMAP" 919 932 depends on MMU 920 920 - select HAVE_CLK 921 921 - select ARCH_REQUIRE_GPIOLIB 922 933 select ARCH_HAS_CPUFREQ 934 934 + select ARCH_HAS_HOLES_MEMORYMODEL 935 935 + select ARCH_REQUIRE_GPIOLIB 923 936 select CLKSRC_MMIO 924 937 select GENERIC_CLOCKEVENTS 925 925 - select ARCH_HAS_HOLES_MEMORYMODEL 938 938 + select HAVE_CLK 926 939 select NEED_MACH_GPIO_H 927 940 help 928 941 Support for TI's OMAP platform (OMAP1/2/3/4). 929 942 930 930 - config PLAT_SPEAR 931 931 - bool "ST SPEAr" 932 932 - select ARM_AMBA 933 933 - select ARCH_REQUIRE_GPIOLIB 934 934 - select CLKDEV_LOOKUP 935 935 - select COMMON_CLK 936 936 - select CLKSRC_MMIO 937 937 - select GENERIC_CLOCKEVENTS 938 938 - select HAVE_CLK 939 939 - help 940 940 - Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 941 941 - 942 943 config ARCH_VT8500 943 944 bool "VIA/WonderMedia 85xx" 944 944 - select CPU_ARM926T 945 945 - select GENERIC_GPIO 946 945 select ARCH_HAS_CPUFREQ 947 947 - select GENERIC_CLOCKEVENTS 948 946 select ARCH_REQUIRE_GPIOLIB 949 949 - select USE_OF 950 950 - select COMMON_CLK 951 951 - select HAVE_CLK 952 947 select CLKDEV_LOOKUP 948 948 + select COMMON_CLK 949 949 + select CPU_ARM926T 950 950 + select GENERIC_CLOCKEVENTS 951 951 + select GENERIC_GPIO 952 952 + select HAVE_CLK 953 953 + select USE_OF 953 954 help 954 955 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 955 956 956 957 config ARCH_ZYNQ 957 958 bool "Xilinx Zynq ARM Cortex A9 Platform" 959 959 + select ARM_AMBA 960 960 + select ARM_GIC 961 961 + select CLKDEV_LOOKUP 958 962 select CPU_V7 959 963 select GENERIC_CLOCKEVENTS 960 960 - select CLKDEV_LOOKUP 961 961 - select ARM_GIC 962 962 - select ARM_AMBA 963 964 select ICST 964 965 select MIGHT_HAVE_CACHE_L2X0 965 966 select USE_OF ··· 974 975 975 976 config ARCH_MULTI_V4 976 977 bool "ARMv4 based platforms (FA526, StrongARM)" 977 977 - select ARCH_MULTI_V4_V5 978 978 depends on !ARCH_MULTI_V6_V7 979 979 + select ARCH_MULTI_V4_V5 979 980 980 981 config ARCH_MULTI_V4T 981 982 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 982 982 - select ARCH_MULTI_V4_V5 983 983 depends on !ARCH_MULTI_V6_V7 984 984 + select ARCH_MULTI_V4_V5 984 985 985 986 config ARCH_MULTI_V5 986 987 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 987 987 - select ARCH_MULTI_V4_V5 988 988 depends on !ARCH_MULTI_V6_V7 989 989 + select ARCH_MULTI_V4_V5 989 990 990 991 config ARCH_MULTI_V4_V5 991 992 bool 992 993 993 994 config ARCH_MULTI_V6 994 995 bool "ARMv6 based platforms (ARM11, Scorpion, ...)" 995 995 - select CPU_V6 996 996 select ARCH_MULTI_V6_V7 997 997 + select CPU_V6 997 998 998 999 config ARCH_MULTI_V7 999 1000 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)" 1000 1000 - select CPU_V7 1001 1001 - select ARCH_VEXPRESS 1002 1001 default y 1003 1002 select ARCH_MULTI_V6_V7 1003 1003 + select ARCH_VEXPRESS 1004 1004 + select CPU_V7 1004 1005 1005 1006 config ARCH_MULTI_V6_V7 1006 1007 bool ··· 1137 1138 config PLAT_ORION 1138 1139 bool 1139 1140 select CLKSRC_MMIO 1141 1141 + select COMMON_CLK 1140 1142 select GENERIC_IRQ_CHIP 1141 1143 select IRQ_DOMAIN 1142 1142 - select COMMON_CLK 1143 1144 1144 1145 config PLAT_ORION_LEGACY 1145 1146 bool ··· 1497 1498 depends on GENERIC_CLOCKEVENTS 1498 1499 depends on HAVE_SMP 1499 1500 depends on MMU 1500 1500 - select USE_GENERIC_SMP_HELPERS 1501 1501 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1502 1502 + select USE_GENERIC_SMP_HELPERS 1502 1503 help 1503 1504 This enables support for systems with more than one CPU. If you have 1504 1505 a system with only one CPU, like most personal computers, say N. If ··· 1857 1858 1858 1859 config USE_OF 1859 1860 bool "Flattened Device Tree support" 1861 1861 + select IRQ_DOMAIN 1860 1862 select OF 1861 1863 select OF_EARLY_FLATTREE 1862 1862 - select IRQ_DOMAIN 1863 1864 help 1864 1865 Include support for flattened device tree machine descriptions. 1865 1866 ··· 2141 2142 bool 2142 2143 depends on CPU_FREQ && ARCH_PXA && PXA25x 2143 2144 default y 2144 2144 - select CPU_FREQ_TABLE 2145 2145 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2146 2146 + select CPU_FREQ_TABLE 2146 2147 2147 2148 config CPU_FREQ_S3C 2148 2149 bool

+2 -2

arch/arm/common/Kconfig

reviewed

··· 1 1 config ARM_GIC 2 2 + bool 2 3 select IRQ_DOMAIN 3 4 select MULTI_IRQ_HANDLER 4 4 - bool 5 5 6 6 config GIC_NON_BANKED 7 7 bool 8 8 9 9 config ARM_VIC 10 10 + bool 10 11 select IRQ_DOMAIN 11 12 select MULTI_IRQ_HANDLER 12 12 - bool 13 13 14 14 config ARM_VIC_NR 15 15 int

-2

arch/arm/include/asm/Kbuild

reviewed

··· 1 1 - include include/asm-generic/Kbuild.asm 2 1 3 3 - header-y += hwcap.h 4 2 5 3 generic-y += auxvec.h 6 4 generic-y += bitsperlong.h

arch/arm/include/asm/a.out.h arch/arm/include/uapi/asm/a.out.h

reviewed

arch/arm/include/asm/byteorder.h arch/arm/include/uapi/asm/byteorder.h

reviewed

arch/arm/include/asm/fcntl.h arch/arm/include/uapi/asm/fcntl.h

reviewed

+1 -26

arch/arm/include/asm/hwcap.h

reviewed

··· 1 1 #ifndef __ASMARM_HWCAP_H 2 2 #define __ASMARM_HWCAP_H 3 3 4 4 - /* 5 5 - * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP 6 6 - */ 7 7 - #define HWCAP_SWP (1 << 0) 8 8 - #define HWCAP_HALF (1 << 1) 9 9 - #define HWCAP_THUMB (1 << 2) 10 10 - #define HWCAP_26BIT (1 << 3) /* Play it safe */ 11 11 - #define HWCAP_FAST_MULT (1 << 4) 12 12 - #define HWCAP_FPA (1 << 5) 13 13 - #define HWCAP_VFP (1 << 6) 14 14 - #define HWCAP_EDSP (1 << 7) 15 15 - #define HWCAP_JAVA (1 << 8) 16 16 - #define HWCAP_IWMMXT (1 << 9) 17 17 - #define HWCAP_CRUNCH (1 << 10) 18 18 - #define HWCAP_THUMBEE (1 << 11) 19 19 - #define HWCAP_NEON (1 << 12) 20 20 - #define HWCAP_VFPv3 (1 << 13) 21 21 - #define HWCAP_VFPv3D16 (1 << 14) 22 22 - #define HWCAP_TLS (1 << 15) 23 23 - #define HWCAP_VFPv4 (1 << 16) 24 24 - #define HWCAP_IDIVA (1 << 17) 25 25 - #define HWCAP_IDIVT (1 << 18) 26 26 - #define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) 4 4 + #include <uapi/asm/hwcap.h> 27 5 28 28 - #if defined(__KERNEL__) 29 6 #if !defined(__ASSEMBLY__) 30 7 /* 31 8 * This yields a mask that user programs can use to figure out what ··· 11 34 #define ELF_HWCAP (elf_hwcap) 12 35 extern unsigned int elf_hwcap; 13 36 #endif 14 14 - #endif 15 15 - 16 37 #endif

arch/arm/include/asm/ioctls.h arch/arm/include/uapi/asm/ioctls.h

reviewed

arch/arm/include/asm/kvm_para.h arch/arm/include/uapi/asm/kvm_para.h

reviewed

arch/arm/include/asm/mman.h arch/arm/include/uapi/asm/mman.h

reviewed

arch/arm/include/asm/posix_types.h arch/arm/include/uapi/asm/posix_types.h

reviewed

+1 -126

arch/arm/include/asm/ptrace.h

reviewed

··· 10 10 #ifndef __ASM_ARM_PTRACE_H 11 11 #define __ASM_ARM_PTRACE_H 12 12 13 13 - #include <asm/hwcap.h> 14 14 - 15 15 - #define PTRACE_GETREGS 12 16 16 - #define PTRACE_SETREGS 13 17 17 - #define PTRACE_GETFPREGS 14 18 18 - #define PTRACE_SETFPREGS 15 19 19 - /* PTRACE_ATTACH is 16 */ 20 20 - /* PTRACE_DETACH is 17 */ 21 21 - #define PTRACE_GETWMMXREGS 18 22 22 - #define PTRACE_SETWMMXREGS 19 23 23 - /* 20 is unused */ 24 24 - #define PTRACE_OLDSETOPTIONS 21 25 25 - #define PTRACE_GET_THREAD_AREA 22 26 26 - #define PTRACE_SET_SYSCALL 23 27 27 - /* PTRACE_SYSCALL is 24 */ 28 28 - #define PTRACE_GETCRUNCHREGS 25 29 29 - #define PTRACE_SETCRUNCHREGS 26 30 30 - #define PTRACE_GETVFPREGS 27 31 31 - #define PTRACE_SETVFPREGS 28 32 32 - #define PTRACE_GETHBPREGS 29 33 33 - #define PTRACE_SETHBPREGS 30 34 34 - 35 35 - /* 36 36 - * PSR bits 37 37 - */ 38 38 - #define USR26_MODE 0x00000000 39 39 - #define FIQ26_MODE 0x00000001 40 40 - #define IRQ26_MODE 0x00000002 41 41 - #define SVC26_MODE 0x00000003 42 42 - #define USR_MODE 0x00000010 43 43 - #define FIQ_MODE 0x00000011 44 44 - #define IRQ_MODE 0x00000012 45 45 - #define SVC_MODE 0x00000013 46 46 - #define ABT_MODE 0x00000017 47 47 - #define HYP_MODE 0x0000001a 48 48 - #define UND_MODE 0x0000001b 49 49 - #define SYSTEM_MODE 0x0000001f 50 50 - #define MODE32_BIT 0x00000010 51 51 - #define MODE_MASK 0x0000001f 52 52 - #define PSR_T_BIT 0x00000020 53 53 - #define PSR_F_BIT 0x00000040 54 54 - #define PSR_I_BIT 0x00000080 55 55 - #define PSR_A_BIT 0x00000100 56 56 - #define PSR_E_BIT 0x00000200 57 57 - #define PSR_J_BIT 0x01000000 58 58 - #define PSR_Q_BIT 0x08000000 59 59 - #define PSR_V_BIT 0x10000000 60 60 - #define PSR_C_BIT 0x20000000 61 61 - #define PSR_Z_BIT 0x40000000 62 62 - #define PSR_N_BIT 0x80000000 63 63 - 64 64 - /* 65 65 - * Groups of PSR bits 66 66 - */ 67 67 - #define PSR_f 0xff000000 /* Flags */ 68 68 - #define PSR_s 0x00ff0000 /* Status */ 69 69 - #define PSR_x 0x0000ff00 /* Extension */ 70 70 - #define PSR_c 0x000000ff /* Control */ 71 71 - 72 72 - /* 73 73 - * ARMv7 groups of PSR bits 74 74 - */ 75 75 - #define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */ 76 76 - #define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */ 77 77 - #define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 78 78 - #define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ 79 79 - 80 80 - /* 81 81 - * Default endianness state 82 82 - */ 83 83 - #ifdef CONFIG_CPU_ENDIAN_BE8 84 84 - #define PSR_ENDSTATE PSR_E_BIT 85 85 - #else 86 86 - #define PSR_ENDSTATE 0 87 87 - #endif 88 88 - 89 89 - /* 90 90 - * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 91 91 - * process is located in memory. 92 92 - */ 93 93 - #define PT_TEXT_ADDR 0x10000 94 94 - #define PT_DATA_ADDR 0x10004 95 95 - #define PT_TEXT_END_ADDR 0x10008 13 13 + #include <uapi/asm/ptrace.h> 96 14 97 15 #ifndef __ASSEMBLY__ 98 98 - 99 99 - /* 100 100 - * This struct defines the way the registers are stored on the 101 101 - * stack during a system call. Note that sizeof(struct pt_regs) 102 102 - * has to be a multiple of 8. 103 103 - */ 104 104 - #ifndef __KERNEL__ 105 105 - struct pt_regs { 106 106 - long uregs[18]; 107 107 - }; 108 108 - #else /* __KERNEL__ */ 109 16 struct pt_regs { 110 17 unsigned long uregs[18]; 111 18 }; 112 112 - #endif /* __KERNEL__ */ 113 113 - 114 114 - #define ARM_cpsr uregs[16] 115 115 - #define ARM_pc uregs[15] 116 116 - #define ARM_lr uregs[14] 117 117 - #define ARM_sp uregs[13] 118 118 - #define ARM_ip uregs[12] 119 119 - #define ARM_fp uregs[11] 120 120 - #define ARM_r10 uregs[10] 121 121 - #define ARM_r9 uregs[9] 122 122 - #define ARM_r8 uregs[8] 123 123 - #define ARM_r7 uregs[7] 124 124 - #define ARM_r6 uregs[6] 125 125 - #define ARM_r5 uregs[5] 126 126 - #define ARM_r4 uregs[4] 127 127 - #define ARM_r3 uregs[3] 128 128 - #define ARM_r2 uregs[2] 129 129 - #define ARM_r1 uregs[1] 130 130 - #define ARM_r0 uregs[0] 131 131 - #define ARM_ORIG_r0 uregs[17] 132 132 - 133 133 - /* 134 134 - * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS 135 135 - * and core dumps. 136 136 - */ 137 137 - #define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ ) 138 138 - 139 139 - #ifdef __KERNEL__ 140 19 141 20 #define user_mode(regs) \ 142 21 (((regs)->ARM_cpsr & 0xf) == 0) ··· 139 260 (struct pt_regs *)((sp | (THREAD_SIZE - 1)) - 7) - 1; \ 140 261 }) 141 262 142 142 - #endif /* __KERNEL__ */ 143 143 - 144 263 #endif /* __ASSEMBLY__ */ 145 145 - 146 264 #endif 147 147 -

+1 -171

arch/arm/include/asm/setup.h

reviewed

··· 14 14 #ifndef __ASMARM_SETUP_H 15 15 #define __ASMARM_SETUP_H 16 16 17 17 - #include <linux/types.h> 17 17 + #include <uapi/asm/setup.h> 18 18 19 19 - #define COMMAND_LINE_SIZE 1024 20 20 - 21 21 - /* The list ends with an ATAG_NONE node. */ 22 22 - #define ATAG_NONE 0x00000000 23 23 - 24 24 - struct tag_header { 25 25 - __u32 size; 26 26 - __u32 tag; 27 27 - }; 28 28 - 29 29 - /* The list must start with an ATAG_CORE node */ 30 30 - #define ATAG_CORE 0x54410001 31 31 - 32 32 - struct tag_core { 33 33 - __u32 flags; /* bit 0 = read-only */ 34 34 - __u32 pagesize; 35 35 - __u32 rootdev; 36 36 - }; 37 37 - 38 38 - /* it is allowed to have multiple ATAG_MEM nodes */ 39 39 - #define ATAG_MEM 0x54410002 40 40 - 41 41 - struct tag_mem32 { 42 42 - __u32 size; 43 43 - __u32 start; /* physical start address */ 44 44 - }; 45 45 - 46 46 - /* VGA text type displays */ 47 47 - #define ATAG_VIDEOTEXT 0x54410003 48 48 - 49 49 - struct tag_videotext { 50 50 - __u8 x; 51 51 - __u8 y; 52 52 - __u16 video_page; 53 53 - __u8 video_mode; 54 54 - __u8 video_cols; 55 55 - __u16 video_ega_bx; 56 56 - __u8 video_lines; 57 57 - __u8 video_isvga; 58 58 - __u16 video_points; 59 59 - }; 60 60 - 61 61 - /* describes how the ramdisk will be used in kernel */ 62 62 - #define ATAG_RAMDISK 0x54410004 63 63 - 64 64 - struct tag_ramdisk { 65 65 - __u32 flags; /* bit 0 = load, bit 1 = prompt */ 66 66 - __u32 size; /* decompressed ramdisk size in _kilo_ bytes */ 67 67 - __u32 start; /* starting block of floppy-based RAM disk image */ 68 68 - }; 69 69 - 70 70 - /* describes where the compressed ramdisk image lives (virtual address) */ 71 71 - /* 72 72 - * this one accidentally used virtual addresses - as such, 73 73 - * it's deprecated. 74 74 - */ 75 75 - #define ATAG_INITRD 0x54410005 76 76 - 77 77 - /* describes where the compressed ramdisk image lives (physical address) */ 78 78 - #define ATAG_INITRD2 0x54420005 79 79 - 80 80 - struct tag_initrd { 81 81 - __u32 start; /* physical start address */ 82 82 - __u32 size; /* size of compressed ramdisk image in bytes */ 83 83 - }; 84 84 - 85 85 - /* board serial number. "64 bits should be enough for everybody" */ 86 86 - #define ATAG_SERIAL 0x54410006 87 87 - 88 88 - struct tag_serialnr { 89 89 - __u32 low; 90 90 - __u32 high; 91 91 - }; 92 92 - 93 93 - /* board revision */ 94 94 - #define ATAG_REVISION 0x54410007 95 95 - 96 96 - struct tag_revision { 97 97 - __u32 rev; 98 98 - }; 99 99 - 100 100 - /* initial values for vesafb-type framebuffers. see struct screen_info 101 101 - * in include/linux/tty.h 102 102 - */ 103 103 - #define ATAG_VIDEOLFB 0x54410008 104 104 - 105 105 - struct tag_videolfb { 106 106 - __u16 lfb_width; 107 107 - __u16 lfb_height; 108 108 - __u16 lfb_depth; 109 109 - __u16 lfb_linelength; 110 110 - __u32 lfb_base; 111 111 - __u32 lfb_size; 112 112 - __u8 red_size; 113 113 - __u8 red_pos; 114 114 - __u8 green_size; 115 115 - __u8 green_pos; 116 116 - __u8 blue_size; 117 117 - __u8 blue_pos; 118 118 - __u8 rsvd_size; 119 119 - __u8 rsvd_pos; 120 120 - }; 121 121 - 122 122 - /* command line: \0 terminated string */ 123 123 - #define ATAG_CMDLINE 0x54410009 124 124 - 125 125 - struct tag_cmdline { 126 126 - char cmdline[1]; /* this is the minimum size */ 127 127 - }; 128 128 - 129 129 - /* acorn RiscPC specific information */ 130 130 - #define ATAG_ACORN 0x41000101 131 131 - 132 132 - struct tag_acorn { 133 133 - __u32 memc_control_reg; 134 134 - __u32 vram_pages; 135 135 - __u8 sounddefault; 136 136 - __u8 adfsdrives; 137 137 - }; 138 138 - 139 139 - /* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ 140 140 - #define ATAG_MEMCLK 0x41000402 141 141 - 142 142 - struct tag_memclk { 143 143 - __u32 fmemclk; 144 144 - }; 145 145 - 146 146 - struct tag { 147 147 - struct tag_header hdr; 148 148 - union { 149 149 - struct tag_core core; 150 150 - struct tag_mem32 mem; 151 151 - struct tag_videotext videotext; 152 152 - struct tag_ramdisk ramdisk; 153 153 - struct tag_initrd initrd; 154 154 - struct tag_serialnr serialnr; 155 155 - struct tag_revision revision; 156 156 - struct tag_videolfb videolfb; 157 157 - struct tag_cmdline cmdline; 158 158 - 159 159 - /* 160 160 - * Acorn specific 161 161 - */ 162 162 - struct tag_acorn acorn; 163 163 - 164 164 - /* 165 165 - * DC21285 specific 166 166 - */ 167 167 - struct tag_memclk memclk; 168 168 - } u; 169 169 - }; 170 170 - 171 171 - struct tagtable { 172 172 - __u32 tag; 173 173 - int (*parse)(const struct tag *); 174 174 - }; 175 175 - 176 176 - #define tag_member_present(tag,member) \ 177 177 - ((unsigned long)(&((struct tag *)0L)->member + 1) \ 178 178 - <= (tag)->hdr.size * 4) 179 179 - 180 180 - #define tag_next(t) ((struct tag *)((__u32 *)(t) + (t)->hdr.size)) 181 181 - #define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) 182 182 - 183 183 - #define for_each_tag(t,base) \ 184 184 - for (t = base; t->hdr.size; t = tag_next(t)) 185 185 - 186 186 - #ifdef __KERNEL__ 187 19 188 20 #define __tag __used __attribute__((__section__(".taglist.init"))) 189 21 #define __tagtable(tag, fn) \ ··· 52 220 extern int arm_add_memory(phys_addr_t start, phys_addr_t size); 53 221 extern void early_print(const char *str, ...); 54 222 extern void dump_machine_table(void); 55 55 - 56 56 - #endif /* __KERNEL__ */ 57 223 58 224 #endif

arch/arm/include/asm/sigcontext.h arch/arm/include/uapi/asm/sigcontext.h

reviewed

+1 -126

arch/arm/include/asm/signal.h

reviewed

··· 1 1 #ifndef _ASMARM_SIGNAL_H 2 2 #define _ASMARM_SIGNAL_H 3 3 4 4 - #include <linux/types.h> 4 4 + #include <uapi/asm/signal.h> 5 5 6 6 - /* Avoid too many header ordering problems. */ 7 7 - struct siginfo; 8 8 - 9 9 - #ifdef __KERNEL__ 10 6 /* Most things should be clean enough to redefine this at will, if care 11 7 is taken to make libc match. */ 12 8 ··· 16 20 unsigned long sig[_NSIG_WORDS]; 17 21 } sigset_t; 18 22 19 19 - #else 20 20 - /* Here we must cater to libcs that poke about in kernel headers. */ 21 21 - 22 22 - #define NSIG 32 23 23 - typedef unsigned long sigset_t; 24 24 - 25 25 - #endif /* __KERNEL__ */ 26 26 - 27 27 - #define SIGHUP 1 28 28 - #define SIGINT 2 29 29 - #define SIGQUIT 3 30 30 - #define SIGILL 4 31 31 - #define SIGTRAP 5 32 32 - #define SIGABRT 6 33 33 - #define SIGIOT 6 34 34 - #define SIGBUS 7 35 35 - #define SIGFPE 8 36 36 - #define SIGKILL 9 37 37 - #define SIGUSR1 10 38 38 - #define SIGSEGV 11 39 39 - #define SIGUSR2 12 40 40 - #define SIGPIPE 13 41 41 - #define SIGALRM 14 42 42 - #define SIGTERM 15 43 43 - #define SIGSTKFLT 16 44 44 - #define SIGCHLD 17 45 45 - #define SIGCONT 18 46 46 - #define SIGSTOP 19 47 47 - #define SIGTSTP 20 48 48 - #define SIGTTIN 21 49 49 - #define SIGTTOU 22 50 50 - #define SIGURG 23 51 51 - #define SIGXCPU 24 52 52 - #define SIGXFSZ 25 53 53 - #define SIGVTALRM 26 54 54 - #define SIGPROF 27 55 55 - #define SIGWINCH 28 56 56 - #define SIGIO 29 57 57 - #define SIGPOLL SIGIO 58 58 - /* 59 59 - #define SIGLOST 29 60 60 - */ 61 61 - #define SIGPWR 30 62 62 - #define SIGSYS 31 63 63 - #define SIGUNUSED 31 64 64 - 65 65 - /* These should not be considered constants from userland. */ 66 66 - #define SIGRTMIN 32 67 67 - #define SIGRTMAX _NSIG 68 68 - 69 69 - #define SIGSWI 32 70 70 - 71 71 - /* 72 72 - * SA_FLAGS values: 73 73 - * 74 74 - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. 75 75 - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. 76 76 - * SA_SIGINFO deliver the signal with SIGINFO structs 77 77 - * SA_THIRTYTWO delivers the signal in 32-bit mode, even if the task 78 78 - * is running in 26-bit. 79 79 - * SA_ONSTACK allows alternate signal stacks (see sigaltstack(2)). 80 80 - * SA_RESTART flag to get restarting signals (which were the default long ago) 81 81 - * SA_NODEFER prevents the current signal from being masked in the handler. 82 82 - * SA_RESETHAND clears the handler when the signal is delivered. 83 83 - * 84 84 - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single 85 85 - * Unix names RESETHAND and NODEFER respectively. 86 86 - */ 87 87 - #define SA_NOCLDSTOP 0x00000001 88 88 - #define SA_NOCLDWAIT 0x00000002 89 89 - #define SA_SIGINFO 0x00000004 90 90 - #define SA_THIRTYTWO 0x02000000 91 91 - #define SA_RESTORER 0x04000000 92 92 - #define SA_ONSTACK 0x08000000 93 93 - #define SA_RESTART 0x10000000 94 94 - #define SA_NODEFER 0x40000000 95 95 - #define SA_RESETHAND 0x80000000 96 96 - 97 97 - #define SA_NOMASK SA_NODEFER 98 98 - #define SA_ONESHOT SA_RESETHAND 99 99 - 100 100 - 101 101 - /* 102 102 - * sigaltstack controls 103 103 - */ 104 104 - #define SS_ONSTACK 1 105 105 - #define SS_DISABLE 2 106 106 - 107 107 - #define MINSIGSTKSZ 2048 108 108 - #define SIGSTKSZ 8192 109 109 - 110 110 - #include <asm-generic/signal-defs.h> 111 111 - 112 112 - #ifdef __KERNEL__ 113 23 struct old_sigaction { 114 24 __sighandler_t sa_handler; 115 25 old_sigset_t sa_mask; ··· 34 132 struct sigaction sa; 35 133 }; 36 134 37 37 - #else 38 38 - /* Here we must cater to libcs that poke about in kernel headers. */ 39 39 - 40 40 - struct sigaction { 41 41 - union { 42 42 - __sighandler_t _sa_handler; 43 43 - void (*_sa_sigaction)(int, struct siginfo *, void *); 44 44 - } _u; 45 45 - sigset_t sa_mask; 46 46 - unsigned long sa_flags; 47 47 - void (*sa_restorer)(void); 48 48 - }; 49 49 - 50 50 - #define sa_handler _u._sa_handler 51 51 - #define sa_sigaction _u._sa_sigaction 52 52 - 53 53 - #endif /* __KERNEL__ */ 54 54 - 55 55 - typedef struct sigaltstack { 56 56 - void __user *ss_sp; 57 57 - int ss_flags; 58 58 - size_t ss_size; 59 59 - } stack_t; 60 60 - 61 61 - #ifdef __KERNEL__ 62 135 #include <asm/sigcontext.h> 63 136 #define ptrace_signal_deliver(regs, cookie) do { } while (0) 64 64 - #endif 65 65 - 66 137 #endif

arch/arm/include/asm/stat.h arch/arm/include/uapi/asm/stat.h

reviewed

arch/arm/include/asm/statfs.h arch/arm/include/uapi/asm/statfs.h

reviewed

+1 -36

arch/arm/include/asm/swab.h

reviewed

··· 15 15 #ifndef __ASM_ARM_SWAB_H 16 16 #define __ASM_ARM_SWAB_H 17 17 18 18 - #include <linux/compiler.h> 19 19 - #include <linux/types.h> 18 18 + #include <uapi/asm/swab.h> 20 19 21 21 - #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) 22 22 - # define __SWAB_64_THRU_32__ 23 23 - #endif 24 24 - 25 25 - #if defined(__KERNEL__) 26 20 #if __LINUX_ARM_ARCH__ >= 6 27 21 28 22 static inline __attribute_const__ __u32 __arch_swahb32(__u32 x) ··· 35 41 #define __arch_swab32 __arch_swab32 36 42 37 43 #endif 38 38 - #endif 39 39 - 40 40 - #if !defined(__KERNEL__) || __LINUX_ARM_ARCH__ < 6 41 41 - static inline __attribute_const__ __u32 __arch_swab32(__u32 x) 42 42 - { 43 43 - __u32 t; 44 44 - 45 45 - #ifndef __thumb__ 46 46 - if (!__builtin_constant_p(x)) { 47 47 - /* 48 48 - * The compiler needs a bit of a hint here to always do the 49 49 - * right thing and not screw it up to different degrees 50 50 - * depending on the gcc version. 51 51 - */ 52 52 - asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x)); 53 53 - } else 54 54 - #endif 55 55 - t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */ 56 56 - 57 57 - x = (x << 24) | (x >> 8); /* mov r0,r0,ror #8 */ 58 58 - t &= ~0x00FF0000; /* bic r1,r1,#0x00FF0000 */ 59 59 - x ^= (t >> 8); /* eor r0,r0,r1,lsr #8 */ 60 60 - 61 61 - return x; 62 62 - } 63 63 - #define __arch_swab32 __arch_swab32 64 64 - 65 65 - #endif 66 66 - 67 44 #endif

+1 -439

arch/arm/include/asm/unistd.h

reviewed

··· 13 13 #ifndef __ASM_ARM_UNISTD_H 14 14 #define __ASM_ARM_UNISTD_H 15 15 16 16 - #define __NR_OABI_SYSCALL_BASE 0x900000 16 16 + #include <uapi/asm/unistd.h> 17 17 18 18 - #if defined(__thumb__) || defined(__ARM_EABI__) 19 19 - #define __NR_SYSCALL_BASE 0 20 20 - #else 21 21 - #define __NR_SYSCALL_BASE __NR_OABI_SYSCALL_BASE 22 22 - #endif 23 23 - 24 24 - /* 25 25 - * This file contains the system call numbers. 26 26 - */ 27 27 - 28 28 - #define __NR_restart_syscall (__NR_SYSCALL_BASE+ 0) 29 29 - #define __NR_exit (__NR_SYSCALL_BASE+ 1) 30 30 - #define __NR_fork (__NR_SYSCALL_BASE+ 2) 31 31 - #define __NR_read (__NR_SYSCALL_BASE+ 3) 32 32 - #define __NR_write (__NR_SYSCALL_BASE+ 4) 33 33 - #define __NR_open (__NR_SYSCALL_BASE+ 5) 34 34 - #define __NR_close (__NR_SYSCALL_BASE+ 6) 35 35 - /* 7 was sys_waitpid */ 36 36 - #define __NR_creat (__NR_SYSCALL_BASE+ 8) 37 37 - #define __NR_link (__NR_SYSCALL_BASE+ 9) 38 38 - #define __NR_unlink (__NR_SYSCALL_BASE+ 10) 39 39 - #define __NR_execve (__NR_SYSCALL_BASE+ 11) 40 40 - #define __NR_chdir (__NR_SYSCALL_BASE+ 12) 41 41 - #define __NR_time (__NR_SYSCALL_BASE+ 13) 42 42 - #define __NR_mknod (__NR_SYSCALL_BASE+ 14) 43 43 - #define __NR_chmod (__NR_SYSCALL_BASE+ 15) 44 44 - #define __NR_lchown (__NR_SYSCALL_BASE+ 16) 45 45 - /* 17 was sys_break */ 46 46 - /* 18 was sys_stat */ 47 47 - #define __NR_lseek (__NR_SYSCALL_BASE+ 19) 48 48 - #define __NR_getpid (__NR_SYSCALL_BASE+ 20) 49 49 - #define __NR_mount (__NR_SYSCALL_BASE+ 21) 50 50 - #define __NR_umount (__NR_SYSCALL_BASE+ 22) 51 51 - #define __NR_setuid (__NR_SYSCALL_BASE+ 23) 52 52 - #define __NR_getuid (__NR_SYSCALL_BASE+ 24) 53 53 - #define __NR_stime (__NR_SYSCALL_BASE+ 25) 54 54 - #define __NR_ptrace (__NR_SYSCALL_BASE+ 26) 55 55 - #define __NR_alarm (__NR_SYSCALL_BASE+ 27) 56 56 - /* 28 was sys_fstat */ 57 57 - #define __NR_pause (__NR_SYSCALL_BASE+ 29) 58 58 - #define __NR_utime (__NR_SYSCALL_BASE+ 30) 59 59 - /* 31 was sys_stty */ 60 60 - /* 32 was sys_gtty */ 61 61 - #define __NR_access (__NR_SYSCALL_BASE+ 33) 62 62 - #define __NR_nice (__NR_SYSCALL_BASE+ 34) 63 63 - /* 35 was sys_ftime */ 64 64 - #define __NR_sync (__NR_SYSCALL_BASE+ 36) 65 65 - #define __NR_kill (__NR_SYSCALL_BASE+ 37) 66 66 - #define __NR_rename (__NR_SYSCALL_BASE+ 38) 67 67 - #define __NR_mkdir (__NR_SYSCALL_BASE+ 39) 68 68 - #define __NR_rmdir (__NR_SYSCALL_BASE+ 40) 69 69 - #define __NR_dup (__NR_SYSCALL_BASE+ 41) 70 70 - #define __NR_pipe (__NR_SYSCALL_BASE+ 42) 71 71 - #define __NR_times (__NR_SYSCALL_BASE+ 43) 72 72 - /* 44 was sys_prof */ 73 73 - #define __NR_brk (__NR_SYSCALL_BASE+ 45) 74 74 - #define __NR_setgid (__NR_SYSCALL_BASE+ 46) 75 75 - #define __NR_getgid (__NR_SYSCALL_BASE+ 47) 76 76 - /* 48 was sys_signal */ 77 77 - #define __NR_geteuid (__NR_SYSCALL_BASE+ 49) 78 78 - #define __NR_getegid (__NR_SYSCALL_BASE+ 50) 79 79 - #define __NR_acct (__NR_SYSCALL_BASE+ 51) 80 80 - #define __NR_umount2 (__NR_SYSCALL_BASE+ 52) 81 81 - /* 53 was sys_lock */ 82 82 - #define __NR_ioctl (__NR_SYSCALL_BASE+ 54) 83 83 - #define __NR_fcntl (__NR_SYSCALL_BASE+ 55) 84 84 - /* 56 was sys_mpx */ 85 85 - #define __NR_setpgid (__NR_SYSCALL_BASE+ 57) 86 86 - /* 58 was sys_ulimit */ 87 87 - /* 59 was sys_olduname */ 88 88 - #define __NR_umask (__NR_SYSCALL_BASE+ 60) 89 89 - #define __NR_chroot (__NR_SYSCALL_BASE+ 61) 90 90 - #define __NR_ustat (__NR_SYSCALL_BASE+ 62) 91 91 - #define __NR_dup2 (__NR_SYSCALL_BASE+ 63) 92 92 - #define __NR_getppid (__NR_SYSCALL_BASE+ 64) 93 93 - #define __NR_getpgrp (__NR_SYSCALL_BASE+ 65) 94 94 - #define __NR_setsid (__NR_SYSCALL_BASE+ 66) 95 95 - #define __NR_sigaction (__NR_SYSCALL_BASE+ 67) 96 96 - /* 68 was sys_sgetmask */ 97 97 - /* 69 was sys_ssetmask */ 98 98 - #define __NR_setreuid (__NR_SYSCALL_BASE+ 70) 99 99 - #define __NR_setregid (__NR_SYSCALL_BASE+ 71) 100 100 - #define __NR_sigsuspend (__NR_SYSCALL_BASE+ 72) 101 101 - #define __NR_sigpending (__NR_SYSCALL_BASE+ 73) 102 102 - #define __NR_sethostname (__NR_SYSCALL_BASE+ 74) 103 103 - #define __NR_setrlimit (__NR_SYSCALL_BASE+ 75) 104 104 - #define __NR_getrlimit (__NR_SYSCALL_BASE+ 76) /* Back compat 2GB limited rlimit */ 105 105 - #define __NR_getrusage (__NR_SYSCALL_BASE+ 77) 106 106 - #define __NR_gettimeofday (__NR_SYSCALL_BASE+ 78) 107 107 - #define __NR_settimeofday (__NR_SYSCALL_BASE+ 79) 108 108 - #define __NR_getgroups (__NR_SYSCALL_BASE+ 80) 109 109 - #define __NR_setgroups (__NR_SYSCALL_BASE+ 81) 110 110 - #define __NR_select (__NR_SYSCALL_BASE+ 82) 111 111 - #define __NR_symlink (__NR_SYSCALL_BASE+ 83) 112 112 - /* 84 was sys_lstat */ 113 113 - #define __NR_readlink (__NR_SYSCALL_BASE+ 85) 114 114 - #define __NR_uselib (__NR_SYSCALL_BASE+ 86) 115 115 - #define __NR_swapon (__NR_SYSCALL_BASE+ 87) 116 116 - #define __NR_reboot (__NR_SYSCALL_BASE+ 88) 117 117 - #define __NR_readdir (__NR_SYSCALL_BASE+ 89) 118 118 - #define __NR_mmap (__NR_SYSCALL_BASE+ 90) 119 119 - #define __NR_munmap (__NR_SYSCALL_BASE+ 91) 120 120 - #define __NR_truncate (__NR_SYSCALL_BASE+ 92) 121 121 - #define __NR_ftruncate (__NR_SYSCALL_BASE+ 93) 122 122 - #define __NR_fchmod (__NR_SYSCALL_BASE+ 94) 123 123 - #define __NR_fchown (__NR_SYSCALL_BASE+ 95) 124 124 - #define __NR_getpriority (__NR_SYSCALL_BASE+ 96) 125 125 - #define __NR_setpriority (__NR_SYSCALL_BASE+ 97) 126 126 - /* 98 was sys_profil */ 127 127 - #define __NR_statfs (__NR_SYSCALL_BASE+ 99) 128 128 - #define __NR_fstatfs (__NR_SYSCALL_BASE+100) 129 129 - /* 101 was sys_ioperm */ 130 130 - #define __NR_socketcall (__NR_SYSCALL_BASE+102) 131 131 - #define __NR_syslog (__NR_SYSCALL_BASE+103) 132 132 - #define __NR_setitimer (__NR_SYSCALL_BASE+104) 133 133 - #define __NR_getitimer (__NR_SYSCALL_BASE+105) 134 134 - #define __NR_stat (__NR_SYSCALL_BASE+106) 135 135 - #define __NR_lstat (__NR_SYSCALL_BASE+107) 136 136 - #define __NR_fstat (__NR_SYSCALL_BASE+108) 137 137 - /* 109 was sys_uname */ 138 138 - /* 110 was sys_iopl */ 139 139 - #define __NR_vhangup (__NR_SYSCALL_BASE+111) 140 140 - /* 112 was sys_idle */ 141 141 - #define __NR_syscall (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */ 142 142 - #define __NR_wait4 (__NR_SYSCALL_BASE+114) 143 143 - #define __NR_swapoff (__NR_SYSCALL_BASE+115) 144 144 - #define __NR_sysinfo (__NR_SYSCALL_BASE+116) 145 145 - #define __NR_ipc (__NR_SYSCALL_BASE+117) 146 146 - #define __NR_fsync (__NR_SYSCALL_BASE+118) 147 147 - #define __NR_sigreturn (__NR_SYSCALL_BASE+119) 148 148 - #define __NR_clone (__NR_SYSCALL_BASE+120) 149 149 - #define __NR_setdomainname (__NR_SYSCALL_BASE+121) 150 150 - #define __NR_uname (__NR_SYSCALL_BASE+122) 151 151 - /* 123 was sys_modify_ldt */ 152 152 - #define __NR_adjtimex (__NR_SYSCALL_BASE+124) 153 153 - #define __NR_mprotect (__NR_SYSCALL_BASE+125) 154 154 - #define __NR_sigprocmask (__NR_SYSCALL_BASE+126) 155 155 - /* 127 was sys_create_module */ 156 156 - #define __NR_init_module (__NR_SYSCALL_BASE+128) 157 157 - #define __NR_delete_module (__NR_SYSCALL_BASE+129) 158 158 - /* 130 was sys_get_kernel_syms */ 159 159 - #define __NR_quotactl (__NR_SYSCALL_BASE+131) 160 160 - #define __NR_getpgid (__NR_SYSCALL_BASE+132) 161 161 - #define __NR_fchdir (__NR_SYSCALL_BASE+133) 162 162 - #define __NR_bdflush (__NR_SYSCALL_BASE+134) 163 163 - #define __NR_sysfs (__NR_SYSCALL_BASE+135) 164 164 - #define __NR_personality (__NR_SYSCALL_BASE+136) 165 165 - /* 137 was sys_afs_syscall */ 166 166 - #define __NR_setfsuid (__NR_SYSCALL_BASE+138) 167 167 - #define __NR_setfsgid (__NR_SYSCALL_BASE+139) 168 168 - #define __NR__llseek (__NR_SYSCALL_BASE+140) 169 169 - #define __NR_getdents (__NR_SYSCALL_BASE+141) 170 170 - #define __NR__newselect (__NR_SYSCALL_BASE+142) 171 171 - #define __NR_flock (__NR_SYSCALL_BASE+143) 172 172 - #define __NR_msync (__NR_SYSCALL_BASE+144) 173 173 - #define __NR_readv (__NR_SYSCALL_BASE+145) 174 174 - #define __NR_writev (__NR_SYSCALL_BASE+146) 175 175 - #define __NR_getsid (__NR_SYSCALL_BASE+147) 176 176 - #define __NR_fdatasync (__NR_SYSCALL_BASE+148) 177 177 - #define __NR__sysctl (__NR_SYSCALL_BASE+149) 178 178 - #define __NR_mlock (__NR_SYSCALL_BASE+150) 179 179 - #define __NR_munlock (__NR_SYSCALL_BASE+151) 180 180 - #define __NR_mlockall (__NR_SYSCALL_BASE+152) 181 181 - #define __NR_munlockall (__NR_SYSCALL_BASE+153) 182 182 - #define __NR_sched_setparam (__NR_SYSCALL_BASE+154) 183 183 - #define __NR_sched_getparam (__NR_SYSCALL_BASE+155) 184 184 - #define __NR_sched_setscheduler (__NR_SYSCALL_BASE+156) 185 185 - #define __NR_sched_getscheduler (__NR_SYSCALL_BASE+157) 186 186 - #define __NR_sched_yield (__NR_SYSCALL_BASE+158) 187 187 - #define __NR_sched_get_priority_max (__NR_SYSCALL_BASE+159) 188 188 - #define __NR_sched_get_priority_min (__NR_SYSCALL_BASE+160) 189 189 - #define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE+161) 190 190 - #define __NR_nanosleep (__NR_SYSCALL_BASE+162) 191 191 - #define __NR_mremap (__NR_SYSCALL_BASE+163) 192 192 - #define __NR_setresuid (__NR_SYSCALL_BASE+164) 193 193 - #define __NR_getresuid (__NR_SYSCALL_BASE+165) 194 194 - /* 166 was sys_vm86 */ 195 195 - /* 167 was sys_query_module */ 196 196 - #define __NR_poll (__NR_SYSCALL_BASE+168) 197 197 - #define __NR_nfsservctl (__NR_SYSCALL_BASE+169) 198 198 - #define __NR_setresgid (__NR_SYSCALL_BASE+170) 199 199 - #define __NR_getresgid (__NR_SYSCALL_BASE+171) 200 200 - #define __NR_prctl (__NR_SYSCALL_BASE+172) 201 201 - #define __NR_rt_sigreturn (__NR_SYSCALL_BASE+173) 202 202 - #define __NR_rt_sigaction (__NR_SYSCALL_BASE+174) 203 203 - #define __NR_rt_sigprocmask (__NR_SYSCALL_BASE+175) 204 204 - #define __NR_rt_sigpending (__NR_SYSCALL_BASE+176) 205 205 - #define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE+177) 206 206 - #define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE+178) 207 207 - #define __NR_rt_sigsuspend (__NR_SYSCALL_BASE+179) 208 208 - #define __NR_pread64 (__NR_SYSCALL_BASE+180) 209 209 - #define __NR_pwrite64 (__NR_SYSCALL_BASE+181) 210 210 - #define __NR_chown (__NR_SYSCALL_BASE+182) 211 211 - #define __NR_getcwd (__NR_SYSCALL_BASE+183) 212 212 - #define __NR_capget (__NR_SYSCALL_BASE+184) 213 213 - #define __NR_capset (__NR_SYSCALL_BASE+185) 214 214 - #define __NR_sigaltstack (__NR_SYSCALL_BASE+186) 215 215 - #define __NR_sendfile (__NR_SYSCALL_BASE+187) 216 216 - /* 188 reserved */ 217 217 - /* 189 reserved */ 218 218 - #define __NR_vfork (__NR_SYSCALL_BASE+190) 219 219 - #define __NR_ugetrlimit (__NR_SYSCALL_BASE+191) /* SuS compliant getrlimit */ 220 220 - #define __NR_mmap2 (__NR_SYSCALL_BASE+192) 221 221 - #define __NR_truncate64 (__NR_SYSCALL_BASE+193) 222 222 - #define __NR_ftruncate64 (__NR_SYSCALL_BASE+194) 223 223 - #define __NR_stat64 (__NR_SYSCALL_BASE+195) 224 224 - #define __NR_lstat64 (__NR_SYSCALL_BASE+196) 225 225 - #define __NR_fstat64 (__NR_SYSCALL_BASE+197) 226 226 - #define __NR_lchown32 (__NR_SYSCALL_BASE+198) 227 227 - #define __NR_getuid32 (__NR_SYSCALL_BASE+199) 228 228 - #define __NR_getgid32 (__NR_SYSCALL_BASE+200) 229 229 - #define __NR_geteuid32 (__NR_SYSCALL_BASE+201) 230 230 - #define __NR_getegid32 (__NR_SYSCALL_BASE+202) 231 231 - #define __NR_setreuid32 (__NR_SYSCALL_BASE+203) 232 232 - #define __NR_setregid32 (__NR_SYSCALL_BASE+204) 233 233 - #define __NR_getgroups32 (__NR_SYSCALL_BASE+205) 234 234 - #define __NR_setgroups32 (__NR_SYSCALL_BASE+206) 235 235 - #define __NR_fchown32 (__NR_SYSCALL_BASE+207) 236 236 - #define __NR_setresuid32 (__NR_SYSCALL_BASE+208) 237 237 - #define __NR_getresuid32 (__NR_SYSCALL_BASE+209) 238 238 - #define __NR_setresgid32 (__NR_SYSCALL_BASE+210) 239 239 - #define __NR_getresgid32 (__NR_SYSCALL_BASE+211) 240 240 - #define __NR_chown32 (__NR_SYSCALL_BASE+212) 241 241 - #define __NR_setuid32 (__NR_SYSCALL_BASE+213) 242 242 - #define __NR_setgid32 (__NR_SYSCALL_BASE+214) 243 243 - #define __NR_setfsuid32 (__NR_SYSCALL_BASE+215) 244 244 - #define __NR_setfsgid32 (__NR_SYSCALL_BASE+216) 245 245 - #define __NR_getdents64 (__NR_SYSCALL_BASE+217) 246 246 - #define __NR_pivot_root (__NR_SYSCALL_BASE+218) 247 247 - #define __NR_mincore (__NR_SYSCALL_BASE+219) 248 248 - #define __NR_madvise (__NR_SYSCALL_BASE+220) 249 249 - #define __NR_fcntl64 (__NR_SYSCALL_BASE+221) 250 250 - /* 222 for tux */ 251 251 - /* 223 is unused */ 252 252 - #define __NR_gettid (__NR_SYSCALL_BASE+224) 253 253 - #define __NR_readahead (__NR_SYSCALL_BASE+225) 254 254 - #define __NR_setxattr (__NR_SYSCALL_BASE+226) 255 255 - #define __NR_lsetxattr (__NR_SYSCALL_BASE+227) 256 256 - #define __NR_fsetxattr (__NR_SYSCALL_BASE+228) 257 257 - #define __NR_getxattr (__NR_SYSCALL_BASE+229) 258 258 - #define __NR_lgetxattr (__NR_SYSCALL_BASE+230) 259 259 - #define __NR_fgetxattr (__NR_SYSCALL_BASE+231) 260 260 - #define __NR_listxattr (__NR_SYSCALL_BASE+232) 261 261 - #define __NR_llistxattr (__NR_SYSCALL_BASE+233) 262 262 - #define __NR_flistxattr (__NR_SYSCALL_BASE+234) 263 263 - #define __NR_removexattr (__NR_SYSCALL_BASE+235) 264 264 - #define __NR_lremovexattr (__NR_SYSCALL_BASE+236) 265 265 - #define __NR_fremovexattr (__NR_SYSCALL_BASE+237) 266 266 - #define __NR_tkill (__NR_SYSCALL_BASE+238) 267 267 - #define __NR_sendfile64 (__NR_SYSCALL_BASE+239) 268 268 - #define __NR_futex (__NR_SYSCALL_BASE+240) 269 269 - #define __NR_sched_setaffinity (__NR_SYSCALL_BASE+241) 270 270 - #define __NR_sched_getaffinity (__NR_SYSCALL_BASE+242) 271 271 - #define __NR_io_setup (__NR_SYSCALL_BASE+243) 272 272 - #define __NR_io_destroy (__NR_SYSCALL_BASE+244) 273 273 - #define __NR_io_getevents (__NR_SYSCALL_BASE+245) 274 274 - #define __NR_io_submit (__NR_SYSCALL_BASE+246) 275 275 - #define __NR_io_cancel (__NR_SYSCALL_BASE+247) 276 276 - #define __NR_exit_group (__NR_SYSCALL_BASE+248) 277 277 - #define __NR_lookup_dcookie (__NR_SYSCALL_BASE+249) 278 278 - #define __NR_epoll_create (__NR_SYSCALL_BASE+250) 279 279 - #define __NR_epoll_ctl (__NR_SYSCALL_BASE+251) 280 280 - #define __NR_epoll_wait (__NR_SYSCALL_BASE+252) 281 281 - #define __NR_remap_file_pages (__NR_SYSCALL_BASE+253) 282 282 - /* 254 for set_thread_area */ 283 283 - /* 255 for get_thread_area */ 284 284 - #define __NR_set_tid_address (__NR_SYSCALL_BASE+256) 285 285 - #define __NR_timer_create (__NR_SYSCALL_BASE+257) 286 286 - #define __NR_timer_settime (__NR_SYSCALL_BASE+258) 287 287 - #define __NR_timer_gettime (__NR_SYSCALL_BASE+259) 288 288 - #define __NR_timer_getoverrun (__NR_SYSCALL_BASE+260) 289 289 - #define __NR_timer_delete (__NR_SYSCALL_BASE+261) 290 290 - #define __NR_clock_settime (__NR_SYSCALL_BASE+262) 291 291 - #define __NR_clock_gettime (__NR_SYSCALL_BASE+263) 292 292 - #define __NR_clock_getres (__NR_SYSCALL_BASE+264) 293 293 - #define __NR_clock_nanosleep (__NR_SYSCALL_BASE+265) 294 294 - #define __NR_statfs64 (__NR_SYSCALL_BASE+266) 295 295 - #define __NR_fstatfs64 (__NR_SYSCALL_BASE+267) 296 296 - #define __NR_tgkill (__NR_SYSCALL_BASE+268) 297 297 - #define __NR_utimes (__NR_SYSCALL_BASE+269) 298 298 - #define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE+270) 299 299 - #define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271) 300 300 - #define __NR_pciconfig_read (__NR_SYSCALL_BASE+272) 301 301 - #define __NR_pciconfig_write (__NR_SYSCALL_BASE+273) 302 302 - #define __NR_mq_open (__NR_SYSCALL_BASE+274) 303 303 - #define __NR_mq_unlink (__NR_SYSCALL_BASE+275) 304 304 - #define __NR_mq_timedsend (__NR_SYSCALL_BASE+276) 305 305 - #define __NR_mq_timedreceive (__NR_SYSCALL_BASE+277) 306 306 - #define __NR_mq_notify (__NR_SYSCALL_BASE+278) 307 307 - #define __NR_mq_getsetattr (__NR_SYSCALL_BASE+279) 308 308 - #define __NR_waitid (__NR_SYSCALL_BASE+280) 309 309 - #define __NR_socket (__NR_SYSCALL_BASE+281) 310 310 - #define __NR_bind (__NR_SYSCALL_BASE+282) 311 311 - #define __NR_connect (__NR_SYSCALL_BASE+283) 312 312 - #define __NR_listen (__NR_SYSCALL_BASE+284) 313 313 - #define __NR_accept (__NR_SYSCALL_BASE+285) 314 314 - #define __NR_getsockname (__NR_SYSCALL_BASE+286) 315 315 - #define __NR_getpeername (__NR_SYSCALL_BASE+287) 316 316 - #define __NR_socketpair (__NR_SYSCALL_BASE+288) 317 317 - #define __NR_send (__NR_SYSCALL_BASE+289) 318 318 - #define __NR_sendto (__NR_SYSCALL_BASE+290) 319 319 - #define __NR_recv (__NR_SYSCALL_BASE+291) 320 320 - #define __NR_recvfrom (__NR_SYSCALL_BASE+292) 321 321 - #define __NR_shutdown (__NR_SYSCALL_BASE+293) 322 322 - #define __NR_setsockopt (__NR_SYSCALL_BASE+294) 323 323 - #define __NR_getsockopt (__NR_SYSCALL_BASE+295) 324 324 - #define __NR_sendmsg (__NR_SYSCALL_BASE+296) 325 325 - #define __NR_recvmsg (__NR_SYSCALL_BASE+297) 326 326 - #define __NR_semop (__NR_SYSCALL_BASE+298) 327 327 - #define __NR_semget (__NR_SYSCALL_BASE+299) 328 328 - #define __NR_semctl (__NR_SYSCALL_BASE+300) 329 329 - #define __NR_msgsnd (__NR_SYSCALL_BASE+301) 330 330 - #define __NR_msgrcv (__NR_SYSCALL_BASE+302) 331 331 - #define __NR_msgget (__NR_SYSCALL_BASE+303) 332 332 - #define __NR_msgctl (__NR_SYSCALL_BASE+304) 333 333 - #define __NR_shmat (__NR_SYSCALL_BASE+305) 334 334 - #define __NR_shmdt (__NR_SYSCALL_BASE+306) 335 335 - #define __NR_shmget (__NR_SYSCALL_BASE+307) 336 336 - #define __NR_shmctl (__NR_SYSCALL_BASE+308) 337 337 - #define __NR_add_key (__NR_SYSCALL_BASE+309) 338 338 - #define __NR_request_key (__NR_SYSCALL_BASE+310) 339 339 - #define __NR_keyctl (__NR_SYSCALL_BASE+311) 340 340 - #define __NR_semtimedop (__NR_SYSCALL_BASE+312) 341 341 - #define __NR_vserver (__NR_SYSCALL_BASE+313) 342 342 - #define __NR_ioprio_set (__NR_SYSCALL_BASE+314) 343 343 - #define __NR_ioprio_get (__NR_SYSCALL_BASE+315) 344 344 - #define __NR_inotify_init (__NR_SYSCALL_BASE+316) 345 345 - #define __NR_inotify_add_watch (__NR_SYSCALL_BASE+317) 346 346 - #define __NR_inotify_rm_watch (__NR_SYSCALL_BASE+318) 347 347 - #define __NR_mbind (__NR_SYSCALL_BASE+319) 348 348 - #define __NR_get_mempolicy (__NR_SYSCALL_BASE+320) 349 349 - #define __NR_set_mempolicy (__NR_SYSCALL_BASE+321) 350 350 - #define __NR_openat (__NR_SYSCALL_BASE+322) 351 351 - #define __NR_mkdirat (__NR_SYSCALL_BASE+323) 352 352 - #define __NR_mknodat (__NR_SYSCALL_BASE+324) 353 353 - #define __NR_fchownat (__NR_SYSCALL_BASE+325) 354 354 - #define __NR_futimesat (__NR_SYSCALL_BASE+326) 355 355 - #define __NR_fstatat64 (__NR_SYSCALL_BASE+327) 356 356 - #define __NR_unlinkat (__NR_SYSCALL_BASE+328) 357 357 - #define __NR_renameat (__NR_SYSCALL_BASE+329) 358 358 - #define __NR_linkat (__NR_SYSCALL_BASE+330) 359 359 - #define __NR_symlinkat (__NR_SYSCALL_BASE+331) 360 360 - #define __NR_readlinkat (__NR_SYSCALL_BASE+332) 361 361 - #define __NR_fchmodat (__NR_SYSCALL_BASE+333) 362 362 - #define __NR_faccessat (__NR_SYSCALL_BASE+334) 363 363 - #define __NR_pselect6 (__NR_SYSCALL_BASE+335) 364 364 - #define __NR_ppoll (__NR_SYSCALL_BASE+336) 365 365 - #define __NR_unshare (__NR_SYSCALL_BASE+337) 366 366 - #define __NR_set_robust_list (__NR_SYSCALL_BASE+338) 367 367 - #define __NR_get_robust_list (__NR_SYSCALL_BASE+339) 368 368 - #define __NR_splice (__NR_SYSCALL_BASE+340) 369 369 - #define __NR_arm_sync_file_range (__NR_SYSCALL_BASE+341) 370 370 - #define __NR_sync_file_range2 __NR_arm_sync_file_range 371 371 - #define __NR_tee (__NR_SYSCALL_BASE+342) 372 372 - #define __NR_vmsplice (__NR_SYSCALL_BASE+343) 373 373 - #define __NR_move_pages (__NR_SYSCALL_BASE+344) 374 374 - #define __NR_getcpu (__NR_SYSCALL_BASE+345) 375 375 - #define __NR_epoll_pwait (__NR_SYSCALL_BASE+346) 376 376 - #define __NR_kexec_load (__NR_SYSCALL_BASE+347) 377 377 - #define __NR_utimensat (__NR_SYSCALL_BASE+348) 378 378 - #define __NR_signalfd (__NR_SYSCALL_BASE+349) 379 379 - #define __NR_timerfd_create (__NR_SYSCALL_BASE+350) 380 380 - #define __NR_eventfd (__NR_SYSCALL_BASE+351) 381 381 - #define __NR_fallocate (__NR_SYSCALL_BASE+352) 382 382 - #define __NR_timerfd_settime (__NR_SYSCALL_BASE+353) 383 383 - #define __NR_timerfd_gettime (__NR_SYSCALL_BASE+354) 384 384 - #define __NR_signalfd4 (__NR_SYSCALL_BASE+355) 385 385 - #define __NR_eventfd2 (__NR_SYSCALL_BASE+356) 386 386 - #define __NR_epoll_create1 (__NR_SYSCALL_BASE+357) 387 387 - #define __NR_dup3 (__NR_SYSCALL_BASE+358) 388 388 - #define __NR_pipe2 (__NR_SYSCALL_BASE+359) 389 389 - #define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) 390 390 - #define __NR_preadv (__NR_SYSCALL_BASE+361) 391 391 - #define __NR_pwritev (__NR_SYSCALL_BASE+362) 392 392 - #define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) 393 393 - #define __NR_perf_event_open (__NR_SYSCALL_BASE+364) 394 394 - #define __NR_recvmmsg (__NR_SYSCALL_BASE+365) 395 395 - #define __NR_accept4 (__NR_SYSCALL_BASE+366) 396 396 - #define __NR_fanotify_init (__NR_SYSCALL_BASE+367) 397 397 - #define __NR_fanotify_mark (__NR_SYSCALL_BASE+368) 398 398 - #define __NR_prlimit64 (__NR_SYSCALL_BASE+369) 399 399 - #define __NR_name_to_handle_at (__NR_SYSCALL_BASE+370) 400 400 - #define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371) 401 401 - #define __NR_clock_adjtime (__NR_SYSCALL_BASE+372) 402 402 - #define __NR_syncfs (__NR_SYSCALL_BASE+373) 403 403 - #define __NR_sendmmsg (__NR_SYSCALL_BASE+374) 404 404 - #define __NR_setns (__NR_SYSCALL_BASE+375) 405 405 - #define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) 406 406 - #define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) 407 407 - /* 378 for kcmp */ 408 408 - 409 409 - /* 410 410 - * This may need to be greater than __NR_last_syscall+1 in order to 411 411 - * account for the padding in the syscall table 412 412 - */ 413 413 - #ifdef __KERNEL__ 414 18 #define __NR_syscalls (380) 415 415 - #endif /* __KERNEL__ */ 416 416 - 417 417 - /* 418 418 - * The following SWIs are ARM private. 419 419 - */ 420 420 - #define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000) 421 421 - #define __ARM_NR_breakpoint (__ARM_NR_BASE+1) 422 422 - #define __ARM_NR_cacheflush (__ARM_NR_BASE+2) 423 423 - #define __ARM_NR_usr26 (__ARM_NR_BASE+3) 424 424 - #define __ARM_NR_usr32 (__ARM_NR_BASE+4) 425 425 - #define __ARM_NR_set_tls (__ARM_NR_BASE+5) 426 426 - 427 427 - /* 428 428 - * *NOTE*: This is a ghost syscall private to the kernel. Only the 429 429 - * __kuser_cmpxchg code in entry-armv.S should be aware of its 430 430 - * existence. Don't ever use this from user code. 431 431 - */ 432 432 - #ifdef __KERNEL__ 433 19 #define __ARM_NR_cmpxchg (__ARM_NR_BASE+0x00fff0) 434 434 - #endif 435 435 - 436 436 - /* 437 437 - * The following syscalls are obsolete and no longer available for EABI. 438 438 - */ 439 439 - #if !defined(__KERNEL__) 440 440 - #if defined(__ARM_EABI__) 441 441 - #undef __NR_time 442 442 - #undef __NR_umount 443 443 - #undef __NR_stime 444 444 - #undef __NR_alarm 445 445 - #undef __NR_utime 446 446 - #undef __NR_getrlimit 447 447 - #undef __NR_select 448 448 - #undef __NR_readdir 449 449 - #undef __NR_mmap 450 450 - #undef __NR_socketcall 451 451 - #undef __NR_syscall 452 452 - #undef __NR_ipc 453 453 - #endif 454 454 - #endif 455 455 - 456 456 - #ifdef __KERNEL__ 457 20 458 21 #define __ARCH_WANT_STAT64 459 22 #define __ARCH_WANT_SYS_GETHOSTNAME ··· 58 495 #define __IGNORE_migrate_pages 59 496 #define __IGNORE_kcmp 60 497 61 61 - #endif /* __KERNEL__ */ 62 498 #endif /* __ASM_ARM_UNISTD_H */

+16

arch/arm/include/uapi/asm/Kbuild

reviewed

··· 1 1 # UAPI Header export list 2 2 include include/uapi/asm-generic/Kbuild.asm 3 3 4 4 + header-y += a.out.h 5 5 + header-y += byteorder.h 6 6 + header-y += fcntl.h 7 7 + header-y += hwcap.h 8 8 + header-y += ioctls.h 9 9 + header-y += kvm_para.h 10 10 + header-y += mman.h 11 11 + header-y += posix_types.h 12 12 + header-y += ptrace.h 13 13 + header-y += setup.h 14 14 + header-y += sigcontext.h 15 15 + header-y += signal.h 16 16 + header-y += stat.h 17 17 + header-y += statfs.h 18 18 + header-y += swab.h 19 19 + header-y += unistd.h

+29

arch/arm/include/uapi/asm/hwcap.h

reviewed

··· 1 1 + #ifndef _UAPI__ASMARM_HWCAP_H 2 2 + #define _UAPI__ASMARM_HWCAP_H 3 3 + 4 4 + /* 5 5 + * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP 6 6 + */ 7 7 + #define HWCAP_SWP (1 << 0) 8 8 + #define HWCAP_HALF (1 << 1) 9 9 + #define HWCAP_THUMB (1 << 2) 10 10 + #define HWCAP_26BIT (1 << 3) /* Play it safe */ 11 11 + #define HWCAP_FAST_MULT (1 << 4) 12 12 + #define HWCAP_FPA (1 << 5) 13 13 + #define HWCAP_VFP (1 << 6) 14 14 + #define HWCAP_EDSP (1 << 7) 15 15 + #define HWCAP_JAVA (1 << 8) 16 16 + #define HWCAP_IWMMXT (1 << 9) 17 17 + #define HWCAP_CRUNCH (1 << 10) 18 18 + #define HWCAP_THUMBEE (1 << 11) 19 19 + #define HWCAP_NEON (1 << 12) 20 20 + #define HWCAP_VFPv3 (1 << 13) 21 21 + #define HWCAP_VFPv3D16 (1 << 14) 22 22 + #define HWCAP_TLS (1 << 15) 23 23 + #define HWCAP_VFPv4 (1 << 16) 24 24 + #define HWCAP_IDIVA (1 << 17) 25 25 + #define HWCAP_IDIVT (1 << 18) 26 26 + #define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) 27 27 + 28 28 + 29 29 + #endif /* _UAPI__ASMARM_HWCAP_H */

+138

arch/arm/include/uapi/asm/ptrace.h

reviewed

··· 1 1 + /* 2 2 + * arch/arm/include/asm/ptrace.h 3 3 + * 4 4 + * Copyright (C) 1996-2003 Russell King 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify 7 7 + * it under the terms of the GNU General Public License version 2 as 8 8 + * published by the Free Software Foundation. 9 9 + */ 10 10 + #ifndef _UAPI__ASM_ARM_PTRACE_H 11 11 + #define _UAPI__ASM_ARM_PTRACE_H 12 12 + 13 13 + #include <asm/hwcap.h> 14 14 + 15 15 + #define PTRACE_GETREGS 12 16 16 + #define PTRACE_SETREGS 13 17 17 + #define PTRACE_GETFPREGS 14 18 18 + #define PTRACE_SETFPREGS 15 19 19 + /* PTRACE_ATTACH is 16 */ 20 20 + /* PTRACE_DETACH is 17 */ 21 21 + #define PTRACE_GETWMMXREGS 18 22 22 + #define PTRACE_SETWMMXREGS 19 23 23 + /* 20 is unused */ 24 24 + #define PTRACE_OLDSETOPTIONS 21 25 25 + #define PTRACE_GET_THREAD_AREA 22 26 26 + #define PTRACE_SET_SYSCALL 23 27 27 + /* PTRACE_SYSCALL is 24 */ 28 28 + #define PTRACE_GETCRUNCHREGS 25 29 29 + #define PTRACE_SETCRUNCHREGS 26 30 30 + #define PTRACE_GETVFPREGS 27 31 31 + #define PTRACE_SETVFPREGS 28 32 32 + #define PTRACE_GETHBPREGS 29 33 33 + #define PTRACE_SETHBPREGS 30 34 34 + 35 35 + /* 36 36 + * PSR bits 37 37 + */ 38 38 + #define USR26_MODE 0x00000000 39 39 + #define FIQ26_MODE 0x00000001 40 40 + #define IRQ26_MODE 0x00000002 41 41 + #define SVC26_MODE 0x00000003 42 42 + #define USR_MODE 0x00000010 43 43 + #define FIQ_MODE 0x00000011 44 44 + #define IRQ_MODE 0x00000012 45 45 + #define SVC_MODE 0x00000013 46 46 + #define ABT_MODE 0x00000017 47 47 + #define HYP_MODE 0x0000001a 48 48 + #define UND_MODE 0x0000001b 49 49 + #define SYSTEM_MODE 0x0000001f 50 50 + #define MODE32_BIT 0x00000010 51 51 + #define MODE_MASK 0x0000001f 52 52 + #define PSR_T_BIT 0x00000020 53 53 + #define PSR_F_BIT 0x00000040 54 54 + #define PSR_I_BIT 0x00000080 55 55 + #define PSR_A_BIT 0x00000100 56 56 + #define PSR_E_BIT 0x00000200 57 57 + #define PSR_J_BIT 0x01000000 58 58 + #define PSR_Q_BIT 0x08000000 59 59 + #define PSR_V_BIT 0x10000000 60 60 + #define PSR_C_BIT 0x20000000 61 61 + #define PSR_Z_BIT 0x40000000 62 62 + #define PSR_N_BIT 0x80000000 63 63 + 64 64 + /* 65 65 + * Groups of PSR bits 66 66 + */ 67 67 + #define PSR_f 0xff000000 /* Flags */ 68 68 + #define PSR_s 0x00ff0000 /* Status */ 69 69 + #define PSR_x 0x0000ff00 /* Extension */ 70 70 + #define PSR_c 0x000000ff /* Control */ 71 71 + 72 72 + /* 73 73 + * ARMv7 groups of PSR bits 74 74 + */ 75 75 + #define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */ 76 76 + #define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */ 77 77 + #define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 78 78 + #define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ 79 79 + 80 80 + /* 81 81 + * Default endianness state 82 82 + */ 83 83 + #ifdef CONFIG_CPU_ENDIAN_BE8 84 84 + #define PSR_ENDSTATE PSR_E_BIT 85 85 + #else 86 86 + #define PSR_ENDSTATE 0 87 87 + #endif 88 88 + 89 89 + /* 90 90 + * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 91 91 + * process is located in memory. 92 92 + */ 93 93 + #define PT_TEXT_ADDR 0x10000 94 94 + #define PT_DATA_ADDR 0x10004 95 95 + #define PT_TEXT_END_ADDR 0x10008 96 96 + 97 97 + #ifndef __ASSEMBLY__ 98 98 + 99 99 + /* 100 100 + * This struct defines the way the registers are stored on the 101 101 + * stack during a system call. Note that sizeof(struct pt_regs) 102 102 + * has to be a multiple of 8. 103 103 + */ 104 104 + #ifndef __KERNEL__ 105 105 + struct pt_regs { 106 106 + long uregs[18]; 107 107 + }; 108 108 + #endif /* __KERNEL__ */ 109 109 + 110 110 + #define ARM_cpsr uregs[16] 111 111 + #define ARM_pc uregs[15] 112 112 + #define ARM_lr uregs[14] 113 113 + #define ARM_sp uregs[13] 114 114 + #define ARM_ip uregs[12] 115 115 + #define ARM_fp uregs[11] 116 116 + #define ARM_r10 uregs[10] 117 117 + #define ARM_r9 uregs[9] 118 118 + #define ARM_r8 uregs[8] 119 119 + #define ARM_r7 uregs[7] 120 120 + #define ARM_r6 uregs[6] 121 121 + #define ARM_r5 uregs[5] 122 122 + #define ARM_r4 uregs[4] 123 123 + #define ARM_r3 uregs[3] 124 124 + #define ARM_r2 uregs[2] 125 125 + #define ARM_r1 uregs[1] 126 126 + #define ARM_r0 uregs[0] 127 127 + #define ARM_ORIG_r0 uregs[17] 128 128 + 129 129 + /* 130 130 + * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS 131 131 + * and core dumps. 132 132 + */ 133 133 + #define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ ) 134 134 + 135 135 + 136 136 + #endif /* __ASSEMBLY__ */ 137 137 + 138 138 + #endif /* _UAPI__ASM_ARM_PTRACE_H */

+187

arch/arm/include/uapi/asm/setup.h

reviewed

··· 1 1 + /* 2 2 + * linux/include/asm/setup.h 3 3 + * 4 4 + * Copyright (C) 1997-1999 Russell King 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify 7 7 + * it under the terms of the GNU General Public License version 2 as 8 8 + * published by the Free Software Foundation. 9 9 + * 10 10 + * Structure passed to kernel to tell it about the 11 11 + * hardware it's running on. See Documentation/arm/Setup 12 12 + * for more info. 13 13 + */ 14 14 + #ifndef _UAPI__ASMARM_SETUP_H 15 15 + #define _UAPI__ASMARM_SETUP_H 16 16 + 17 17 + #include <linux/types.h> 18 18 + 19 19 + #define COMMAND_LINE_SIZE 1024 20 20 + 21 21 + /* The list ends with an ATAG_NONE node. */ 22 22 + #define ATAG_NONE 0x00000000 23 23 + 24 24 + struct tag_header { 25 25 + __u32 size; 26 26 + __u32 tag; 27 27 + }; 28 28 + 29 29 + /* The list must start with an ATAG_CORE node */ 30 30 + #define ATAG_CORE 0x54410001 31 31 + 32 32 + struct tag_core { 33 33 + __u32 flags; /* bit 0 = read-only */ 34 34 + __u32 pagesize; 35 35 + __u32 rootdev; 36 36 + }; 37 37 + 38 38 + /* it is allowed to have multiple ATAG_MEM nodes */ 39 39 + #define ATAG_MEM 0x54410002 40 40 + 41 41 + struct tag_mem32 { 42 42 + __u32 size; 43 43 + __u32 start; /* physical start address */ 44 44 + }; 45 45 + 46 46 + /* VGA text type displays */ 47 47 + #define ATAG_VIDEOTEXT 0x54410003 48 48 + 49 49 + struct tag_videotext { 50 50 + __u8 x; 51 51 + __u8 y; 52 52 + __u16 video_page; 53 53 + __u8 video_mode; 54 54 + __u8 video_cols; 55 55 + __u16 video_ega_bx; 56 56 + __u8 video_lines; 57 57 + __u8 video_isvga; 58 58 + __u16 video_points; 59 59 + }; 60 60 + 61 61 + /* describes how the ramdisk will be used in kernel */ 62 62 + #define ATAG_RAMDISK 0x54410004 63 63 + 64 64 + struct tag_ramdisk { 65 65 + __u32 flags; /* bit 0 = load, bit 1 = prompt */ 66 66 + __u32 size; /* decompressed ramdisk size in _kilo_ bytes */ 67 67 + __u32 start; /* starting block of floppy-based RAM disk image */ 68 68 + }; 69 69 + 70 70 + /* describes where the compressed ramdisk image lives (virtual address) */ 71 71 + /* 72 72 + * this one accidentally used virtual addresses - as such, 73 73 + * it's deprecated. 74 74 + */ 75 75 + #define ATAG_INITRD 0x54410005 76 76 + 77 77 + /* describes where the compressed ramdisk image lives (physical address) */ 78 78 + #define ATAG_INITRD2 0x54420005 79 79 + 80 80 + struct tag_initrd { 81 81 + __u32 start; /* physical start address */ 82 82 + __u32 size; /* size of compressed ramdisk image in bytes */ 83 83 + }; 84 84 + 85 85 + /* board serial number. "64 bits should be enough for everybody" */ 86 86 + #define ATAG_SERIAL 0x54410006 87 87 + 88 88 + struct tag_serialnr { 89 89 + __u32 low; 90 90 + __u32 high; 91 91 + }; 92 92 + 93 93 + /* board revision */ 94 94 + #define ATAG_REVISION 0x54410007 95 95 + 96 96 + struct tag_revision { 97 97 + __u32 rev; 98 98 + }; 99 99 + 100 100 + /* initial values for vesafb-type framebuffers. see struct screen_info 101 101 + * in include/linux/tty.h 102 102 + */ 103 103 + #define ATAG_VIDEOLFB 0x54410008 104 104 + 105 105 + struct tag_videolfb { 106 106 + __u16 lfb_width; 107 107 + __u16 lfb_height; 108 108 + __u16 lfb_depth; 109 109 + __u16 lfb_linelength; 110 110 + __u32 lfb_base; 111 111 + __u32 lfb_size; 112 112 + __u8 red_size; 113 113 + __u8 red_pos; 114 114 + __u8 green_size; 115 115 + __u8 green_pos; 116 116 + __u8 blue_size; 117 117 + __u8 blue_pos; 118 118 + __u8 rsvd_size; 119 119 + __u8 rsvd_pos; 120 120 + }; 121 121 + 122 122 + /* command line: \0 terminated string */ 123 123 + #define ATAG_CMDLINE 0x54410009 124 124 + 125 125 + struct tag_cmdline { 126 126 + char cmdline[1]; /* this is the minimum size */ 127 127 + }; 128 128 + 129 129 + /* acorn RiscPC specific information */ 130 130 + #define ATAG_ACORN 0x41000101 131 131 + 132 132 + struct tag_acorn { 133 133 + __u32 memc_control_reg; 134 134 + __u32 vram_pages; 135 135 + __u8 sounddefault; 136 136 + __u8 adfsdrives; 137 137 + }; 138 138 + 139 139 + /* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ 140 140 + #define ATAG_MEMCLK 0x41000402 141 141 + 142 142 + struct tag_memclk { 143 143 + __u32 fmemclk; 144 144 + }; 145 145 + 146 146 + struct tag { 147 147 + struct tag_header hdr; 148 148 + union { 149 149 + struct tag_core core; 150 150 + struct tag_mem32 mem; 151 151 + struct tag_videotext videotext; 152 152 + struct tag_ramdisk ramdisk; 153 153 + struct tag_initrd initrd; 154 154 + struct tag_serialnr serialnr; 155 155 + struct tag_revision revision; 156 156 + struct tag_videolfb videolfb; 157 157 + struct tag_cmdline cmdline; 158 158 + 159 159 + /* 160 160 + * Acorn specific 161 161 + */ 162 162 + struct tag_acorn acorn; 163 163 + 164 164 + /* 165 165 + * DC21285 specific 166 166 + */ 167 167 + struct tag_memclk memclk; 168 168 + } u; 169 169 + }; 170 170 + 171 171 + struct tagtable { 172 172 + __u32 tag; 173 173 + int (*parse)(const struct tag *); 174 174 + }; 175 175 + 176 176 + #define tag_member_present(tag,member) \ 177 177 + ((unsigned long)(&((struct tag *)0L)->member + 1) \ 178 178 + <= (tag)->hdr.size * 4) 179 179 + 180 180 + #define tag_next(t) ((struct tag *)((__u32 *)(t) + (t)->hdr.size)) 181 181 + #define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) 182 182 + 183 183 + #define for_each_tag(t,base) \ 184 184 + for (t = base; t->hdr.size; t = tag_next(t)) 185 185 + 186 186 + 187 187 + #endif /* _UAPI__ASMARM_SETUP_H */

+127

arch/arm/include/uapi/asm/signal.h

reviewed

··· 1 1 + #ifndef _UAPI_ASMARM_SIGNAL_H 2 2 + #define _UAPI_ASMARM_SIGNAL_H 3 3 + 4 4 + #include <linux/types.h> 5 5 + 6 6 + /* Avoid too many header ordering problems. */ 7 7 + struct siginfo; 8 8 + 9 9 + #ifndef __KERNEL__ 10 10 + /* Here we must cater to libcs that poke about in kernel headers. */ 11 11 + 12 12 + #define NSIG 32 13 13 + typedef unsigned long sigset_t; 14 14 + 15 15 + #endif /* __KERNEL__ */ 16 16 + 17 17 + #define SIGHUP 1 18 18 + #define SIGINT 2 19 19 + #define SIGQUIT 3 20 20 + #define SIGILL 4 21 21 + #define SIGTRAP 5 22 22 + #define SIGABRT 6 23 23 + #define SIGIOT 6 24 24 + #define SIGBUS 7 25 25 + #define SIGFPE 8 26 26 + #define SIGKILL 9 27 27 + #define SIGUSR1 10 28 28 + #define SIGSEGV 11 29 29 + #define SIGUSR2 12 30 30 + #define SIGPIPE 13 31 31 + #define SIGALRM 14 32 32 + #define SIGTERM 15 33 33 + #define SIGSTKFLT 16 34 34 + #define SIGCHLD 17 35 35 + #define SIGCONT 18 36 36 + #define SIGSTOP 19 37 37 + #define SIGTSTP 20 38 38 + #define SIGTTIN 21 39 39 + #define SIGTTOU 22 40 40 + #define SIGURG 23 41 41 + #define SIGXCPU 24 42 42 + #define SIGXFSZ 25 43 43 + #define SIGVTALRM 26 44 44 + #define SIGPROF 27 45 45 + #define SIGWINCH 28 46 46 + #define SIGIO 29 47 47 + #define SIGPOLL SIGIO 48 48 + /* 49 49 + #define SIGLOST 29 50 50 + */ 51 51 + #define SIGPWR 30 52 52 + #define SIGSYS 31 53 53 + #define SIGUNUSED 31 54 54 + 55 55 + /* These should not be considered constants from userland. */ 56 56 + #define SIGRTMIN 32 57 57 + #define SIGRTMAX _NSIG 58 58 + 59 59 + #define SIGSWI 32 60 60 + 61 61 + /* 62 62 + * SA_FLAGS values: 63 63 + * 64 64 + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. 65 65 + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. 66 66 + * SA_SIGINFO deliver the signal with SIGINFO structs 67 67 + * SA_THIRTYTWO delivers the signal in 32-bit mode, even if the task 68 68 + * is running in 26-bit. 69 69 + * SA_ONSTACK allows alternate signal stacks (see sigaltstack(2)). 70 70 + * SA_RESTART flag to get restarting signals (which were the default long ago) 71 71 + * SA_NODEFER prevents the current signal from being masked in the handler. 72 72 + * SA_RESETHAND clears the handler when the signal is delivered. 73 73 + * 74 74 + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single 75 75 + * Unix names RESETHAND and NODEFER respectively. 76 76 + */ 77 77 + #define SA_NOCLDSTOP 0x00000001 78 78 + #define SA_NOCLDWAIT 0x00000002 79 79 + #define SA_SIGINFO 0x00000004 80 80 + #define SA_THIRTYTWO 0x02000000 81 81 + #define SA_RESTORER 0x04000000 82 82 + #define SA_ONSTACK 0x08000000 83 83 + #define SA_RESTART 0x10000000 84 84 + #define SA_NODEFER 0x40000000 85 85 + #define SA_RESETHAND 0x80000000 86 86 + 87 87 + #define SA_NOMASK SA_NODEFER 88 88 + #define SA_ONESHOT SA_RESETHAND 89 89 + 90 90 + 91 91 + /* 92 92 + * sigaltstack controls 93 93 + */ 94 94 + #define SS_ONSTACK 1 95 95 + #define SS_DISABLE 2 96 96 + 97 97 + #define MINSIGSTKSZ 2048 98 98 + #define SIGSTKSZ 8192 99 99 + 100 100 + #include <asm-generic/signal-defs.h> 101 101 + 102 102 + #ifndef __KERNEL__ 103 103 + /* Here we must cater to libcs that poke about in kernel headers. */ 104 104 + 105 105 + struct sigaction { 106 106 + union { 107 107 + __sighandler_t _sa_handler; 108 108 + void (*_sa_sigaction)(int, struct siginfo *, void *); 109 109 + } _u; 110 110 + sigset_t sa_mask; 111 111 + unsigned long sa_flags; 112 112 + void (*sa_restorer)(void); 113 113 + }; 114 114 + 115 115 + #define sa_handler _u._sa_handler 116 116 + #define sa_sigaction _u._sa_sigaction 117 117 + 118 118 + #endif /* __KERNEL__ */ 119 119 + 120 120 + typedef struct sigaltstack { 121 121 + void __user *ss_sp; 122 122 + int ss_flags; 123 123 + size_t ss_size; 124 124 + } stack_t; 125 125 + 126 126 + 127 127 + #endif /* _UAPI_ASMARM_SIGNAL_H */

+53

arch/arm/include/uapi/asm/swab.h

reviewed

··· 1 1 + /* 2 2 + * arch/arm/include/asm/byteorder.h 3 3 + * 4 4 + * ARM Endian-ness. In little endian mode, the data bus is connected such 5 5 + * that byte accesses appear as: 6 6 + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 7 7 + * and word accesses (data or instruction) appear as: 8 8 + * d0...d31 9 9 + * 10 10 + * When in big endian mode, byte accesses appear as: 11 11 + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 12 12 + * and word accesses (data or instruction) appear as: 13 13 + * d0...d31 14 14 + */ 15 15 + #ifndef _UAPI__ASM_ARM_SWAB_H 16 16 + #define _UAPI__ASM_ARM_SWAB_H 17 17 + 18 18 + #include <linux/compiler.h> 19 19 + #include <linux/types.h> 20 20 + 21 21 + #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) 22 22 + # define __SWAB_64_THRU_32__ 23 23 + #endif 24 24 + 25 25 + 26 26 + #if !defined(__KERNEL__) || __LINUX_ARM_ARCH__ < 6 27 27 + static inline __attribute_const__ __u32 __arch_swab32(__u32 x) 28 28 + { 29 29 + __u32 t; 30 30 + 31 31 + #ifndef __thumb__ 32 32 + if (!__builtin_constant_p(x)) { 33 33 + /* 34 34 + * The compiler needs a bit of a hint here to always do the 35 35 + * right thing and not screw it up to different degrees 36 36 + * depending on the gcc version. 37 37 + */ 38 38 + asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x)); 39 39 + } else 40 40 + #endif 41 41 + t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */ 42 42 + 43 43 + x = (x << 24) | (x >> 8); /* mov r0,r0,ror #8 */ 44 44 + t &= ~0x00FF0000; /* bic r1,r1,#0x00FF0000 */ 45 45 + x ^= (t >> 8); /* eor r0,r0,r1,lsr #8 */ 46 46 + 47 47 + return x; 48 48 + } 49 49 + #define __arch_swab32 __arch_swab32 50 50 + 51 51 + #endif 52 52 + 53 53 + #endif /* _UAPI__ASM_ARM_SWAB_H */

+450

arch/arm/include/uapi/asm/unistd.h

reviewed

··· 1 1 + /* 2 2 + * arch/arm/include/asm/unistd.h 3 3 + * 4 4 + * Copyright (C) 2001-2005 Russell King 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify 7 7 + * it under the terms of the GNU General Public License version 2 as 8 8 + * published by the Free Software Foundation. 9 9 + * 10 10 + * Please forward _all_ changes to this file to rmk@arm.linux.org.uk, 11 11 + * no matter what the change is. Thanks! 12 12 + */ 13 13 + #ifndef _UAPI__ASM_ARM_UNISTD_H 14 14 + #define _UAPI__ASM_ARM_UNISTD_H 15 15 + 16 16 + #define __NR_OABI_SYSCALL_BASE 0x900000 17 17 + 18 18 + #if defined(__thumb__) || defined(__ARM_EABI__) 19 19 + #define __NR_SYSCALL_BASE 0 20 20 + #else 21 21 + #define __NR_SYSCALL_BASE __NR_OABI_SYSCALL_BASE 22 22 + #endif 23 23 + 24 24 + /* 25 25 + * This file contains the system call numbers. 26 26 + */ 27 27 + 28 28 + #define __NR_restart_syscall (__NR_SYSCALL_BASE+ 0) 29 29 + #define __NR_exit (__NR_SYSCALL_BASE+ 1) 30 30 + #define __NR_fork (__NR_SYSCALL_BASE+ 2) 31 31 + #define __NR_read (__NR_SYSCALL_BASE+ 3) 32 32 + #define __NR_write (__NR_SYSCALL_BASE+ 4) 33 33 + #define __NR_open (__NR_SYSCALL_BASE+ 5) 34 34 + #define __NR_close (__NR_SYSCALL_BASE+ 6) 35 35 + /* 7 was sys_waitpid */ 36 36 + #define __NR_creat (__NR_SYSCALL_BASE+ 8) 37 37 + #define __NR_link (__NR_SYSCALL_BASE+ 9) 38 38 + #define __NR_unlink (__NR_SYSCALL_BASE+ 10) 39 39 + #define __NR_execve (__NR_SYSCALL_BASE+ 11) 40 40 + #define __NR_chdir (__NR_SYSCALL_BASE+ 12) 41 41 + #define __NR_time (__NR_SYSCALL_BASE+ 13) 42 42 + #define __NR_mknod (__NR_SYSCALL_BASE+ 14) 43 43 + #define __NR_chmod (__NR_SYSCALL_BASE+ 15) 44 44 + #define __NR_lchown (__NR_SYSCALL_BASE+ 16) 45 45 + /* 17 was sys_break */ 46 46 + /* 18 was sys_stat */ 47 47 + #define __NR_lseek (__NR_SYSCALL_BASE+ 19) 48 48 + #define __NR_getpid (__NR_SYSCALL_BASE+ 20) 49 49 + #define __NR_mount (__NR_SYSCALL_BASE+ 21) 50 50 + #define __NR_umount (__NR_SYSCALL_BASE+ 22) 51 51 + #define __NR_setuid (__NR_SYSCALL_BASE+ 23) 52 52 + #define __NR_getuid (__NR_SYSCALL_BASE+ 24) 53 53 + #define __NR_stime (__NR_SYSCALL_BASE+ 25) 54 54 + #define __NR_ptrace (__NR_SYSCALL_BASE+ 26) 55 55 + #define __NR_alarm (__NR_SYSCALL_BASE+ 27) 56 56 + /* 28 was sys_fstat */ 57 57 + #define __NR_pause (__NR_SYSCALL_BASE+ 29) 58 58 + #define __NR_utime (__NR_SYSCALL_BASE+ 30) 59 59 + /* 31 was sys_stty */ 60 60 + /* 32 was sys_gtty */ 61 61 + #define __NR_access (__NR_SYSCALL_BASE+ 33) 62 62 + #define __NR_nice (__NR_SYSCALL_BASE+ 34) 63 63 + /* 35 was sys_ftime */ 64 64 + #define __NR_sync (__NR_SYSCALL_BASE+ 36) 65 65 + #define __NR_kill (__NR_SYSCALL_BASE+ 37) 66 66 + #define __NR_rename (__NR_SYSCALL_BASE+ 38) 67 67 + #define __NR_mkdir (__NR_SYSCALL_BASE+ 39) 68 68 + #define __NR_rmdir (__NR_SYSCALL_BASE+ 40) 69 69 + #define __NR_dup (__NR_SYSCALL_BASE+ 41) 70 70 + #define __NR_pipe (__NR_SYSCALL_BASE+ 42) 71 71 + #define __NR_times (__NR_SYSCALL_BASE+ 43) 72 72 + /* 44 was sys_prof */ 73 73 + #define __NR_brk (__NR_SYSCALL_BASE+ 45) 74 74 + #define __NR_setgid (__NR_SYSCALL_BASE+ 46) 75 75 + #define __NR_getgid (__NR_SYSCALL_BASE+ 47) 76 76 + /* 48 was sys_signal */ 77 77 + #define __NR_geteuid (__NR_SYSCALL_BASE+ 49) 78 78 + #define __NR_getegid (__NR_SYSCALL_BASE+ 50) 79 79 + #define __NR_acct (__NR_SYSCALL_BASE+ 51) 80 80 + #define __NR_umount2 (__NR_SYSCALL_BASE+ 52) 81 81 + /* 53 was sys_lock */ 82 82 + #define __NR_ioctl (__NR_SYSCALL_BASE+ 54) 83 83 + #define __NR_fcntl (__NR_SYSCALL_BASE+ 55) 84 84 + /* 56 was sys_mpx */ 85 85 + #define __NR_setpgid (__NR_SYSCALL_BASE+ 57) 86 86 + /* 58 was sys_ulimit */ 87 87 + /* 59 was sys_olduname */ 88 88 + #define __NR_umask (__NR_SYSCALL_BASE+ 60) 89 89 + #define __NR_chroot (__NR_SYSCALL_BASE+ 61) 90 90 + #define __NR_ustat (__NR_SYSCALL_BASE+ 62) 91 91 + #define __NR_dup2 (__NR_SYSCALL_BASE+ 63) 92 92 + #define __NR_getppid (__NR_SYSCALL_BASE+ 64) 93 93 + #define __NR_getpgrp (__NR_SYSCALL_BASE+ 65) 94 94 + #define __NR_setsid (__NR_SYSCALL_BASE+ 66) 95 95 + #define __NR_sigaction (__NR_SYSCALL_BASE+ 67) 96 96 + /* 68 was sys_sgetmask */ 97 97 + /* 69 was sys_ssetmask */ 98 98 + #define __NR_setreuid (__NR_SYSCALL_BASE+ 70) 99 99 + #define __NR_setregid (__NR_SYSCALL_BASE+ 71) 100 100 + #define __NR_sigsuspend (__NR_SYSCALL_BASE+ 72) 101 101 + #define __NR_sigpending (__NR_SYSCALL_BASE+ 73) 102 102 + #define __NR_sethostname (__NR_SYSCALL_BASE+ 74) 103 103 + #define __NR_setrlimit (__NR_SYSCALL_BASE+ 75) 104 104 + #define __NR_getrlimit (__NR_SYSCALL_BASE+ 76) /* Back compat 2GB limited rlimit */ 105 105 + #define __NR_getrusage (__NR_SYSCALL_BASE+ 77) 106 106 + #define __NR_gettimeofday (__NR_SYSCALL_BASE+ 78) 107 107 + #define __NR_settimeofday (__NR_SYSCALL_BASE+ 79) 108 108 + #define __NR_getgroups (__NR_SYSCALL_BASE+ 80) 109 109 + #define __NR_setgroups (__NR_SYSCALL_BASE+ 81) 110 110 + #define __NR_select (__NR_SYSCALL_BASE+ 82) 111 111 + #define __NR_symlink (__NR_SYSCALL_BASE+ 83) 112 112 + /* 84 was sys_lstat */ 113 113 + #define __NR_readlink (__NR_SYSCALL_BASE+ 85) 114 114 + #define __NR_uselib (__NR_SYSCALL_BASE+ 86) 115 115 + #define __NR_swapon (__NR_SYSCALL_BASE+ 87) 116 116 + #define __NR_reboot (__NR_SYSCALL_BASE+ 88) 117 117 + #define __NR_readdir (__NR_SYSCALL_BASE+ 89) 118 118 + #define __NR_mmap (__NR_SYSCALL_BASE+ 90) 119 119 + #define __NR_munmap (__NR_SYSCALL_BASE+ 91) 120 120 + #define __NR_truncate (__NR_SYSCALL_BASE+ 92) 121 121 + #define __NR_ftruncate (__NR_SYSCALL_BASE+ 93) 122 122 + #define __NR_fchmod (__NR_SYSCALL_BASE+ 94) 123 123 + #define __NR_fchown (__NR_SYSCALL_BASE+ 95) 124 124 + #define __NR_getpriority (__NR_SYSCALL_BASE+ 96) 125 125 + #define __NR_setpriority (__NR_SYSCALL_BASE+ 97) 126 126 + /* 98 was sys_profil */ 127 127 + #define __NR_statfs (__NR_SYSCALL_BASE+ 99) 128 128 + #define __NR_fstatfs (__NR_SYSCALL_BASE+100) 129 129 + /* 101 was sys_ioperm */ 130 130 + #define __NR_socketcall (__NR_SYSCALL_BASE+102) 131 131 + #define __NR_syslog (__NR_SYSCALL_BASE+103) 132 132 + #define __NR_setitimer (__NR_SYSCALL_BASE+104) 133 133 + #define __NR_getitimer (__NR_SYSCALL_BASE+105) 134 134 + #define __NR_stat (__NR_SYSCALL_BASE+106) 135 135 + #define __NR_lstat (__NR_SYSCALL_BASE+107) 136 136 + #define __NR_fstat (__NR_SYSCALL_BASE+108) 137 137 + /* 109 was sys_uname */ 138 138 + /* 110 was sys_iopl */ 139 139 + #define __NR_vhangup (__NR_SYSCALL_BASE+111) 140 140 + /* 112 was sys_idle */ 141 141 + #define __NR_syscall (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */ 142 142 + #define __NR_wait4 (__NR_SYSCALL_BASE+114) 143 143 + #define __NR_swapoff (__NR_SYSCALL_BASE+115) 144 144 + #define __NR_sysinfo (__NR_SYSCALL_BASE+116) 145 145 + #define __NR_ipc (__NR_SYSCALL_BASE+117) 146 146 + #define __NR_fsync (__NR_SYSCALL_BASE+118) 147 147 + #define __NR_sigreturn (__NR_SYSCALL_BASE+119) 148 148 + #define __NR_clone (__NR_SYSCALL_BASE+120) 149 149 + #define __NR_setdomainname (__NR_SYSCALL_BASE+121) 150 150 + #define __NR_uname (__NR_SYSCALL_BASE+122) 151 151 + /* 123 was sys_modify_ldt */ 152 152 + #define __NR_adjtimex (__NR_SYSCALL_BASE+124) 153 153 + #define __NR_mprotect (__NR_SYSCALL_BASE+125) 154 154 + #define __NR_sigprocmask (__NR_SYSCALL_BASE+126) 155 155 + /* 127 was sys_create_module */ 156 156 + #define __NR_init_module (__NR_SYSCALL_BASE+128) 157 157 + #define __NR_delete_module (__NR_SYSCALL_BASE+129) 158 158 + /* 130 was sys_get_kernel_syms */ 159 159 + #define __NR_quotactl (__NR_SYSCALL_BASE+131) 160 160 + #define __NR_getpgid (__NR_SYSCALL_BASE+132) 161 161 + #define __NR_fchdir (__NR_SYSCALL_BASE+133) 162 162 + #define __NR_bdflush (__NR_SYSCALL_BASE+134) 163 163 + #define __NR_sysfs (__NR_SYSCALL_BASE+135) 164 164 + #define __NR_personality (__NR_SYSCALL_BASE+136) 165 165 + /* 137 was sys_afs_syscall */ 166 166 + #define __NR_setfsuid (__NR_SYSCALL_BASE+138) 167 167 + #define __NR_setfsgid (__NR_SYSCALL_BASE+139) 168 168 + #define __NR__llseek (__NR_SYSCALL_BASE+140) 169 169 + #define __NR_getdents (__NR_SYSCALL_BASE+141) 170 170 + #define __NR__newselect (__NR_SYSCALL_BASE+142) 171 171 + #define __NR_flock (__NR_SYSCALL_BASE+143) 172 172 + #define __NR_msync (__NR_SYSCALL_BASE+144) 173 173 + #define __NR_readv (__NR_SYSCALL_BASE+145) 174 174 + #define __NR_writev (__NR_SYSCALL_BASE+146) 175 175 + #define __NR_getsid (__NR_SYSCALL_BASE+147) 176 176 + #define __NR_fdatasync (__NR_SYSCALL_BASE+148) 177 177 + #define __NR__sysctl (__NR_SYSCALL_BASE+149) 178 178 + #define __NR_mlock (__NR_SYSCALL_BASE+150) 179 179 + #define __NR_munlock (__NR_SYSCALL_BASE+151) 180 180 + #define __NR_mlockall (__NR_SYSCALL_BASE+152) 181 181 + #define __NR_munlockall (__NR_SYSCALL_BASE+153) 182 182 + #define __NR_sched_setparam (__NR_SYSCALL_BASE+154) 183 183 + #define __NR_sched_getparam (__NR_SYSCALL_BASE+155) 184 184 + #define __NR_sched_setscheduler (__NR_SYSCALL_BASE+156) 185 185 + #define __NR_sched_getscheduler (__NR_SYSCALL_BASE+157) 186 186 + #define __NR_sched_yield (__NR_SYSCALL_BASE+158) 187 187 + #define __NR_sched_get_priority_max (__NR_SYSCALL_BASE+159) 188 188 + #define __NR_sched_get_priority_min (__NR_SYSCALL_BASE+160) 189 189 + #define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE+161) 190 190 + #define __NR_nanosleep (__NR_SYSCALL_BASE+162) 191 191 + #define __NR_mremap (__NR_SYSCALL_BASE+163) 192 192 + #define __NR_setresuid (__NR_SYSCALL_BASE+164) 193 193 + #define __NR_getresuid (__NR_SYSCALL_BASE+165) 194 194 + /* 166 was sys_vm86 */ 195 195 + /* 167 was sys_query_module */ 196 196 + #define __NR_poll (__NR_SYSCALL_BASE+168) 197 197 + #define __NR_nfsservctl (__NR_SYSCALL_BASE+169) 198 198 + #define __NR_setresgid (__NR_SYSCALL_BASE+170) 199 199 + #define __NR_getresgid (__NR_SYSCALL_BASE+171) 200 200 + #define __NR_prctl (__NR_SYSCALL_BASE+172) 201 201 + #define __NR_rt_sigreturn (__NR_SYSCALL_BASE+173) 202 202 + #define __NR_rt_sigaction (__NR_SYSCALL_BASE+174) 203 203 + #define __NR_rt_sigprocmask (__NR_SYSCALL_BASE+175) 204 204 + #define __NR_rt_sigpending (__NR_SYSCALL_BASE+176) 205 205 + #define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE+177) 206 206 + #define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE+178) 207 207 + #define __NR_rt_sigsuspend (__NR_SYSCALL_BASE+179) 208 208 + #define __NR_pread64 (__NR_SYSCALL_BASE+180) 209 209 + #define __NR_pwrite64 (__NR_SYSCALL_BASE+181) 210 210 + #define __NR_chown (__NR_SYSCALL_BASE+182) 211 211 + #define __NR_getcwd (__NR_SYSCALL_BASE+183) 212 212 + #define __NR_capget (__NR_SYSCALL_BASE+184) 213 213 + #define __NR_capset (__NR_SYSCALL_BASE+185) 214 214 + #define __NR_sigaltstack (__NR_SYSCALL_BASE+186) 215 215 + #define __NR_sendfile (__NR_SYSCALL_BASE+187) 216 216 + /* 188 reserved */ 217 217 + /* 189 reserved */ 218 218 + #define __NR_vfork (__NR_SYSCALL_BASE+190) 219 219 + #define __NR_ugetrlimit (__NR_SYSCALL_BASE+191) /* SuS compliant getrlimit */ 220 220 + #define __NR_mmap2 (__NR_SYSCALL_BASE+192) 221 221 + #define __NR_truncate64 (__NR_SYSCALL_BASE+193) 222 222 + #define __NR_ftruncate64 (__NR_SYSCALL_BASE+194) 223 223 + #define __NR_stat64 (__NR_SYSCALL_BASE+195) 224 224 + #define __NR_lstat64 (__NR_SYSCALL_BASE+196) 225 225 + #define __NR_fstat64 (__NR_SYSCALL_BASE+197) 226 226 + #define __NR_lchown32 (__NR_SYSCALL_BASE+198) 227 227 + #define __NR_getuid32 (__NR_SYSCALL_BASE+199) 228 228 + #define __NR_getgid32 (__NR_SYSCALL_BASE+200) 229 229 + #define __NR_geteuid32 (__NR_SYSCALL_BASE+201) 230 230 + #define __NR_getegid32 (__NR_SYSCALL_BASE+202) 231 231 + #define __NR_setreuid32 (__NR_SYSCALL_BASE+203) 232 232 + #define __NR_setregid32 (__NR_SYSCALL_BASE+204) 233 233 + #define __NR_getgroups32 (__NR_SYSCALL_BASE+205) 234 234 + #define __NR_setgroups32 (__NR_SYSCALL_BASE+206) 235 235 + #define __NR_fchown32 (__NR_SYSCALL_BASE+207) 236 236 + #define __NR_setresuid32 (__NR_SYSCALL_BASE+208) 237 237 + #define __NR_getresuid32 (__NR_SYSCALL_BASE+209) 238 238 + #define __NR_setresgid32 (__NR_SYSCALL_BASE+210) 239 239 + #define __NR_getresgid32 (__NR_SYSCALL_BASE+211) 240 240 + #define __NR_chown32 (__NR_SYSCALL_BASE+212) 241 241 + #define __NR_setuid32 (__NR_SYSCALL_BASE+213) 242 242 + #define __NR_setgid32 (__NR_SYSCALL_BASE+214) 243 243 + #define __NR_setfsuid32 (__NR_SYSCALL_BASE+215) 244 244 + #define __NR_setfsgid32 (__NR_SYSCALL_BASE+216) 245 245 + #define __NR_getdents64 (__NR_SYSCALL_BASE+217) 246 246 + #define __NR_pivot_root (__NR_SYSCALL_BASE+218) 247 247 + #define __NR_mincore (__NR_SYSCALL_BASE+219) 248 248 + #define __NR_madvise (__NR_SYSCALL_BASE+220) 249 249 + #define __NR_fcntl64 (__NR_SYSCALL_BASE+221) 250 250 + /* 222 for tux */ 251 251 + /* 223 is unused */ 252 252 + #define __NR_gettid (__NR_SYSCALL_BASE+224) 253 253 + #define __NR_readahead (__NR_SYSCALL_BASE+225) 254 254 + #define __NR_setxattr (__NR_SYSCALL_BASE+226) 255 255 + #define __NR_lsetxattr (__NR_SYSCALL_BASE+227) 256 256 + #define __NR_fsetxattr (__NR_SYSCALL_BASE+228) 257 257 + #define __NR_getxattr (__NR_SYSCALL_BASE+229) 258 258 + #define __NR_lgetxattr (__NR_SYSCALL_BASE+230) 259 259 + #define __NR_fgetxattr (__NR_SYSCALL_BASE+231) 260 260 + #define __NR_listxattr (__NR_SYSCALL_BASE+232) 261 261 + #define __NR_llistxattr (__NR_SYSCALL_BASE+233) 262 262 + #define __NR_flistxattr (__NR_SYSCALL_BASE+234) 263 263 + #define __NR_removexattr (__NR_SYSCALL_BASE+235) 264 264 + #define __NR_lremovexattr (__NR_SYSCALL_BASE+236) 265 265 + #define __NR_fremovexattr (__NR_SYSCALL_BASE+237) 266 266 + #define __NR_tkill (__NR_SYSCALL_BASE+238) 267 267 + #define __NR_sendfile64 (__NR_SYSCALL_BASE+239) 268 268 + #define __NR_futex (__NR_SYSCALL_BASE+240) 269 269 + #define __NR_sched_setaffinity (__NR_SYSCALL_BASE+241) 270 270 + #define __NR_sched_getaffinity (__NR_SYSCALL_BASE+242) 271 271 + #define __NR_io_setup (__NR_SYSCALL_BASE+243) 272 272 + #define __NR_io_destroy (__NR_SYSCALL_BASE+244) 273 273 + #define __NR_io_getevents (__NR_SYSCALL_BASE+245) 274 274 + #define __NR_io_submit (__NR_SYSCALL_BASE+246) 275 275 + #define __NR_io_cancel (__NR_SYSCALL_BASE+247) 276 276 + #define __NR_exit_group (__NR_SYSCALL_BASE+248) 277 277 + #define __NR_lookup_dcookie (__NR_SYSCALL_BASE+249) 278 278 + #define __NR_epoll_create (__NR_SYSCALL_BASE+250) 279 279 + #define __NR_epoll_ctl (__NR_SYSCALL_BASE+251) 280 280 + #define __NR_epoll_wait (__NR_SYSCALL_BASE+252) 281 281 + #define __NR_remap_file_pages (__NR_SYSCALL_BASE+253) 282 282 + /* 254 for set_thread_area */ 283 283 + /* 255 for get_thread_area */ 284 284 + #define __NR_set_tid_address (__NR_SYSCALL_BASE+256) 285 285 + #define __NR_timer_create (__NR_SYSCALL_BASE+257) 286 286 + #define __NR_timer_settime (__NR_SYSCALL_BASE+258) 287 287 + #define __NR_timer_gettime (__NR_SYSCALL_BASE+259) 288 288 + #define __NR_timer_getoverrun (__NR_SYSCALL_BASE+260) 289 289 + #define __NR_timer_delete (__NR_SYSCALL_BASE+261) 290 290 + #define __NR_clock_settime (__NR_SYSCALL_BASE+262) 291 291 + #define __NR_clock_gettime (__NR_SYSCALL_BASE+263) 292 292 + #define __NR_clock_getres (__NR_SYSCALL_BASE+264) 293 293 + #define __NR_clock_nanosleep (__NR_SYSCALL_BASE+265) 294 294 + #define __NR_statfs64 (__NR_SYSCALL_BASE+266) 295 295 + #define __NR_fstatfs64 (__NR_SYSCALL_BASE+267) 296 296 + #define __NR_tgkill (__NR_SYSCALL_BASE+268) 297 297 + #define __NR_utimes (__NR_SYSCALL_BASE+269) 298 298 + #define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE+270) 299 299 + #define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271) 300 300 + #define __NR_pciconfig_read (__NR_SYSCALL_BASE+272) 301 301 + #define __NR_pciconfig_write (__NR_SYSCALL_BASE+273) 302 302 + #define __NR_mq_open (__NR_SYSCALL_BASE+274) 303 303 + #define __NR_mq_unlink (__NR_SYSCALL_BASE+275) 304 304 + #define __NR_mq_timedsend (__NR_SYSCALL_BASE+276) 305 305 + #define __NR_mq_timedreceive (__NR_SYSCALL_BASE+277) 306 306 + #define __NR_mq_notify (__NR_SYSCALL_BASE+278) 307 307 + #define __NR_mq_getsetattr (__NR_SYSCALL_BASE+279) 308 308 + #define __NR_waitid (__NR_SYSCALL_BASE+280) 309 309 + #define __NR_socket (__NR_SYSCALL_BASE+281) 310 310 + #define __NR_bind (__NR_SYSCALL_BASE+282) 311 311 + #define __NR_connect (__NR_SYSCALL_BASE+283) 312 312 + #define __NR_listen (__NR_SYSCALL_BASE+284) 313 313 + #define __NR_accept (__NR_SYSCALL_BASE+285) 314 314 + #define __NR_getsockname (__NR_SYSCALL_BASE+286) 315 315 + #define __NR_getpeername (__NR_SYSCALL_BASE+287) 316 316 + #define __NR_socketpair (__NR_SYSCALL_BASE+288) 317 317 + #define __NR_send (__NR_SYSCALL_BASE+289) 318 318 + #define __NR_sendto (__NR_SYSCALL_BASE+290) 319 319 + #define __NR_recv (__NR_SYSCALL_BASE+291) 320 320 + #define __NR_recvfrom (__NR_SYSCALL_BASE+292) 321 321 + #define __NR_shutdown (__NR_SYSCALL_BASE+293) 322 322 + #define __NR_setsockopt (__NR_SYSCALL_BASE+294) 323 323 + #define __NR_getsockopt (__NR_SYSCALL_BASE+295) 324 324 + #define __NR_sendmsg (__NR_SYSCALL_BASE+296) 325 325 + #define __NR_recvmsg (__NR_SYSCALL_BASE+297) 326 326 + #define __NR_semop (__NR_SYSCALL_BASE+298) 327 327 + #define __NR_semget (__NR_SYSCALL_BASE+299) 328 328 + #define __NR_semctl (__NR_SYSCALL_BASE+300) 329 329 + #define __NR_msgsnd (__NR_SYSCALL_BASE+301) 330 330 + #define __NR_msgrcv (__NR_SYSCALL_BASE+302) 331 331 + #define __NR_msgget (__NR_SYSCALL_BASE+303) 332 332 + #define __NR_msgctl (__NR_SYSCALL_BASE+304) 333 333 + #define __NR_shmat (__NR_SYSCALL_BASE+305) 334 334 + #define __NR_shmdt (__NR_SYSCALL_BASE+306) 335 335 + #define __NR_shmget (__NR_SYSCALL_BASE+307) 336 336 + #define __NR_shmctl (__NR_SYSCALL_BASE+308) 337 337 + #define __NR_add_key (__NR_SYSCALL_BASE+309) 338 338 + #define __NR_request_key (__NR_SYSCALL_BASE+310) 339 339 + #define __NR_keyctl (__NR_SYSCALL_BASE+311) 340 340 + #define __NR_semtimedop (__NR_SYSCALL_BASE+312) 341 341 + #define __NR_vserver (__NR_SYSCALL_BASE+313) 342 342 + #define __NR_ioprio_set (__NR_SYSCALL_BASE+314) 343 343 + #define __NR_ioprio_get (__NR_SYSCALL_BASE+315) 344 344 + #define __NR_inotify_init (__NR_SYSCALL_BASE+316) 345 345 + #define __NR_inotify_add_watch (__NR_SYSCALL_BASE+317) 346 346 + #define __NR_inotify_rm_watch (__NR_SYSCALL_BASE+318) 347 347 + #define __NR_mbind (__NR_SYSCALL_BASE+319) 348 348 + #define __NR_get_mempolicy (__NR_SYSCALL_BASE+320) 349 349 + #define __NR_set_mempolicy (__NR_SYSCALL_BASE+321) 350 350 + #define __NR_openat (__NR_SYSCALL_BASE+322) 351 351 + #define __NR_mkdirat (__NR_SYSCALL_BASE+323) 352 352 + #define __NR_mknodat (__NR_SYSCALL_BASE+324) 353 353 + #define __NR_fchownat (__NR_SYSCALL_BASE+325) 354 354 + #define __NR_futimesat (__NR_SYSCALL_BASE+326) 355 355 + #define __NR_fstatat64 (__NR_SYSCALL_BASE+327) 356 356 + #define __NR_unlinkat (__NR_SYSCALL_BASE+328) 357 357 + #define __NR_renameat (__NR_SYSCALL_BASE+329) 358 358 + #define __NR_linkat (__NR_SYSCALL_BASE+330) 359 359 + #define __NR_symlinkat (__NR_SYSCALL_BASE+331) 360 360 + #define __NR_readlinkat (__NR_SYSCALL_BASE+332) 361 361 + #define __NR_fchmodat (__NR_SYSCALL_BASE+333) 362 362 + #define __NR_faccessat (__NR_SYSCALL_BASE+334) 363 363 + #define __NR_pselect6 (__NR_SYSCALL_BASE+335) 364 364 + #define __NR_ppoll (__NR_SYSCALL_BASE+336) 365 365 + #define __NR_unshare (__NR_SYSCALL_BASE+337) 366 366 + #define __NR_set_robust_list (__NR_SYSCALL_BASE+338) 367 367 + #define __NR_get_robust_list (__NR_SYSCALL_BASE+339) 368 368 + #define __NR_splice (__NR_SYSCALL_BASE+340) 369 369 + #define __NR_arm_sync_file_range (__NR_SYSCALL_BASE+341) 370 370 + #define __NR_sync_file_range2 __NR_arm_sync_file_range 371 371 + #define __NR_tee (__NR_SYSCALL_BASE+342) 372 372 + #define __NR_vmsplice (__NR_SYSCALL_BASE+343) 373 373 + #define __NR_move_pages (__NR_SYSCALL_BASE+344) 374 374 + #define __NR_getcpu (__NR_SYSCALL_BASE+345) 375 375 + #define __NR_epoll_pwait (__NR_SYSCALL_BASE+346) 376 376 + #define __NR_kexec_load (__NR_SYSCALL_BASE+347) 377 377 + #define __NR_utimensat (__NR_SYSCALL_BASE+348) 378 378 + #define __NR_signalfd (__NR_SYSCALL_BASE+349) 379 379 + #define __NR_timerfd_create (__NR_SYSCALL_BASE+350) 380 380 + #define __NR_eventfd (__NR_SYSCALL_BASE+351) 381 381 + #define __NR_fallocate (__NR_SYSCALL_BASE+352) 382 382 + #define __NR_timerfd_settime (__NR_SYSCALL_BASE+353) 383 383 + #define __NR_timerfd_gettime (__NR_SYSCALL_BASE+354) 384 384 + #define __NR_signalfd4 (__NR_SYSCALL_BASE+355) 385 385 + #define __NR_eventfd2 (__NR_SYSCALL_BASE+356) 386 386 + #define __NR_epoll_create1 (__NR_SYSCALL_BASE+357) 387 387 + #define __NR_dup3 (__NR_SYSCALL_BASE+358) 388 388 + #define __NR_pipe2 (__NR_SYSCALL_BASE+359) 389 389 + #define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) 390 390 + #define __NR_preadv (__NR_SYSCALL_BASE+361) 391 391 + #define __NR_pwritev (__NR_SYSCALL_BASE+362) 392 392 + #define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) 393 393 + #define __NR_perf_event_open (__NR_SYSCALL_BASE+364) 394 394 + #define __NR_recvmmsg (__NR_SYSCALL_BASE+365) 395 395 + #define __NR_accept4 (__NR_SYSCALL_BASE+366) 396 396 + #define __NR_fanotify_init (__NR_SYSCALL_BASE+367) 397 397 + #define __NR_fanotify_mark (__NR_SYSCALL_BASE+368) 398 398 + #define __NR_prlimit64 (__NR_SYSCALL_BASE+369) 399 399 + #define __NR_name_to_handle_at (__NR_SYSCALL_BASE+370) 400 400 + #define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371) 401 401 + #define __NR_clock_adjtime (__NR_SYSCALL_BASE+372) 402 402 + #define __NR_syncfs (__NR_SYSCALL_BASE+373) 403 403 + #define __NR_sendmmsg (__NR_SYSCALL_BASE+374) 404 404 + #define __NR_setns (__NR_SYSCALL_BASE+375) 405 405 + #define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) 406 406 + #define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) 407 407 + /* 378 for kcmp */ 408 408 + 409 409 + /* 410 410 + * This may need to be greater than __NR_last_syscall+1 in order to 411 411 + * account for the padding in the syscall table 412 412 + */ 413 413 + 414 414 + /* 415 415 + * The following SWIs are ARM private. 416 416 + */ 417 417 + #define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000) 418 418 + #define __ARM_NR_breakpoint (__ARM_NR_BASE+1) 419 419 + #define __ARM_NR_cacheflush (__ARM_NR_BASE+2) 420 420 + #define __ARM_NR_usr26 (__ARM_NR_BASE+3) 421 421 + #define __ARM_NR_usr32 (__ARM_NR_BASE+4) 422 422 + #define __ARM_NR_set_tls (__ARM_NR_BASE+5) 423 423 + 424 424 + /* 425 425 + * *NOTE*: This is a ghost syscall private to the kernel. Only the 426 426 + * __kuser_cmpxchg code in entry-armv.S should be aware of its 427 427 + * existence. Don't ever use this from user code. 428 428 + */ 429 429 + 430 430 + /* 431 431 + * The following syscalls are obsolete and no longer available for EABI. 432 432 + */ 433 433 + #if !defined(__KERNEL__) 434 434 + #if defined(__ARM_EABI__) 435 435 + #undef __NR_time 436 436 + #undef __NR_umount 437 437 + #undef __NR_stime 438 438 + #undef __NR_alarm 439 439 + #undef __NR_utime 440 440 + #undef __NR_getrlimit 441 441 + #undef __NR_select 442 442 + #undef __NR_readdir 443 443 + #undef __NR_mmap 444 444 + #undef __NR_socketcall 445 445 + #undef __NR_syscall 446 446 + #undef __NR_ipc 447 447 + #endif 448 448 + #endif 449 449 + 450 450 + #endif /* _UAPI__ASM_ARM_UNISTD_H */

+13 -13

arch/arm/mach-at91/Kconfig

reviewed

··· 19 19 20 20 config SOC_AT91SAM9 21 21 bool 22 22 - select GENERIC_CLOCKEVENTS 23 22 select CPU_ARM926T 23 23 + select GENERIC_CLOCKEVENTS 24 24 25 25 menu "Atmel AT91 System-on-Chip" 26 26 ··· 28 28 29 29 config SOC_AT91SAM9 30 30 bool 31 31 + select AT91_SAM9_SMC 32 32 + select AT91_SAM9_TIME 31 33 select CPU_ARM926T 32 34 select MULTI_IRQ_HANDLER 33 35 select SPARSE_IRQ 34 34 - select AT91_SAM9_TIME 35 35 - select AT91_SAM9_SMC 36 36 37 37 config SOC_AT91RM9200 38 38 bool "AT91RM9200" 39 39 select CPU_ARM920T 40 40 - select MULTI_IRQ_HANDLER 41 41 - select SPARSE_IRQ 42 40 select GENERIC_CLOCKEVENTS 43 41 select HAVE_AT91_DBGU0 42 42 + select MULTI_IRQ_HANDLER 43 43 + select SPARSE_IRQ 44 44 45 45 config SOC_AT91SAM9260 46 46 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" 47 47 - select SOC_AT91SAM9 48 47 select HAVE_AT91_DBGU0 49 48 select HAVE_NET_MACB 49 49 + select SOC_AT91SAM9 50 50 help 51 51 Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE 52 52 or AT91SAM9G20 SoC. 53 53 54 54 config SOC_AT91SAM9261 55 55 bool "AT91SAM9261 or AT91SAM9G10" 56 56 - select SOC_AT91SAM9 57 56 select HAVE_AT91_DBGU0 58 57 select HAVE_FB_ATMEL 58 58 + select SOC_AT91SAM9 59 59 help 60 60 Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. 61 61 62 62 config SOC_AT91SAM9263 63 63 bool "AT91SAM9263" 64 64 - select SOC_AT91SAM9 65 64 select HAVE_AT91_DBGU1 66 65 select HAVE_FB_ATMEL 67 66 select HAVE_NET_MACB 67 67 + select SOC_AT91SAM9 68 68 69 69 config SOC_AT91SAM9RL 70 70 bool "AT91SAM9RL" 71 71 - select SOC_AT91SAM9 72 71 select HAVE_AT91_DBGU0 73 72 select HAVE_FB_ATMEL 73 73 + select SOC_AT91SAM9 74 74 75 75 config SOC_AT91SAM9G45 76 76 bool "AT91SAM9G45 or AT91SAM9M10 families" 77 77 - select SOC_AT91SAM9 78 77 select HAVE_AT91_DBGU1 79 78 select HAVE_FB_ATMEL 80 79 select HAVE_NET_MACB 80 80 + select SOC_AT91SAM9 81 81 help 82 82 Select this if you are using one of Atmel's AT91SAM9G45 family SoC. 83 83 This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. 84 84 85 85 config SOC_AT91SAM9X5 86 86 bool "AT91SAM9x5 family" 87 87 - select SOC_AT91SAM9 88 87 select HAVE_AT91_DBGU0 89 88 select HAVE_FB_ATMEL 90 89 select HAVE_NET_MACB 90 90 + select SOC_AT91SAM9 91 91 help 92 92 Select this if you are using one of Atmel's AT91SAM9x5 family SoC. 93 93 This means that your SAM9 name finishes with a '5' (except if it is ··· 97 97 98 98 config SOC_AT91SAM9N12 99 99 bool "AT91SAM9N12 family" 100 100 - select SOC_AT91SAM9 101 100 select HAVE_AT91_DBGU0 102 101 select HAVE_FB_ATMEL 102 102 + select SOC_AT91SAM9 103 103 help 104 104 Select this if you are using Atmel's AT91SAM9N12 SoC. 105 105 ··· 144 144 config ARCH_AT91X40 145 145 bool "AT91x40" 146 146 depends on !MMU 147 147 + select ARCH_USES_GETTIMEOFFSET 147 148 select MULTI_IRQ_HANDLER 148 149 select SPARSE_IRQ 149 149 - select ARCH_USES_GETTIMEOFFSET 150 150 151 151 endchoice 152 152

+2 -2

arch/arm/mach-clps711x/Kconfig

reviewed

··· 23 23 24 24 config ARCH_EDB7211 25 25 bool "EDB7211" 26 26 - select ISA 27 27 - select ARCH_SPARSEMEM_ENABLE 28 26 select ARCH_SELECT_MEMORY_MODEL 27 27 + select ARCH_SPARSEMEM_ENABLE 28 28 + select ISA 29 29 help 30 30 Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211 31 31 evaluation board.

+8 -8

arch/arm/mach-davinci/Kconfig

reviewed

··· 4 4 bool 5 5 6 6 config CP_INTC 7 7 - select IRQ_DOMAIN 8 7 bool 8 8 + select IRQ_DOMAIN 9 9 10 10 config ARCH_DAVINCI_DMx 11 11 - select CPU_ARM926T 12 11 bool 12 12 + select CPU_ARM926T 13 13 14 14 menu "TI DaVinci Implementations" 15 15 ··· 32 32 33 33 config ARCH_DAVINCI_DA830 34 34 bool "DA830/OMAP-L137/AM17x based system" 35 35 - select CP_INTC 36 35 select ARCH_DAVINCI_DA8XX 37 36 select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 37 37 + select CP_INTC 38 38 39 39 config ARCH_DAVINCI_DA850 40 40 bool "DA850/OMAP-L138/AM18x based system" 41 41 - select CP_INTC 42 41 select ARCH_DAVINCI_DA8XX 43 42 select ARCH_HAS_CPUFREQ 43 43 + select CP_INTC 44 44 45 45 config ARCH_DAVINCI_DA8XX 46 46 - select CPU_ARM926T 47 46 bool 47 47 + select CPU_ARM926T 48 48 49 49 config ARCH_DAVINCI_DM365 50 50 bool "DaVinci 365 based system" ··· 52 52 select ARCH_DAVINCI_DMx 53 53 54 54 config ARCH_DAVINCI_TNETV107X 55 55 + bool "TNETV107X based system" 55 56 select CPU_V6 56 57 select CP_INTC 57 57 - bool "TNETV107X based system" 58 58 59 59 comment "DaVinci Board Type" 60 60 ··· 103 103 bool "TI DM6467 EVM" 104 104 default ARCH_DAVINCI_DM646x 105 105 depends on ARCH_DAVINCI_DM646x 106 106 - select MACH_DAVINCI_DM6467TEVM 107 106 select EEPROM_AT24 108 107 select I2C 108 108 + select MACH_DAVINCI_DM6467TEVM 109 109 help 110 110 Configure this option to specify the whether the board used 111 111 for development is a DM6467 EVM ··· 127 127 bool "TI DA830/OMAP-L137/AM17x Reference Platform" 128 128 default ARCH_DAVINCI_DA830 129 129 depends on ARCH_DAVINCI_DA830 130 130 - select GPIO_PCF857X 131 130 select EEPROM_AT24 131 131 + select GPIO_PCF857X 132 132 select I2C 133 133 help 134 134 Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.

+105 -106

arch/arm/mach-exynos/Kconfig

reviewed

··· 31 31 bool "SAMSUNG EXYNOS4210" 32 32 default y 33 33 depends on ARCH_EXYNOS4 34 34 - select SAMSUNG_DMADEV 35 34 select ARM_CPU_SUSPEND if PM 35 35 + select PM_GENERIC_DOMAINS 36 36 select S5P_PM if PM 37 37 select S5P_SLEEP if PM 38 38 - select PM_GENERIC_DOMAINS 38 38 + select SAMSUNG_DMADEV 39 39 help 40 40 Enable EXYNOS4210 CPU support 41 41 ··· 43 43 bool "SAMSUNG EXYNOS4212" 44 44 default y 45 45 depends on ARCH_EXYNOS4 46 46 - select SAMSUNG_DMADEV 47 46 select S5P_PM if PM 48 47 select S5P_SLEEP if PM 48 48 + select SAMSUNG_DMADEV 49 49 help 50 50 Enable EXYNOS4212 SoC support 51 51 ··· 61 61 bool "SAMSUNG EXYNOS5250" 62 62 default y 63 63 depends on ARCH_EXYNOS5 64 64 - select SAMSUNG_DMADEV 65 64 select S5P_PM if PM 66 65 select S5P_SLEEP if PM 66 66 + select SAMSUNG_DMADEV 67 67 help 68 68 Enable EXYNOS5250 SoC support 69 69 ··· 189 189 config MACH_SMDKV310 190 190 bool "SMDKV310" 191 191 select CPU_EXYNOS4210 192 192 - select S5P_DEV_FIMD0 193 193 - select S3C_DEV_RTC 194 194 - select S3C_DEV_WDT 195 195 - select S3C_DEV_I2C1 196 196 - select S5P_DEV_FIMC0 197 197 - select S5P_DEV_FIMC1 198 198 - select S5P_DEV_FIMC2 199 199 - select S5P_DEV_FIMC3 200 200 - select S5P_DEV_G2D 201 201 - select S5P_DEV_I2C_HDMIPHY 202 202 - select S5P_DEV_JPEG 203 203 - select S5P_DEV_MFC 204 204 - select S5P_DEV_TV 205 205 - select S5P_DEV_USB_EHCI 206 206 - select S3C_DEV_HSMMC 207 207 - select S3C_DEV_HSMMC1 208 208 - select S3C_DEV_HSMMC2 209 209 - select S3C_DEV_HSMMC3 210 210 - select S3C_DEV_USB_HSOTG 211 211 - select SAMSUNG_DEV_BACKLIGHT 212 212 - select EXYNOS_DEV_DRM 213 213 - select EXYNOS_DEV_SYSMMU 214 192 select EXYNOS4_DEV_AHCI 215 215 - select SAMSUNG_DEV_KEYPAD 216 216 - select EXYNOS_DEV_DMA 217 217 - select SAMSUNG_DEV_PWM 218 193 select EXYNOS4_DEV_USB_OHCI 219 194 select EXYNOS4_SETUP_FIMD0 220 195 select EXYNOS4_SETUP_I2C1 221 196 select EXYNOS4_SETUP_KEYPAD 222 197 select EXYNOS4_SETUP_SDHCI 223 198 select EXYNOS4_SETUP_USB_PHY 199 199 + select EXYNOS_DEV_DMA 200 200 + select EXYNOS_DEV_DRM 201 201 + select EXYNOS_DEV_SYSMMU 224 202 select S3C24XX_PWM 203 203 + select S3C_DEV_HSMMC 204 204 + select S3C_DEV_HSMMC1 205 205 + select S3C_DEV_HSMMC2 206 206 + select S3C_DEV_HSMMC3 207 207 + select S3C_DEV_I2C1 208 208 + select S3C_DEV_RTC 209 209 + select S3C_DEV_USB_HSOTG 210 210 + select S3C_DEV_WDT 211 211 + select S5P_DEV_FIMC0 212 212 + select S5P_DEV_FIMC1 213 213 + select S5P_DEV_FIMC2 214 214 + select S5P_DEV_FIMC3 215 215 + select S5P_DEV_FIMD0 216 216 + select S5P_DEV_G2D 217 217 + select S5P_DEV_I2C_HDMIPHY 218 218 + select S5P_DEV_JPEG 219 219 + select S5P_DEV_MFC 220 220 + select S5P_DEV_TV 221 221 + select S5P_DEV_USB_EHCI 222 222 + select SAMSUNG_DEV_BACKLIGHT 223 223 + select SAMSUNG_DEV_KEYPAD 224 224 + select SAMSUNG_DEV_PWM 225 225 help 226 226 Machine support for Samsung SMDKV310 227 227 228 228 config MACH_ARMLEX4210 229 229 bool "ARMLEX4210" 230 230 select CPU_EXYNOS4210 231 231 - select S3C_DEV_RTC 232 232 - select S3C_DEV_WDT 231 231 + select EXYNOS4_DEV_AHCI 232 232 + select EXYNOS4_SETUP_SDHCI 233 233 + select EXYNOS_DEV_DMA 233 234 select S3C_DEV_HSMMC 234 235 select S3C_DEV_HSMMC2 235 236 select S3C_DEV_HSMMC3 236 236 - select EXYNOS4_DEV_AHCI 237 237 - select EXYNOS_DEV_DMA 238 238 - select EXYNOS4_SETUP_SDHCI 237 237 + select S3C_DEV_RTC 238 238 + select S3C_DEV_WDT 239 239 help 240 240 Machine support for Samsung ARMLEX4210 based on EXYNOS4210 241 241 242 242 config MACH_UNIVERSAL_C210 243 243 bool "Mobile UNIVERSAL_C210 Board" 244 244 - select CPU_EXYNOS4210 245 245 - select S5P_HRT 246 244 select CLKSRC_MMIO 245 245 + select CPU_EXYNOS4210 246 246 + select EXYNOS4_SETUP_FIMC 247 247 + select EXYNOS4_SETUP_FIMD0 248 248 + select EXYNOS4_SETUP_I2C1 249 249 + select EXYNOS4_SETUP_I2C3 250 250 + select EXYNOS4_SETUP_I2C5 251 251 + select EXYNOS4_SETUP_SDHCI 252 252 + select EXYNOS4_SETUP_USB_PHY 253 253 + select EXYNOS_DEV_DMA 254 254 + select EXYNOS_DEV_DRM 255 255 + select EXYNOS_DEV_SYSMMU 247 256 select HAVE_SCHED_CLOCK 248 248 - select S5P_GPIO_INT 249 249 - select S5P_DEV_FIMC0 250 250 - select S5P_DEV_FIMC1 251 251 - select S5P_DEV_FIMC2 252 252 - select S5P_DEV_FIMC3 253 253 - select S5P_DEV_G2D 254 254 - select S5P_DEV_CSIS0 255 255 - select S5P_DEV_JPEG 256 256 - select S5P_DEV_FIMD0 257 257 select S3C_DEV_HSMMC 258 258 select S3C_DEV_HSMMC2 259 259 select S3C_DEV_HSMMC3 ··· 261 261 select S3C_DEV_I2C3 262 262 select S3C_DEV_I2C5 263 263 select S3C_DEV_USB_HSOTG 264 264 + select S5P_DEV_CSIS0 265 265 + select S5P_DEV_FIMC0 266 266 + select S5P_DEV_FIMC1 267 267 + select S5P_DEV_FIMC2 268 268 + select S5P_DEV_FIMC3 269 269 + select S5P_DEV_FIMD0 270 270 + select S5P_DEV_G2D 264 271 select S5P_DEV_I2C_HDMIPHY 272 272 + select S5P_DEV_JPEG 265 273 select S5P_DEV_MFC 266 274 select S5P_DEV_ONENAND 267 275 select S5P_DEV_TV 268 268 - select EXYNOS_DEV_SYSMMU 269 269 - select EXYNOS_DEV_DMA 270 270 - select EXYNOS_DEV_DRM 271 271 - select EXYNOS4_SETUP_FIMD0 272 272 - select EXYNOS4_SETUP_I2C1 273 273 - select EXYNOS4_SETUP_I2C3 274 274 - select EXYNOS4_SETUP_I2C5 275 275 - select EXYNOS4_SETUP_SDHCI 276 276 - select EXYNOS4_SETUP_FIMC 276 276 + select S5P_GPIO_INT 277 277 + select S5P_HRT 277 278 select S5P_SETUP_MIPIPHY 278 278 - select EXYNOS4_SETUP_USB_PHY 279 279 help 280 280 Machine support for Samsung Mobile Universal S5PC210 Reference 281 281 Board. ··· 283 283 config MACH_NURI 284 284 bool "Mobile NURI Board" 285 285 select CPU_EXYNOS4210 286 286 - select S5P_GPIO_INT 287 287 - select S3C_DEV_WDT 288 288 - select S3C_DEV_RTC 289 289 - select S5P_DEV_FIMD0 290 290 - select S3C_DEV_HSMMC 291 291 - select S3C_DEV_HSMMC2 292 292 - select S3C_DEV_HSMMC3 293 293 - select S3C_DEV_I2C1 294 294 - select S3C_DEV_I2C3 295 295 - select S3C_DEV_I2C5 296 296 - select S3C_DEV_I2C6 297 297 - select S3C_DEV_USB_HSOTG 298 298 - select S5P_DEV_CSIS0 299 299 - select S5P_DEV_JPEG 300 300 - select S5P_DEV_FIMC0 301 301 - select S5P_DEV_FIMC1 302 302 - select S5P_DEV_FIMC2 303 303 - select S5P_DEV_FIMC3 304 304 - select S5P_DEV_G2D 305 305 - select S5P_DEV_MFC 306 306 - select S5P_DEV_USB_EHCI 307 307 - select S5P_SETUP_MIPIPHY 308 308 - select EXYNOS_DEV_DMA 309 309 - select EXYNOS_DEV_DRM 310 286 select EXYNOS4_SETUP_FIMC 311 287 select EXYNOS4_SETUP_FIMD0 312 288 select EXYNOS4_SETUP_I2C1 ··· 291 315 select EXYNOS4_SETUP_I2C6 292 316 select EXYNOS4_SETUP_SDHCI 293 317 select EXYNOS4_SETUP_USB_PHY 318 318 + select EXYNOS_DEV_DMA 319 319 + select EXYNOS_DEV_DRM 320 320 + select S3C_DEV_HSMMC 321 321 + select S3C_DEV_HSMMC2 322 322 + select S3C_DEV_HSMMC3 323 323 + select S3C_DEV_I2C1 324 324 + select S3C_DEV_I2C3 325 325 + select S3C_DEV_I2C5 326 326 + select S3C_DEV_I2C6 327 327 + select S3C_DEV_RTC 328 328 + select S3C_DEV_USB_HSOTG 329 329 + select S3C_DEV_WDT 330 330 + select S5P_DEV_CSIS0 331 331 + select S5P_DEV_FIMC0 332 332 + select S5P_DEV_FIMC1 333 333 + select S5P_DEV_FIMC2 334 334 + select S5P_DEV_FIMC3 335 335 + select S5P_DEV_FIMD0 336 336 + select S5P_DEV_G2D 337 337 + select S5P_DEV_JPEG 338 338 + select S5P_DEV_MFC 339 339 + select S5P_DEV_USB_EHCI 340 340 + select S5P_GPIO_INT 294 341 select S5P_SETUP_MIPIPHY 295 295 - select SAMSUNG_DEV_PWM 296 342 select SAMSUNG_DEV_ADC 343 343 + select SAMSUNG_DEV_PWM 297 344 help 298 345 Machine support for Samsung Mobile NURI Board. 299 346 300 347 config MACH_ORIGEN 301 348 bool "ORIGEN" 302 349 select CPU_EXYNOS4210 303 303 - select S3C_DEV_RTC 304 304 - select S3C_DEV_WDT 350 350 + select EXYNOS4_DEV_USB_OHCI 351 351 + select EXYNOS4_SETUP_FIMD0 352 352 + select EXYNOS4_SETUP_SDHCI 353 353 + select EXYNOS4_SETUP_USB_PHY 354 354 + select EXYNOS_DEV_DMA 355 355 + select EXYNOS_DEV_DRM 356 356 + select EXYNOS_DEV_SYSMMU 357 357 + select S3C24XX_PWM 305 358 select S3C_DEV_HSMMC 306 359 select S3C_DEV_HSMMC2 360 360 + select S3C_DEV_RTC 307 361 select S3C_DEV_USB_HSOTG 362 362 + select S3C_DEV_WDT 308 363 select S5P_DEV_FIMC0 309 364 select S5P_DEV_FIMC1 310 365 select S5P_DEV_FIMC2 ··· 349 342 select S5P_DEV_USB_EHCI 350 343 select SAMSUNG_DEV_BACKLIGHT 351 344 select SAMSUNG_DEV_PWM 352 352 - select EXYNOS_DEV_DRM 353 353 - select EXYNOS_DEV_SYSMMU 354 354 - select EXYNOS_DEV_DMA 355 355 - select EXYNOS4_DEV_USB_OHCI 356 356 - select EXYNOS4_SETUP_FIMD0 357 357 - select EXYNOS4_SETUP_SDHCI 358 358 - select EXYNOS4_SETUP_USB_PHY 359 359 - select S3C24XX_PWM 360 345 help 361 346 Machine support for ORIGEN based on Samsung EXYNOS4210 362 347 ··· 356 357 357 358 config MACH_SMDK4212 358 359 bool "SMDK4212" 359 359 - select SOC_EXYNOS4212 360 360 + select EXYNOS4_SETUP_FIMD0 361 361 + select EXYNOS4_SETUP_I2C1 362 362 + select EXYNOS4_SETUP_I2C3 363 363 + select EXYNOS4_SETUP_I2C7 364 364 + select EXYNOS4_SETUP_KEYPAD 365 365 + select EXYNOS4_SETUP_SDHCI 366 366 + select EXYNOS4_SETUP_USB_PHY 367 367 + select EXYNOS_DEV_DMA 368 368 + select EXYNOS_DEV_DRM 369 369 + select EXYNOS_DEV_SYSMMU 370 370 + select S3C24XX_PWM 360 371 select S3C_DEV_HSMMC2 361 372 select S3C_DEV_HSMMC3 362 373 select S3C_DEV_I2C1 ··· 384 375 select SAMSUNG_DEV_BACKLIGHT 385 376 select SAMSUNG_DEV_KEYPAD 386 377 select SAMSUNG_DEV_PWM 387 387 - select EXYNOS_DEV_SYSMMU 388 388 - select EXYNOS_DEV_DMA 389 389 - select EXYNOS_DEV_DRM 390 390 - select EXYNOS4_SETUP_FIMD0 391 391 - select EXYNOS4_SETUP_I2C1 392 392 - select EXYNOS4_SETUP_I2C3 393 393 - select EXYNOS4_SETUP_I2C7 394 394 - select EXYNOS4_SETUP_KEYPAD 395 395 - select EXYNOS4_SETUP_SDHCI 396 396 - select EXYNOS4_SETUP_USB_PHY 397 397 - select S3C24XX_PWM 378 378 + select SOC_EXYNOS4212 398 379 help 399 380 Machine support for Samsung SMDK4212 400 381 ··· 392 393 393 394 config MACH_SMDK4412 394 395 bool "SMDK4412" 395 395 - select SOC_EXYNOS4412 396 396 select MACH_SMDK4212 397 397 + select SOC_EXYNOS4412 397 398 help 398 399 Machine support for Samsung SMDK4412 399 400 endif ··· 403 404 config MACH_EXYNOS4_DT 404 405 bool "Samsung Exynos4 Machine using device tree" 405 406 depends on ARCH_EXYNOS4 406 406 - select CPU_EXYNOS4210 407 407 - select USE_OF 408 407 select ARM_AMBA 408 408 + select CPU_EXYNOS4210 409 409 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD 410 410 select PINCTRL 411 411 select PINCTRL_EXYNOS4 412 412 + select USE_OF 412 413 help 413 414 Machine support for Samsung Exynos4 machine with device tree enabled. 414 415 Select this if a fdt blob is available for the Exynos4 SoC based board. ··· 418 419 config MACH_EXYNOS5_DT 419 420 bool "SAMSUNG EXYNOS5 Machine using device tree" 420 421 depends on ARCH_EXYNOS5 422 422 + select ARM_AMBA 421 423 select SOC_EXYNOS5250 422 424 select USE_OF 423 423 - select ARM_AMBA 424 425 help 425 426 Machine support for Samsung EXYNOS5 machine with device tree enabled. 426 427 Select this if a fdt blob is available for the EXYNOS5 SoC based board.

+1 -1

arch/arm/mach-footbridge/Kconfig

reviewed

··· 91 91 92 92 # EBSA285 board in either host or addin mode 93 93 config ARCH_EBSA285 94 94 - select ARCH_MAY_HAVE_PC_FDC 95 94 bool 95 95 + select ARCH_MAY_HAVE_PC_FDC 96 96 97 97 endif

+1 -1

arch/arm/mach-h720x/Kconfig

reviewed

··· 12 12 13 13 config ARCH_H7202 14 14 bool "hms30c7202" 15 15 + depends on ARCH_H720X 15 16 select CPU_H7202 16 17 select ZONE_DMA 17 17 - depends on ARCH_H720X 18 18 help 19 19 Say Y here if you are using the Hynix HMS30C7202 Reference Board 20 20

+60 -60

arch/arm/mach-imx/Kconfig

reviewed

··· 41 41 42 42 config SOC_IMX21 43 43 bool 44 44 - select MACH_MX21 45 45 - select CPU_ARM926T 46 44 select COMMON_CLK 45 45 + select CPU_ARM926T 47 46 select IMX_HAVE_IOMUX_V1 47 47 + select MACH_MX21 48 48 select MXC_AVIC 49 49 50 50 config SOC_IMX25 51 51 bool 52 52 select ARCH_MX25 53 53 + select ARCH_MXC_IOMUX_V3 53 54 select COMMON_CLK 54 55 select CPU_ARM926T 55 56 select HAVE_CAN_FLEXCAN if CAN 56 56 - select ARCH_MXC_IOMUX_V3 57 57 select MXC_AVIC 58 58 59 59 config SOC_IMX27 60 60 bool 61 61 - select MACH_MX27 62 62 - select CPU_ARM926T 63 61 select COMMON_CLK 62 62 + select CPU_ARM926T 64 63 select IMX_HAVE_IOMUX_V1 64 64 + select MACH_MX27 65 65 select MXC_AVIC 66 66 67 67 config SOC_IMX31 68 68 bool 69 69 + select COMMON_CLK 69 70 select CPU_V6 70 71 select IMX_HAVE_PLATFORM_MXC_RNGA 71 72 select MXC_AVIC 72 72 - select COMMON_CLK 73 73 select SMP_ON_UP if SMP 74 74 75 75 config SOC_IMX35 76 76 bool 77 77 - select CPU_V6K 78 77 select ARCH_MXC_IOMUX_V3 79 78 select COMMON_CLK 79 79 + select CPU_V6K 80 80 + select HAVE_CAN_FLEXCAN if CAN 80 81 select HAVE_EPIT 81 82 select MXC_AVIC 82 83 select SMP_ON_UP if SMP 83 83 - select HAVE_CAN_FLEXCAN if CAN 84 84 85 85 config SOC_IMX5 86 86 - select CPU_V7 87 87 - select MXC_TZIC 88 88 - select COMMON_CLK 89 89 - select ARCH_MXC_IOMUX_V3 86 86 + bool 90 87 select ARCH_HAS_CPUFREQ 91 88 select ARCH_MX5 92 92 - bool 89 89 + select ARCH_MXC_IOMUX_V3 90 90 + select COMMON_CLK 91 91 + select CPU_V7 92 92 + select MXC_TZIC 93 93 94 94 config SOC_IMX50 95 95 bool 96 96 - select SOC_IMX5 97 96 select ARCH_MX50 97 97 + select SOC_IMX5 98 98 99 99 config SOC_IMX51 100 100 bool 101 101 - select SOC_IMX5 102 101 select ARCH_MX5 103 102 select ARCH_MX51 104 103 select PINCTRL 105 104 select PINCTRL_IMX51 105 105 + select SOC_IMX5 106 106 107 107 if ARCH_IMX_V4_V5 108 108 ··· 112 112 113 113 config ARCH_MX1ADS 114 114 bool "MX1ADS platform" 115 115 - select MACH_MXLADS 116 116 - select SOC_IMX1 117 115 select IMX_HAVE_PLATFORM_IMX_I2C 118 116 select IMX_HAVE_PLATFORM_IMX_UART 117 117 + select MACH_MXLADS 118 118 + select SOC_IMX1 119 119 help 120 120 Say Y here if you are using Motorola MX1ADS/MXLADS boards 121 121 ··· 127 127 128 128 config MACH_APF9328 129 129 bool "APF9328" 130 130 - select SOC_IMX1 131 130 select IMX_HAVE_PLATFORM_IMX_I2C 132 131 select IMX_HAVE_PLATFORM_IMX_UART 132 132 + select SOC_IMX1 133 133 help 134 134 Say Yes here if you are using the Armadeus APF9328 development board 135 135 ··· 137 137 138 138 config MACH_MX21ADS 139 139 bool "MX21ADS platform" 140 140 - select SOC_IMX21 141 140 select IMX_HAVE_PLATFORM_IMX_FB 142 141 select IMX_HAVE_PLATFORM_IMX_UART 143 142 select IMX_HAVE_PLATFORM_MXC_MMC 144 143 select IMX_HAVE_PLATFORM_MXC_NAND 144 144 + select SOC_IMX21 145 145 help 146 146 Include support for MX21ADS platform. This includes specific 147 147 configurations for the board and its peripherals. ··· 150 150 151 151 config MACH_MX25_3DS 152 152 bool "Support MX25PDK (3DS) Platform" 153 153 - select SOC_IMX25 154 153 select IMX_HAVE_PLATFORM_FLEXCAN 155 154 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 156 155 select IMX_HAVE_PLATFORM_IMX2_WDT 157 156 select IMX_HAVE_PLATFORM_IMXDI_RTC 158 158 - select IMX_HAVE_PLATFORM_IMX_I2C 159 157 select IMX_HAVE_PLATFORM_IMX_FB 158 158 + select IMX_HAVE_PLATFORM_IMX_I2C 160 159 select IMX_HAVE_PLATFORM_IMX_KEYPAD 161 160 select IMX_HAVE_PLATFORM_IMX_UART 162 161 select IMX_HAVE_PLATFORM_MXC_EHCI 163 162 select IMX_HAVE_PLATFORM_MXC_NAND 164 163 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 164 164 + select SOC_IMX25 165 165 166 166 config MACH_EUKREA_CPUIMX25SD 167 167 bool "Support Eukrea CPUIMX25 Platform" 168 168 - select SOC_IMX25 169 168 select IMX_HAVE_PLATFORM_FLEXCAN 170 169 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 171 170 select IMX_HAVE_PLATFORM_IMX2_WDT ··· 176 177 select IMX_HAVE_PLATFORM_MXC_NAND 177 178 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 178 179 select MXC_ULPI if USB_ULPI 180 180 + select SOC_IMX25 179 181 180 182 choice 181 183 prompt "Baseboard" ··· 199 199 200 200 config MACH_MX27ADS 201 201 bool "MX27ADS platform" 202 202 - select SOC_IMX27 203 202 select IMX_HAVE_PLATFORM_IMX_FB 204 203 select IMX_HAVE_PLATFORM_IMX_I2C 205 204 select IMX_HAVE_PLATFORM_IMX_UART 206 205 select IMX_HAVE_PLATFORM_MXC_MMC 207 206 select IMX_HAVE_PLATFORM_MXC_NAND 208 207 select IMX_HAVE_PLATFORM_MXC_W1 208 208 + select SOC_IMX27 209 209 help 210 210 Include support for MX27ADS platform. This includes specific 211 211 configurations for the board and its peripherals. 212 212 213 213 config MACH_PCM038 214 214 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" 215 215 - select SOC_IMX27 216 215 select IMX_HAVE_PLATFORM_IMX2_WDT 217 216 select IMX_HAVE_PLATFORM_IMX_I2C 218 217 select IMX_HAVE_PLATFORM_IMX_UART ··· 220 221 select IMX_HAVE_PLATFORM_MXC_W1 221 222 select IMX_HAVE_PLATFORM_SPI_IMX 222 223 select MXC_ULPI if USB_ULPI 224 224 + select SOC_IMX27 223 225 help 224 226 Include support for phyCORE-i.MX27 (aka pcm038) platform. This 225 227 includes specific configurations for the module and its peripherals. ··· 242 242 243 243 config MACH_CPUIMX27 244 244 bool "Eukrea CPUIMX27 module" 245 245 - select SOC_IMX27 246 245 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 247 246 select IMX_HAVE_PLATFORM_IMX2_WDT 248 247 select IMX_HAVE_PLATFORM_IMX_I2C ··· 250 251 select IMX_HAVE_PLATFORM_MXC_NAND 251 252 select IMX_HAVE_PLATFORM_MXC_W1 252 253 select MXC_ULPI if USB_ULPI 254 254 + select SOC_IMX27 253 255 help 254 256 Include support for Eukrea CPUIMX27 platform. This includes 255 257 specific configurations for the module and its peripherals. ··· 292 292 293 293 config MACH_MX27_3DS 294 294 bool "MX27PDK platform" 295 295 - select SOC_IMX27 296 295 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 297 296 select IMX_HAVE_PLATFORM_IMX2_WDT 298 297 select IMX_HAVE_PLATFORM_IMX_FB ··· 305 306 select IMX_HAVE_PLATFORM_SPI_IMX 306 307 select MXC_DEBUG_BOARD 307 308 select MXC_ULPI if USB_ULPI 309 309 + select SOC_IMX27 308 310 help 309 311 Include support for MX27PDK platform. This includes specific 310 312 configurations for the board and its peripherals. 311 313 312 314 config MACH_IMX27_VISSTRIM_M10 313 315 bool "Vista Silicon i.MX27 Visstrim_m10" 314 314 - select SOC_IMX27 315 316 select IMX_HAVE_PLATFORM_GPIO_KEYS 316 317 select IMX_HAVE_PLATFORM_IMX_I2C 317 318 select IMX_HAVE_PLATFORM_IMX_SSI ··· 320 321 select IMX_HAVE_PLATFORM_MXC_EHCI 321 322 select IMX_HAVE_PLATFORM_MXC_MMC 322 323 select LEDS_GPIO_REGISTER 324 324 + select SOC_IMX27 323 325 help 324 326 Include support for Visstrim_m10 platform and its different variants. 325 327 This includes specific configurations for the board and its ··· 328 328 329 329 config MACH_IMX27LITE 330 330 bool "LogicPD MX27 LITEKIT platform" 331 331 - select SOC_IMX27 332 332 - select IMX_HAVE_PLATFORM_IMX_UART 333 331 select IMX_HAVE_PLATFORM_IMX_SSI 332 332 + select IMX_HAVE_PLATFORM_IMX_UART 333 333 + select SOC_IMX27 334 334 help 335 335 Include support for MX27 LITEKIT platform. This includes specific 336 336 configurations for the board and its peripherals. 337 337 338 338 config MACH_PCA100 339 339 bool "Phytec phyCARD-s (pca100)" 340 340 - select SOC_IMX27 341 340 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 342 341 select IMX_HAVE_PLATFORM_IMX2_WDT 343 342 select IMX_HAVE_PLATFORM_IMX_FB ··· 349 350 select IMX_HAVE_PLATFORM_MXC_W1 350 351 select IMX_HAVE_PLATFORM_SPI_IMX 351 352 select MXC_ULPI if USB_ULPI 353 353 + select SOC_IMX27 352 354 help 353 355 Include support for phyCARD-s (aka pca100) platform. This 354 356 includes specific configurations for the module and its peripherals. 355 357 356 358 config MACH_MXT_TD60 357 359 bool "Maxtrack i-MXT TD60" 358 358 - select SOC_IMX27 359 360 select IMX_HAVE_PLATFORM_IMX_FB 360 361 select IMX_HAVE_PLATFORM_IMX_I2C 361 362 select IMX_HAVE_PLATFORM_IMX_UART 362 363 select IMX_HAVE_PLATFORM_MXC_MMC 363 364 select IMX_HAVE_PLATFORM_MXC_NAND 365 365 + select SOC_IMX27 364 366 help 365 367 Include support for i-MXT (aka td60) platform. This 366 368 includes specific configurations for the module and its peripherals. 367 369 368 370 config MACH_IMX27IPCAM 369 371 bool "IMX27 IPCAM platform" 370 370 - select SOC_IMX27 371 372 select IMX_HAVE_PLATFORM_IMX2_WDT 372 373 select IMX_HAVE_PLATFORM_IMX_UART 374 374 + select SOC_IMX27 373 375 help 374 376 Include support for IMX27 IPCAM platform. This includes specific 375 377 configurations for the board and its peripherals. ··· 390 390 391 391 config MACH_MX31ADS 392 392 bool "Support MX31ADS platforms" 393 393 - select SOC_IMX31 393 393 + default y 394 394 select IMX_HAVE_PLATFORM_IMX_I2C 395 395 select IMX_HAVE_PLATFORM_IMX_SSI 396 396 select IMX_HAVE_PLATFORM_IMX_UART 397 397 - default y 397 397 + select SOC_IMX31 398 398 help 399 399 Include support for MX31ADS platform. This includes specific 400 400 configurations for the board and its peripherals. ··· 412 412 413 413 config MACH_MX31LILLY 414 414 bool "Support MX31 LILLY-1131 platforms (INCO startec)" 415 415 - select SOC_IMX31 416 415 select IMX_HAVE_PLATFORM_IMX_UART 417 416 select IMX_HAVE_PLATFORM_IPU_CORE 418 417 select IMX_HAVE_PLATFORM_MXC_EHCI 419 418 select IMX_HAVE_PLATFORM_MXC_MMC 420 419 select IMX_HAVE_PLATFORM_SPI_IMX 421 420 select MXC_ULPI if USB_ULPI 421 421 + select SOC_IMX31 422 422 help 423 423 Include support for mx31 based LILLY1131 modules. This includes 424 424 specific configurations for the board and its peripherals. 425 425 426 426 config MACH_MX31LITE 427 427 bool "Support MX31 LITEKIT (LogicPD)" 428 428 - select SOC_IMX31 429 429 - select MXC_ULPI if USB_ULPI 430 428 select IMX_HAVE_PLATFORM_IMX2_WDT 431 429 select IMX_HAVE_PLATFORM_IMX_UART 432 430 select IMX_HAVE_PLATFORM_MXC_EHCI ··· 433 435 select IMX_HAVE_PLATFORM_MXC_RTC 434 436 select IMX_HAVE_PLATFORM_SPI_IMX 435 437 select LEDS_GPIO_REGISTER 438 438 + select MXC_ULPI if USB_ULPI 439 439 + select SOC_IMX31 436 440 help 437 441 Include support for MX31 LITEKIT platform. This includes specific 438 442 configurations for the board and its peripherals. 439 443 440 444 config MACH_PCM037 441 445 bool "Support Phytec pcm037 (i.MX31) platforms" 442 442 - select SOC_IMX31 443 446 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 444 447 select IMX_HAVE_PLATFORM_IMX2_WDT 445 448 select IMX_HAVE_PLATFORM_IMX_I2C ··· 451 452 select IMX_HAVE_PLATFORM_MXC_NAND 452 453 select IMX_HAVE_PLATFORM_MXC_W1 453 454 select MXC_ULPI if USB_ULPI 455 455 + select SOC_IMX31 454 456 help 455 457 Include support for Phytec pcm037 platform. This includes 456 458 specific configurations for the board and its peripherals. ··· 468 468 469 469 config MACH_MX31_3DS 470 470 bool "Support MX31PDK (3DS)" 471 471 - select SOC_IMX31 472 472 - select MXC_DEBUG_BOARD 473 471 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 474 472 select IMX_HAVE_PLATFORM_IMX2_WDT 475 473 select IMX_HAVE_PLATFORM_IMX_I2C ··· 479 481 select IMX_HAVE_PLATFORM_MXC_MMC 480 482 select IMX_HAVE_PLATFORM_MXC_NAND 481 483 select IMX_HAVE_PLATFORM_SPI_IMX 484 484 + select MXC_DEBUG_BOARD 482 485 select MXC_ULPI if USB_ULPI 486 486 + select SOC_IMX31 483 487 help 484 488 Include support for MX31PDK (3DS) platform. This includes specific 485 489 configurations for the board and its peripherals. ··· 497 497 498 498 config MACH_MX31MOBOARD 499 499 bool "Support mx31moboard platforms (EPFL Mobots group)" 500 500 - select SOC_IMX31 501 500 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 502 501 select IMX_HAVE_PLATFORM_IMX2_WDT 503 502 select IMX_HAVE_PLATFORM_IMX_I2C ··· 508 509 select IMX_HAVE_PLATFORM_SPI_IMX 509 510 select LEDS_GPIO_REGISTER 510 511 select MXC_ULPI if USB_ULPI 512 512 + select SOC_IMX31 511 513 help 512 514 Include support for mx31moboard platform. This includes specific 513 515 configurations for the board and its peripherals. 514 516 515 517 config MACH_QONG 516 518 bool "Support Dave/DENX QongEVB-LITE platform" 517 517 - select SOC_IMX31 518 518 - select IMX_HAVE_PLATFORM_IMX_UART 519 519 select IMX_HAVE_PLATFORM_IMX2_WDT 520 520 + select IMX_HAVE_PLATFORM_IMX_UART 521 521 + select SOC_IMX31 520 522 help 521 523 Include support for Dave/DENX QongEVB-LITE platform. This includes 522 524 specific configurations for the board and its peripherals. 523 525 524 526 config MACH_ARMADILLO5X0 525 527 bool "Support Atmark Armadillo-500 Development Base Board" 526 526 - select SOC_IMX31 527 528 select IMX_HAVE_PLATFORM_GPIO_KEYS 528 529 select IMX_HAVE_PLATFORM_IMX_I2C 529 530 select IMX_HAVE_PLATFORM_IMX_UART ··· 532 533 select IMX_HAVE_PLATFORM_MXC_MMC 533 534 select IMX_HAVE_PLATFORM_MXC_NAND 534 535 select MXC_ULPI if USB_ULPI 536 536 + select SOC_IMX31 535 537 help 536 538 Include support for Atmark Armadillo-500 platform. This includes 537 539 specific configurations for the board and its peripherals. 538 540 539 541 config MACH_KZM_ARM11_01 540 542 bool "Support KZM-ARM11-01(Kyoto Microcomputer)" 541 541 - select SOC_IMX31 542 543 select IMX_HAVE_PLATFORM_IMX_UART 544 544 + select SOC_IMX31 543 545 help 544 546 Include support for KZM-ARM11-01. This includes specific 545 547 configurations for the board and its peripherals. 546 548 547 549 config MACH_BUG 548 550 bool "Support Buglabs BUGBase platform" 549 549 - select SOC_IMX31 550 550 - select IMX_HAVE_PLATFORM_IMX_UART 551 551 default y 552 552 + select IMX_HAVE_PLATFORM_IMX_UART 553 553 + select SOC_IMX31 552 554 help 553 555 Include support for BUGBase 1.3 platform. This includes specific 554 556 configurations for the board and its peripherals. ··· 565 565 566 566 config MACH_PCM043 567 567 bool "Support Phytec pcm043 (i.MX35) platforms" 568 568 - select SOC_IMX35 569 568 select IMX_HAVE_PLATFORM_FLEXCAN 570 569 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 571 570 select IMX_HAVE_PLATFORM_IMX2_WDT ··· 576 577 select IMX_HAVE_PLATFORM_MXC_NAND 577 578 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 578 579 select MXC_ULPI if USB_ULPI 580 580 + select SOC_IMX35 579 581 help 580 582 Include support for Phytec pcm043 platform. This includes 581 583 specific configurations for the board and its peripherals. 582 584 583 585 config MACH_MX35_3DS 584 586 bool "Support MX35PDK platform" 585 585 - select SOC_IMX35 586 586 - select MXC_DEBUG_BOARD 587 587 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 588 588 select IMX_HAVE_PLATFORM_IMX2_WDT 589 589 select IMX_HAVE_PLATFORM_IMX_FB ··· 593 595 select IMX_HAVE_PLATFORM_MXC_NAND 594 596 select IMX_HAVE_PLATFORM_MXC_RTC 595 597 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 598 598 + select MXC_DEBUG_BOARD 599 599 + select SOC_IMX35 596 600 help 597 601 Include support for MX35PDK platform. This includes specific 598 602 configurations for the board and its peripherals. 599 603 600 604 config MACH_EUKREA_CPUIMX35SD 601 605 bool "Support Eukrea CPUIMX35 Platform" 602 602 - select SOC_IMX35 603 606 select IMX_HAVE_PLATFORM_FLEXCAN 604 607 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 605 608 select IMX_HAVE_PLATFORM_IMX2_WDT ··· 610 611 select IMX_HAVE_PLATFORM_MXC_NAND 611 612 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 612 613 select MXC_ULPI if USB_ULPI 614 614 + select SOC_IMX35 613 615 help 614 616 Include support for Eukrea CPUIMX35 platform. This includes 615 617 specific configurations for the board and its peripherals. ··· 635 635 636 636 config MACH_VPR200 637 637 bool "Support VPR200 platform" 638 638 - select SOC_IMX35 639 638 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 640 639 select IMX_HAVE_PLATFORM_GPIO_KEYS 641 640 select IMX_HAVE_PLATFORM_IMX2_WDT 642 642 - select IMX_HAVE_PLATFORM_IMX_UART 643 641 select IMX_HAVE_PLATFORM_IMX_I2C 642 642 + select IMX_HAVE_PLATFORM_IMX_UART 644 643 select IMX_HAVE_PLATFORM_IPU_CORE 645 644 select IMX_HAVE_PLATFORM_MXC_EHCI 646 645 select IMX_HAVE_PLATFORM_MXC_NAND 647 646 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 647 647 + select SOC_IMX35 648 648 help 649 649 Include support for VPR200 platform. This includes specific 650 650 configurations for the board and its peripherals. ··· 654 654 config MACH_MX50_RDP 655 655 bool "Support MX50 reference design platform" 656 656 depends on BROKEN 657 657 - select SOC_IMX50 658 657 select IMX_HAVE_PLATFORM_IMX_I2C 659 658 select IMX_HAVE_PLATFORM_IMX_UART 660 659 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 661 660 select IMX_HAVE_PLATFORM_SPI_IMX 661 661 + select SOC_IMX50 662 662 help 663 663 Include support for MX50 reference design platform (RDP) board. This 664 664 includes specific configurations for the board and its peripherals. ··· 667 667 668 668 config MACH_IMX51_DT 669 669 bool "Support i.MX51 platforms from device tree" 670 670 - select SOC_IMX51 671 670 select MACH_MX51_BABBAGE 671 671 + select SOC_IMX51 672 672 help 673 673 Include support for Freescale i.MX51 based platforms 674 674 using the device tree for discovery 675 675 676 676 config MACH_MX51_BABBAGE 677 677 bool "Support MX51 BABBAGE platforms" 678 678 - select SOC_IMX51 679 678 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 680 679 select IMX_HAVE_PLATFORM_IMX2_WDT 681 680 select IMX_HAVE_PLATFORM_IMX_I2C ··· 682 683 select IMX_HAVE_PLATFORM_MXC_EHCI 683 684 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 684 685 select IMX_HAVE_PLATFORM_SPI_IMX 686 686 + select SOC_IMX51 685 687 help 686 688 Include support for MX51 Babbage platform, also known as MX51EVK in 687 689 u-boot. This includes specific configurations for the board and its ··· 690 690 691 691 config MACH_MX51_3DS 692 692 bool "Support MX51PDK (3DS)" 693 693 - select SOC_IMX51 694 693 select IMX_HAVE_PLATFORM_IMX2_WDT 695 694 select IMX_HAVE_PLATFORM_IMX_KEYPAD 696 695 select IMX_HAVE_PLATFORM_IMX_UART 697 696 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 698 697 select IMX_HAVE_PLATFORM_SPI_IMX 699 698 select MXC_DEBUG_BOARD 699 699 + select SOC_IMX51 700 700 help 701 701 Include support for MX51PDK (3DS) platform. This includes specific 702 702 configurations for the board and its peripherals. 703 703 704 704 config MACH_EUKREA_CPUIMX51SD 705 705 bool "Support Eukrea CPUIMX51SD module" 706 706 - select SOC_IMX51 707 706 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 707 707 + select IMX_HAVE_PLATFORM_IMX2_WDT 708 708 select IMX_HAVE_PLATFORM_IMX_I2C 709 709 select IMX_HAVE_PLATFORM_IMX_UART 710 710 - select IMX_HAVE_PLATFORM_IMX2_WDT 711 710 select IMX_HAVE_PLATFORM_MXC_EHCI 712 711 select IMX_HAVE_PLATFORM_MXC_NAND 713 712 select IMX_HAVE_PLATFORM_SPI_IMX 713 713 + select SOC_IMX51 714 714 help 715 715 Include support for Eukrea CPUIMX51SD platform. This includes 716 716 specific configurations for the module and its peripherals. ··· 736 736 737 737 config SOC_IMX53 738 738 bool "i.MX53 support" 739 739 - select SOC_IMX5 740 739 select ARCH_MX5 741 740 select ARCH_MX53 742 741 select HAVE_CAN_FLEXCAN if CAN 743 742 select PINCTRL 744 743 select PINCTRL_IMX53 744 744 + select SOC_IMX5 745 745 746 746 help 747 747 This enables support for Freescale i.MX53 processor.

+1 -1

arch/arm/mach-ixp4xx/Kconfig

reviewed

··· 234 234 235 235 config IXP4XX_NPE 236 236 tristate "IXP4xx Network Processor Engine support" 237 237 - select HOTPLUG 238 237 select FW_LOADER 238 238 + select HOTPLUG 239 239 help 240 240 This driver supports IXP4xx built-in network coprocessors 241 241 and is automatically selected by Ethernet and HSS drivers.

+3 -3

arch/arm/mach-mmp/Kconfig

reviewed

··· 107 107 108 108 config CPU_PXA168 109 109 bool 110 110 - select CPU_MOHAWK 111 110 select COMMON_CLK 111 111 + select CPU_MOHAWK 112 112 help 113 113 Select code specific to PXA168 114 114 115 115 config CPU_PXA910 116 116 bool 117 117 - select CPU_MOHAWK 118 117 select COMMON_CLK 118 118 + select CPU_MOHAWK 119 119 help 120 120 Select code specific to PXA910 121 121 122 122 config CPU_MMP2 123 123 bool 124 124 - select CPU_PJ4 125 124 select COMMON_CLK 125 125 + select CPU_PJ4 126 126 help 127 127 Select code specific to MMP2. MMP2 is ARMv7 compatible. 128 128

+16 -16

arch/arm/mach-msm/Kconfig

reviewed

··· 10 10 11 11 config ARCH_MSM7X00A 12 12 bool "MSM7x00A / MSM7x01A" 13 13 - select MACH_TROUT if !MACH_HALIBUT 14 13 select ARCH_MSM_ARM11 15 15 - select MSM_SMD 16 16 - select MSM_SMD_PKG3 17 14 select CPU_V6 18 15 select GPIO_MSM_V1 16 16 + select MACH_TROUT if !MACH_HALIBUT 19 17 select MSM_PROC_COMM 18 18 + select MSM_SMD 19 19 + select MSM_SMD_PKG3 20 20 21 21 config ARCH_MSM7X30 22 22 bool "MSM7x30" 23 23 - select MACH_MSM7X30_SURF # if ! 24 23 select ARCH_MSM_SCORPION 24 24 + select CPU_V7 25 25 + select GPIO_MSM_V1 26 26 + select MACH_MSM7X30_SURF # if ! 27 27 + select MSM_GPIOMUX 28 28 + select MSM_PROC_COMM 25 29 select MSM_SMD 26 30 select MSM_VIC 27 27 - select CPU_V7 28 28 - select MSM_GPIOMUX 29 29 - select GPIO_MSM_V1 30 30 - select MSM_PROC_COMM 31 31 32 32 config ARCH_QSD8X50 33 33 bool "QSD8X50" 34 34 - select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5 35 34 select ARCH_MSM_SCORPION 35 35 + select CPU_V7 36 36 + select GPIO_MSM_V1 37 37 + select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5 38 38 + select MSM_GPIOMUX 39 39 + select MSM_PROC_COMM 36 40 select MSM_SMD 37 41 select MSM_VIC 38 38 - select CPU_V7 39 39 - select MSM_GPIOMUX 40 40 - select GPIO_MSM_V1 41 41 - select MSM_PROC_COMM 42 42 43 43 endchoice 44 44 ··· 47 47 select ARCH_MSM_SCORPIONMP 48 48 select ARM_GIC 49 49 select CPU_V7 50 50 - select MSM_V2_TLMM 51 50 select GPIO_MSM_V2 52 51 select MSM_GPIOMUX 53 52 select MSM_SCM if SMP 53 53 + select MSM_V2_TLMM 54 54 select USE_OF 55 55 56 56 config ARCH_MSM8960 ··· 58 58 select ARCH_MSM_SCORPIONMP 59 59 select ARM_GIC 60 60 select CPU_V7 61 61 - select MSM_V2_TLMM 62 61 select MSM_GPIOMUX 63 62 select MSM_SCM if SMP 63 63 + select MSM_V2_TLMM 64 64 select USE_OF 65 65 66 66 config MSM_HAS_DEBUG_UART_HS ··· 110 110 111 111 config MACH_QSD8X50A_ST1_5 112 112 depends on ARCH_QSD8X50 113 113 - select MSM_SOC_REV_A 114 113 bool "QSD8x50A ST1.5" 114 114 + select MSM_SOC_REV_A 115 115 help 116 116 Support for the Qualcomm ST1.5. 117 117

+2 -2

arch/arm/mach-nomadik/Kconfig

reviewed

··· 4 4 5 5 config MACH_NOMADIK_8815NHK 6 6 bool "ST 8815 Nomadik Hardware Kit (evaluation board)" 7 7 - select NOMADIK_8815 8 7 select HAS_MTU 8 8 + select NOMADIK_8815 9 9 10 10 endmenu 11 11 ··· 16 16 tristate "Driver for bit-bang busses found on the 8815 NHK" 17 17 depends on I2C && MACH_NOMADIK_8815NHK 18 18 depends on PINCTRL_NOMADIK 19 19 - select I2C_ALGOBIT 20 19 default y 20 20 + select I2C_ALGOBIT 21 21 22 22 endif

+4 -4

arch/arm/mach-omap1/Kconfig

reviewed

··· 8 8 config ARCH_OMAP730 9 9 depends on ARCH_OMAP1 10 10 bool "OMAP730 Based System" 11 11 + select ARCH_OMAP_OTG 11 12 select CPU_ARM926T 12 13 select OMAP_MPU_TIMER 13 13 - select ARCH_OMAP_OTG 14 14 15 15 config ARCH_OMAP850 16 16 depends on ARCH_OMAP1 17 17 bool "OMAP850 Based System" 18 18 - select CPU_ARM926T 19 18 select ARCH_OMAP_OTG 19 19 + select CPU_ARM926T 20 20 21 21 config ARCH_OMAP15XX 22 22 depends on ARCH_OMAP1 ··· 28 28 config ARCH_OMAP16XX 29 29 depends on ARCH_OMAP1 30 30 bool "OMAP16xx Based System" 31 31 - select CPU_ARM926T 32 31 select ARCH_OMAP_OTG 32 32 + select CPU_ARM926T 33 33 34 34 comment "OMAP Board Type" 35 35 depends on ARCH_OMAP1 ··· 132 132 133 133 config MACH_SX1 134 134 bool "Siemens SX1" 135 135 - select I2C 136 135 depends on ARCH_OMAP1 && ARCH_OMAP15XX 136 136 + select I2C 137 137 help 138 138 Support for the Siemens SX1 phone. To boot the kernel, 139 139 you'll need a SX1 compatible bootloader; check out

+38 -38

arch/arm/mach-omap2/Kconfig

reviewed

··· 6 6 bool "Typical OMAP configuration" 7 7 default y 8 8 select AEABI 9 9 - select REGULATOR 10 10 - select PM_RUNTIME 11 11 - select VFP 12 12 - select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5 13 13 - select SERIAL_OMAP 14 14 - select SERIAL_OMAP_CONSOLE 9 9 + select HIGHMEM 15 10 select I2C 16 11 select I2C_OMAP 17 12 select MENELAUS if ARCH_OMAP2 13 13 + select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5 14 14 + select PINCTRL 15 15 + select PM_RUNTIME 16 16 + select REGULATOR 17 17 + select SERIAL_OMAP 18 18 + select SERIAL_OMAP_CONSOLE 18 19 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 19 20 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 20 20 - select HIGHMEM 21 21 - select PINCTRL 21 21 + select VFP 22 22 help 23 23 Compile a kernel suitable for booting most boards 24 24 ··· 40 40 bool "TI OMAP3" 41 41 depends on ARCH_OMAP2PLUS 42 42 default y 43 43 - select CPU_V7 44 44 - select USB_ARCH_HAS_EHCI if USB_SUPPORT 45 43 select ARCH_HAS_OPP 46 46 - select PM_RUNTIME if CPU_IDLE 47 47 - select PM_OPP if PM 48 44 select ARM_CPU_SUSPEND if PM 45 45 + select CPU_V7 49 46 select MULTI_IRQ_HANDLER 50 50 - select SOC_HAS_OMAP2_SDRC 51 47 select OMAP_INTERCONNECT 48 48 + select PM_OPP if PM 49 49 + select PM_RUNTIME if CPU_IDLE 50 50 + select SOC_HAS_OMAP2_SDRC 51 51 + select USB_ARCH_HAS_EHCI if USB_SUPPORT 52 52 53 53 config ARCH_OMAP4 54 54 bool "TI OMAP4" 55 55 default y 56 56 depends on ARCH_OMAP2PLUS 57 57 + select ARCH_HAS_OPP 58 58 + select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 59 59 + select ARM_CPU_SUSPEND if PM 60 60 + select ARM_ERRATA_720789 61 61 + select ARM_GIC 57 62 select CACHE_L2X0 58 63 select CPU_V7 59 59 - select ARM_GIC 60 64 select HAVE_SMP 61 65 select LOCAL_TIMERS if SMP 66 66 + select OMAP_INTERCONNECT 62 67 select PL310_ERRATA_588369 63 68 select PL310_ERRATA_727915 64 64 - select ARM_ERRATA_720789 65 65 - select ARCH_HAS_OPP 66 66 - select PM_RUNTIME if CPU_IDLE 67 69 select PM_OPP if PM 70 70 + select PM_RUNTIME if CPU_IDLE 68 71 select USB_ARCH_HAS_EHCI if USB_SUPPORT 69 69 - select ARM_CPU_SUSPEND if PM 70 70 - select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 71 71 - select OMAP_INTERCONNECT 72 72 73 73 config SOC_OMAP5 74 74 bool "TI OMAP5" 75 75 - select CPU_V7 76 76 - select ARM_GIC 77 77 - select HAVE_SMP 78 78 - select ARM_CPU_SUSPEND if PM 79 79 - select SOC_HAS_REALTIME_COUNTER 80 75 select ARM_ARCH_TIMER 76 76 + select ARM_CPU_SUSPEND if PM 77 77 + select ARM_GIC 78 78 + select CPU_V7 79 79 + select HAVE_SMP 80 80 + select SOC_HAS_REALTIME_COUNTER 81 81 82 82 comment "OMAP Core Type" 83 83 depends on ARCH_OMAP2 ··· 109 109 config SOC_AM33XX 110 110 bool "AM33XX support" 111 111 default y 112 112 - select CPU_V7 113 112 select ARM_CPU_SUSPEND if PM 113 113 + select CPU_V7 114 114 select MULTI_IRQ_HANDLER 115 115 116 116 config OMAP_PACKAGE_ZAF ··· 157 157 bool "OMAP 2420 H4 board" 158 158 depends on SOC_OMAP2420 159 159 default y 160 160 - select OMAP_PACKAGE_ZAF 161 160 select OMAP_DEBUG_DEVICES 161 161 + select OMAP_PACKAGE_ZAF 162 162 163 163 config MACH_OMAP_APOLLON 164 164 bool "OMAP 2420 Apollon board" ··· 193 193 config MACH_OMAP3530_LV_SOM 194 194 bool "OMAP3 Logic 3530 LV SOM board" 195 195 depends on ARCH_OMAP3 196 196 - select OMAP_PACKAGE_CBB 197 196 default y 197 197 + select OMAP_PACKAGE_CBB 198 198 help 199 199 Support for the LogicPD OMAP3530 SOM Development kit 200 200 for full description please see the products webpage at ··· 203 203 config MACH_OMAP3_TORPEDO 204 204 bool "OMAP3 Logic 35x Torpedo board" 205 205 depends on ARCH_OMAP3 206 206 - select OMAP_PACKAGE_CBB 207 206 default y 207 207 + select OMAP_PACKAGE_CBB 208 208 help 209 209 Support for the LogicPD OMAP35x Torpedo Development kit 210 210 for full description please see the products webpage at ··· 265 265 bool "Nokia N800/N810" 266 266 depends on SOC_OMAP2420 267 267 default y 268 268 - select OMAP_PACKAGE_ZAC 269 268 select MACH_NOKIA_N800 270 269 select MACH_NOKIA_N810 271 270 select MACH_NOKIA_N810_WIMAX 271 271 + select OMAP_PACKAGE_ZAC 272 272 273 273 config MACH_NOKIA_RM680 274 274 bool "Nokia RM-680/696 board" 275 275 depends on ARCH_OMAP3 276 276 default y 277 277 - select OMAP_PACKAGE_CBB 278 277 select MACH_NOKIA_RM696 278 278 + select OMAP_PACKAGE_CBB 279 279 280 280 config MACH_NOKIA_RX51 281 281 bool "Nokia RX-51 board" ··· 288 288 depends on ARCH_OMAP3 289 289 default y 290 290 select OMAP_PACKAGE_CBB 291 291 - select SERIAL_8250 292 292 - select SERIAL_CORE_CONSOLE 293 293 - select SERIAL_8250_CONSOLE 294 291 select REGULATOR_FIXED_VOLTAGE if REGULATOR 292 292 + select SERIAL_8250 293 293 + select SERIAL_8250_CONSOLE 294 294 + select SERIAL_CORE_CONSOLE 295 295 296 296 config MACH_OMAP_ZOOM3 297 297 bool "OMAP3630 Zoom3 board" 298 298 depends on ARCH_OMAP3 299 299 default y 300 300 select OMAP_PACKAGE_CBP 301 301 - select SERIAL_8250 302 302 - select SERIAL_CORE_CONSOLE 303 303 - select SERIAL_8250_CONSOLE 304 301 select REGULATOR_FIXED_VOLTAGE if REGULATOR 302 302 + select SERIAL_8250 303 303 + select SERIAL_8250_CONSOLE 304 304 + select SERIAL_CORE_CONSOLE 305 305 306 306 config MACH_CM_T35 307 307 bool "CompuLab CM-T35/CM-T3730 modules" ··· 329 329 bool "IGEP OMAP3 module" 330 330 depends on ARCH_OMAP3 331 331 default y 332 332 - select OMAP_PACKAGE_CBB 333 332 select MACH_IGEP0020 333 333 + select OMAP_PACKAGE_CBB 334 334 335 335 config MACH_SBC3530 336 336 bool "OMAP3 SBC STALKER board"

+1 -1

arch/arm/mach-prima2/Kconfig

reviewed

··· 6 6 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 7 7 default y 8 8 select CPU_V7 9 9 - select ZONE_DMA 10 9 select SIRF_IRQ 10 10 + select ZONE_DMA 11 11 help 12 12 Support for CSR SiRFSoC ARM Cortex A9 Platform 13 13

+62 -62

arch/arm/mach-pxa/Kconfig

reviewed

··· 27 27 28 28 config MACH_PXA3XX_DT 29 29 bool "Support PXA3xx platforms from device tree" 30 30 - select PXA3xx 31 30 select CPU_PXA300 32 32 - select POWER_SUPPLY 33 31 select HAVE_PWM 32 32 + select POWER_SUPPLY 33 33 + select PXA3xx 34 34 select USE_OF 35 35 help 36 36 Include support for Marvell PXA3xx based platforms using ··· 44 44 45 45 config MACH_MAINSTONE 46 46 bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)" 47 47 - select PXA27x 48 47 select HAVE_PWM 48 48 + select PXA27x 49 49 50 50 config MACH_ZYLONITE 51 51 bool 52 52 - select PXA3xx 53 52 select HAVE_PWM 53 53 + select PXA3xx 54 54 55 55 config MACH_ZYLONITE300 56 56 bool "PXA3xx Development Platform (aka Zylonite) PXA300/310" ··· 65 65 66 66 config MACH_LITTLETON 67 67 bool "PXA3xx Form Factor Platform (aka Littleton)" 68 68 - select PXA3xx 69 68 select CPU_PXA300 70 69 select CPU_PXA310 70 70 + select PXA3xx 71 71 72 72 config MACH_TAVOREVB 73 73 bool "PXA930 Evaluation Board (aka TavorEVB)" 74 74 - select PXA3xx 75 74 select CPU_PXA930 75 75 + select PXA3xx 76 76 77 77 config MACH_SAAR 78 78 bool "PXA930 Handheld Platform (aka SAAR)" 79 79 - select PXA3xx 80 79 select CPU_PXA930 80 80 + select PXA3xx 81 81 82 82 comment "Third Party Dev Platforms (sorted by vendor name)" 83 83 ··· 87 87 88 88 config ARCH_VIPER 89 89 bool "Arcom/Eurotech VIPER SBC" 90 90 - select PXA25x 91 91 - select ISA 92 92 - select I2C_GPIO 93 93 - select HAVE_PWM 94 94 - select PXA_HAVE_ISA_IRQS 95 90 select ARCOM_PCMCIA 91 91 + select HAVE_PWM 92 92 + select I2C_GPIO 93 93 + select ISA 94 94 + select PXA25x 95 95 + select PXA_HAVE_ISA_IRQS 96 96 97 97 config MACH_ARCOM_ZEUS 98 98 bool "Arcom/Eurotech ZEUS SBC" 99 99 - select PXA27x 100 100 - select ISA 101 101 - select PXA_HAVE_ISA_IRQS 102 99 select ARCOM_PCMCIA 100 100 + select ISA 101 101 + select PXA27x 102 102 + select PXA_HAVE_ISA_IRQS 103 103 104 104 config MACH_BALLOON3 105 105 bool "Balloon 3 board" 106 106 - select PXA27x 107 106 select IWMMXT 107 107 + select PXA27x 108 108 109 109 config MACH_CSB726 110 110 bool "Enable Cogent CSB726 System On a Module" 111 111 - select PXA27x 112 111 select IWMMXT 112 112 + select PXA27x 113 113 help 114 114 Say Y here if you intend to run this kernel on a Cogent 115 115 CSB726 System On Module. ··· 121 121 config MACH_ARMCORE 122 122 bool "CompuLab CM-X255/CM-X270 modules" 123 123 select ARCH_HAS_DMA_SET_COHERENT_MASK if PCI 124 124 - select PXA27x 125 124 select IWMMXT 126 126 - select PXA25x 127 125 select MIGHT_HAVE_PCI 128 126 select NEED_MACH_IO_H if PCI 127 127 + select PXA25x 128 128 + select PXA27x 129 129 130 130 config MACH_EM_X270 131 131 bool "CompuLab EM-x270 platform" ··· 137 137 138 138 config MACH_CM_X300 139 139 bool "CompuLab CM-X300 modules" 140 140 - select PXA3xx 141 140 select CPU_PXA300 142 141 select CPU_PXA310 143 142 select HAVE_PWM 143 143 + select PXA3xx 144 144 145 145 config MACH_CAPC7117 146 146 bool "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM" ··· 168 168 169 169 config MACH_INTELMOTE2 170 170 bool "Intel Mote 2 Platform" 171 171 - select PXA27x 172 171 select IWMMXT 172 172 + select PXA27x 173 173 174 174 config MACH_STARGATE2 175 175 bool "Intel Stargate 2 Platform" 176 176 - select PXA27x 177 176 select IWMMXT 177 177 + select PXA27x 178 178 179 179 config MACH_XCEP 180 180 bool "Iskratel Electronics XCEP" 181 181 - select PXA25x 182 181 select MTD 183 183 - select MTD_PHYSMAP 184 184 - select MTD_CFI_INTELEXT 185 182 select MTD_CFI 183 183 + select MTD_CFI_INTELEXT 186 184 select MTD_CHAR 185 185 + select MTD_PHYSMAP 186 186 + select PXA25x 187 187 select SMC91X 188 188 help 189 189 PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash. ··· 195 195 config MACH_TRIZEPS4 196 196 bool "Keith und Koep Trizeps4 DIMM-Module" 197 197 depends on TRIZEPS_PXA 198 198 - select TRIZEPS_PCMCIA 199 198 select PXA27x 199 199 + select TRIZEPS_PCMCIA 200 200 201 201 config MACH_TRIZEPS4WL 202 202 bool "Keith und Koep Trizeps4-WL DIMM-Module" 203 203 depends on TRIZEPS_PXA 204 204 - select TRIZEPS_PCMCIA 205 204 select PXA27x 205 205 + select TRIZEPS_PCMCIA 206 206 207 207 choice 208 208 prompt "Select base board for Trizeps module" ··· 231 231 232 232 config MACH_LOGICPD_PXA270 233 233 bool "LogicPD PXA270 Card Engine Development Platform" 234 234 - select PXA27x 235 234 select HAVE_PWM 235 235 + select PXA27x 236 236 237 237 config MACH_PCM027 238 238 bool "Phytec phyCORE-PXA270 CPU module (PCM-027)" 239 239 - select PXA27x 240 239 select IWMMXT 240 240 + select PXA27x 241 241 242 242 config MACH_PCM990_BASEBOARD 243 243 bool "PHYTEC PCM-990 development board" 244 244 - select HAVE_PWM 245 244 depends on MACH_PCM027 245 245 + select HAVE_PWM 246 246 247 247 choice 248 248 prompt "display on pcm990" ··· 266 266 config MACH_COLIBRI_PXA270_INCOME 267 267 bool "Income s.r.o. PXA270 SBC" 268 268 depends on MACH_COLIBRI 269 269 - select PXA27x 270 269 select HAVE_PWM 270 270 + select PXA27x 271 271 272 272 config MACH_COLIBRI300 273 273 bool "Toradex Colibri PXA300/310" 274 274 - select PXA3xx 275 274 select CPU_PXA300 276 275 select CPU_PXA310 276 276 + select PXA3xx 277 277 278 278 config MACH_COLIBRI320 279 279 bool "Toradex Colibri PXA320" 280 280 - select PXA3xx 281 280 select CPU_PXA320 281 281 + select PXA3xx 282 282 283 283 config MACH_COLIBRI_EVALBOARD 284 284 bool "Toradex Colibri Evaluation Carrier Board support" ··· 286 286 287 287 config MACH_VPAC270 288 288 bool "Voipac PXA270" 289 289 - select PXA27x 290 289 select HAVE_PATA_PLATFORM 290 290 + select PXA27x 291 291 help 292 292 PXA270 based Single Board Computer. 293 293 ··· 295 295 296 296 config MACH_H4700 297 297 bool "HP iPAQ hx4700" 298 298 - select PXA27x 299 299 - select IWMMXT 300 298 select HAVE_PWM 299 299 + select IWMMXT 300 300 + select PXA27x 301 301 302 302 config MACH_H5000 303 303 bool "HP iPAQ h5000" ··· 309 309 310 310 config MACH_MAGICIAN 311 311 bool "Enable HTC Magician Support" 312 312 - select PXA27x 313 313 - select IWMMXT 314 312 select HAVE_PWM 313 313 + select IWMMXT 314 314 + select PXA27x 315 315 316 316 config MACH_MIOA701 317 317 bool "Mitac Mio A701 Support" 318 318 - select PXA27x 319 319 - select IWMMXT 320 320 - select HAVE_PWM 321 318 select GPIO_SYSFS 319 319 + select HAVE_PWM 320 320 + select IWMMXT 321 321 + select PXA27x 322 322 help 323 323 Say Y here if you intend to run this kernel on a 324 324 MIO A701. Currently there is only basic support ··· 326 326 327 327 config PXA_EZX 328 328 bool "Motorola EZX Platform" 329 329 - select PXA27x 330 330 - select IWMMXT 331 329 select HAVE_PWM 330 330 + select IWMMXT 331 331 + select PXA27x 332 332 333 333 config MACH_EZX_A780 334 334 bool "Motorola EZX A780" ··· 393 393 bool "Palm Tungsten|T5" 394 394 default y 395 395 depends on ARCH_PXA_PALM 396 396 - select PXA27x 397 396 select IWMMXT 398 397 select MACH_PALM27X 398 398 + select PXA27x 399 399 help 400 400 Say Y here if you intend to run this kernel on a Palm Tungsten|T5 401 401 handheld computer. ··· 404 404 bool "Palm T|X" 405 405 default y 406 406 depends on ARCH_PXA_PALM 407 407 - select PXA27x 408 407 select IWMMXT 409 408 select MACH_PALM27X 409 409 + select PXA27x 410 410 help 411 411 Say Y here if you intend to run this kernel on a Palm T|X 412 412 handheld computer. ··· 415 415 bool "Palm Zire 72" 416 416 default y 417 417 depends on ARCH_PXA_PALM 418 418 - select PXA27x 419 418 select IWMMXT 420 419 select MACH_PALM27X 420 420 + select PXA27x 421 421 help 422 422 Say Y here if you intend to run this kernel on Palm Zire 72 423 423 handheld computer. ··· 426 426 bool "Palm LifeDrive" 427 427 default y 428 428 depends on ARCH_PXA_PALM 429 429 - select PXA27x 430 429 select IWMMXT 431 430 select MACH_PALM27X 431 431 + select PXA27x 432 432 help 433 433 Say Y here if you intend to run this kernel on a Palm LifeDrive 434 434 handheld computer. ··· 441 441 bool "Palm Centro 685 (GSM)" 442 442 default y 443 443 depends on ARCH_PXA_PALM 444 444 - select MACH_PALM27X 445 445 - select PXA27x 446 444 select IWMMXT 445 445 + select MACH_PALM27X 447 446 select PALM_TREO 447 447 + select PXA27x 448 448 help 449 449 Say Y here if you intend to run this kernel on Palm Centro 685 (GSM) 450 450 smartphone. ··· 453 453 bool "Palm Treo 680" 454 454 default y 455 455 depends on ARCH_PXA_PALM 456 456 - select MACH_PALM27X 457 457 - select PXA27x 458 456 select IWMMXT 457 457 + select MACH_PALM27X 459 458 select PALM_TREO 459 459 + select PXA27x 460 460 help 461 461 Say Y here if you intend to run this kernel on Palm Treo 680 462 462 smartphone. 463 463 464 464 config MACH_RAUMFELD_RC 465 465 bool "Raumfeld Controller" 466 466 - select PXA3xx 467 466 select CPU_PXA300 468 468 - select POWER_SUPPLY 469 467 select HAVE_PWM 468 468 + select POWER_SUPPLY 469 469 + select PXA3xx 470 470 471 471 config MACH_RAUMFELD_CONNECTOR 472 472 bool "Raumfeld Connector" 473 473 + select CPU_PXA300 473 474 select POWER_SUPPLY 474 475 select PXA3xx 475 475 - select CPU_PXA300 476 476 477 477 config MACH_RAUMFELD_SPEAKER 478 478 bool "Raumfeld Speaker" 479 479 + select CPU_PXA300 479 480 select POWER_SUPPLY 480 481 select PXA3xx 481 481 - select CPU_PXA300 482 482 483 483 config PXA_SHARPSL 484 484 bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" 485 485 - select SHARP_SCOOP 486 485 select SHARP_PARAM 486 486 + select SHARP_SCOOP 487 487 help 488 488 Say Y here if you intend to run this kernel on a 489 489 Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi), ··· 526 526 config MACH_AKITA 527 527 bool "Enable Sharp SL-1000 (Akita) Support" 528 528 depends on PXA_SHARPSL 529 529 - select PXA27x 530 530 - select PXA_SHARP_Cxx00 531 531 - select MACH_SPITZ 532 529 select I2C 533 530 select I2C_PXA 531 531 + select MACH_SPITZ 532 532 + select PXA27x 533 533 + select PXA_SHARP_Cxx00 534 534 535 535 config MACH_SPITZ 536 536 bool "Enable Sharp Zaurus SL-3000 (Spitz) Support" ··· 575 575 576 576 config ARCH_PXA_ESERIES 577 577 bool "PXA based Toshiba e-series PDAs" 578 578 - select PXA25x 579 578 select FB_W100 579 579 + select PXA25x 580 580 581 581 config MACH_E330 582 582 bool "Toshiba e330" ··· 628 628 629 629 config MACH_ZIPIT2 630 630 bool "Zipit Z2 Handheld" 631 631 - select PXA27x 632 631 select HAVE_PWM 632 632 + select PXA27x 633 633 endif 634 634 endmenu 635 635 ··· 720 720 config SHARPSL_PM_MAX1111 721 721 bool 722 722 select HWMON 723 723 + select SENSORS_MAX1111 723 724 select SPI 724 725 select SPI_MASTER 725 725 - select SENSORS_MAX1111 726 726 727 727 config PXA_HAVE_ISA_IRQS 728 728 bool

+6 -6

arch/arm/mach-realview/Kconfig

reviewed

··· 21 21 config REALVIEW_EB_ARM11MP 22 22 bool "Support ARM11MPCore Tile" 23 23 depends on MACH_REALVIEW_EB 24 24 - select CPU_V6K 25 24 select ARCH_HAS_BARRIERS if SMP 25 25 + select CPU_V6K 26 26 select HAVE_SMP 27 27 select MIGHT_HAVE_CACHE_L2X0 28 28 help ··· 40 40 41 41 config MACH_REALVIEW_PB11MP 42 42 bool "Support RealView(R) Platform Baseboard for ARM11MPCore" 43 43 - select CPU_V6K 43 43 + select ARCH_HAS_BARRIERS if SMP 44 44 select ARM_GIC 45 45 + select CPU_V6K 45 46 select HAVE_PATA_PLATFORM 46 47 select HAVE_SMP 47 48 select MIGHT_HAVE_CACHE_L2X0 48 48 - select ARCH_HAS_BARRIERS if SMP 49 49 help 50 50 Include support for the ARM(R) RealView(R) Platform Baseboard for 51 51 the ARM11MPCore. This platform has an on-board ARM11MPCore and has ··· 54 54 # ARMv6 CPU without K extensions, but does have the new exclusive ops 55 55 config MACH_REALVIEW_PB1176 56 56 bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S" 57 57 - select CPU_V6 58 57 select ARM_GIC 58 58 + select CPU_V6 59 59 select HAVE_TCM 60 60 select MIGHT_HAVE_CACHE_L2X0 61 61 help ··· 73 73 74 74 config MACH_REALVIEW_PBA8 75 75 bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform" 76 76 - select CPU_V7 77 76 select ARM_GIC 77 77 + select CPU_V7 78 78 select HAVE_PATA_PLATFORM 79 79 help 80 80 Include support for the ARM(R) RealView Platform Baseboard for ··· 83 83 84 84 config MACH_REALVIEW_PBX 85 85 bool "Support RealView(R) Platform Baseboard Explore" 86 86 + select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET 86 87 select ARM_GIC 87 88 select HAVE_PATA_PLATFORM 88 89 select HAVE_SMP 89 90 select MIGHT_HAVE_CACHE_L2X0 90 90 - select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET 91 91 select ZONE_DMA if SPARSEMEM 92 92 help 93 93 Include support for the ARM(R) RealView(R) Platform Baseboard

+1 -1

arch/arm/mach-s3c2412/Kconfig

reviewed

··· 7 7 config S3C2412_CPUFREQ 8 8 bool 9 9 depends on CPU_FREQ_S3C24XX && CPU_S3C2412 10 10 - select S3C2412_IOTIMING 11 10 default y 11 11 + select S3C2412_IOTIMING 12 12 help 13 13 CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.

+1 -1

arch/arm/mach-s3c2440/Kconfig

reviewed

··· 5 5 config S3C2440_CPUFREQ 6 6 bool "S3C2440/S3C2442 CPU Frequency scaling support" 7 7 depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442) 8 8 - select S3C2410_CPUFREQ_UTILS 9 8 default y 9 9 + select S3C2410_CPUFREQ_UTILS 10 10 help 11 11 CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. 12 12

+44 -44

arch/arm/mach-s3c24xx/Kconfig

reviewed

··· 17 17 bool "SAMSUNG S3C2410" 18 18 default y 19 19 select CPU_ARM920T 20 20 - select S3C2410_CLOCK 21 20 select CPU_LLSERIAL_S3C2410 22 22 - select S3C2410_PM if PM 21 21 + select S3C2410_CLOCK 23 22 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX 23 23 + select S3C2410_PM if PM 24 24 help 25 25 Support for S3C2410 and S3C2410A family from the S3C24XX line 26 26 of Samsung Mobile CPUs. ··· 30 30 depends on ARCH_S3C24XX 31 31 select CPU_ARM926T 32 32 select CPU_LLSERIAL_S3C2440 33 33 - select S3C2412_PM if PM 34 33 select S3C2412_DMA if S3C24XX_DMA 34 34 + select S3C2412_PM if PM 35 35 help 36 36 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line 37 37 ··· 40 40 depends on ARCH_S3C24XX 41 41 select CPU_ARM926T 42 42 select CPU_LLSERIAL_S3C2440 43 43 - select SAMSUNG_CLKSRC 43 43 + select S3C2416_PM if PM 44 44 select S3C2443_COMMON 45 45 select S3C2443_DMA if S3C24XX_DMA 46 46 - select S3C2416_PM if PM 46 46 + select SAMSUNG_CLKSRC 47 47 help 48 48 Support for the S3C2416 SoC from the S3C24XX line 49 49 ··· 75 75 depends on ARCH_S3C24XX 76 76 select CPU_ARM920T 77 77 select CPU_LLSERIAL_S3C2440 78 78 - select SAMSUNG_CLKSRC 79 78 select S3C2443_COMMON 80 79 select S3C2443_DMA if S3C24XX_DMA 80 80 + select SAMSUNG_CLKSRC 81 81 help 82 82 Support for the S3C2443 SoC from the S3C24XX line 83 83 ··· 156 156 157 157 config ARCH_BAST 158 158 bool "Simtec Electronics BAST (EB2410ITX)" 159 159 - select S3C2410_IOTIMING if S3C2410_CPUFREQ 160 160 - select S3C24XX_SIMTEC_PM if PM 161 161 - select S3C24XX_SIMTEC_NOR 162 162 - select S3C24XX_SIMTEC_USB 163 163 - select MACH_BAST_IDE 164 164 - select S3C24XX_DCLK 165 159 select ISA 160 160 + select MACH_BAST_IDE 161 161 + select S3C2410_IOTIMING if S3C2410_CPUFREQ 162 162 + select S3C24XX_DCLK 163 163 + select S3C24XX_SIMTEC_NOR 164 164 + select S3C24XX_SIMTEC_PM if PM 165 165 + select S3C24XX_SIMTEC_USB 166 166 select S3C_DEV_HWMON 167 167 - select S3C_DEV_USB_HOST 168 167 select S3C_DEV_NAND 168 168 + select S3C_DEV_USB_HOST 169 169 help 170 170 Say Y here if you are using the Simtec Electronics EB2410ITX 171 171 development board (also known as BAST) ··· 181 181 config ARCH_H1940 182 182 bool "IPAQ H1940" 183 183 select PM_H1940 if PM 184 184 - select S3C_DEV_USB_HOST 185 185 - select S3C_DEV_NAND 186 184 select S3C24XX_SETUP_TS 185 185 + select S3C_DEV_NAND 186 186 + select S3C_DEV_USB_HOST 187 187 help 188 188 Say Y here if you are using the HP IPAQ H1940 189 189 ··· 203 203 config MACH_N30 204 204 bool "Acer N30 family" 205 205 select MACH_N35 206 206 - select S3C_DEV_USB_HOST 207 206 select S3C_DEV_NAND 207 207 + select S3C_DEV_USB_HOST 208 208 help 209 209 Say Y here if you want suppt for the Acer N30, Acer N35, 210 210 Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. 211 211 212 212 config MACH_OTOM 213 213 bool "NexVision OTOM Board" 214 214 - select S3C_DEV_USB_HOST 215 214 select S3C_DEV_NAND 215 215 + select S3C_DEV_USB_HOST 216 216 help 217 217 Say Y here if you are using the Nex Vision OTOM board 218 218 219 219 config MACH_QT2410 220 220 bool "QT2410" 221 221 - select S3C_DEV_USB_HOST 222 221 select S3C_DEV_NAND 222 222 + select S3C_DEV_USB_HOST 223 223 help 224 224 Say Y here if you are using the Armzone QT2410 225 225 ··· 239 239 240 240 config MACH_VR1000 241 241 bool "Thorcom VR1000" 242 242 - select S3C24XX_SIMTEC_PM if PM 242 242 + select MACH_BAST_IDE 243 243 select S3C24XX_DCLK 244 244 select S3C24XX_SIMTEC_NOR 245 245 - select MACH_BAST_IDE 246 246 - select S3C_DEV_USB_HOST 245 245 + select S3C24XX_SIMTEC_PM if PM 247 246 select S3C24XX_SIMTEC_USB 247 247 + select S3C_DEV_USB_HOST 248 248 help 249 249 Say Y here if you are using the Thorcom VR1000 board. 250 250 ··· 285 285 286 286 config MACH_JIVE 287 287 bool "Logitech Jive" 288 288 - select S3C_DEV_USB_HOST 289 288 select S3C_DEV_NAND 289 289 + select S3C_DEV_USB_HOST 290 290 help 291 291 Say Y here if you are using the Logitech Jive. 292 292 ··· 314 314 bool "SMDK2413" 315 315 select MACH_S3C2413 316 316 select S3C24XX_SMDK 317 317 - select S3C_DEV_USB_HOST 318 317 select S3C_DEV_NAND 318 318 + select S3C_DEV_USB_HOST 319 319 help 320 320 Say Y here if you are using an SMDK2413 321 321 322 322 config MACH_VSTMS 323 323 bool "VMSTMS" 324 324 - select S3C_DEV_USB_HOST 325 324 select S3C_DEV_NAND 325 325 + select S3C_DEV_USB_HOST 326 326 help 327 327 Say Y here if you are using an VSTMS board 328 328 ··· 351 351 352 352 config MACH_SMDK2416 353 353 bool "SMDK2416" 354 354 + select S3C2416_SETUP_SDHCI 354 355 select S3C24XX_SMDK 355 356 select S3C_DEV_FB 356 357 select S3C_DEV_HSMMC 357 358 select S3C_DEV_HSMMC1 358 359 select S3C_DEV_NAND 359 360 select S3C_DEV_USB_HOST 360 360 - select S3C2416_SETUP_SDHCI 361 361 help 362 362 Say Y here if you are using an SMDK2416 363 363 ··· 379 379 380 380 config MACH_ANUBIS 381 381 bool "Simtec Electronics ANUBIS" 382 382 - select S3C24XX_DCLK 383 383 - select S3C24XX_SIMTEC_PM if PM 384 382 select HAVE_PATA_PLATFORM 385 385 - select S3C24XX_GPIO_EXTRA64 386 383 select S3C2440_XTAL_12000000 384 384 + select S3C24XX_DCLK 385 385 + select S3C24XX_GPIO_EXTRA64 386 386 + select S3C24XX_SIMTEC_PM if PM 387 387 select S3C_DEV_USB_HOST 388 388 help 389 389 Say Y here if you are using the Simtec Electronics ANUBIS ··· 391 391 392 392 config MACH_AT2440EVB 393 393 bool "Avantech AT2440EVB development board" 394 394 - select S3C_DEV_USB_HOST 395 394 select S3C_DEV_NAND 395 395 + select S3C_DEV_USB_HOST 396 396 help 397 397 Say Y here if you are using the AT2440EVB development board 398 398 399 399 config MACH_MINI2440 400 400 bool "MINI2440 development board" 401 401 select EEPROM_AT24 402 402 - select NEW_LEDS 403 402 select LEDS_CLASS 404 403 select LEDS_TRIGGER 405 404 select LEDS_TRIGGER_BACKLIGHT 405 405 + select NEW_LEDS 406 406 select S3C_DEV_NAND 407 407 select S3C_DEV_USB_HOST 408 408 help ··· 412 412 config MACH_NEXCODER_2440 413 413 bool "NexVision NEXCODER 2440 Light Board" 414 414 select S3C2440_XTAL_12000000 415 415 - select S3C_DEV_USB_HOST 416 415 select S3C_DEV_NAND 416 416 + select S3C_DEV_USB_HOST 417 417 help 418 418 Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board 419 419 420 420 config MACH_OSIRIS 421 421 bool "Simtec IM2440D20 (OSIRIS) module" 422 422 - select S3C24XX_DCLK 423 423 - select S3C24XX_SIMTEC_PM if PM 424 424 - select S3C24XX_GPIO_EXTRA128 425 425 - select S3C2440_XTAL_12000000 426 422 select S3C2410_IOTIMING if S3C2440_CPUFREQ 427 427 - select S3C_DEV_USB_HOST 423 423 + select S3C2440_XTAL_12000000 424 424 + select S3C24XX_DCLK 425 425 + select S3C24XX_GPIO_EXTRA128 426 426 + select S3C24XX_SIMTEC_PM if PM 428 427 select S3C_DEV_NAND 428 428 + select S3C_DEV_USB_HOST 429 429 help 430 430 Say Y here if you are using the Simtec IM2440D20 module, also 431 431 known as the Osiris. ··· 445 445 446 446 config MACH_RX3715 447 447 bool "HP iPAQ rx3715" 448 448 - select S3C2440_XTAL_16934400 449 448 select PM_H1940 if PM 449 449 + select S3C2440_XTAL_16934400 450 450 select S3C_DEV_NAND 451 451 help 452 452 Say Y here if you are using the HP iPAQ rx3715. ··· 455 455 bool "SMDK2440" 456 456 select S3C2440_XTAL_16934400 457 457 select S3C24XX_SMDK 458 458 - select S3C_DEV_USB_HOST 459 458 select S3C_DEV_NAND 459 459 + select S3C_DEV_USB_HOST 460 460 help 461 461 Say Y here if you are using the SMDK2440. 462 462 ··· 478 478 479 479 config MACH_NEO1973_GTA02 480 480 bool "Openmoko GTA02 / Freerunner phone" 481 481 + select I2C 482 482 + select MACH_NEO1973 481 483 select MFD_PCF50633 482 484 select PCF50633_GPIO 483 483 - select I2C 484 485 select POWER_SUPPLY 485 485 - select MACH_NEO1973 486 486 select S3C24XX_PWM 487 487 select S3C_DEV_USB_HOST 488 488 help ··· 490 490 491 491 config MACH_RX1950 492 492 bool "HP iPAQ rx1950" 493 493 - select S3C24XX_DCLK 494 494 - select PM_H1940 if PM 495 493 select I2C 496 496 - select S3C24XX_PWM 497 497 - select S3C_DEV_NAND 494 494 + select PM_H1940 if PM 498 495 select S3C2410_IOTIMING if S3C2440_CPUFREQ 499 496 select S3C2440_XTAL_16934400 497 497 + select S3C24XX_DCLK 498 498 + select S3C24XX_PWM 499 499 + select S3C_DEV_NAND 500 500 help 501 501 Say Y here if you're using HP iPAQ rx1950 502 502

+48 -48

arch/arm/mach-s3c64xx/Kconfig

reviewed

··· 7 7 config PLAT_S3C64XX 8 8 bool 9 9 depends on ARCH_S3C64XX 10 10 - select SAMSUNG_WAKEMASK 11 11 - select PM_GENERIC_DOMAINS 12 10 default y 11 11 + select PM_GENERIC_DOMAINS 12 12 + select SAMSUNG_WAKEMASK 13 13 help 14 14 Base platform code for any Samsung S3C64XX device 15 15 ··· 31 31 select S3C_DMA 32 32 33 33 config S3C64XX_SETUP_SDHCI 34 34 - select S3C64XX_SETUP_SDHCI_GPIO 35 34 bool 35 35 + select S3C64XX_SETUP_SDHCI_GPIO 36 36 help 37 37 Internal configuration for default SDHCI setup for S3C6400 and 38 38 S3C6410 SoCs. ··· 93 93 config MACH_SMDK6400 94 94 bool "SMDK6400" 95 95 select CPU_S3C6400 96 96 + select S3C64XX_SETUP_SDHCI 96 97 select S3C_DEV_HSMMC 97 98 select S3C_DEV_NAND 98 98 - select S3C64XX_SETUP_SDHCI 99 99 help 100 100 Machine support for the Samsung SMDK6400 101 101 ··· 104 104 config MACH_ANW6410 105 105 bool "A&W6410" 106 106 select CPU_S3C6410 107 107 - select S3C_DEV_FB 108 107 select S3C64XX_SETUP_FB_24BPP 108 108 + select S3C_DEV_FB 109 109 help 110 110 Machine support for the A&W6410 111 111 112 112 config MACH_MINI6410 113 113 bool "MINI6410" 114 114 select CPU_S3C6410 115 115 + select S3C64XX_SETUP_FB_24BPP 116 116 + select S3C64XX_SETUP_SDHCI 117 117 + select S3C_DEV_FB 115 118 select S3C_DEV_HSMMC 116 119 select S3C_DEV_HSMMC1 117 117 - select S3C64XX_SETUP_SDHCI 118 118 - select S3C_DEV_USB_HOST 119 120 select S3C_DEV_NAND 120 120 - select S3C_DEV_FB 121 121 - select S3C64XX_SETUP_FB_24BPP 121 121 + select S3C_DEV_USB_HOST 122 122 select SAMSUNG_DEV_ADC 123 123 select SAMSUNG_DEV_TS 124 124 help ··· 127 127 config MACH_REAL6410 128 128 bool "REAL6410" 129 129 select CPU_S3C6410 130 130 - select S3C_DEV_HSMMC 131 131 - select S3C_DEV_HSMMC1 130 130 + select S3C64XX_SETUP_FB_24BPP 132 131 select S3C64XX_SETUP_SDHCI 133 132 select S3C_DEV_FB 134 134 - select S3C64XX_SETUP_FB_24BPP 133 133 + select S3C_DEV_HSMMC 134 134 + select S3C_DEV_HSMMC1 135 135 select S3C_DEV_NAND 136 136 + select S3C_DEV_USB_HOST 136 137 select SAMSUNG_DEV_ADC 137 138 select SAMSUNG_DEV_TS 138 138 - select S3C_DEV_USB_HOST 139 139 help 140 140 Machine support for the CoreWind REAL6410 141 141 142 142 config MACH_SMDK6410 143 143 bool "SMDK6410" 144 144 select CPU_S3C6410 145 145 - select SAMSUNG_DEV_ADC 145 145 + select HAVE_S3C2410_WATCHDOG if WATCHDOG 146 146 + select S3C64XX_SETUP_FB_24BPP 147 147 + select S3C64XX_SETUP_I2C1 148 148 + select S3C64XX_SETUP_IDE 149 149 + select S3C64XX_SETUP_KEYPAD 150 150 + select S3C64XX_SETUP_SDHCI 151 151 + select S3C64XX_SETUP_USB_PHY 152 152 + select S3C_DEV_FB 146 153 select S3C_DEV_HSMMC 147 154 select S3C_DEV_HSMMC1 148 155 select S3C_DEV_I2C1 149 149 - select SAMSUNG_DEV_IDE 150 150 - select S3C_DEV_FB 151 156 select S3C_DEV_RTC 152 152 - select SAMSUNG_DEV_TS 153 157 select S3C_DEV_USB_HOST 154 158 select S3C_DEV_USB_HSOTG 155 159 select S3C_DEV_WDT 160 160 + select SAMSUNG_DEV_ADC 156 161 select SAMSUNG_DEV_BACKLIGHT 162 162 + select SAMSUNG_DEV_IDE 157 163 select SAMSUNG_DEV_KEYPAD 158 164 select SAMSUNG_DEV_PWM 159 159 - select HAVE_S3C2410_WATCHDOG if WATCHDOG 160 160 - select S3C64XX_SETUP_SDHCI 161 161 - select S3C64XX_SETUP_I2C1 162 162 - select S3C64XX_SETUP_IDE 163 163 - select S3C64XX_SETUP_FB_24BPP 164 164 - select S3C64XX_SETUP_KEYPAD 165 165 - select S3C64XX_SETUP_USB_PHY 165 165 + select SAMSUNG_DEV_TS 166 166 help 167 167 Machine support for the Samsung SMDK6410 168 168 ··· 198 198 config SMDK6410_WM1190_EV1 199 199 bool "Support Wolfson Microelectronics 1190-EV1 PMIC card" 200 200 depends on MACH_SMDK6410 201 201 + select MFD_WM8350_CONFIG_MODE_0 202 202 + select MFD_WM8350_CONFIG_MODE_3 203 203 + select MFD_WM8350_I2C 204 204 + select MFD_WM8352_CONFIG_MODE_0 201 205 select REGULATOR 202 206 select REGULATOR_WM8350 203 207 select SAMSUNG_GPIO_EXTRA64 204 204 - select MFD_WM8350_I2C 205 205 - select MFD_WM8350_CONFIG_MODE_0 206 206 - select MFD_WM8350_CONFIG_MODE_3 207 207 - select MFD_WM8352_CONFIG_MODE_0 208 208 help 209 209 The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC 210 210 and audio daughtercard for the Samsung SMDK6410 reference ··· 216 216 config SMDK6410_WM1192_EV1 217 217 bool "Support Wolfson Microelectronics 1192-EV1 PMIC card" 218 218 depends on MACH_SMDK6410 219 219 + select MFD_WM831X 220 220 + select MFD_WM831X_I2C 219 221 select REGULATOR 220 222 select REGULATOR_WM831X 221 223 select SAMSUNG_GPIO_EXTRA64 222 222 - select MFD_WM831X 223 223 - select MFD_WM831X_I2C 224 224 help 225 225 The Wolfson Microelectronics 1192-EV1 is a WM831x based PMIC 226 226 daughtercard for the Samsung SMDK6410 reference platform. ··· 232 232 config MACH_NCP 233 233 bool "NCP" 234 234 select CPU_S3C6410 235 235 - select S3C_DEV_I2C1 236 236 - select S3C_DEV_HSMMC1 237 235 select S3C64XX_SETUP_I2C1 236 236 + select S3C_DEV_HSMMC1 237 237 + select S3C_DEV_I2C1 238 238 help 239 239 Machine support for the Samsung NCP 240 240 241 241 config MACH_HMT 242 242 bool "Airgoo HMT" 243 243 select CPU_S3C6410 244 244 + select S3C64XX_SETUP_FB_24BPP 244 245 select S3C_DEV_FB 245 246 select S3C_DEV_NAND 246 247 select S3C_DEV_USB_HOST 247 247 - select S3C64XX_SETUP_FB_24BPP 248 248 select SAMSUNG_DEV_PWM 249 249 help 250 250 Machine support for the Airgoo HMT ··· 252 252 config MACH_SMARTQ 253 253 bool 254 254 select CPU_S3C6410 255 255 + select S3C64XX_SETUP_FB_24BPP 256 256 + select S3C64XX_SETUP_SDHCI 257 257 + select S3C64XX_SETUP_USB_PHY 258 258 + select S3C_DEV_FB 255 259 select S3C_DEV_HSMMC 256 260 select S3C_DEV_HSMMC1 257 261 select S3C_DEV_HSMMC2 258 258 - select S3C_DEV_FB 259 262 select S3C_DEV_HWMON 260 263 select S3C_DEV_RTC 261 261 - select S3C_DEV_USB_HSOTG 262 264 select S3C_DEV_USB_HOST 263 263 - select S3C64XX_SETUP_SDHCI 264 264 - select S3C64XX_SETUP_FB_24BPP 265 265 - select S3C64XX_SETUP_USB_PHY 265 265 + select S3C_DEV_USB_HSOTG 266 266 select SAMSUNG_DEV_ADC 267 267 select SAMSUNG_DEV_PWM 268 268 select SAMSUNG_DEV_TS ··· 284 284 config MACH_WLF_CRAGG_6410 285 285 bool "Wolfson Cragganmore 6410" 286 286 select CPU_S3C6410 287 287 - select S3C64XX_SETUP_SDHCI 287 287 + select I2C 288 288 + select LEDS_GPIO_REGISTER 289 289 + select S3C64XX_DEV_SPI0 290 290 + select S3C64XX_SETUP_FB_24BPP 288 291 select S3C64XX_SETUP_I2C1 289 292 select S3C64XX_SETUP_IDE 290 290 - select S3C64XX_SETUP_FB_24BPP 291 293 select S3C64XX_SETUP_KEYPAD 294 294 + select S3C64XX_SETUP_SDHCI 292 295 select S3C64XX_SETUP_SPI 293 296 select S3C64XX_SETUP_USB_PHY 294 294 - select SAMSUNG_DEV_ADC 295 295 - select SAMSUNG_DEV_KEYPAD 296 296 - select S3C_DEV_USB_HOST 297 297 - select S3C_DEV_USB_HSOTG 298 297 select S3C_DEV_HSMMC 299 298 select S3C_DEV_HSMMC1 300 299 select S3C_DEV_HSMMC2 301 300 select S3C_DEV_I2C1 302 302 - select S3C_DEV_WDT 303 301 select S3C_DEV_RTC 304 304 - select S3C64XX_DEV_SPI0 302 302 + select S3C_DEV_USB_HOST 303 303 + select S3C_DEV_USB_HSOTG 304 304 + select S3C_DEV_WDT 305 305 + select SAMSUNG_DEV_ADC 306 306 + select SAMSUNG_DEV_KEYPAD 305 307 select SAMSUNG_GPIO_EXTRA128 306 306 - select I2C 307 307 - select LEDS_GPIO_REGISTER 308 308 help 309 309 Machine support for the Wolfson Cragganmore S3C6410 variant.

+14 -14

arch/arm/mach-s5p64x0/Kconfig

reviewed

··· 9 9 10 10 config CPU_S5P6440 11 11 bool 12 12 - select SAMSUNG_DMADEV 13 12 select S5P_HRT 14 13 select S5P_SLEEP if PM 14 14 + select SAMSUNG_DMADEV 15 15 select SAMSUNG_WAKEMASK if PM 16 16 help 17 17 Enable S5P6440 CPU support 18 18 19 19 config CPU_S5P6450 20 20 bool 21 21 - select SAMSUNG_DMADEV 22 21 select S5P_HRT 23 22 select S5P_SLEEP if PM 23 23 + select SAMSUNG_DMADEV 24 24 select SAMSUNG_WAKEMASK if PM 25 25 help 26 26 Enable S5P6450 CPU support ··· 52 52 bool "SMDK6440" 53 53 select CPU_S5P6440 54 54 select S3C_DEV_FB 55 55 - select S3C_DEV_I2C1 56 56 - select S3C_DEV_RTC 57 57 - select S3C_DEV_WDT 58 55 select S3C_DEV_HSMMC 59 56 select S3C_DEV_HSMMC1 60 57 select S3C_DEV_HSMMC2 58 58 + select S3C_DEV_I2C1 59 59 + select S3C_DEV_RTC 60 60 + select S3C_DEV_WDT 61 61 + select S5P64X0_SETUP_FB_24BPP 62 62 + select S5P64X0_SETUP_I2C1 63 63 + select S5P64X0_SETUP_SDHCI_GPIO 61 64 select SAMSUNG_DEV_ADC 62 65 select SAMSUNG_DEV_BACKLIGHT 63 66 select SAMSUNG_DEV_PWM 64 67 select SAMSUNG_DEV_TS 65 65 - select S5P64X0_SETUP_FB_24BPP 66 66 - select S5P64X0_SETUP_I2C1 67 67 - select S5P64X0_SETUP_SDHCI_GPIO 68 68 help 69 69 Machine support for the Samsung SMDK6440 70 70 ··· 72 72 bool "SMDK6450" 73 73 select CPU_S5P6450 74 74 select S3C_DEV_FB 75 75 - select S3C_DEV_I2C1 76 76 - select S3C_DEV_RTC 77 77 - select S3C_DEV_WDT 78 75 select S3C_DEV_HSMMC 79 76 select S3C_DEV_HSMMC1 80 77 select S3C_DEV_HSMMC2 78 78 + select S3C_DEV_I2C1 79 79 + select S3C_DEV_RTC 80 80 + select S3C_DEV_WDT 81 81 + select S5P64X0_SETUP_FB_24BPP 82 82 + select S5P64X0_SETUP_I2C1 83 83 + select S5P64X0_SETUP_SDHCI_GPIO 81 84 select SAMSUNG_DEV_ADC 82 85 select SAMSUNG_DEV_BACKLIGHT 83 86 select SAMSUNG_DEV_PWM 84 87 select SAMSUNG_DEV_TS 85 85 - select S5P64X0_SETUP_FB_24BPP 86 86 - select S5P64X0_SETUP_I2C1 87 87 - select S5P64X0_SETUP_SDHCI_GPIO 88 88 help 89 89 Machine support for the Samsung SMDK6450 90 90

+6 -6

arch/arm/mach-s5pc100/Kconfig

reviewed

··· 60 60 select S3C_DEV_I2C1 61 61 select S3C_DEV_RTC 62 62 select S3C_DEV_WDT 63 63 - select SAMSUNG_DEV_ADC 64 64 - select SAMSUNG_DEV_BACKLIGHT 65 65 - select SAMSUNG_DEV_IDE 66 66 - select SAMSUNG_DEV_KEYPAD 67 67 - select SAMSUNG_DEV_PWM 68 68 - select SAMSUNG_DEV_TS 69 63 select S5PC100_SETUP_FB_24BPP 70 64 select S5PC100_SETUP_I2C1 71 65 select S5PC100_SETUP_IDE ··· 68 74 select S5P_DEV_FIMC0 69 75 select S5P_DEV_FIMC1 70 76 select S5P_DEV_FIMC2 77 77 + select SAMSUNG_DEV_ADC 78 78 + select SAMSUNG_DEV_BACKLIGHT 79 79 + select SAMSUNG_DEV_IDE 80 80 + select SAMSUNG_DEV_KEYPAD 81 81 + select SAMSUNG_DEV_PWM 82 82 + select SAMSUNG_DEV_TS 71 83 help 72 84 Machine support for the Samsung SMDKC100 73 85

+25 -25

arch/arm/mach-s5pv210/Kconfig

reviewed

··· 11 11 12 12 config CPU_S5PV210 13 13 bool 14 14 - select SAMSUNG_DMADEV 15 14 select S5P_EXT_INT 16 15 select S5P_HRT 17 16 select S5P_PM if PM 18 17 select S5P_SLEEP if PM 18 18 + select SAMSUNG_DMADEV 19 19 help 20 20 Enable S5PV210 CPU support 21 21 ··· 76 76 bool "Aquila" 77 77 select CPU_S5PV210 78 78 select S3C_DEV_FB 79 79 - select S5P_DEV_FIMC0 80 80 - select S5P_DEV_FIMC1 81 81 - select S5P_DEV_FIMC2 82 79 select S3C_DEV_HSMMC 83 80 select S3C_DEV_HSMMC1 84 81 select S3C_DEV_HSMMC2 85 85 - select S5P_DEV_ONENAND 86 82 select S5PV210_SETUP_FB_24BPP 87 83 select S5PV210_SETUP_SDHCI 88 84 select S5PV210_SETUP_USB_PHY 85 85 + select S5P_DEV_FIMC0 86 86 + select S5P_DEV_FIMC1 87 87 + select S5P_DEV_FIMC2 88 88 + select S5P_DEV_ONENAND 89 89 help 90 90 Machine support for the Samsung Aquila target based on S5PC110 SoC 91 91 92 92 config MACH_GONI 93 93 bool "GONI" 94 94 select CPU_S5PV210 95 95 - select S5P_GPIO_INT 96 95 select S3C_DEV_FB 97 97 - select S5P_DEV_FIMC0 98 98 - select S5P_DEV_FIMC1 99 99 - select S5P_DEV_FIMC2 100 96 select S3C_DEV_HSMMC 101 97 select S3C_DEV_HSMMC1 102 98 select S3C_DEV_HSMMC2 103 99 select S3C_DEV_I2C1 104 100 select S3C_DEV_I2C2 105 105 - select S5P_DEV_MFC 106 101 select S3C_DEV_USB_HSOTG 107 107 - select S5P_DEV_ONENAND 108 108 - select SAMSUNG_DEV_KEYPAD 109 109 - select S5P_DEV_TV 110 102 select S5PV210_SETUP_FB_24BPP 103 103 + select S5PV210_SETUP_FIMC 111 104 select S5PV210_SETUP_I2C1 112 105 select S5PV210_SETUP_I2C2 113 106 select S5PV210_SETUP_KEYPAD 114 107 select S5PV210_SETUP_SDHCI 115 115 - select S5PV210_SETUP_FIMC 116 108 select S5PV210_SETUP_USB_PHY 109 109 + select S5P_DEV_FIMC0 110 110 + select S5P_DEV_FIMC1 111 111 + select S5P_DEV_FIMC2 112 112 + select S5P_DEV_MFC 113 113 + select S5P_DEV_ONENAND 114 114 + select S5P_DEV_TV 115 115 + select S5P_GPIO_INT 116 116 + select SAMSUNG_DEV_KEYPAD 117 117 help 118 118 Machine support for Samsung GONI board 119 119 S5PC110(MCP) is one of package option of S5PV210 ··· 125 125 select S3C_DEV_I2C2 126 126 select S3C_DEV_RTC 127 127 select S3C_DEV_WDT 128 128 + select S5PV210_SETUP_I2C1 129 129 + select S5PV210_SETUP_I2C2 130 130 + select S5PV210_SETUP_IDE 128 131 select S5P_DEV_FIMC0 129 132 select S5P_DEV_FIMC1 130 133 select S5P_DEV_FIMC2 131 134 select S5P_DEV_MFC 132 135 select SAMSUNG_DEV_IDE 133 133 - select S5PV210_SETUP_I2C1 134 134 - select S5PV210_SETUP_I2C2 135 135 - select S5PV210_SETUP_IDE 136 136 help 137 137 Machine support for Samsung SMDKC110 138 138 S5PC110(MCP) is one of package option of S5PV210 ··· 154 154 select S3C_DEV_RTC 155 155 select S3C_DEV_USB_HSOTG 156 156 select S3C_DEV_WDT 157 157 + select S5PV210_SETUP_FB_24BPP 158 158 + select S5PV210_SETUP_I2C1 159 159 + select S5PV210_SETUP_I2C2 160 160 + select S5PV210_SETUP_IDE 161 161 + select S5PV210_SETUP_KEYPAD 162 162 + select S5PV210_SETUP_SDHCI 163 163 + select S5PV210_SETUP_USB_PHY 157 164 select S5P_DEV_FIMC0 158 165 select S5P_DEV_FIMC1 159 166 select S5P_DEV_FIMC2 ··· 172 165 select SAMSUNG_DEV_KEYPAD 173 166 select SAMSUNG_DEV_PWM 174 167 select SAMSUNG_DEV_TS 175 175 - select S5PV210_SETUP_FB_24BPP 176 176 - select S5PV210_SETUP_I2C1 177 177 - select S5PV210_SETUP_I2C2 178 178 - select S5PV210_SETUP_IDE 179 179 - select S5PV210_SETUP_KEYPAD 180 180 - select S5PV210_SETUP_SDHCI 181 181 - select S5PV210_SETUP_USB_PHY 182 168 help 183 169 Machine support for Samsung SMDKV210 184 170 185 171 config MACH_TORBRECK 186 172 bool "Torbreck" 187 187 - select CPU_S5PV210 188 173 select ARCH_SPARSEMEM_ENABLE 174 174 + select CPU_S5PV210 189 175 select S3C_DEV_HSMMC 190 176 select S3C_DEV_HSMMC1 191 177 select S3C_DEV_HSMMC2

+6 -6

arch/arm/mach-sa1100/Kconfig

reviewed

··· 49 49 bool "Sharp Zaurus SL5500" 50 50 # FIXME: select CPU_FREQ_SA11x0 51 51 select SHARP_LOCOMO 52 52 - select SHARP_SCOOP 53 52 select SHARP_PARAM 53 53 + select SHARP_SCOOP 54 54 help 55 55 Say Y here to support the Sharp Zaurus SL5500 PDAs. 56 56 57 57 config SA1100_H3100 58 58 bool "Compaq iPAQ H3100" 59 59 - select HTC_EGPIO 60 59 select CPU_FREQ_SA1110 60 60 + select HTC_EGPIO 61 61 help 62 62 Say Y here if you intend to run this kernel on the Compaq iPAQ 63 63 H3100 handheld computer. Information about this machine and the ··· 67 67 68 68 config SA1100_H3600 69 69 bool "Compaq iPAQ H3600/H3700" 70 70 - select HTC_EGPIO 71 70 select CPU_FREQ_SA1110 71 71 + select HTC_EGPIO 72 72 help 73 73 Say Y here if you intend to run this kernel on the Compaq iPAQ 74 74 H3600 handheld computer. Information about this machine and the ··· 78 78 79 79 config SA1100_BADGE4 80 80 bool "HP Labs BadgePAD 4" 81 81 - select SA1111 82 81 select CPU_FREQ_SA1100 82 82 + select SA1111 83 83 help 84 84 Say Y here if you want to build a kernel for the HP Laboratories 85 85 BadgePAD 4. 86 86 87 87 config SA1100_JORNADA720 88 88 bool "HP Jornada 720" 89 89 - select SA1111 90 89 # FIXME: select CPU_FREQ_SA11x0 90 90 + select SA1111 91 91 help 92 92 Say Y here if you want to build a kernel for the HP Jornada 720 93 93 handheld computer. See ··· 95 95 96 96 config SA1100_JORNADA720_SSP 97 97 bool "HP Jornada 720 Extended SSP driver" 98 98 - select SA1100_SSP 99 98 depends on SA1100_JORNADA720 99 99 + select SA1100_SSP 100 100 help 101 101 Say Y here if you have a HP Jornada 7xx handheld computer and you 102 102 want to access devices connected to the MCU. Those include the

+22 -22

arch/arm/mach-shmobile/Kconfig

reviewed

··· 4 4 5 5 config ARCH_SH7367 6 6 bool "SH-Mobile G3 (SH7367)" 7 7 + select ARCH_WANT_OPTIONAL_GPIOLIB 7 8 select CPU_V6 8 9 select SH_CLK_CPG 9 9 - select ARCH_WANT_OPTIONAL_GPIOLIB 10 10 11 11 config ARCH_SH7377 12 12 bool "SH-Mobile G4 (SH7377)" 13 13 + select ARCH_WANT_OPTIONAL_GPIOLIB 13 14 select CPU_V7 14 15 select SH_CLK_CPG 15 15 - select ARCH_WANT_OPTIONAL_GPIOLIB 16 16 17 17 config ARCH_SH7372 18 18 bool "SH-Mobile AP4 (SH7372)" 19 19 - select CPU_V7 20 20 - select SH_CLK_CPG 21 19 select ARCH_WANT_OPTIONAL_GPIOLIB 22 20 select ARM_CPU_SUSPEND if PM || CPU_IDLE 21 21 + select CPU_V7 22 22 + select SH_CLK_CPG 23 23 24 24 config ARCH_SH73A0 25 25 bool "SH-Mobile AG5 (R8A73A00)" 26 26 - select CPU_V7 27 27 - select SH_CLK_CPG 28 26 select ARCH_WANT_OPTIONAL_GPIOLIB 29 27 select ARM_GIC 28 28 + select CPU_V7 30 29 select I2C 30 30 + select SH_CLK_CPG 31 31 32 32 config ARCH_R8A7740 33 33 bool "R-Mobile A1 (R8A77400)" 34 34 + select ARCH_WANT_OPTIONAL_GPIOLIB 34 35 select CPU_V7 35 36 select SH_CLK_CPG 36 36 - select ARCH_WANT_OPTIONAL_GPIOLIB 37 37 38 38 config ARCH_R8A7779 39 39 bool "R-Car H1 (R8A77790)" 40 40 + select ARCH_WANT_OPTIONAL_GPIOLIB 41 41 + select ARM_GIC 40 42 select CPU_V7 41 43 select SH_CLK_CPG 42 42 - select ARM_GIC 43 43 - select ARCH_WANT_OPTIONAL_GPIOLIB 44 44 45 45 config ARCH_EMEV2 46 46 bool "Emma Mobile EV2" 47 47 - select CPU_V7 48 48 - select ARM_GIC 49 47 select ARCH_WANT_OPTIONAL_GPIOLIB 48 48 + select ARM_GIC 49 49 + select CPU_V7 50 50 51 51 comment "SH-Mobile Board Type" 52 52 ··· 65 65 bool "AP4EVB board" 66 66 depends on ARCH_SH7372 67 67 select ARCH_REQUIRE_GPIOLIB 68 68 + select REGULATOR_FIXED_VOLTAGE if REGULATOR 68 69 select SH_LCD_MIPI_DSI 69 70 select SND_SOC_AK4642 if SND_SIMPLE_CARD 70 70 - select REGULATOR_FIXED_VOLTAGE if REGULATOR 71 71 72 72 choice 73 73 prompt "AP4EVB LCD panel selection" ··· 84 84 85 85 config MACH_AG5EVM 86 86 bool "AG5EVM board" 87 87 - select ARCH_REQUIRE_GPIOLIB 88 88 - select SH_LCD_MIPI_DSI 89 89 - select REGULATOR_FIXED_VOLTAGE if REGULATOR 90 87 depends on ARCH_SH73A0 88 88 + select ARCH_REQUIRE_GPIOLIB 89 89 + select REGULATOR_FIXED_VOLTAGE if REGULATOR 90 90 + select SH_LCD_MIPI_DSI 91 91 92 92 config MACH_MACKEREL 93 93 bool "mackerel board" 94 94 depends on ARCH_SH7372 95 95 select ARCH_REQUIRE_GPIOLIB 96 96 - select SND_SOC_AK4642 if SND_SIMPLE_CARD 97 96 select REGULATOR_FIXED_VOLTAGE if REGULATOR 97 97 + select SND_SOC_AK4642 if SND_SIMPLE_CARD 98 98 99 99 config MACH_KOTA2 100 100 bool "KOTA2 board" 101 101 + depends on ARCH_SH73A0 101 102 select ARCH_REQUIRE_GPIOLIB 102 103 select REGULATOR_FIXED_VOLTAGE if REGULATOR 103 103 - depends on ARCH_SH73A0 104 104 105 105 config MACH_BONITO 106 106 bool "bonito board" 107 107 + depends on ARCH_R8A7740 107 108 select ARCH_REQUIRE_GPIOLIB 108 109 select REGULATOR_FIXED_VOLTAGE if REGULATOR 109 109 - depends on ARCH_R8A7740 110 110 111 111 config MACH_ARMADILLO800EVA 112 112 bool "Armadillo-800 EVA board" 113 113 depends on ARCH_R8A7740 114 114 select ARCH_REQUIRE_GPIOLIB 115 115 - select USE_OF 116 115 select REGULATOR_FIXED_VOLTAGE if REGULATOR 117 116 select SND_SOC_WM8978 if SND_SIMPLE_CARD 117 117 + select USE_OF 118 118 119 119 config MACH_MARZEN 120 120 bool "MARZEN board" ··· 125 125 config MACH_KZM9D 126 126 bool "KZM9D board" 127 127 depends on ARCH_EMEV2 128 128 - select USE_OF 129 128 select REGULATOR_FIXED_VOLTAGE if REGULATOR 129 129 + select USE_OF 130 130 131 131 config MACH_KZM9G 132 132 bool "KZM-A9-GT board" 133 133 depends on ARCH_SH73A0 134 134 select ARCH_REQUIRE_GPIOLIB 135 135 - select USE_OF 136 136 - select SND_SOC_AK4642 if SND_SIMPLE_CARD 137 135 select REGULATOR_FIXED_VOLTAGE if REGULATOR 136 136 + select SND_SOC_AK4642 if SND_SIMPLE_CARD 137 137 + select USE_OF 138 138 139 139 comment "SH-Mobile System Configuration" 140 140

+16 -16

arch/arm/mach-tegra/Kconfig

reviewed

··· 4 4 5 5 config ARCH_TEGRA_2x_SOC 6 6 bool "Enable support for Tegra20 family" 7 7 - select CPU_V7 8 8 - select ARM_GIC 9 7 select ARCH_REQUIRE_GPIOLIB 10 10 - select PINCTRL 11 11 - select PINCTRL_TEGRA20 12 12 - select USB_ARCH_HAS_EHCI if USB_SUPPORT 13 13 - select USB_ULPI if USB 14 14 - select USB_ULPI_VIEWPORT if USB_SUPPORT 15 8 select ARM_ERRATA_720789 16 9 select ARM_ERRATA_742230 17 10 select ARM_ERRATA_751472 18 11 select ARM_ERRATA_754327 19 12 select ARM_ERRATA_764369 if SMP 13 13 + select ARM_GIC 14 14 + select CPU_FREQ_TABLE if CPU_FREQ 15 15 + select CPU_V7 16 16 + select PINCTRL 17 17 + select PINCTRL_TEGRA20 20 18 select PL310_ERRATA_727915 if CACHE_L2X0 21 19 select PL310_ERRATA_769419 if CACHE_L2X0 22 22 - select CPU_FREQ_TABLE if CPU_FREQ 20 20 + select USB_ARCH_HAS_EHCI if USB_SUPPORT 21 21 + select USB_ULPI if USB 22 22 + select USB_ULPI_VIEWPORT if USB_SUPPORT 23 23 help 24 24 Support for NVIDIA Tegra AP20 and T20 processors, based on the 25 25 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 26 26 27 27 config ARCH_TEGRA_3x_SOC 28 28 bool "Enable support for Tegra30 family" 29 29 - select CPU_V7 30 30 - select ARM_GIC 31 29 select ARCH_REQUIRE_GPIOLIB 32 32 - select PINCTRL 33 33 - select PINCTRL_TEGRA30 34 34 - select USB_ARCH_HAS_EHCI if USB_SUPPORT 35 35 - select USB_ULPI if USB 36 36 - select USB_ULPI_VIEWPORT if USB_SUPPORT 37 30 select ARM_ERRATA_743622 38 31 select ARM_ERRATA_751472 39 32 select ARM_ERRATA_754322 40 33 select ARM_ERRATA_764369 if SMP 41 41 - select PL310_ERRATA_769419 if CACHE_L2X0 34 34 + select ARM_GIC 42 35 select CPU_FREQ_TABLE if CPU_FREQ 36 36 + select CPU_V7 37 37 + select PINCTRL 38 38 + select PINCTRL_TEGRA30 39 39 + select PL310_ERRATA_769419 if CACHE_L2X0 40 40 + select USB_ARCH_HAS_EHCI if USB_SUPPORT 41 41 + select USB_ULPI if USB 42 42 + select USB_ULPI_VIEWPORT if USB_SUPPORT 43 43 help 44 44 Support for NVIDIA Tegra T30 processor family, based on the 45 45 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

+1 -1

arch/arm/mach-u300/Kconfig

reviewed

··· 7 7 config MACH_U300 8 8 bool "U300" 9 9 select PINCTRL 10 10 - select PINCTRL_U300 11 10 select PINCTRL_COH901 11 11 + select PINCTRL_U300 12 12 13 13 comment "ST-Ericsson U300/U335 Feature Selections" 14 14

+8 -8

arch/arm/mach-ux500/Kconfig

reviewed

··· 3 3 config UX500_SOC_COMMON 4 4 bool 5 5 default y 6 6 - select ARM_GIC 7 7 - select HAS_MTU 8 8 - select PL310_ERRATA_753970 if CACHE_PL310 9 6 select ARM_ERRATA_754322 10 7 select ARM_ERRATA_764369 if SMP 8 8 + select ARM_GIC 11 9 select CACHE_L2X0 10 10 + select COMMON_CLK 11 11 + select HAS_MTU 12 12 select PINCTRL 13 13 select PINCTRL_NOMADIK 14 14 - select COMMON_CLK 14 14 + select PL310_ERRATA_753970 if CACHE_PL310 15 15 16 16 config UX500_SOC_DB8500 17 17 bool 18 18 + select CPU_FREQ_TABLE if CPU_FREQ 18 19 select MFD_DB8500_PRCMU 20 20 + select PINCTRL_DB8500 19 21 select REGULATOR 20 22 select REGULATOR_DB8500_PRCMU 21 21 - select CPU_FREQ_TABLE if CPU_FREQ 22 22 - select PINCTRL_DB8500 23 23 24 24 menu "Ux500 target platform (boards)" 25 25 26 26 config MACH_MOP500 27 27 bool "U8500 Development platform, MOP500 versions" 28 28 - select UX500_SOC_DB8500 29 28 select I2C 30 29 select I2C_NOMADIK 31 31 - select SOC_BUS 32 30 select REGULATOR_FIXED_VOLTAGE 31 31 + select SOC_BUS 32 32 + select UX500_SOC_DB8500 33 33 help 34 34 Include support for the MOP500 development platform. 35 35

+2 -2

arch/arm/mach-versatile/Kconfig

reviewed

··· 3 3 4 4 config ARCH_VERSATILE_PB 5 5 bool "Support Versatile Platform Baseboard for ARM926EJ-S" 6 6 + default y 6 7 select CPU_ARM926T 7 8 select MIGHT_HAVE_PCI 8 8 - default y 9 9 help 10 10 Include support for the ARM(R) Versatile Platform Baseboard 11 11 for the ARM926EJ-S. ··· 19 19 20 20 config MACH_VERSATILE_DT 21 21 bool "Support Versatile platform from device tree" 22 22 - select USE_OF 23 22 select CPU_ARM926T 23 23 + select USE_OF 24 24 help 25 25 Include support for the ARM(R) Versatile/PB platform, 26 26 using the device tree for discovery

+54 -54

arch/arm/mm/Kconfig

reviewed

··· 10 10 depends on !MMU 11 11 select CPU_32v4T 12 12 select CPU_ABRT_LV4T 13 13 - select CPU_PABRT_LEGACY 14 13 select CPU_CACHE_V4 14 14 + select CPU_PABRT_LEGACY 15 15 help 16 16 A 32-bit RISC microprocessor based on the ARM7 processor core 17 17 which has no memory control unit and cache. ··· 24 24 bool "Support ARM720T processor" if ARCH_INTEGRATOR 25 25 select CPU_32v4T 26 26 select CPU_ABRT_LV4T 27 27 - select CPU_PABRT_LEGACY 28 27 select CPU_CACHE_V4 29 28 select CPU_CACHE_VIVT 30 30 - select CPU_CP15_MMU 31 29 select CPU_COPY_V4WT if MMU 30 30 + select CPU_CP15_MMU 31 31 + select CPU_PABRT_LEGACY 32 32 select CPU_TLB_V4WT if MMU 33 33 help 34 34 A 32-bit RISC processor with 8kByte Cache, Write Buffer and ··· 43 43 depends on !MMU 44 44 select CPU_32v4T 45 45 select CPU_ABRT_LV4T 46 46 - select CPU_PABRT_LEGACY 47 46 select CPU_CACHE_V3 # although the core is v4t 48 47 select CPU_CP15_MPU 48 48 + select CPU_PABRT_LEGACY 49 49 help 50 50 A 32-bit RISC processor with 8KB cache or 4KB variants, 51 51 write buffer and MPU(Protection Unit) built around ··· 60 60 depends on !MMU 61 61 select CPU_32v4T 62 62 select CPU_ABRT_NOMMU 63 63 - select CPU_PABRT_LEGACY 64 63 select CPU_CACHE_V4 64 64 + select CPU_PABRT_LEGACY 65 65 help 66 66 A 32-bit RISC microprocessor based on the ARM9 processor core 67 67 which has no memory control unit and cache. ··· 74 74 bool "Support ARM920T processor" if ARCH_INTEGRATOR 75 75 select CPU_32v4T 76 76 select CPU_ABRT_EV4T 77 77 - select CPU_PABRT_LEGACY 78 77 select CPU_CACHE_V4WT 79 78 select CPU_CACHE_VIVT 80 80 - select CPU_CP15_MMU 81 79 select CPU_COPY_V4WB if MMU 80 80 + select CPU_CP15_MMU 81 81 + select CPU_PABRT_LEGACY 82 82 select CPU_TLB_V4WBI if MMU 83 83 help 84 84 The ARM920T is licensed to be produced by numerous vendors, ··· 92 92 bool "Support ARM922T processor" if ARCH_INTEGRATOR 93 93 select CPU_32v4T 94 94 select CPU_ABRT_EV4T 95 95 - select CPU_PABRT_LEGACY 96 95 select CPU_CACHE_V4WT 97 96 select CPU_CACHE_VIVT 98 98 - select CPU_CP15_MMU 99 97 select CPU_COPY_V4WB if MMU 98 98 + select CPU_CP15_MMU 99 99 + select CPU_PABRT_LEGACY 100 100 select CPU_TLB_V4WBI if MMU 101 101 help 102 102 The ARM922T is a version of the ARM920T, but with smaller ··· 111 111 bool "Support ARM925T processor" if ARCH_OMAP1 112 112 select CPU_32v4T 113 113 select CPU_ABRT_EV4T 114 114 - select CPU_PABRT_LEGACY 115 114 select CPU_CACHE_V4WT 116 115 select CPU_CACHE_VIVT 117 117 - select CPU_CP15_MMU 118 116 select CPU_COPY_V4WB if MMU 117 117 + select CPU_CP15_MMU 118 118 + select CPU_PABRT_LEGACY 119 119 select CPU_TLB_V4WBI if MMU 120 120 help 121 121 The ARM925T is a mix between the ARM920T and ARM926T, but with ··· 130 130 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 131 131 select CPU_32v5 132 132 select CPU_ABRT_EV5TJ 133 133 - select CPU_PABRT_LEGACY 134 133 select CPU_CACHE_VIVT 135 135 - select CPU_CP15_MMU 136 134 select CPU_COPY_V4WB if MMU 135 135 + select CPU_CP15_MMU 136 136 + select CPU_PABRT_LEGACY 137 137 select CPU_TLB_V4WBI if MMU 138 138 help 139 139 This is a variant of the ARM920. It has slightly different ··· 148 148 bool 149 149 select CPU_32v4 150 150 select CPU_ABRT_EV4 151 151 - select CPU_PABRT_LEGACY 152 152 - select CPU_CACHE_VIVT 153 153 - select CPU_CP15_MMU 154 151 select CPU_CACHE_FA 152 152 + select CPU_CACHE_VIVT 155 153 select CPU_COPY_FA if MMU 154 154 + select CPU_CP15_MMU 155 155 + select CPU_PABRT_LEGACY 156 156 select CPU_TLB_FA if MMU 157 157 help 158 158 The FA526 is a version of the ARMv4 compatible processor with ··· 167 167 depends on !MMU 168 168 select CPU_32v4T 169 169 select CPU_ABRT_NOMMU 170 170 - select CPU_PABRT_LEGACY 171 170 select CPU_CACHE_VIVT 172 171 select CPU_CP15_MPU 172 172 + select CPU_PABRT_LEGACY 173 173 help 174 174 ARM940T is a member of the ARM9TDMI family of general- 175 175 purpose microprocessors with MPU and separate 4KB ··· 185 185 depends on !MMU 186 186 select CPU_32v5 187 187 select CPU_ABRT_NOMMU 188 188 - select CPU_PABRT_LEGACY 189 188 select CPU_CACHE_VIVT 190 189 select CPU_CP15_MPU 190 190 + select CPU_PABRT_LEGACY 191 191 help 192 192 ARM946E-S is a member of the ARM9E-S family of high- 193 193 performance, 32-bit system-on-chip processor solutions. ··· 201 201 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR 202 202 select CPU_32v5 203 203 select CPU_ABRT_EV4T 204 204 - select CPU_PABRT_LEGACY 205 204 select CPU_CACHE_V4WT 206 205 select CPU_CACHE_VIVT 207 207 - select CPU_CP15_MMU 208 206 select CPU_COPY_V4WB if MMU 207 207 + select CPU_CP15_MMU 208 208 + select CPU_PABRT_LEGACY 209 209 select CPU_TLB_V4WBI if MMU 210 210 help 211 211 The ARM1020 is the 32K cached version of the ARM10 processor, ··· 217 217 # ARM1020E - needs validating 218 218 config CPU_ARM1020E 219 219 bool "Support ARM1020E processor" if ARCH_INTEGRATOR 220 220 + depends on n 220 221 select CPU_32v5 221 222 select CPU_ABRT_EV4T 222 222 - select CPU_PABRT_LEGACY 223 223 select CPU_CACHE_V4WT 224 224 select CPU_CACHE_VIVT 225 225 - select CPU_CP15_MMU 226 225 select CPU_COPY_V4WB if MMU 226 226 + select CPU_CP15_MMU 227 227 + select CPU_PABRT_LEGACY 227 228 select CPU_TLB_V4WBI if MMU 228 228 - depends on n 229 229 230 230 # ARM1022E 231 231 config CPU_ARM1022 232 232 bool "Support ARM1022E processor" if ARCH_INTEGRATOR 233 233 select CPU_32v5 234 234 select CPU_ABRT_EV4T 235 235 - select CPU_PABRT_LEGACY 236 235 select CPU_CACHE_VIVT 237 237 - select CPU_CP15_MMU 238 236 select CPU_COPY_V4WB if MMU # can probably do better 237 237 + select CPU_CP15_MMU 238 238 + select CPU_PABRT_LEGACY 239 239 select CPU_TLB_V4WBI if MMU 240 240 help 241 241 The ARM1022E is an implementation of the ARMv5TE architecture ··· 250 250 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR 251 251 select CPU_32v5 252 252 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 253 253 - select CPU_PABRT_LEGACY 254 253 select CPU_CACHE_VIVT 255 255 - select CPU_CP15_MMU 256 254 select CPU_COPY_V4WB if MMU # can probably do better 255 255 + select CPU_CP15_MMU 256 256 + select CPU_PABRT_LEGACY 257 257 select CPU_TLB_V4WBI if MMU 258 258 help 259 259 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture ··· 268 268 select CPU_32v3 if ARCH_RPC 269 269 select CPU_32v4 if !ARCH_RPC 270 270 select CPU_ABRT_EV4 271 271 - select CPU_PABRT_LEGACY 272 271 select CPU_CACHE_V4WB 273 272 select CPU_CACHE_VIVT 274 274 - select CPU_CP15_MMU 275 273 select CPU_COPY_V4WB if MMU 274 274 + select CPU_CP15_MMU 275 275 + select CPU_PABRT_LEGACY 276 276 select CPU_TLB_V4WB if MMU 277 277 help 278 278 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and ··· 288 288 bool 289 289 select CPU_32v4 290 290 select CPU_ABRT_EV4 291 291 - select CPU_PABRT_LEGACY 292 291 select CPU_CACHE_V4WB 293 292 select CPU_CACHE_VIVT 294 293 select CPU_CP15_MMU 294 294 + select CPU_PABRT_LEGACY 295 295 select CPU_TLB_V4WB if MMU 296 296 297 297 # XScale ··· 299 299 bool 300 300 select CPU_32v5 301 301 select CPU_ABRT_EV5T 302 302 - select CPU_PABRT_LEGACY 303 302 select CPU_CACHE_VIVT 304 303 select CPU_CP15_MMU 304 304 + select CPU_PABRT_LEGACY 305 305 select CPU_TLB_V4WBI if MMU 306 306 307 307 # XScale Core Version 3 ··· 309 309 bool 310 310 select CPU_32v5 311 311 select CPU_ABRT_EV5T 312 312 - select CPU_PABRT_LEGACY 313 312 select CPU_CACHE_VIVT 314 313 select CPU_CP15_MMU 314 314 + select CPU_PABRT_LEGACY 315 315 select CPU_TLB_V4WBI if MMU 316 316 select IO_36 317 317 ··· 320 320 bool 321 321 select CPU_32v5 322 322 select CPU_ABRT_EV5T 323 323 - select CPU_PABRT_LEGACY 324 323 select CPU_CACHE_VIVT 325 325 - select CPU_CP15_MMU 326 326 - select CPU_TLB_V4WBI if MMU 327 324 select CPU_COPY_V4WB if MMU 325 325 + select CPU_CP15_MMU 326 326 + select CPU_PABRT_LEGACY 327 327 + select CPU_TLB_V4WBI if MMU 328 328 329 329 # Feroceon 330 330 config CPU_FEROCEON 331 331 bool 332 332 select CPU_32v5 333 333 select CPU_ABRT_EV5T 334 334 - select CPU_PABRT_LEGACY 335 334 select CPU_CACHE_VIVT 336 336 - select CPU_CP15_MMU 337 335 select CPU_COPY_FEROCEON if MMU 336 336 + select CPU_CP15_MMU 337 337 + select CPU_PABRT_LEGACY 338 338 select CPU_TLB_FEROCEON if MMU 339 339 340 340 config CPU_FEROCEON_OLD_ID ··· 349 349 # Marvell PJ4 350 350 config CPU_PJ4 351 351 bool 352 352 - select CPU_V7 353 352 select ARM_THUMBEE 353 353 + select CPU_V7 354 354 355 355 # ARMv6 356 356 config CPU_V6 357 357 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 358 358 select CPU_32v6 359 359 select CPU_ABRT_EV6 360 360 - select CPU_PABRT_V6 361 360 select CPU_CACHE_V6 362 361 select CPU_CACHE_VIPT 362 362 + select CPU_COPY_V6 if MMU 363 363 select CPU_CP15_MMU 364 364 select CPU_HAS_ASID if MMU 365 365 - select CPU_COPY_V6 if MMU 365 365 + select CPU_PABRT_V6 366 366 select CPU_TLB_V6 if MMU 367 367 368 368 # ARMv6k ··· 371 371 select CPU_32v6 372 372 select CPU_32v6K 373 373 select CPU_ABRT_EV6 374 374 - select CPU_PABRT_V6 375 374 select CPU_CACHE_V6 376 375 select CPU_CACHE_VIPT 376 376 + select CPU_COPY_V6 if MMU 377 377 select CPU_CP15_MMU 378 378 select CPU_HAS_ASID if MMU 379 379 - select CPU_COPY_V6 if MMU 379 379 + select CPU_PABRT_V6 380 380 select CPU_TLB_V6 if MMU 381 381 382 382 # ARMv7 ··· 385 385 select CPU_32v6K 386 386 select CPU_32v7 387 387 select CPU_ABRT_EV7 388 388 - select CPU_PABRT_V7 389 388 select CPU_CACHE_V7 390 389 select CPU_CACHE_VIPT 390 390 + select CPU_COPY_V6 if MMU 391 391 select CPU_CP15_MMU 392 392 select CPU_HAS_ASID if MMU 393 393 - select CPU_COPY_V6 if MMU 393 393 + select CPU_PABRT_V7 394 394 select CPU_TLB_V7 if MMU 395 395 396 396 # Figure out what processor architecture version we should be using. 397 397 # This defines the compiler instruction set which depends on the machine type. 398 398 config CPU_32v3 399 399 bool 400 400 - select TLS_REG_EMUL if SMP || !MMU 401 401 - select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 402 400 select CPU_USE_DOMAINS if MMU 401 401 + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 402 402 + select TLS_REG_EMUL if SMP || !MMU 403 403 404 404 config CPU_32v4 405 405 bool 406 406 - select TLS_REG_EMUL if SMP || !MMU 407 407 - select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 408 406 select CPU_USE_DOMAINS if MMU 407 407 + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 408 408 + select TLS_REG_EMUL if SMP || !MMU 409 409 410 410 config CPU_32v4T 411 411 bool 412 412 - select TLS_REG_EMUL if SMP || !MMU 413 413 - select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 414 412 select CPU_USE_DOMAINS if MMU 413 413 + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 414 414 + select TLS_REG_EMUL if SMP || !MMU 415 415 416 416 config CPU_32v5 417 417 bool 418 418 - select TLS_REG_EMUL if SMP || !MMU 419 419 - select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 420 418 select CPU_USE_DOMAINS if MMU 419 419 + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 420 420 + select TLS_REG_EMUL if SMP || !MMU 421 421 422 422 config CPU_32v6 423 423 bool 424 424 - select TLS_REG_EMUL if !CPU_32v6K && !MMU 425 424 select CPU_USE_DOMAINS if CPU_V6 && MMU 425 425 + select TLS_REG_EMUL if !CPU_32v6K && !MMU 426 426 427 427 config CPU_32v6K 428 428 bool ··· 644 644 config SWP_EMULATE 645 645 bool "Emulate SWP/SWPB instructions" 646 646 depends on !CPU_USE_DOMAINS && CPU_V7 647 647 - select HAVE_PROC_CPU if PROC_FS 648 647 default y if SMP 648 648 + select HAVE_PROC_CPU if PROC_FS 649 649 help 650 650 ARMv6 architecture deprecates use of the SWP/SWPB instructions. 651 651 ARMv7 multiprocessing extensions introduce the ability to disable

+2 -2

arch/arm/plat-mxc/Kconfig

reviewed

··· 10 10 11 11 config ARCH_IMX_V4_V5 12 12 bool "i.MX1, i.MX21, i.MX25, i.MX27" 13 13 - select AUTO_ZRELADDR if !ZBOOT_ROM 14 13 select ARM_PATCH_PHYS_VIRT 14 14 + select AUTO_ZRELADDR if !ZBOOT_ROM 15 15 help 16 16 This enables support for systems based on the Freescale i.MX ARMv4 17 17 and ARMv5 SoCs 18 18 19 19 config ARCH_IMX_V6_V7 20 20 bool "i.MX3, i.MX5, i.MX6" 21 21 - select AUTO_ZRELADDR if !ZBOOT_ROM 22 21 select ARM_PATCH_PHYS_VIRT 22 22 + select AUTO_ZRELADDR if !ZBOOT_ROM 23 23 select MIGHT_HAVE_CACHE_L2X0 24 24 help 25 25 This enables support for systems based on the Freescale i.MX3, i.MX5

+1 -1

arch/arm/plat-mxc/devices/Kconfig

reviewed

··· 3 3 default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53 4 4 5 5 config IMX_HAVE_PLATFORM_FLEXCAN 6 6 - select HAVE_CAN_FLEXCAN if CAN 7 6 bool 7 7 + select HAVE_CAN_FLEXCAN if CAN 8 8 9 9 config IMX_HAVE_PLATFORM_FSL_USB2_UDC 10 10 bool

+1 -1

arch/arm/plat-nomadik/Kconfig

reviewed

··· 5 5 config PLAT_NOMADIK 6 6 bool 7 7 depends on ARCH_NOMADIK || ARCH_U8500 8 8 - select CLKSRC_MMIO 9 8 default y 9 9 + select CLKSRC_MMIO 10 10 help 11 11 Common platform code for Nomadik and other ST-Ericsson 12 12 platforms.

+5 -5

arch/arm/plat-omap/Kconfig

reviewed

··· 14 14 select CLKDEV_LOOKUP 15 15 select CLKSRC_MMIO 16 16 select GENERIC_IRQ_CHIP 17 17 - select IRQ_DOMAIN 18 17 select HAVE_IDE 19 19 - select NEED_MACH_MEMORY_H 18 18 + select IRQ_DOMAIN 20 19 select NEED_MACH_IO_H if PCCARD 20 20 + select NEED_MACH_MEMORY_H 21 21 help 22 22 "Systems based on omap7xx, omap15xx or omap16xx" 23 23 ··· 25 25 bool "TI OMAP2/3/4" 26 26 select CLKDEV_LOOKUP 27 27 select GENERIC_IRQ_CHIP 28 28 - select SPARSE_IRQ 29 28 select OMAP_DM_TIMER 30 30 - select USE_OF 31 29 select PROC_DEVICETREE if PROC_FS 30 30 + select SPARSE_IRQ 31 31 + select USE_OF 32 32 help 33 33 "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5" 34 34 ··· 43 43 44 44 config OMAP_DEBUG_LEDS 45 45 def_bool y if NEW_LEDS 46 46 - select LEDS_CLASS 47 46 depends on OMAP_DEBUG_DEVICES 47 47 + select LEDS_CLASS 48 48 49 49 config POWER_AVS_OMAP 50 50 bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"

+1 -1

arch/arm/plat-s3c24xx/Kconfig

reviewed

··· 6 6 bool 7 7 depends on ARCH_S3C24XX 8 8 default y 9 9 - select NO_IOPORT 10 9 select ARCH_REQUIRE_GPIOLIB 10 10 + select NO_IOPORT 11 11 select S3C_DEV_NAND 12 12 help 13 13 Base platform code for any Samsung S3C24XX device

+7 -7

arch/arm/plat-samsung/Kconfig

reviewed

··· 7 7 config PLAT_SAMSUNG 8 8 bool 9 9 depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P 10 10 - select NO_IOPORT 11 11 - select GENERIC_IRQ_CHIP 12 10 default y 11 11 + select GENERIC_IRQ_CHIP 12 12 + select NO_IOPORT 13 13 help 14 14 Base platform code for all Samsung SoC based systems 15 15 ··· 17 17 bool 18 18 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) 19 19 default y 20 20 - select ARM_VIC if !ARCH_EXYNOS 20 20 + select ARCH_REQUIRE_GPIOLIB 21 21 select ARM_GIC if ARCH_EXYNOS 22 22 + select ARM_VIC if !ARCH_EXYNOS 22 23 select GIC_NON_BANKED if ARCH_EXYNOS4 23 24 select NO_IOPORT 24 24 - select ARCH_REQUIRE_GPIOLIB 25 25 + select PLAT_SAMSUNG 25 26 select S3C_GPIO_TRACK 26 27 select S5P_GPIO_DRVSTR 27 27 - select SAMSUNG_GPIOLIB_4BIT 28 28 - select PLAT_SAMSUNG 29 28 select SAMSUNG_CLKSRC 29 29 + select SAMSUNG_GPIOLIB_4BIT 30 30 select SAMSUNG_IRQ_VIC_TIMER 31 31 help 32 32 Base platform code for Samsung's S5P series SoC. ··· 423 423 424 424 config SAMSUNG_DMADEV 425 425 bool 426 426 + select ARM_AMBA 426 427 select DMADEVICES 427 428 select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \ 428 429 CPU_S5P6450 || CPU_S5P6440) 429 429 - select ARM_AMBA 430 430 help 431 431 Use DMA device engine for PL330 DMAC. 432 432

+2 -2

arch/arm/plat-spear/Kconfig

reviewed

··· 12 12 bool "ST SPEAr13xx with Device Tree" 13 13 select ARM_GIC 14 14 select CPU_V7 15 15 - select USE_OF 16 15 select HAVE_SMP 17 16 select MIGHT_HAVE_CACHE_L2X0 18 17 select PINCTRL 18 18 + select USE_OF 19 19 help 20 20 Supports for ARM's SPEAR13XX family 21 21 ··· 23 23 bool "ST SPEAr3xx with Device Tree" 24 24 select ARM_VIC 25 25 select CPU_ARM926T 26 26 - select USE_OF 27 26 select PINCTRL 27 27 + select USE_OF 28 28 help 29 29 Supports for ARM's SPEAR3XX family 30 30