crypto: hisilicon/qm - mask axi error before memory init

+66 -34

drivers/crypto/hisilicon/hpre/hpre_main.c

··· 39 39 #define HPRE_HAC_RAS_NFE_ENB 0x301414 40 40 #define HPRE_HAC_RAS_FE_ENB 0x301418 41 41 #define HPRE_HAC_INT_SET 0x301500 42 + #define HPRE_AXI_ERROR_MASK GENMASK(21, 10) 42 43 #define HPRE_RNG_TIMEOUT_NUM 0x301A34 43 44 #define HPRE_CORE_INT_ENABLE 0 44 45 #define HPRE_RDCHN_INI_ST 0x301a00 ··· 799 798 val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 800 799 if (enable) { 801 800 val1 |= HPRE_AM_OOO_SHUTDOWN_ENABLE; 802 - val2 = hisi_qm_get_hw_info(qm, hpre_basic_info, 803 - HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 801 + val2 = qm->err_info.dev_err.shutdown_mask; 804 802 } else { 805 803 val1 &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE; 806 804 val2 = 0x0; ··· 813 813 814 814 static void hpre_hw_error_disable(struct hisi_qm *qm) 815 815 { 816 - u32 ce, nfe; 817 - 818 - ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 819 - nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 816 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 817 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 820 818 821 819 /* disable hpre hw error interrupts */ 822 - writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_INT_MASK); 820 + writel(err_mask, qm->io_base + HPRE_INT_MASK); 823 821 /* disable HPRE block master OOO when nfe occurs on Kunpeng930 */ 824 822 hpre_master_ooo_ctrl(qm, false); 825 823 } 826 824 827 825 static void hpre_hw_error_enable(struct hisi_qm *qm) 828 826 { 829 - u32 ce, nfe, err_en; 830 - 831 - ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 832 - nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 827 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 828 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 833 829 834 830 /* clear HPRE hw error source if having */ 835 - writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_HAC_SOURCE_INT); 831 + writel(err_mask, qm->io_base + HPRE_HAC_SOURCE_INT); 836 832 837 833 /* configure error type */ 838 - writel(ce, qm->io_base + HPRE_RAS_CE_ENB); 839 - writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB); 840 - writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 834 + writel(dev_err->ce, qm->io_base + HPRE_RAS_CE_ENB); 835 + writel(dev_err->nfe, qm->io_base + HPRE_RAS_NFE_ENB); 836 + writel(dev_err->fe, qm->io_base + HPRE_RAS_FE_ENB); 841 837 842 838 /* enable HPRE block master OOO when nfe occurs on Kunpeng930 */ 843 839 hpre_master_ooo_ctrl(qm, true); 844 840 845 841 /* enable hpre hw error interrupts */ 846 - err_en = ce | nfe | HPRE_HAC_RAS_FE_ENABLE; 847 - writel(~err_en, qm->io_base + HPRE_INT_MASK); 842 + writel(~err_mask, qm->io_base + HPRE_INT_MASK); 848 843 } 849 844 850 845 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) ··· 1394 1399 1395 1400 static void hpre_disable_error_report(struct hisi_qm *qm, u32 err_type) 1396 1401 { 1397 - u32 nfe_mask; 1402 + u32 nfe_mask = qm->err_info.dev_err.nfe; 1398 1403 1399 - nfe_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 1400 1404 writel(nfe_mask & (~err_type), qm->io_base + HPRE_RAS_NFE_ENB); 1401 1405 } 1402 1406 ··· 1416 1422 1417 1423 err_status = hpre_get_hw_err_status(qm); 1418 1424 if (err_status) { 1419 - if (err_status & qm->err_info.ecc_2bits_mask) 1425 + if (err_status & qm->err_info.dev_err.ecc_2bits_mask) 1420 1426 qm->err_status.is_dev_ecc_mbit = true; 1421 1427 hpre_log_hw_error(qm, err_status); 1422 1428 1423 - if (err_status & qm->err_info.dev_reset_mask) { 1429 + if (err_status & qm->err_info.dev_err.reset_mask) { 1424 1430 /* Disable the same error reporting until device is recovered. */ 1425 1431 hpre_disable_error_report(qm, err_status); 1426 1432 return ACC_ERR_NEED_RESET; ··· 1436 1442 u32 err_status; 1437 1443 1438 1444 err_status = hpre_get_hw_err_status(qm); 1439 - if (err_status & qm->err_info.dev_shutdown_mask) 1445 + if (err_status & qm->err_info.dev_err.shutdown_mask) 1440 1446 return true; 1441 1447 1442 1448 return false; 1443 1449 } 1444 1450 1451 + static void hpre_disable_axi_error(struct hisi_qm *qm) 1452 + { 1453 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 1454 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 1455 + u32 val; 1456 + 1457 + val = ~(err_mask & (~HPRE_AXI_ERROR_MASK)); 1458 + writel(val, qm->io_base + HPRE_INT_MASK); 1459 + 1460 + if (qm->ver > QM_HW_V2) 1461 + writel(dev_err->shutdown_mask & (~HPRE_AXI_ERROR_MASK), 1462 + qm->io_base + HPRE_OOO_SHUTDOWN_SEL); 1463 + } 1464 + 1465 + static void hpre_enable_axi_error(struct hisi_qm *qm) 1466 + { 1467 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 1468 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 1469 + 1470 + /* clear axi error source */ 1471 + writel(HPRE_AXI_ERROR_MASK, qm->io_base + HPRE_HAC_SOURCE_INT); 1472 + 1473 + writel(~err_mask, qm->io_base + HPRE_INT_MASK); 1474 + 1475 + if (qm->ver > QM_HW_V2) 1476 + writel(dev_err->shutdown_mask, qm->io_base + HPRE_OOO_SHUTDOWN_SEL); 1477 + } 1478 + 1445 1479 static void hpre_err_info_init(struct hisi_qm *qm) 1446 1480 { 1447 1481 struct hisi_qm_err_info *err_info = &qm->err_info; 1482 + struct hisi_qm_err_mask *qm_err = &err_info->qm_err; 1483 + struct hisi_qm_err_mask *dev_err = &err_info->dev_err; 1448 1484 1449 - err_info->fe = HPRE_HAC_RAS_FE_ENABLE; 1450 - err_info->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver); 1451 - err_info->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver); 1452 - err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | HPRE_OOO_ECC_2BIT_ERR; 1453 - err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1454 - HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1455 - err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1456 - HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1457 - err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1458 - HPRE_QM_RESET_MASK_CAP, qm->cap_ver); 1459 - err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1460 - HPRE_RESET_MASK_CAP, qm->cap_ver); 1485 + qm_err->fe = HPRE_HAC_RAS_FE_ENABLE; 1486 + qm_err->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver); 1487 + qm_err->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver); 1488 + qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1489 + HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1490 + qm_err->reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1491 + HPRE_QM_RESET_MASK_CAP, qm->cap_ver); 1492 + qm_err->ecc_2bits_mask = QM_ECC_MBIT; 1493 + 1494 + dev_err->fe = HPRE_HAC_RAS_FE_ENABLE; 1495 + dev_err->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 1496 + dev_err->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 1497 + dev_err->shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1498 + HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1499 + dev_err->reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1500 + HPRE_RESET_MASK_CAP, qm->cap_ver); 1501 + dev_err->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | HPRE_OOO_ECC_2BIT_ERR; 1502 + 1461 1503 err_info->msi_wr_port = HPRE_WR_MSI_PORT; 1462 1504 err_info->acpi_rst = "HRST"; 1463 1505 } ··· 1511 1481 .err_info_init = hpre_err_info_init, 1512 1482 .get_err_result = hpre_get_err_result, 1513 1483 .dev_is_abnormal = hpre_dev_is_abnormal, 1484 + .disable_axi_error = hpre_disable_axi_error, 1485 + .enable_axi_error = hpre_enable_axi_error, 1514 1486 }; 1515 1487 1516 1488 static int hpre_pf_probe_init(struct hpre *hpre)

+47 -19

drivers/crypto/hisilicon/qm.c

··· 147 147 #define QM_RAS_CE_TIMES_PER_IRQ 1 148 148 #define QM_OOO_SHUTDOWN_SEL 0x1040f8 149 149 #define QM_AXI_RRESP_ERR BIT(0) 150 - #define QM_ECC_MBIT BIT(2) 151 150 #define QM_DB_TIMEOUT BIT(10) 152 151 #define QM_OF_FIFO_OF BIT(11) 152 + #define QM_RAS_AXI_ERROR (BIT(0) | BIT(1) | BIT(12)) 153 153 154 154 #define QM_RESET_WAIT_TIMEOUT 400 155 155 #define QM_PEH_VENDOR_ID 0x1000d8 ··· 165 165 #define ACC_MASTER_TRANS_RETURN 0x300150 166 166 #define ACC_MASTER_GLOBAL_CTRL 0x300000 167 167 #define ACC_AM_CFG_PORT_WR_EN 0x30001c 168 - #define QM_RAS_NFE_MBIT_DISABLE ~QM_ECC_MBIT 169 168 #define ACC_AM_ROB_ECC_INT_STS 0x300104 170 169 #define ACC_ROB_ECC_ERR_MULTPL BIT(1) 171 170 #define QM_MSI_CAP_ENABLE BIT(16) ··· 521 522 return false; 522 523 523 524 err_status = qm_get_hw_error_status(pf_qm); 524 - if (err_status & pf_qm->err_info.qm_shutdown_mask) 525 + if (err_status & pf_qm->err_info.qm_err.shutdown_mask) 525 526 return true; 526 527 527 528 if (pf_qm->err_ini->dev_is_abnormal) ··· 1396 1397 1397 1398 static void qm_hw_error_cfg(struct hisi_qm *qm) 1398 1399 { 1399 - struct hisi_qm_err_info *err_info = &qm->err_info; 1400 + struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err; 1400 1401 1401 - qm->error_mask = err_info->nfe | err_info->ce | err_info->fe; 1402 + qm->error_mask = qm_err->nfe | qm_err->ce | qm_err->fe; 1402 1403 /* clear QM hw residual error source */ 1403 1404 writel(qm->error_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE); 1404 1405 1405 1406 /* configure error type */ 1406 - writel(err_info->ce, qm->io_base + QM_RAS_CE_ENABLE); 1407 + writel(qm_err->ce, qm->io_base + QM_RAS_CE_ENABLE); 1407 1408 writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD); 1408 - writel(err_info->nfe, qm->io_base + QM_RAS_NFE_ENABLE); 1409 - writel(err_info->fe, qm->io_base + QM_RAS_FE_ENABLE); 1409 + writel(qm_err->nfe, qm->io_base + QM_RAS_NFE_ENABLE); 1410 + writel(qm_err->fe, qm->io_base + QM_RAS_FE_ENABLE); 1410 1411 } 1411 1412 1412 1413 static void qm_hw_error_init_v2(struct hisi_qm *qm) ··· 1435 1436 qm_hw_error_cfg(qm); 1436 1437 1437 1438 /* enable close master ooo when hardware error happened */ 1438 - writel(qm->err_info.qm_shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL); 1439 + writel(qm->err_info.qm_err.shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL); 1439 1440 1440 1441 irq_unmask = ~qm->error_mask; 1441 1442 irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK); ··· 1497 1498 1498 1499 static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm) 1499 1500 { 1501 + struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err; 1500 1502 u32 error_status; 1501 1503 1502 1504 error_status = qm_get_hw_error_status(qm); ··· 1506 1506 qm->err_status.is_qm_ecc_mbit = true; 1507 1507 1508 1508 qm_log_hw_error(qm, error_status); 1509 - if (error_status & qm->err_info.qm_reset_mask) { 1509 + if (error_status & qm_err->reset_mask) { 1510 1510 /* Disable the same error reporting until device is recovered. */ 1511 - writel(qm->err_info.nfe & (~error_status), 1512 - qm->io_base + QM_RAS_NFE_ENABLE); 1511 + writel(qm_err->nfe & (~error_status), qm->io_base + QM_RAS_NFE_ENABLE); 1513 1512 return ACC_ERR_NEED_RESET; 1514 1513 } 1515 1514 1516 1515 /* Clear error source if not need reset. */ 1517 1516 writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE); 1518 - writel(qm->err_info.nfe, qm->io_base + QM_RAS_NFE_ENABLE); 1519 - writel(qm->err_info.ce, qm->io_base + QM_RAS_CE_ENABLE); 1517 + writel(qm_err->nfe, qm->io_base + QM_RAS_NFE_ENABLE); 1518 + writel(qm_err->ce, qm->io_base + QM_RAS_CE_ENABLE); 1520 1519 } 1521 1520 1522 1521 return ACC_ERR_RECOVERED; ··· 4226 4227 !qm->err_status.is_qm_ecc_mbit && 4227 4228 !qm->err_ini->close_axi_master_ooo) { 4228 4229 nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE); 4229 - writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE, 4230 + writel(nfe_enb & ~qm->err_info.qm_err.ecc_2bits_mask, 4230 4231 qm->io_base + QM_RAS_NFE_ENABLE); 4231 - writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET); 4232 + writel(qm->err_info.qm_err.ecc_2bits_mask, qm->io_base + QM_ABNORMAL_INT_SET); 4232 4233 } 4233 4234 } 4234 4235 ··· 4507 4508 qm->io_base + ACC_AM_CFG_PORT_WR_EN); 4508 4509 4509 4510 /* clear dev ecc 2bit error source if having */ 4510 - value = qm_get_dev_err_status(qm) & qm->err_info.ecc_2bits_mask; 4511 + value = qm_get_dev_err_status(qm) & qm->err_info.dev_err.ecc_2bits_mask; 4511 4512 if (value && qm->err_ini->clear_dev_hw_err_status) 4512 4513 qm->err_ini->clear_dev_hw_err_status(qm, value); 4513 4514 4514 4515 /* clear QM ecc mbit error source */ 4515 - writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SOURCE); 4516 + writel(qm->err_info.qm_err.ecc_2bits_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE); 4516 4517 4517 4518 /* clear AM Reorder Buffer ecc mbit source */ 4518 4519 writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS); ··· 4537 4538 clear_flags: 4538 4539 qm->err_status.is_qm_ecc_mbit = false; 4539 4540 qm->err_status.is_dev_ecc_mbit = false; 4541 + } 4542 + 4543 + static void qm_disable_axi_error(struct hisi_qm *qm) 4544 + { 4545 + struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err; 4546 + u32 val; 4547 + 4548 + val = ~(qm->error_mask & (~QM_RAS_AXI_ERROR)); 4549 + writel(val, qm->io_base + QM_ABNORMAL_INT_MASK); 4550 + if (qm->ver > QM_HW_V2) 4551 + writel(qm_err->shutdown_mask & (~QM_RAS_AXI_ERROR), 4552 + qm->io_base + QM_OOO_SHUTDOWN_SEL); 4553 + 4554 + if (qm->err_ini->disable_axi_error) 4555 + qm->err_ini->disable_axi_error(qm); 4556 + } 4557 + 4558 + static void qm_enable_axi_error(struct hisi_qm *qm) 4559 + { 4560 + /* clear axi error source */ 4561 + writel(QM_RAS_AXI_ERROR, qm->io_base + QM_ABNORMAL_INT_SOURCE); 4562 + 4563 + writel(~qm->error_mask, qm->io_base + QM_ABNORMAL_INT_MASK); 4564 + if (qm->ver > QM_HW_V2) 4565 + writel(qm->err_info.qm_err.shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL); 4566 + 4567 + if (qm->err_ini->enable_axi_error) 4568 + qm->err_ini->enable_axi_error(qm); 4540 4569 } 4541 4570 4542 4571 static int qm_controller_reset_done(struct hisi_qm *qm) ··· 4600 4573 4601 4574 qm_restart_prepare(qm); 4602 4575 hisi_qm_dev_err_init(qm); 4576 + qm_disable_axi_error(qm); 4603 4577 if (qm->err_ini->open_axi_master_ooo) 4604 4578 qm->err_ini->open_axi_master_ooo(qm); 4605 4579 ··· 4623 4595 ret = qm_wait_vf_prepare_finish(qm); 4624 4596 if (ret) 4625 4597 pci_err(pdev, "failed to start by vfs in soft reset!\n"); 4626 - 4598 + qm_enable_axi_error(qm); 4627 4599 qm_cmd_init(qm); 4628 4600 qm_restart_done(qm); 4629 4601

+62 -28

drivers/crypto/hisilicon/sec2/sec_main.c

··· 47 47 #define SEC_RAS_FE_ENB_MSK 0x0 48 48 #define SEC_OOO_SHUTDOWN_SEL 0x301014 49 49 #define SEC_RAS_DISABLE 0x0 50 + #define SEC_AXI_ERROR_MASK (BIT(0) | BIT(1)) 51 + 50 52 #define SEC_MEM_START_INIT_REG 0x301100 51 53 #define SEC_MEM_INIT_DONE_REG 0x301104 52 54 ··· 715 713 val1 = readl(qm->io_base + SEC_CONTROL_REG); 716 714 if (enable) { 717 715 val1 |= SEC_AXI_SHUTDOWN_ENABLE; 718 - val2 = hisi_qm_get_hw_info(qm, sec_basic_info, 719 - SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 716 + val2 = qm->err_info.dev_err.shutdown_mask; 720 717 } else { 721 718 val1 &= SEC_AXI_SHUTDOWN_DISABLE; 722 719 val2 = 0x0; ··· 729 728 730 729 static void sec_hw_error_enable(struct hisi_qm *qm) 731 730 { 732 - u32 ce, nfe; 731 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 732 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 733 733 734 734 if (qm->ver == QM_HW_V1) { 735 735 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); ··· 738 736 return; 739 737 } 740 738 741 - ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver); 742 - nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); 743 - 744 739 /* clear SEC hw error source if having */ 745 - writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE); 740 + writel(err_mask, qm->io_base + SEC_CORE_INT_SOURCE); 746 741 747 742 /* enable RAS int */ 748 - writel(ce, qm->io_base + SEC_RAS_CE_REG); 749 - writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); 750 - writel(nfe, qm->io_base + SEC_RAS_NFE_REG); 743 + writel(dev_err->ce, qm->io_base + SEC_RAS_CE_REG); 744 + writel(dev_err->fe, qm->io_base + SEC_RAS_FE_REG); 745 + writel(dev_err->nfe, qm->io_base + SEC_RAS_NFE_REG); 751 746 752 747 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */ 753 748 sec_master_ooo_ctrl(qm, true); 754 749 755 750 /* enable SEC hw error interrupts */ 756 - writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK); 751 + writel(err_mask, qm->io_base + SEC_CORE_INT_MASK); 757 752 } 758 753 759 754 static void sec_hw_error_disable(struct hisi_qm *qm) ··· 1107 1108 1108 1109 static void sec_disable_error_report(struct hisi_qm *qm, u32 err_type) 1109 1110 { 1110 - u32 nfe_mask; 1111 + u32 nfe_mask = qm->err_info.dev_err.nfe; 1111 1112 1112 - nfe_mask = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); 1113 1113 writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG); 1114 1114 } 1115 1115 ··· 1127 1129 1128 1130 err_status = sec_get_hw_err_status(qm); 1129 1131 if (err_status) { 1130 - if (err_status & qm->err_info.ecc_2bits_mask) 1132 + if (err_status & qm->err_info.dev_err.ecc_2bits_mask) 1131 1133 qm->err_status.is_dev_ecc_mbit = true; 1132 1134 sec_log_hw_error(qm, err_status); 1133 1135 1134 - if (err_status & qm->err_info.dev_reset_mask) { 1136 + if (err_status & qm->err_info.dev_err.reset_mask) { 1135 1137 /* Disable the same error reporting until device is recovered. */ 1136 1138 sec_disable_error_report(qm, err_status); 1137 1139 return ACC_ERR_NEED_RESET; ··· 1147 1149 u32 err_status; 1148 1150 1149 1151 err_status = sec_get_hw_err_status(qm); 1150 - if (err_status & qm->err_info.dev_shutdown_mask) 1152 + if (err_status & qm->err_info.dev_err.shutdown_mask) 1151 1153 return true; 1152 1154 1153 1155 return false; 1154 1156 } 1155 1157 1158 + static void sec_disable_axi_error(struct hisi_qm *qm) 1159 + { 1160 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 1161 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 1162 + 1163 + writel(err_mask & ~SEC_AXI_ERROR_MASK, qm->io_base + SEC_CORE_INT_MASK); 1164 + 1165 + if (qm->ver > QM_HW_V2) 1166 + writel(dev_err->shutdown_mask & (~SEC_AXI_ERROR_MASK), 1167 + qm->io_base + SEC_OOO_SHUTDOWN_SEL); 1168 + } 1169 + 1170 + static void sec_enable_axi_error(struct hisi_qm *qm) 1171 + { 1172 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 1173 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 1174 + 1175 + /* clear axi error source */ 1176 + writel(SEC_AXI_ERROR_MASK, qm->io_base + SEC_CORE_INT_SOURCE); 1177 + 1178 + writel(err_mask, qm->io_base + SEC_CORE_INT_MASK); 1179 + 1180 + if (qm->ver > QM_HW_V2) 1181 + writel(dev_err->shutdown_mask, qm->io_base + SEC_OOO_SHUTDOWN_SEL); 1182 + } 1183 + 1156 1184 static void sec_err_info_init(struct hisi_qm *qm) 1157 1185 { 1158 1186 struct hisi_qm_err_info *err_info = &qm->err_info; 1187 + struct hisi_qm_err_mask *qm_err = &err_info->qm_err; 1188 + struct hisi_qm_err_mask *dev_err = &err_info->dev_err; 1159 1189 1160 - err_info->fe = SEC_RAS_FE_ENB_MSK; 1161 - err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver); 1162 - err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver); 1163 - err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC; 1164 - err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1165 - SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1166 - err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1167 - SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1168 - err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1169 - SEC_QM_RESET_MASK_CAP, qm->cap_ver); 1170 - err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1171 - SEC_RESET_MASK_CAP, qm->cap_ver); 1190 + qm_err->fe = SEC_RAS_FE_ENB_MSK; 1191 + qm_err->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver); 1192 + qm_err->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver); 1193 + qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1194 + SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1195 + qm_err->reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1196 + SEC_QM_RESET_MASK_CAP, qm->cap_ver); 1197 + qm_err->ecc_2bits_mask = QM_ECC_MBIT; 1198 + 1199 + dev_err->fe = SEC_RAS_FE_ENB_MSK; 1200 + dev_err->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver); 1201 + dev_err->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); 1202 + dev_err->shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1203 + SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1204 + dev_err->reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1205 + SEC_RESET_MASK_CAP, qm->cap_ver); 1206 + dev_err->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC; 1207 + 1172 1208 err_info->msi_wr_port = BIT(0); 1173 1209 err_info->acpi_rst = "SRST"; 1174 1210 } ··· 1220 1188 .err_info_init = sec_err_info_init, 1221 1189 .get_err_result = sec_get_err_result, 1222 1190 .dev_is_abnormal = sec_dev_is_abnormal, 1191 + .disable_axi_error = sec_disable_axi_error, 1192 + .enable_axi_error = sec_enable_axi_error, 1223 1193 }; 1224 1194 1225 1195 static int sec_pf_probe_init(struct sec_dev *sec)

+68 -34

drivers/crypto/hisilicon/zip/zip_main.c

··· 65 65 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 66 66 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 67 67 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 68 + #define HZIP_AXI_ERROR_MASK (BIT(2) | BIT(3)) 68 69 #define HZIP_SQE_SIZE 128 69 70 #define HZIP_PF_DEF_Q_NUM 64 70 71 #define HZIP_PF_DEF_Q_BASE 0 ··· 663 662 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 664 663 if (enable) { 665 664 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 666 - val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 667 - ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 665 + val2 = qm->err_info.dev_err.shutdown_mask; 668 666 } else { 669 667 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 670 668 val2 = 0x0; ··· 677 677 678 678 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 679 679 { 680 - u32 nfe, ce; 680 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 681 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 681 682 682 683 if (qm->ver == QM_HW_V1) { 683 684 writel(HZIP_CORE_INT_MASK_ALL, ··· 687 686 return; 688 687 } 689 688 690 - nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 691 - ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 692 - 693 689 /* clear ZIP hw error source if having */ 694 - writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 690 + writel(err_mask, qm->io_base + HZIP_CORE_INT_SOURCE); 695 691 696 692 /* configure error type */ 697 - writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 698 - writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 699 - writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 693 + writel(dev_err->ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 694 + writel(dev_err->fe, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 695 + writel(dev_err->nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 700 696 701 697 hisi_zip_master_ooo_ctrl(qm, true); 702 698 703 699 /* enable ZIP hw error interrupts */ 704 - writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 700 + writel(~err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG); 705 701 706 702 hisi_dae_hw_error_enable(qm); 707 703 } 708 704 709 705 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 710 706 { 711 - u32 nfe, ce; 707 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 708 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 712 709 713 710 /* disable ZIP hw error interrupts */ 714 - nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 715 - ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 716 - writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); 711 + writel(err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG); 717 712 718 713 hisi_zip_master_ooo_ctrl(qm, false); 719 714 ··· 1183 1186 1184 1187 static void hisi_zip_disable_error_report(struct hisi_qm *qm, u32 err_type) 1185 1188 { 1186 - u32 nfe_mask; 1189 + u32 nfe_mask = qm->err_info.dev_err.nfe; 1187 1190 1188 - nfe_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1189 1191 writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1190 1192 } 1191 1193 ··· 1226 1230 /* Get device hardware new error status */ 1227 1231 err_status = hisi_zip_get_hw_err_status(qm); 1228 1232 if (err_status) { 1229 - if (err_status & qm->err_info.ecc_2bits_mask) 1233 + if (err_status & qm->err_info.dev_err.ecc_2bits_mask) 1230 1234 qm->err_status.is_dev_ecc_mbit = true; 1231 1235 hisi_zip_log_hw_error(qm, err_status); 1232 1236 1233 - if (err_status & qm->err_info.dev_reset_mask) { 1237 + if (err_status & qm->err_info.dev_err.reset_mask) { 1234 1238 /* Disable the same error reporting until device is recovered. */ 1235 1239 hisi_zip_disable_error_report(qm, err_status); 1236 - return ACC_ERR_NEED_RESET; 1240 + zip_result = ACC_ERR_NEED_RESET; 1237 1241 } else { 1238 1242 hisi_zip_clear_hw_err_status(qm, err_status); 1239 1243 } ··· 1251 1255 u32 err_status; 1252 1256 1253 1257 err_status = hisi_zip_get_hw_err_status(qm); 1254 - if (err_status & qm->err_info.dev_shutdown_mask) 1258 + if (err_status & qm->err_info.dev_err.shutdown_mask) 1255 1259 return true; 1256 1260 1257 1261 return hisi_dae_dev_is_abnormal(qm); ··· 1262 1266 return hisi_dae_close_axi_master_ooo(qm); 1263 1267 } 1264 1268 1269 + static void hisi_zip_disable_axi_error(struct hisi_qm *qm) 1270 + { 1271 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 1272 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 1273 + u32 val; 1274 + 1275 + val = ~(err_mask & (~HZIP_AXI_ERROR_MASK)); 1276 + writel(val, qm->io_base + HZIP_CORE_INT_MASK_REG); 1277 + 1278 + if (qm->ver > QM_HW_V2) 1279 + writel(dev_err->shutdown_mask & (~HZIP_AXI_ERROR_MASK), 1280 + qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 1281 + } 1282 + 1283 + static void hisi_zip_enable_axi_error(struct hisi_qm *qm) 1284 + { 1285 + struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 1286 + u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 1287 + 1288 + /* clear axi error source */ 1289 + writel(HZIP_AXI_ERROR_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 1290 + 1291 + writel(~err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG); 1292 + 1293 + if (qm->ver > QM_HW_V2) 1294 + writel(dev_err->shutdown_mask, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 1295 + } 1296 + 1265 1297 static void hisi_zip_err_info_init(struct hisi_qm *qm) 1266 1298 { 1267 1299 struct hisi_qm_err_info *err_info = &qm->err_info; 1300 + struct hisi_qm_err_mask *qm_err = &err_info->qm_err; 1301 + struct hisi_qm_err_mask *dev_err = &err_info->dev_err; 1268 1302 1269 - err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1270 - err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1271 - err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1272 - ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1273 - err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1274 - err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1275 - ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1276 - err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1277 - ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1278 - err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1279 - ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1280 - err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1281 - ZIP_RESET_MASK_CAP, qm->cap_ver); 1303 + qm_err->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1304 + qm_err->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1305 + qm_err->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1306 + ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1307 + qm_err->ecc_2bits_mask = QM_ECC_MBIT; 1308 + qm_err->reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1309 + ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1310 + qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1311 + ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1312 + 1313 + dev_err->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1314 + dev_err->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 1315 + dev_err->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1316 + dev_err->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1317 + dev_err->shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1318 + ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1319 + dev_err->reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1320 + ZIP_RESET_MASK_CAP, qm->cap_ver); 1321 + 1282 1322 err_info->msi_wr_port = HZIP_WR_PORT; 1283 1323 err_info->acpi_rst = "ZRST"; 1284 1324 } ··· 1334 1302 .get_err_result = hisi_zip_get_err_result, 1335 1303 .set_priv_status = hisi_zip_set_priv_status, 1336 1304 .dev_is_abnormal = hisi_zip_dev_is_abnormal, 1305 + .disable_axi_error = hisi_zip_disable_axi_error, 1306 + .enable_axi_error = hisi_zip_enable_axi_error, 1337 1307 }; 1338 1308 1339 1309 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)

+14 -7

include/linux/hisi_acc_qm.h

··· 104 104 #define UACCE_MODE_SVA 1 /* use uacce sva mode */ 105 105 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce" 106 106 107 + #define QM_ECC_MBIT BIT(2) 108 + 107 109 enum qm_stop_reason { 108 110 QM_NORMAL, 109 111 QM_SOFT_RESET, ··· 242 240 ACC_ERR_RECOVERED, 243 241 }; 244 242 245 - struct hisi_qm_err_info { 246 - char *acpi_rst; 247 - u32 msi_wr_port; 243 + struct hisi_qm_err_mask { 248 244 u32 ecc_2bits_mask; 249 - u32 qm_shutdown_mask; 250 - u32 dev_shutdown_mask; 251 - u32 qm_reset_mask; 252 - u32 dev_reset_mask; 245 + u32 shutdown_mask; 246 + u32 reset_mask; 253 247 u32 ce; 254 248 u32 nfe; 255 249 u32 fe; 250 + }; 251 + 252 + struct hisi_qm_err_info { 253 + char *acpi_rst; 254 + u32 msi_wr_port; 255 + struct hisi_qm_err_mask qm_err; 256 + struct hisi_qm_err_mask dev_err; 256 257 }; 257 258 258 259 struct hisi_qm_err_status { ··· 278 273 enum acc_err_result (*get_err_result)(struct hisi_qm *qm); 279 274 bool (*dev_is_abnormal)(struct hisi_qm *qm); 280 275 int (*set_priv_status)(struct hisi_qm *qm); 276 + void (*disable_axi_error)(struct hisi_qm *qm); 277 + void (*enable_axi_error)(struct hisi_qm *qm); 281 278 }; 282 279 283 280 struct hisi_qm_cap_info {

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