Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
platform/x86: amd-pmc: Add support for AMD Spill to DRAM STB feature
Spill to DRAM functionality is a feature that allows STB (Smart Trace
Buffer) to spill data from SRAM into DRAM on some future AMD ASICs. The
size allocated for STB is more than the earlier SoC's which helps to
collect more tracing and telemetry data.
Co-developed-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20220204122527.3873552-1-Sanket.Goswami@amd.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
authored by
Sanket Goswami
and committed by
Hans de Goede
3d7d407d
dbce412a
+130
-14
+130
-14
drivers/platform/x86/amd-pmc.c
+130
-14
drivers/platform/x86/amd-pmc.c
···
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#define AMD_PMC_STB_PMI_0 0x03E30600
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#define AMD_PMC_STB_PREDEF 0xC6000001
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/* STB S2D(Spill to DRAM) has different message port offset */
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#define STB_SPILL_TO_DRAM 0xBE
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#define AMD_S2D_REGISTER_MESSAGE 0xA20
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#define AMD_S2D_REGISTER_RESPONSE 0xA80
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#define AMD_S2D_REGISTER_ARGUMENT 0xA88
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+
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/* STB Spill to DRAM Parameters */
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#define S2D_TELEMETRY_BYTES_MAX 0x100000
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#define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
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/* Base address of SMU for mapping physical address to virtual address */
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#define AMD_PMC_SMU_INDEX_ADDRESS 0xB8
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#define AMD_PMC_SMU_INDEX_DATA 0xBC
···
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MSG_OS_HINT_RN,
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};
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enum s2d_arg {
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S2D_TELEMETRY_SIZE = 0x01,
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S2D_PHYS_ADDR_LOW,
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S2D_PHYS_ADDR_HIGH,
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};
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struct amd_pmc_bit_map {
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const char *name;
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u32 bit_mask;
···
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struct amd_pmc_dev {
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void __iomem *regbase;
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void __iomem *smu_virt_addr;
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void __iomem *stb_virt_addr;
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void __iomem *fch_virt_addr;
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bool msg_port;
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u32 base_addr;
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u32 cpu_id;
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u32 active_ips;
···
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.release = amd_pmc_stb_debugfs_release,
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};
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static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
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{
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struct amd_pmc_dev *dev = filp->f_inode->i_private;
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u32 *buf;
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buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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memcpy_fromio(buf, dev->stb_virt_addr, S2D_TELEMETRY_BYTES_MAX);
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filp->private_data = buf;
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return 0;
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}
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static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
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loff_t *pos)
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{
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if (!filp->private_data)
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return -EINVAL;
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return simple_read_from_buffer(buf, size, pos, filp->private_data,
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S2D_TELEMETRY_BYTES_MAX);
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}
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static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
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{
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kfree(filp->private_data);
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return 0;
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}
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static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
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.owner = THIS_MODULE,
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.open = amd_pmc_stb_debugfs_open_v2,
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.read = amd_pmc_stb_debugfs_read_v2,
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.release = amd_pmc_stb_debugfs_release_v2,
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};
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static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
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struct seq_file *s)
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{
···
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debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
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&amd_pmc_idlemask_fops);
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/* Enable STB only when the module_param is set */
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if (enable_stb)
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debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
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&amd_pmc_stb_debugfs_fops);
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if (enable_stb) {
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if (dev->cpu_id == AMD_CPU_ID_YC)
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debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
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&amd_pmc_stb_debugfs_fops_v2);
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else
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debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
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&amd_pmc_stb_debugfs_fops);
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}
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}
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#else
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static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
···
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static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
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{
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u32 value;
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u32 value, message, argument, response;
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value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_RESPONSE);
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if (dev->msg_port) {
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message = AMD_S2D_REGISTER_MESSAGE;
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argument = AMD_S2D_REGISTER_ARGUMENT;
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response = AMD_S2D_REGISTER_RESPONSE;
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} else {
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message = AMD_PMC_REGISTER_MESSAGE;
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argument = AMD_PMC_REGISTER_ARGUMENT;
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response = AMD_PMC_REGISTER_RESPONSE;
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}
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value = amd_pmc_reg_read(dev, response);
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dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
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value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
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value = amd_pmc_reg_read(dev, argument);
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dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
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value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_MESSAGE);
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value = amd_pmc_reg_read(dev, message);
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dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
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}
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static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
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{
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int rc;
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u32 val;
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u32 val, message, argument, response;
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mutex_lock(&dev->lock);
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if (dev->msg_port) {
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message = AMD_S2D_REGISTER_MESSAGE;
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argument = AMD_S2D_REGISTER_ARGUMENT;
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response = AMD_S2D_REGISTER_RESPONSE;
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} else {
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message = AMD_PMC_REGISTER_MESSAGE;
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argument = AMD_PMC_REGISTER_ARGUMENT;
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response = AMD_PMC_REGISTER_RESPONSE;
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}
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/* Wait until we get a valid response */
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rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
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rc = readx_poll_timeout(ioread32, dev->regbase + response,
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val, val != 0, PMC_MSG_DELAY_MIN_US,
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PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
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if (rc) {
···
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}
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/* Write zero to response register */
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amd_pmc_reg_write(dev, AMD_PMC_REGISTER_RESPONSE, 0);
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amd_pmc_reg_write(dev, response, 0);
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/* Write argument into response register */
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amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, arg);
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amd_pmc_reg_write(dev, argument, arg);
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/* Write message ID to message ID register */
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amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
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amd_pmc_reg_write(dev, message, msg);
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/* Wait until we get a valid response */
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rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
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rc = readx_poll_timeout(ioread32, dev->regbase + response,
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val, val != 0, PMC_MSG_DELAY_MIN_US,
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PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
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if (rc) {
···
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if (ret) {
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/* PMFW may take longer time to return back the data */
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usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
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*data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
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*data = amd_pmc_reg_read(dev, argument);
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}
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break;
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case AMD_PMC_RESULT_CMD_REJECT_BUSY:
···
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{ }
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};
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static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
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{
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u32 size, phys_addr_low, phys_addr_hi;
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u64 stb_phys_addr;
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/* Spill to DRAM feature uses separate SMU message port */
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dev->msg_port = 1;
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amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
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if (size != S2D_TELEMETRY_BYTES_MAX)
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return -EIO;
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/* Get STB DRAM address */
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amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
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amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
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stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
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/* Clear msg_port for other SMU operation */
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dev->msg_port = 0;
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dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
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if (!dev->stb_virt_addr)
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return -ENOMEM;
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return 0;
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}
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static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
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{
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int err;
···
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err = amd_pmc_setup_smu_logging(dev);
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if (err)
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dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
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if (enable_stb && dev->cpu_id == AMD_CPU_ID_YC) {
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err = amd_pmc_s2d_init(dev);
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if (err)
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return err;
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}
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amd_pmc_get_smu_version(dev);
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platform_set_drvdata(pdev, dev);