tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Thomas Gleixner:

- Add a missing NULL pointer check in free_irq()

- Fix a memory leak/memory corruption in the generic irq chip

- Add missing rcu annotations for radix tree access

- Use ffs instead of fls when extracting data from a chip register in
the MIPS GIC irq driver

- Fix the unmasking of IPI interrupts in the MIPS GIC driver so they
end up at the target CPU and not at CPU0

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irq/generic-chip: Don't replace domain's name
irqdomain: Add __rcu annotations to radix tree accessors
irqchip/mips-gic: Use effective affinity to unmask
irqchip/mips-gic: Fix shifts to extract register fields
genirq: Check __free_irq() return value for NULL

Linus Torvalds 3d9d62b9 156069f8

+14 -8
+8 -5
drivers/irqchip/irq-mips-gic.c
··· 175 175 176 176 static void gic_unmask_irq(struct irq_data *d) 177 177 { 178 - struct cpumask *affinity = irq_data_get_affinity_mask(d); 179 178 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); 180 179 unsigned int cpu; 181 180 182 181 write_gic_smask(intr); 183 182 184 183 gic_clear_pcpu_masks(intr); 185 - cpu = cpumask_first_and(affinity, cpu_online_mask); 184 + cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); 186 185 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu)); 187 186 } 188 187 ··· 419 420 irq_hw_number_t hw, unsigned int cpu) 420 421 { 421 422 int intr = GIC_HWIRQ_TO_SHARED(hw); 423 + struct irq_data *data; 422 424 unsigned long flags; 425 + 426 + data = irq_get_irq_data(virq); 423 427 424 428 spin_lock_irqsave(&gic_lock, flags); 425 429 write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); 426 430 write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); 427 431 gic_clear_pcpu_masks(intr); 428 432 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu)); 433 + irq_data_update_effective_affinity(data, cpumask_of(cpu)); 429 434 spin_unlock_irqrestore(&gic_lock, flags); 430 435 431 436 return 0; ··· 648 645 649 646 /* Find the first available CPU vector. */ 650 647 i = 0; 651 - reserved = (C_SW0 | C_SW1) >> __fls(C_SW0); 648 + reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0); 652 649 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", 653 650 i++, &cpu_vec)) 654 651 reserved |= BIT(cpu_vec); ··· 687 684 688 685 gicconfig = read_gic_config(); 689 686 gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS; 690 - gic_shared_intrs >>= __fls(GIC_CONFIG_NUMINTERRUPTS); 687 + gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS); 691 688 gic_shared_intrs = (gic_shared_intrs + 1) * 8; 692 689 693 690 gic_vpes = gicconfig & GIC_CONFIG_PVPS; 694 - gic_vpes >>= __fls(GIC_CONFIG_PVPS); 691 + gic_vpes >>= __ffs(GIC_CONFIG_PVPS); 695 692 gic_vpes = gic_vpes + 1; 696 693 697 694 if (cpu_has_veic) {
-1
kernel/irq/generic-chip.c
··· 322 322 /* Calc pointer to the next generic chip */ 323 323 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type); 324 324 } 325 - d->name = name; 326 325 return 0; 327 326 } 328 327 EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
+2 -2
kernel/irq/irqdomain.c
··· 945 945 struct irq_desc *desc; 946 946 struct irq_domain *domain; 947 947 struct radix_tree_iter iter; 948 - void **slot; 948 + void __rcu **slot; 949 949 int i; 950 950 951 951 seq_printf(m, " %-16s %-6s %-10s %-10s %s\n", ··· 1453 1453 /* The irq_data was moved, fix the revmap to refer to the new location */ 1454 1454 static void irq_domain_fix_revmap(struct irq_data *d) 1455 1455 { 1456 - void **slot; 1456 + void __rcu **slot; 1457 1457 1458 1458 if (d->hwirq < d->domain->revmap_size) 1459 1459 return; /* Not using radix tree. */
+4
kernel/irq/manage.c
··· 1643 1643 #endif 1644 1644 1645 1645 action = __free_irq(irq, dev_id); 1646 + 1647 + if (!action) 1648 + return NULL; 1649 + 1646 1650 devname = action->name; 1647 1651 kfree(action); 1648 1652 return devname;