Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
i915: Set object to gtt domain when faulting it back in
drm/i915: Apply a big hammer to 865 GEM object CPU cache flushing.
drm/i915: Fix tiling pitch handling on 8xx.
+34
-6
+21
-2
drivers/gpu/drm/i915/i915_gem.c
+21
-2
drivers/gpu/drm/i915/i915_gem.c
···
1145
1145
mutex_unlock(&dev->struct_mutex);
1146
1146
return VM_FAULT_SIGBUS;
1147
1147
}
1148
+
1149
+
ret = i915_gem_object_set_to_gtt_domain(obj, write);
1150
+
if (ret) {
1151
+
mutex_unlock(&dev->struct_mutex);
1152
+
return VM_FAULT_SIGBUS;
1153
+
}
1154
+
1148
1155
list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1149
1156
}
1150
1157
···
2135
2128
return;
2136
2129
}
2137
2130
2138
-
pitch_val = (obj_priv->stride / 128) - 1;
2139
-
WARN_ON(pitch_val & ~0x0000000f);
2131
+
pitch_val = obj_priv->stride / 128;
2132
+
pitch_val = ffs(pitch_val) - 1;
2133
+
WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2134
+
2140
2135
val = obj_priv->gtt_offset;
2141
2136
if (obj_priv->tiling_mode == I915_TILING_Y)
2142
2137
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
···
2429
2420
*/
2430
2421
if (obj_priv->pages == NULL)
2431
2422
return;
2423
+
2424
+
/* XXX: The 865 in particular appears to be weird in how it handles
2425
+
* cache flushing. We haven't figured it out, but the
2426
+
* clflush+agp_chipset_flush doesn't appear to successfully get the
2427
+
* data visible to the PGU, while wbinvd + agp_chipset_flush does.
2428
+
*/
2429
+
if (IS_I865G(obj->dev)) {
2430
+
wbinvd();
2431
+
return;
2432
+
}
2432
2433
2433
2434
drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2434
2435
}
+11
-3
drivers/gpu/drm/i915/i915_gem_tiling.c
+11
-3
drivers/gpu/drm/i915/i915_gem_tiling.c
···
213
213
if (tiling_mode == I915_TILING_NONE)
214
214
return true;
215
215
216
-
if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
216
+
if (!IS_I9XX(dev) ||
217
+
(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
217
218
tile_width = 128;
218
219
else
219
220
tile_width = 512;
···
226
225
if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
227
226
return false;
228
227
} else if (IS_I9XX(dev)) {
229
-
if (stride / tile_width > I830_FENCE_MAX_PITCH_VAL ||
228
+
uint32_t pitch_val = ffs(stride / tile_width) - 1;
229
+
230
+
/* XXX: For Y tiling, FENCE_MAX_PITCH_VAL is actually 6 (8KB)
231
+
* instead of 4 (2KB) on 945s.
232
+
*/
233
+
if (pitch_val > I915_FENCE_MAX_PITCH_VAL ||
230
234
size > (I830_FENCE_MAX_SIZE_VAL << 20))
231
235
return false;
232
236
} else {
233
-
if (stride / 128 > I830_FENCE_MAX_PITCH_VAL ||
237
+
uint32_t pitch_val = ffs(stride / tile_width) - 1;
238
+
239
+
if (pitch_val > I830_FENCE_MAX_PITCH_VAL ||
234
240
size > (I830_FENCE_MAX_SIZE_VAL << 19))
235
241
return false;
236
242
}
+2
-1
drivers/gpu/drm/i915/i915_reg.h
+2
-1
drivers/gpu/drm/i915/i915_reg.h
···
190
190
#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
191
191
#define I830_FENCE_PITCH_SHIFT 4
192
192
#define I830_FENCE_REG_VALID (1<<0)
193
-
#define I830_FENCE_MAX_PITCH_VAL 0x10
193
+
#define I915_FENCE_MAX_PITCH_VAL 0x10
194
+
#define I830_FENCE_MAX_PITCH_VAL 6
194
195
#define I830_FENCE_MAX_SIZE_VAL (1<<8)
195
196
196
197
#define I915_FENCE_START_MASK 0x0ff00000