tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"A bunch of fixes:
- vmware memory corruption
- ttm spinlock balance
- cirrus/mgag200 work in the presence of efifb
and finally Alex and Jerome managed to track down a magic set of bits
that on certain rv740 and evergreen cards allow the correct use of the
complete set of render backends, this makes the cards operate
correctly in a number of scenarios we had issues in before, it also
manages to boost speed on benchmarks my large amounts on these
specific gpus."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/edid: Make the header fixup threshold tunable
drm/radeon: fix regression in UMS CS ioctl
drm/vmwgfx: Fix nasty write past alloced memory area
drm/ttm: Fix spinlock imbalance
drm/radeon: fixup tiling group size and backendmap on r6xx-r9xx (v4)
drm/radeon: fix HD6790, HD6570 backend programming
drm/radeon: properly program gart on rv740, juniper, cypress, barts, hemlock
drm/radeon: fix bank information in tiling config
drm/mgag200: kick off conflicting framebuffers earlier.
drm/cirrus: kick out conflicting framebuffers earlier
cirrus: avoid crash if driver fails to load

Linus Torvalds 3ded7acf 37b22400

+320 -1016
+19
drivers/gpu/drm/cirrus/cirrus_drv.c
··· 35 35 {0,} 36 36 }; 37 37 38 + 39 + static void cirrus_kick_out_firmware_fb(struct pci_dev *pdev) 40 + { 41 + struct apertures_struct *ap; 42 + bool primary = false; 43 + 44 + ap = alloc_apertures(1); 45 + ap->ranges[0].base = pci_resource_start(pdev, 0); 46 + ap->ranges[0].size = pci_resource_len(pdev, 0); 47 + 48 + #ifdef CONFIG_X86 49 + primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 50 + #endif 51 + remove_conflicting_framebuffers(ap, "cirrusdrmfb", primary); 52 + kfree(ap); 53 + } 54 + 38 55 static int __devinit 39 56 cirrus_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 40 57 { 58 + cirrus_kick_out_firmware_fb(pdev); 59 + 41 60 return drm_get_pci_dev(pdev, ent, &driver); 42 61 } 43 62
+1 -1
drivers/gpu/drm/cirrus/cirrus_drv.h
··· 145 145 struct ttm_bo_device bdev; 146 146 atomic_t validate_sequence; 147 147 } ttm; 148 - 148 + bool mm_inited; 149 149 }; 150 150 151 151
+5
drivers/gpu/drm/cirrus/cirrus_ttm.c
··· 275 275 pci_resource_len(dev->pdev, 0), 276 276 DRM_MTRR_WC); 277 277 278 + cirrus->mm_inited = true; 278 279 return 0; 279 280 } 280 281 281 282 void cirrus_mm_fini(struct cirrus_device *cirrus) 282 283 { 283 284 struct drm_device *dev = cirrus->dev; 285 + 286 + if (!cirrus->mm_inited) 287 + return; 288 + 284 289 ttm_bo_device_release(&cirrus->ttm.bdev); 285 290 286 291 cirrus_ttm_global_release(cirrus);
+9 -2
drivers/gpu/drm/drm_edid.c
··· 30 30 #include <linux/kernel.h> 31 31 #include <linux/slab.h> 32 32 #include <linux/i2c.h> 33 - #include <linux/export.h> 33 + #include <linux/module.h> 34 34 #include "drmP.h" 35 35 #include "drm_edid.h" 36 36 #include "drm_edid_modes.h" ··· 149 149 } 150 150 EXPORT_SYMBOL(drm_edid_header_is_valid); 151 151 152 + static int edid_fixup __read_mostly = 6; 153 + module_param_named(edid_fixup, edid_fixup, int, 0400); 154 + MODULE_PARM_DESC(edid_fixup, 155 + "Minimum number of valid EDID header bytes (0-8, default 6)"); 152 156 153 157 /* 154 158 * Sanity check the EDID block (base or extension). Return 0 if the block ··· 164 160 u8 csum = 0; 165 161 struct edid *edid = (struct edid *)raw_edid; 166 162 163 + if (edid_fixup > 8 || edid_fixup < 0) 164 + edid_fixup = 6; 165 + 167 166 if (block == 0) { 168 167 int score = drm_edid_header_is_valid(raw_edid); 169 168 if (score == 8) ; 170 - else if (score >= 6) { 169 + else if (score >= edid_fixup) { 171 170 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 172 171 memcpy(raw_edid, edid_header, sizeof(edid_header)); 173 172 } else {
+19
drivers/gpu/drm/mgag200/mgag200_drv.c
··· 41 41 42 42 MODULE_DEVICE_TABLE(pci, pciidlist); 43 43 44 + static void mgag200_kick_out_firmware_fb(struct pci_dev *pdev) 45 + { 46 + struct apertures_struct *ap; 47 + bool primary = false; 48 + 49 + ap = alloc_apertures(1); 50 + ap->ranges[0].base = pci_resource_start(pdev, 0); 51 + ap->ranges[0].size = pci_resource_len(pdev, 0); 52 + 53 + #ifdef CONFIG_X86 54 + primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 55 + #endif 56 + remove_conflicting_framebuffers(ap, "mgag200drmfb", primary); 57 + kfree(ap); 58 + } 59 + 60 + 44 61 static int __devinit 45 62 mga_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 46 63 { 64 + mgag200_kick_out_firmware_fb(pdev); 65 + 47 66 return drm_get_pci_dev(pdev, ent, &driver); 48 67 } 49 68
+58 -328
drivers/gpu/drm/radeon/evergreen.c
··· 1029 1029 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 1030 1030 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 1031 1031 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 1032 + if ((rdev->family == CHIP_JUNIPER) || 1033 + (rdev->family == CHIP_CYPRESS) || 1034 + (rdev->family == CHIP_HEMLOCK) || 1035 + (rdev->family == CHIP_BARTS)) 1036 + WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); 1032 1037 } 1033 1038 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1034 1039 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); ··· 1558 1553 /* 1559 1554 * Core functions 1560 1555 */ 1561 - static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 1562 - u32 num_tile_pipes, 1563 - u32 num_backends, 1564 - u32 backend_disable_mask) 1565 - { 1566 - u32 backend_map = 0; 1567 - u32 enabled_backends_mask = 0; 1568 - u32 enabled_backends_count = 0; 1569 - u32 cur_pipe; 1570 - u32 swizzle_pipe[EVERGREEN_MAX_PIPES]; 1571 - u32 cur_backend = 0; 1572 - u32 i; 1573 - bool force_no_swizzle; 1574 - 1575 - if (num_tile_pipes > EVERGREEN_MAX_PIPES) 1576 - num_tile_pipes = EVERGREEN_MAX_PIPES; 1577 - if (num_tile_pipes < 1) 1578 - num_tile_pipes = 1; 1579 - if (num_backends > EVERGREEN_MAX_BACKENDS) 1580 - num_backends = EVERGREEN_MAX_BACKENDS; 1581 - if (num_backends < 1) 1582 - num_backends = 1; 1583 - 1584 - for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { 1585 - if (((backend_disable_mask >> i) & 1) == 0) { 1586 - enabled_backends_mask |= (1 << i); 1587 - ++enabled_backends_count; 1588 - } 1589 - if (enabled_backends_count == num_backends) 1590 - break; 1591 - } 1592 - 1593 - if (enabled_backends_count == 0) { 1594 - enabled_backends_mask = 1; 1595 - enabled_backends_count = 1; 1596 - } 1597 - 1598 - if (enabled_backends_count != num_backends) 1599 - num_backends = enabled_backends_count; 1600 - 1601 - memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES); 1602 - switch (rdev->family) { 1603 - case CHIP_CEDAR: 1604 - case CHIP_REDWOOD: 1605 - case CHIP_PALM: 1606 - case CHIP_SUMO: 1607 - case CHIP_SUMO2: 1608 - case CHIP_TURKS: 1609 - case CHIP_CAICOS: 1610 - force_no_swizzle = false; 1611 - break; 1612 - case CHIP_CYPRESS: 1613 - case CHIP_HEMLOCK: 1614 - case CHIP_JUNIPER: 1615 - case CHIP_BARTS: 1616 - default: 1617 - force_no_swizzle = true; 1618 - break; 1619 - } 1620 - if (force_no_swizzle) { 1621 - bool last_backend_enabled = false; 1622 - 1623 - force_no_swizzle = false; 1624 - for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { 1625 - if (((enabled_backends_mask >> i) & 1) == 1) { 1626 - if (last_backend_enabled) 1627 - force_no_swizzle = true; 1628 - last_backend_enabled = true; 1629 - } else 1630 - last_backend_enabled = false; 1631 - } 1632 - } 1633 - 1634 - switch (num_tile_pipes) { 1635 - case 1: 1636 - case 3: 1637 - case 5: 1638 - case 7: 1639 - DRM_ERROR("odd number of pipes!\n"); 1640 - break; 1641 - case 2: 1642 - swizzle_pipe[0] = 0; 1643 - swizzle_pipe[1] = 1; 1644 - break; 1645 - case 4: 1646 - if (force_no_swizzle) { 1647 - swizzle_pipe[0] = 0; 1648 - swizzle_pipe[1] = 1; 1649 - swizzle_pipe[2] = 2; 1650 - swizzle_pipe[3] = 3; 1651 - } else { 1652 - swizzle_pipe[0] = 0; 1653 - swizzle_pipe[1] = 2; 1654 - swizzle_pipe[2] = 1; 1655 - swizzle_pipe[3] = 3; 1656 - } 1657 - break; 1658 - case 6: 1659 - if (force_no_swizzle) { 1660 - swizzle_pipe[0] = 0; 1661 - swizzle_pipe[1] = 1; 1662 - swizzle_pipe[2] = 2; 1663 - swizzle_pipe[3] = 3; 1664 - swizzle_pipe[4] = 4; 1665 - swizzle_pipe[5] = 5; 1666 - } else { 1667 - swizzle_pipe[0] = 0; 1668 - swizzle_pipe[1] = 2; 1669 - swizzle_pipe[2] = 4; 1670 - swizzle_pipe[3] = 1; 1671 - swizzle_pipe[4] = 3; 1672 - swizzle_pipe[5] = 5; 1673 - } 1674 - break; 1675 - case 8: 1676 - if (force_no_swizzle) { 1677 - swizzle_pipe[0] = 0; 1678 - swizzle_pipe[1] = 1; 1679 - swizzle_pipe[2] = 2; 1680 - swizzle_pipe[3] = 3; 1681 - swizzle_pipe[4] = 4; 1682 - swizzle_pipe[5] = 5; 1683 - swizzle_pipe[6] = 6; 1684 - swizzle_pipe[7] = 7; 1685 - } else { 1686 - swizzle_pipe[0] = 0; 1687 - swizzle_pipe[1] = 2; 1688 - swizzle_pipe[2] = 4; 1689 - swizzle_pipe[3] = 6; 1690 - swizzle_pipe[4] = 1; 1691 - swizzle_pipe[5] = 3; 1692 - swizzle_pipe[6] = 5; 1693 - swizzle_pipe[7] = 7; 1694 - } 1695 - break; 1696 - } 1697 - 1698 - for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1699 - while (((1 << cur_backend) & enabled_backends_mask) == 0) 1700 - cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; 1701 - 1702 - backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); 1703 - 1704 - cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; 1705 - } 1706 - 1707 - return backend_map; 1708 - } 1709 - 1710 1556 static void evergreen_gpu_init(struct radeon_device *rdev) 1711 1557 { 1712 - u32 cc_rb_backend_disable = 0; 1713 - u32 cc_gc_shader_pipe_config; 1714 - u32 gb_addr_config = 0; 1558 + u32 gb_addr_config; 1715 1559 u32 mc_shared_chmap, mc_arb_ramcfg; 1716 - u32 gb_backend_map; 1717 - u32 grbm_gfx_index; 1718 1560 u32 sx_debug_1; 1719 1561 u32 smx_dc_ctl0; 1720 1562 u32 sq_config; ··· 1576 1724 u32 sq_stack_resource_mgmt_3; 1577 1725 u32 vgt_cache_invalidation; 1578 1726 u32 hdp_host_path_cntl, tmp; 1727 + u32 disabled_rb_mask; 1579 1728 int i, j, num_shader_engines, ps_thread_count; 1580 1729 1581 1730 switch (rdev->family) { ··· 1601 1748 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1602 1749 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1603 1750 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1751 + gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN; 1604 1752 break; 1605 1753 case CHIP_JUNIPER: 1606 1754 rdev->config.evergreen.num_ses = 1; ··· 1623 1769 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1624 1770 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1625 1771 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1772 + gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN; 1626 1773 break; 1627 1774 case CHIP_REDWOOD: 1628 1775 rdev->config.evergreen.num_ses = 1; ··· 1645 1790 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1646 1791 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1647 1792 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1793 + gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; 1648 1794 break; 1649 1795 case CHIP_CEDAR: 1650 1796 default: ··· 1668 1812 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1669 1813 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1670 1814 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1815 + gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; 1671 1816 break; 1672 1817 case CHIP_PALM: 1673 1818 rdev->config.evergreen.num_ses = 1; ··· 1690 1833 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1691 1834 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1692 1835 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1836 + gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; 1693 1837 break; 1694 1838 case CHIP_SUMO: 1695 1839 rdev->config.evergreen.num_ses = 1; ··· 1718 1860 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1719 1861 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1720 1862 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1863 + gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; 1721 1864 break; 1722 1865 case CHIP_SUMO2: 1723 1866 rdev->config.evergreen.num_ses = 1; ··· 1740 1881 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1741 1882 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1742 1883 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1884 + gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; 1743 1885 break; 1744 1886 case CHIP_BARTS: 1745 1887 rdev->config.evergreen.num_ses = 2; ··· 1762 1902 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1763 1903 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1764 1904 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1905 + gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN; 1765 1906 break; 1766 1907 case CHIP_TURKS: 1767 1908 rdev->config.evergreen.num_ses = 1; ··· 1784 1923 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1785 1924 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1786 1925 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1926 + gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN; 1787 1927 break; 1788 1928 case CHIP_CAICOS: 1789 1929 rdev->config.evergreen.num_ses = 1; ··· 1806 1944 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1807 1945 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1808 1946 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1947 + gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN; 1809 1948 break; 1810 1949 } 1811 1950 ··· 1823 1960 1824 1961 evergreen_fix_pci_max_read_req_size(rdev); 1825 1962 1826 - cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2; 1827 - 1828 - cc_gc_shader_pipe_config |= 1829 - INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes) 1830 - & EVERGREEN_MAX_PIPES_MASK); 1831 - cc_gc_shader_pipe_config |= 1832 - INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds) 1833 - & EVERGREEN_MAX_SIMDS_MASK); 1834 - 1835 - cc_rb_backend_disable = 1836 - BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends) 1837 - & EVERGREEN_MAX_BACKENDS_MASK); 1838 - 1839 - 1840 1963 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1841 1964 if ((rdev->family == CHIP_PALM) || 1842 1965 (rdev->family == CHIP_SUMO) || ··· 1830 1981 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); 1831 1982 else 1832 1983 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1833 - 1834 - switch (rdev->config.evergreen.max_tile_pipes) { 1835 - case 1: 1836 - default: 1837 - gb_addr_config |= NUM_PIPES(0); 1838 - break; 1839 - case 2: 1840 - gb_addr_config |= NUM_PIPES(1); 1841 - break; 1842 - case 4: 1843 - gb_addr_config |= NUM_PIPES(2); 1844 - break; 1845 - case 8: 1846 - gb_addr_config |= NUM_PIPES(3); 1847 - break; 1848 - } 1849 - 1850 - gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1851 - gb_addr_config |= BANK_INTERLEAVE_SIZE(0); 1852 - gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1); 1853 - gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1); 1854 - gb_addr_config |= NUM_GPUS(0); /* Hemlock? */ 1855 - gb_addr_config |= MULTI_GPU_TILE_SIZE(2); 1856 - 1857 - if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2) 1858 - gb_addr_config |= ROW_SIZE(2); 1859 - else 1860 - gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT); 1861 - 1862 - if (rdev->ddev->pdev->device == 0x689e) { 1863 - u32 efuse_straps_4; 1864 - u32 efuse_straps_3; 1865 - u8 efuse_box_bit_131_124; 1866 - 1867 - WREG32(RCU_IND_INDEX, 0x204); 1868 - efuse_straps_4 = RREG32(RCU_IND_DATA); 1869 - WREG32(RCU_IND_INDEX, 0x203); 1870 - efuse_straps_3 = RREG32(RCU_IND_DATA); 1871 - efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28)); 1872 - 1873 - switch(efuse_box_bit_131_124) { 1874 - case 0x00: 1875 - gb_backend_map = 0x76543210; 1876 - break; 1877 - case 0x55: 1878 - gb_backend_map = 0x77553311; 1879 - break; 1880 - case 0x56: 1881 - gb_backend_map = 0x77553300; 1882 - break; 1883 - case 0x59: 1884 - gb_backend_map = 0x77552211; 1885 - break; 1886 - case 0x66: 1887 - gb_backend_map = 0x77443300; 1888 - break; 1889 - case 0x99: 1890 - gb_backend_map = 0x66552211; 1891 - break; 1892 - case 0x5a: 1893 - gb_backend_map = 0x77552200; 1894 - break; 1895 - case 0xaa: 1896 - gb_backend_map = 0x66442200; 1897 - break; 1898 - case 0x95: 1899 - gb_backend_map = 0x66553311; 1900 - break; 1901 - default: 1902 - DRM_ERROR("bad backend map, using default\n"); 1903 - gb_backend_map = 1904 - evergreen_get_tile_pipe_to_backend_map(rdev, 1905 - rdev->config.evergreen.max_tile_pipes, 1906 - rdev->config.evergreen.max_backends, 1907 - ((EVERGREEN_MAX_BACKENDS_MASK << 1908 - rdev->config.evergreen.max_backends) & 1909 - EVERGREEN_MAX_BACKENDS_MASK)); 1910 - break; 1911 - } 1912 - } else if (rdev->ddev->pdev->device == 0x68b9) { 1913 - u32 efuse_straps_3; 1914 - u8 efuse_box_bit_127_124; 1915 - 1916 - WREG32(RCU_IND_INDEX, 0x203); 1917 - efuse_straps_3 = RREG32(RCU_IND_DATA); 1918 - efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28); 1919 - 1920 - switch(efuse_box_bit_127_124) { 1921 - case 0x0: 1922 - gb_backend_map = 0x00003210; 1923 - break; 1924 - case 0x5: 1925 - case 0x6: 1926 - case 0x9: 1927 - case 0xa: 1928 - gb_backend_map = 0x00003311; 1929 - break; 1930 - default: 1931 - DRM_ERROR("bad backend map, using default\n"); 1932 - gb_backend_map = 1933 - evergreen_get_tile_pipe_to_backend_map(rdev, 1934 - rdev->config.evergreen.max_tile_pipes, 1935 - rdev->config.evergreen.max_backends, 1936 - ((EVERGREEN_MAX_BACKENDS_MASK << 1937 - rdev->config.evergreen.max_backends) & 1938 - EVERGREEN_MAX_BACKENDS_MASK)); 1939 - break; 1940 - } 1941 - } else { 1942 - switch (rdev->family) { 1943 - case CHIP_CYPRESS: 1944 - case CHIP_HEMLOCK: 1945 - case CHIP_BARTS: 1946 - gb_backend_map = 0x66442200; 1947 - break; 1948 - case CHIP_JUNIPER: 1949 - gb_backend_map = 0x00002200; 1950 - break; 1951 - default: 1952 - gb_backend_map = 1953 - evergreen_get_tile_pipe_to_backend_map(rdev, 1954 - rdev->config.evergreen.max_tile_pipes, 1955 - rdev->config.evergreen.max_backends, 1956 - ((EVERGREEN_MAX_BACKENDS_MASK << 1957 - rdev->config.evergreen.max_backends) & 1958 - EVERGREEN_MAX_BACKENDS_MASK)); 1959 - } 1960 - } 1961 1984 1962 1985 /* setup tiling info dword. gb_addr_config is not adequate since it does 1963 1986 * not have bank info, so create a custom tiling dword. ··· 1857 2136 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ 1858 2137 if (rdev->flags & RADEON_IS_IGP) 1859 2138 rdev->config.evergreen.tile_config |= 1 << 4; 1860 - else 1861 - rdev->config.evergreen.tile_config |= 1862 - ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 1863 - rdev->config.evergreen.tile_config |= 1864 - ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8; 2139 + else { 2140 + if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 2141 + rdev->config.evergreen.tile_config |= 1 << 4; 2142 + else 2143 + rdev->config.evergreen.tile_config |= 0 << 4; 2144 + } 2145 + rdev->config.evergreen.tile_config |= 0 << 8; 1865 2146 rdev->config.evergreen.tile_config |= 1866 2147 ((gb_addr_config & 0x30000000) >> 28) << 12; 1867 2148 1868 - rdev->config.evergreen.backend_map = gb_backend_map; 1869 - WREG32(GB_BACKEND_MAP, gb_backend_map); 2149 + num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1; 2150 + 2151 + if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) { 2152 + u32 efuse_straps_4; 2153 + u32 efuse_straps_3; 2154 + 2155 + WREG32(RCU_IND_INDEX, 0x204); 2156 + efuse_straps_4 = RREG32(RCU_IND_DATA); 2157 + WREG32(RCU_IND_INDEX, 0x203); 2158 + efuse_straps_3 = RREG32(RCU_IND_DATA); 2159 + tmp = (((efuse_straps_4 & 0xf) << 4) | 2160 + ((efuse_straps_3 & 0xf0000000) >> 28)); 2161 + } else { 2162 + tmp = 0; 2163 + for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) { 2164 + u32 rb_disable_bitmap; 2165 + 2166 + WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 2167 + WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 2168 + rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; 2169 + tmp <<= 4; 2170 + tmp |= rb_disable_bitmap; 2171 + } 2172 + } 2173 + /* enabled rb are just the one not disabled :) */ 2174 + disabled_rb_mask = tmp; 2175 + 2176 + WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 2177 + WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 2178 + 1870 2179 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1871 2180 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1872 2181 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1873 2182 1874 - num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; 1875 - grbm_gfx_index = INSTANCE_BROADCAST_WRITES; 1876 - 1877 - for (i = 0; i < rdev->config.evergreen.num_ses; i++) { 1878 - u32 rb = cc_rb_backend_disable | (0xf0 << 16); 1879 - u32 sp = cc_gc_shader_pipe_config; 1880 - u32 gfx = grbm_gfx_index | SE_INDEX(i); 1881 - 1882 - if (i == num_shader_engines) { 1883 - rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK); 1884 - sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK); 1885 - } 1886 - 1887 - WREG32(GRBM_GFX_INDEX, gfx); 1888 - WREG32(RLC_GFX_INDEX, gfx); 1889 - 1890 - WREG32(CC_RB_BACKEND_DISABLE, rb); 1891 - WREG32(CC_SYS_RB_BACKEND_DISABLE, rb); 1892 - WREG32(GC_USER_RB_BACKEND_DISABLE, rb); 1893 - WREG32(CC_GC_SHADER_PIPE_CONFIG, sp); 1894 - } 1895 - 1896 - grbm_gfx_index |= SE_BROADCAST_WRITES; 1897 - WREG32(GRBM_GFX_INDEX, grbm_gfx_index); 1898 - WREG32(RLC_GFX_INDEX, grbm_gfx_index); 2183 + tmp = gb_addr_config & NUM_PIPES_MASK; 2184 + tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, 2185 + EVERGREEN_MAX_BACKENDS, disabled_rb_mask); 2186 + WREG32(GB_BACKEND_MAP, tmp); 1899 2187 1900 2188 WREG32(CGTS_SYS_TCC_DISABLE, 0); 1901 2189 WREG32(CGTS_TCC_DISABLE, 0);
+11
drivers/gpu/drm/radeon/evergreend.h
··· 37 37 #define EVERGREEN_MAX_PIPES_MASK 0xFF 38 38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF 39 39 40 + #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 41 + #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 42 + #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 43 + #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 44 + #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 45 + #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 46 + #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 47 + #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 48 + 40 49 /* Registers */ 41 50 42 51 #define RCU_IND_INDEX 0x100 ··· 63 54 #define BACKEND_DISABLE(x) ((x) << 16) 64 55 #define GB_ADDR_CONFIG 0x98F8 65 56 #define NUM_PIPES(x) ((x) << 0) 57 + #define NUM_PIPES_MASK 0x0000000f 66 58 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 67 59 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 68 60 #define NUM_SHADER_ENGINES(x) ((x) << 12) ··· 462 452 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 463 453 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 464 454 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 455 + #define MC_VM_MD_L1_TLB3_CNTL 0x2698 465 456 466 457 #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C 467 458 #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
+35 -325
drivers/gpu/drm/radeon/ni.c
··· 417 417 /* 418 418 * Core functions 419 419 */ 420 - static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 421 - u32 num_tile_pipes, 422 - u32 num_backends_per_asic, 423 - u32 *backend_disable_mask_per_asic, 424 - u32 num_shader_engines) 425 - { 426 - u32 backend_map = 0; 427 - u32 enabled_backends_mask = 0; 428 - u32 enabled_backends_count = 0; 429 - u32 num_backends_per_se; 430 - u32 cur_pipe; 431 - u32 swizzle_pipe[CAYMAN_MAX_PIPES]; 432 - u32 cur_backend = 0; 433 - u32 i; 434 - bool force_no_swizzle; 435 - 436 - /* force legal values */ 437 - if (num_tile_pipes < 1) 438 - num_tile_pipes = 1; 439 - if (num_tile_pipes > rdev->config.cayman.max_tile_pipes) 440 - num_tile_pipes = rdev->config.cayman.max_tile_pipes; 441 - if (num_shader_engines < 1) 442 - num_shader_engines = 1; 443 - if (num_shader_engines > rdev->config.cayman.max_shader_engines) 444 - num_shader_engines = rdev->config.cayman.max_shader_engines; 445 - if (num_backends_per_asic < num_shader_engines) 446 - num_backends_per_asic = num_shader_engines; 447 - if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines)) 448 - num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines; 449 - 450 - /* make sure we have the same number of backends per se */ 451 - num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines); 452 - /* set up the number of backends per se */ 453 - num_backends_per_se = num_backends_per_asic / num_shader_engines; 454 - if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) { 455 - num_backends_per_se = rdev->config.cayman.max_backends_per_se; 456 - num_backends_per_asic = num_backends_per_se * num_shader_engines; 457 - } 458 - 459 - /* create enable mask and count for enabled backends */ 460 - for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { 461 - if (((*backend_disable_mask_per_asic >> i) & 1) == 0) { 462 - enabled_backends_mask |= (1 << i); 463 - ++enabled_backends_count; 464 - } 465 - if (enabled_backends_count == num_backends_per_asic) 466 - break; 467 - } 468 - 469 - /* force the backends mask to match the current number of backends */ 470 - if (enabled_backends_count != num_backends_per_asic) { 471 - u32 this_backend_enabled; 472 - u32 shader_engine; 473 - u32 backend_per_se; 474 - 475 - enabled_backends_mask = 0; 476 - enabled_backends_count = 0; 477 - *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK; 478 - for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { 479 - /* calc the current se */ 480 - shader_engine = i / rdev->config.cayman.max_backends_per_se; 481 - /* calc the backend per se */ 482 - backend_per_se = i % rdev->config.cayman.max_backends_per_se; 483 - /* default to not enabled */ 484 - this_backend_enabled = 0; 485 - if ((shader_engine < num_shader_engines) && 486 - (backend_per_se < num_backends_per_se)) 487 - this_backend_enabled = 1; 488 - if (this_backend_enabled) { 489 - enabled_backends_mask |= (1 << i); 490 - *backend_disable_mask_per_asic &= ~(1 << i); 491 - ++enabled_backends_count; 492 - } 493 - } 494 - } 495 - 496 - 497 - memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES); 498 - switch (rdev->family) { 499 - case CHIP_CAYMAN: 500 - case CHIP_ARUBA: 501 - force_no_swizzle = true; 502 - break; 503 - default: 504 - force_no_swizzle = false; 505 - break; 506 - } 507 - if (force_no_swizzle) { 508 - bool last_backend_enabled = false; 509 - 510 - force_no_swizzle = false; 511 - for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { 512 - if (((enabled_backends_mask >> i) & 1) == 1) { 513 - if (last_backend_enabled) 514 - force_no_swizzle = true; 515 - last_backend_enabled = true; 516 - } else 517 - last_backend_enabled = false; 518 - } 519 - } 520 - 521 - switch (num_tile_pipes) { 522 - case 1: 523 - case 3: 524 - case 5: 525 - case 7: 526 - DRM_ERROR("odd number of pipes!\n"); 527 - break; 528 - case 2: 529 - swizzle_pipe[0] = 0; 530 - swizzle_pipe[1] = 1; 531 - break; 532 - case 4: 533 - if (force_no_swizzle) { 534 - swizzle_pipe[0] = 0; 535 - swizzle_pipe[1] = 1; 536 - swizzle_pipe[2] = 2; 537 - swizzle_pipe[3] = 3; 538 - } else { 539 - swizzle_pipe[0] = 0; 540 - swizzle_pipe[1] = 2; 541 - swizzle_pipe[2] = 1; 542 - swizzle_pipe[3] = 3; 543 - } 544 - break; 545 - case 6: 546 - if (force_no_swizzle) { 547 - swizzle_pipe[0] = 0; 548 - swizzle_pipe[1] = 1; 549 - swizzle_pipe[2] = 2; 550 - swizzle_pipe[3] = 3; 551 - swizzle_pipe[4] = 4; 552 - swizzle_pipe[5] = 5; 553 - } else { 554 - swizzle_pipe[0] = 0; 555 - swizzle_pipe[1] = 2; 556 - swizzle_pipe[2] = 4; 557 - swizzle_pipe[3] = 1; 558 - swizzle_pipe[4] = 3; 559 - swizzle_pipe[5] = 5; 560 - } 561 - break; 562 - case 8: 563 - if (force_no_swizzle) { 564 - swizzle_pipe[0] = 0; 565 - swizzle_pipe[1] = 1; 566 - swizzle_pipe[2] = 2; 567 - swizzle_pipe[3] = 3; 568 - swizzle_pipe[4] = 4; 569 - swizzle_pipe[5] = 5; 570 - swizzle_pipe[6] = 6; 571 - swizzle_pipe[7] = 7; 572 - } else { 573 - swizzle_pipe[0] = 0; 574 - swizzle_pipe[1] = 2; 575 - swizzle_pipe[2] = 4; 576 - swizzle_pipe[3] = 6; 577 - swizzle_pipe[4] = 1; 578 - swizzle_pipe[5] = 3; 579 - swizzle_pipe[6] = 5; 580 - swizzle_pipe[7] = 7; 581 - } 582 - break; 583 - } 584 - 585 - for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 586 - while (((1 << cur_backend) & enabled_backends_mask) == 0) 587 - cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; 588 - 589 - backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); 590 - 591 - cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; 592 - } 593 - 594 - return backend_map; 595 - } 596 - 597 - static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, 598 - u32 disable_mask_per_se, 599 - u32 max_disable_mask_per_se, 600 - u32 num_shader_engines) 601 - { 602 - u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se); 603 - u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se; 604 - 605 - if (num_shader_engines == 1) 606 - return disable_mask_per_asic; 607 - else if (num_shader_engines == 2) 608 - return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se); 609 - else 610 - return 0xffffffff; 611 - } 612 - 613 420 static void cayman_gpu_init(struct radeon_device *rdev) 614 421 { 615 - u32 cc_rb_backend_disable = 0; 616 - u32 cc_gc_shader_pipe_config; 617 422 u32 gb_addr_config = 0; 618 423 u32 mc_shared_chmap, mc_arb_ramcfg; 619 - u32 gb_backend_map; 620 424 u32 cgts_tcc_disable; 621 425 u32 sx_debug_1; 622 426 u32 smx_dc_ctl0; 623 - u32 gc_user_shader_pipe_config; 624 - u32 gc_user_rb_backend_disable; 625 - u32 cgts_user_tcc_disable; 626 427 u32 cgts_sm_ctrl_reg; 627 428 u32 hdp_host_path_cntl; 628 429 u32 tmp; 430 + u32 disabled_rb_mask; 629 431 int i, j; 630 432 631 433 switch (rdev->family) { ··· 452 650 rdev->config.cayman.sc_prim_fifo_size = 0x100; 453 651 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 454 652 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 653 + gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; 455 654 break; 456 655 case CHIP_ARUBA: 457 656 default: ··· 490 687 rdev->config.cayman.sc_prim_fifo_size = 0x40; 491 688 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 492 689 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 690 + gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; 493 691 break; 494 692 } 495 693 ··· 510 706 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 511 707 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 512 708 513 - cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE); 514 - cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); 515 - cgts_tcc_disable = 0xffff0000; 516 - for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) 517 - cgts_tcc_disable &= ~(1 << (16 + i)); 518 - gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE); 519 - gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG); 520 - cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE); 521 - 522 - rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines; 523 - tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; 524 - rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp); 525 - rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes; 526 - tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT; 527 - rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp); 528 - tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; 529 - rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp); 530 - tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; 531 - rdev->config.cayman.backend_disable_mask_per_asic = 532 - cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK, 533 - rdev->config.cayman.num_shader_engines); 534 - rdev->config.cayman.backend_map = 535 - cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, 536 - rdev->config.cayman.num_backends_per_se * 537 - rdev->config.cayman.num_shader_engines, 538 - &rdev->config.cayman.backend_disable_mask_per_asic, 539 - rdev->config.cayman.num_shader_engines); 540 - tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT; 541 - rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp); 542 - tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT; 543 - rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; 544 - if (rdev->config.cayman.mem_max_burst_length_bytes > 512) 545 - rdev->config.cayman.mem_max_burst_length_bytes = 512; 546 709 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 547 710 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 548 711 if (rdev->config.cayman.mem_row_size_in_kb > 4) ··· 518 747 rdev->config.cayman.shader_engine_tile_size = 32; 519 748 rdev->config.cayman.num_gpus = 1; 520 749 rdev->config.cayman.multi_gpu_tile_size = 64; 521 - 522 - //gb_addr_config = 0x02011003 523 - #if 0 524 - gb_addr_config = RREG32(GB_ADDR_CONFIG); 525 - #else 526 - gb_addr_config = 0; 527 - switch (rdev->config.cayman.num_tile_pipes) { 528 - case 1: 529 - default: 530 - gb_addr_config |= NUM_PIPES(0); 531 - break; 532 - case 2: 533 - gb_addr_config |= NUM_PIPES(1); 534 - break; 535 - case 4: 536 - gb_addr_config |= NUM_PIPES(2); 537 - break; 538 - case 8: 539 - gb_addr_config |= NUM_PIPES(3); 540 - break; 541 - } 542 - 543 - tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1; 544 - gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp); 545 - gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1); 546 - tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1; 547 - gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp); 548 - switch (rdev->config.cayman.num_gpus) { 549 - case 1: 550 - default: 551 - gb_addr_config |= NUM_GPUS(0); 552 - break; 553 - case 2: 554 - gb_addr_config |= NUM_GPUS(1); 555 - break; 556 - case 4: 557 - gb_addr_config |= NUM_GPUS(2); 558 - break; 559 - } 560 - switch (rdev->config.cayman.multi_gpu_tile_size) { 561 - case 16: 562 - gb_addr_config |= MULTI_GPU_TILE_SIZE(0); 563 - break; 564 - case 32: 565 - default: 566 - gb_addr_config |= MULTI_GPU_TILE_SIZE(1); 567 - break; 568 - case 64: 569 - gb_addr_config |= MULTI_GPU_TILE_SIZE(2); 570 - break; 571 - case 128: 572 - gb_addr_config |= MULTI_GPU_TILE_SIZE(3); 573 - break; 574 - } 575 - switch (rdev->config.cayman.mem_row_size_in_kb) { 576 - case 1: 577 - default: 578 - gb_addr_config |= ROW_SIZE(0); 579 - break; 580 - case 2: 581 - gb_addr_config |= ROW_SIZE(1); 582 - break; 583 - case 4: 584 - gb_addr_config |= ROW_SIZE(2); 585 - break; 586 - } 587 - #endif 588 750 589 751 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; 590 752 rdev->config.cayman.num_tile_pipes = (1 << tmp); ··· 532 828 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; 533 829 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; 534 830 535 - //gb_backend_map = 0x76541032; 536 - #if 0 537 - gb_backend_map = RREG32(GB_BACKEND_MAP); 538 - #else 539 - gb_backend_map = 540 - cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, 541 - rdev->config.cayman.num_backends_per_se * 542 - rdev->config.cayman.num_shader_engines, 543 - &rdev->config.cayman.backend_disable_mask_per_asic, 544 - rdev->config.cayman.num_shader_engines); 545 - #endif 831 + 546 832 /* setup tiling info dword. gb_addr_config is not adequate since it does 547 833 * not have bank info, so create a custom tiling dword. 548 834 * bits 3:0 num_pipes ··· 560 866 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ 561 867 if (rdev->flags & RADEON_IS_IGP) 562 868 rdev->config.cayman.tile_config |= 1 << 4; 563 - else 564 - rdev->config.cayman.tile_config |= 565 - ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 869 + else { 870 + if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 871 + rdev->config.cayman.tile_config |= 1 << 4; 872 + else 873 + rdev->config.cayman.tile_config |= 0 << 4; 874 + } 566 875 rdev->config.cayman.tile_config |= 567 876 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 568 877 rdev->config.cayman.tile_config |= 569 878 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 570 879 571 - rdev->config.cayman.backend_map = gb_backend_map; 572 - WREG32(GB_BACKEND_MAP, gb_backend_map); 880 + tmp = 0; 881 + for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { 882 + u32 rb_disable_bitmap; 883 + 884 + WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 885 + WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 886 + rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; 887 + tmp <<= 4; 888 + tmp |= rb_disable_bitmap; 889 + } 890 + /* enabled rb are just the one not disabled :) */ 891 + disabled_rb_mask = tmp; 892 + 893 + WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 894 + WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 895 + 573 896 WREG32(GB_ADDR_CONFIG, gb_addr_config); 574 897 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 575 898 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 576 899 577 - /* primary versions */ 578 - WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 579 - WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 580 - WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 900 + tmp = gb_addr_config & NUM_PIPES_MASK; 901 + tmp = r6xx_remap_render_backend(rdev, tmp, 902 + rdev->config.cayman.max_backends_per_se * 903 + rdev->config.cayman.max_shader_engines, 904 + CAYMAN_MAX_BACKENDS, disabled_rb_mask); 905 + WREG32(GB_BACKEND_MAP, tmp); 581 906 907 + cgts_tcc_disable = 0xffff0000; 908 + for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) 909 + cgts_tcc_disable &= ~(1 << (16 + i)); 582 910 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); 583 911 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); 584 - 585 - /* user versions */ 586 - WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable); 587 - WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 588 - WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 589 - 590 912 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); 591 913 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); 592 914
+11
drivers/gpu/drm/radeon/nid.h
··· 41 41 #define CAYMAN_MAX_TCC 16 42 42 #define CAYMAN_MAX_TCC_MASK 0xFF 43 43 44 + #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 45 + #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 46 + 44 47 #define DMIF_ADDR_CONFIG 0xBD4 45 48 #define SRBM_GFX_CNTL 0x0E44 46 49 #define RINGID(x) (((x) & 0x3) << 0) ··· 151 148 #define CGTS_SYS_TCC_DISABLE 0x3F90 152 149 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 153 150 151 + #define RLC_GFX_INDEX 0x3FC4 152 + 154 153 #define CONFIG_MEMSIZE 0x5428 155 154 156 155 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 ··· 216 211 #define SOFT_RESET_TA (1 << 12) 217 212 #define SOFT_RESET_VGT (1 << 14) 218 213 #define SOFT_RESET_IA (1 << 15) 214 + 215 + #define GRBM_GFX_INDEX 0x802C 216 + #define INSTANCE_INDEX(x) ((x) << 0) 217 + #define SE_INDEX(x) ((x) << 16) 218 + #define INSTANCE_BROADCAST_WRITES (1 << 30) 219 + #define SE_BROADCAST_WRITES (1 << 31) 219 220 220 221 #define SCRATCH_REG0 0x8500 221 222 #define SCRATCH_REG1 0x8504
+65 -126
drivers/gpu/drm/radeon/r600.c
··· 1376 1376 return r600_gpu_soft_reset(rdev); 1377 1377 } 1378 1378 1379 - static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 1380 - u32 num_backends, 1381 - u32 backend_disable_mask) 1379 + u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1380 + u32 tiling_pipe_num, 1381 + u32 max_rb_num, 1382 + u32 total_max_rb_num, 1383 + u32 disabled_rb_mask) 1382 1384 { 1383 - u32 backend_map = 0; 1384 - u32 enabled_backends_mask; 1385 - u32 enabled_backends_count; 1386 - u32 cur_pipe; 1387 - u32 swizzle_pipe[R6XX_MAX_PIPES]; 1388 - u32 cur_backend; 1389 - u32 i; 1385 + u32 rendering_pipe_num, rb_num_width, req_rb_num; 1386 + u32 pipe_rb_ratio, pipe_rb_remain; 1387 + u32 data = 0, mask = 1 << (max_rb_num - 1); 1388 + unsigned i, j; 1390 1389 1391 - if (num_tile_pipes > R6XX_MAX_PIPES) 1392 - num_tile_pipes = R6XX_MAX_PIPES; 1393 - if (num_tile_pipes < 1) 1394 - num_tile_pipes = 1; 1395 - if (num_backends > R6XX_MAX_BACKENDS) 1396 - num_backends = R6XX_MAX_BACKENDS; 1397 - if (num_backends < 1) 1398 - num_backends = 1; 1390 + /* mask out the RBs that don't exist on that asic */ 1391 + disabled_rb_mask |= (0xff << max_rb_num) & 0xff; 1399 1392 1400 - enabled_backends_mask = 0; 1401 - enabled_backends_count = 0; 1402 - for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 1403 - if (((backend_disable_mask >> i) & 1) == 0) { 1404 - enabled_backends_mask |= (1 << i); 1405 - ++enabled_backends_count; 1393 + rendering_pipe_num = 1 << tiling_pipe_num; 1394 + req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1395 + BUG_ON(rendering_pipe_num < req_rb_num); 1396 + 1397 + pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1398 + pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1399 + 1400 + if (rdev->family <= CHIP_RV740) { 1401 + /* r6xx/r7xx */ 1402 + rb_num_width = 2; 1403 + } else { 1404 + /* eg+ */ 1405 + rb_num_width = 4; 1406 + } 1407 + 1408 + for (i = 0; i < max_rb_num; i++) { 1409 + if (!(mask & disabled_rb_mask)) { 1410 + for (j = 0; j < pipe_rb_ratio; j++) { 1411 + data <<= rb_num_width; 1412 + data |= max_rb_num - i - 1; 1413 + } 1414 + if (pipe_rb_remain) { 1415 + data <<= rb_num_width; 1416 + data |= max_rb_num - i - 1; 1417 + pipe_rb_remain--; 1418 + } 1406 1419 } 1407 - if (enabled_backends_count == num_backends) 1408 - break; 1420 + mask >>= 1; 1409 1421 } 1410 1422 1411 - if (enabled_backends_count == 0) { 1412 - enabled_backends_mask = 1; 1413 - enabled_backends_count = 1; 1414 - } 1415 - 1416 - if (enabled_backends_count != num_backends) 1417 - num_backends = enabled_backends_count; 1418 - 1419 - memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 1420 - switch (num_tile_pipes) { 1421 - case 1: 1422 - swizzle_pipe[0] = 0; 1423 - break; 1424 - case 2: 1425 - swizzle_pipe[0] = 0; 1426 - swizzle_pipe[1] = 1; 1427 - break; 1428 - case 3: 1429 - swizzle_pipe[0] = 0; 1430 - swizzle_pipe[1] = 1; 1431 - swizzle_pipe[2] = 2; 1432 - break; 1433 - case 4: 1434 - swizzle_pipe[0] = 0; 1435 - swizzle_pipe[1] = 1; 1436 - swizzle_pipe[2] = 2; 1437 - swizzle_pipe[3] = 3; 1438 - break; 1439 - case 5: 1440 - swizzle_pipe[0] = 0; 1441 - swizzle_pipe[1] = 1; 1442 - swizzle_pipe[2] = 2; 1443 - swizzle_pipe[3] = 3; 1444 - swizzle_pipe[4] = 4; 1445 - break; 1446 - case 6: 1447 - swizzle_pipe[0] = 0; 1448 - swizzle_pipe[1] = 2; 1449 - swizzle_pipe[2] = 4; 1450 - swizzle_pipe[3] = 5; 1451 - swizzle_pipe[4] = 1; 1452 - swizzle_pipe[5] = 3; 1453 - break; 1454 - case 7: 1455 - swizzle_pipe[0] = 0; 1456 - swizzle_pipe[1] = 2; 1457 - swizzle_pipe[2] = 4; 1458 - swizzle_pipe[3] = 6; 1459 - swizzle_pipe[4] = 1; 1460 - swizzle_pipe[5] = 3; 1461 - swizzle_pipe[6] = 5; 1462 - break; 1463 - case 8: 1464 - swizzle_pipe[0] = 0; 1465 - swizzle_pipe[1] = 2; 1466 - swizzle_pipe[2] = 4; 1467 - swizzle_pipe[3] = 6; 1468 - swizzle_pipe[4] = 1; 1469 - swizzle_pipe[5] = 3; 1470 - swizzle_pipe[6] = 5; 1471 - swizzle_pipe[7] = 7; 1472 - break; 1473 - } 1474 - 1475 - cur_backend = 0; 1476 - for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1477 - while (((1 << cur_backend) & enabled_backends_mask) == 0) 1478 - cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 1479 - 1480 - backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1481 - 1482 - cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 1483 - } 1484 - 1485 - return backend_map; 1423 + return data; 1486 1424 } 1487 1425 1488 1426 int r600_count_pipe_bits(uint32_t val) ··· 1438 1500 { 1439 1501 u32 tiling_config; 1440 1502 u32 ramcfg; 1441 - u32 backend_map; 1442 1503 u32 cc_rb_backend_disable; 1443 1504 u32 cc_gc_shader_pipe_config; 1444 1505 u32 tmp; ··· 1448 1511 u32 sq_thread_resource_mgmt = 0; 1449 1512 u32 sq_stack_resource_mgmt_1 = 0; 1450 1513 u32 sq_stack_resource_mgmt_2 = 0; 1514 + u32 disabled_rb_mask; 1451 1515 1452 - /* FIXME: implement */ 1516 + rdev->config.r600.tiling_group_size = 256; 1453 1517 switch (rdev->family) { 1454 1518 case CHIP_R600: 1455 1519 rdev->config.r600.max_pipes = 4; ··· 1554 1616 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1555 1617 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1556 1618 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1557 - if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) 1558 - rdev->config.r600.tiling_group_size = 512; 1559 - else 1560 - rdev->config.r600.tiling_group_size = 256; 1619 + 1561 1620 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1562 1621 if (tmp > 3) { 1563 1622 tiling_config |= ROW_TILING(3); ··· 1566 1631 tiling_config |= BANK_SWAPS(1); 1567 1632 1568 1633 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1569 - cc_rb_backend_disable |= 1570 - BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); 1634 + tmp = R6XX_MAX_BACKENDS - 1635 + r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); 1636 + if (tmp < rdev->config.r600.max_backends) { 1637 + rdev->config.r600.max_backends = tmp; 1638 + } 1571 1639 1572 - cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1573 - cc_gc_shader_pipe_config |= 1574 - INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); 1575 - cc_gc_shader_pipe_config |= 1576 - INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); 1640 + cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 1641 + tmp = R6XX_MAX_PIPES - 1642 + r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); 1643 + if (tmp < rdev->config.r600.max_pipes) { 1644 + rdev->config.r600.max_pipes = tmp; 1645 + } 1646 + tmp = R6XX_MAX_SIMDS - 1647 + r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 1648 + if (tmp < rdev->config.r600.max_simds) { 1649 + rdev->config.r600.max_simds = tmp; 1650 + } 1577 1651 1578 - backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, 1579 - (R6XX_MAX_BACKENDS - 1580 - r600_count_pipe_bits((cc_rb_backend_disable & 1581 - R6XX_MAX_BACKENDS_MASK) >> 16)), 1582 - (cc_rb_backend_disable >> 16)); 1652 + disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 1653 + tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1654 + tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 1655 + R6XX_MAX_BACKENDS, disabled_rb_mask); 1656 + tiling_config |= tmp << 16; 1657 + rdev->config.r600.backend_map = tmp; 1658 + 1583 1659 rdev->config.r600.tile_config = tiling_config; 1584 - rdev->config.r600.backend_map = backend_map; 1585 - tiling_config |= BACKEND_MAP(backend_map); 1586 1660 WREG32(GB_TILING_CONFIG, tiling_config); 1587 1661 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1588 1662 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1589 - 1590 - /* Setup pipes */ 1591 - WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1592 - WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1593 - WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1594 1663 1595 1664 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1596 1665 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
+2
drivers/gpu/drm/radeon/r600d.h
··· 219 219 #define BACKEND_MAP(x) ((x) << 16) 220 220 221 221 #define GB_TILING_CONFIG 0x98F0 222 + #define PIPE_TILING__SHIFT 1 223 + #define PIPE_TILING__MASK 0x0000000e 222 224 223 225 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 224 226 #define INACTIVE_QD_PIPES(x) ((x) << 8)
+5
drivers/gpu/drm/radeon/radeon.h
··· 1848 1848 extern void r600_hdmi_enable(struct drm_encoder *encoder); 1849 1849 extern void r600_hdmi_disable(struct drm_encoder *encoder); 1850 1850 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1851 + extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1852 + u32 tiling_pipe_num, 1853 + u32 max_rb_num, 1854 + u32 total_max_rb_num, 1855 + u32 enabled_rb_mask); 1851 1856 1852 1857 /* 1853 1858 * evergreen functions used by radeon_encoder.c
+18 -15
drivers/gpu/drm/radeon/radeon_cs.c
··· 147 147 sync_to_ring, p->ring); 148 148 } 149 149 150 + /* XXX: note that this is called from the legacy UMS CS ioctl as well */ 150 151 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) 151 152 { 152 153 struct drm_radeon_cs *cs = data; ··· 246 245 } 247 246 } 248 247 249 - if ((p->cs_flags & RADEON_CS_USE_VM) && 250 - !p->rdev->vm_manager.enabled) { 251 - DRM_ERROR("VM not active on asic!\n"); 252 - return -EINVAL; 248 + /* these are KMS only */ 249 + if (p->rdev) { 250 + if ((p->cs_flags & RADEON_CS_USE_VM) && 251 + !p->rdev->vm_manager.enabled) { 252 + DRM_ERROR("VM not active on asic!\n"); 253 + return -EINVAL; 254 + } 255 + 256 + /* we only support VM on SI+ */ 257 + if ((p->rdev->family >= CHIP_TAHITI) && 258 + ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { 259 + DRM_ERROR("VM required on SI+!\n"); 260 + return -EINVAL; 261 + } 262 + 263 + if (radeon_cs_get_ring(p, ring, priority)) 264 + return -EINVAL; 253 265 } 254 - 255 - /* we only support VM on SI+ */ 256 - if ((p->rdev->family >= CHIP_TAHITI) && 257 - ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { 258 - DRM_ERROR("VM required on SI+!\n"); 259 - return -EINVAL; 260 - } 261 - 262 - if (radeon_cs_get_ring(p, ring, priority)) 263 - return -EINVAL; 264 - 265 266 266 267 /* deal with non-vm */ 267 268 if ((p->chunk_ib_idx != -1) &&
+56 -218
drivers/gpu/drm/radeon/rv770.c
··· 151 151 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 152 152 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 153 153 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 154 + if (rdev->family == CHIP_RV740) 155 + WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); 154 156 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 155 157 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 156 158 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); ··· 365 363 /* 366 364 * Core functions 367 365 */ 368 - static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 369 - u32 num_tile_pipes, 370 - u32 num_backends, 371 - u32 backend_disable_mask) 372 - { 373 - u32 backend_map = 0; 374 - u32 enabled_backends_mask; 375 - u32 enabled_backends_count; 376 - u32 cur_pipe; 377 - u32 swizzle_pipe[R7XX_MAX_PIPES]; 378 - u32 cur_backend; 379 - u32 i; 380 - bool force_no_swizzle; 381 - 382 - if (num_tile_pipes > R7XX_MAX_PIPES) 383 - num_tile_pipes = R7XX_MAX_PIPES; 384 - if (num_tile_pipes < 1) 385 - num_tile_pipes = 1; 386 - if (num_backends > R7XX_MAX_BACKENDS) 387 - num_backends = R7XX_MAX_BACKENDS; 388 - if (num_backends < 1) 389 - num_backends = 1; 390 - 391 - enabled_backends_mask = 0; 392 - enabled_backends_count = 0; 393 - for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 394 - if (((backend_disable_mask >> i) & 1) == 0) { 395 - enabled_backends_mask |= (1 << i); 396 - ++enabled_backends_count; 397 - } 398 - if (enabled_backends_count == num_backends) 399 - break; 400 - } 401 - 402 - if (enabled_backends_count == 0) { 403 - enabled_backends_mask = 1; 404 - enabled_backends_count = 1; 405 - } 406 - 407 - if (enabled_backends_count != num_backends) 408 - num_backends = enabled_backends_count; 409 - 410 - switch (rdev->family) { 411 - case CHIP_RV770: 412 - case CHIP_RV730: 413 - force_no_swizzle = false; 414 - break; 415 - case CHIP_RV710: 416 - case CHIP_RV740: 417 - default: 418 - force_no_swizzle = true; 419 - break; 420 - } 421 - 422 - memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 423 - switch (num_tile_pipes) { 424 - case 1: 425 - swizzle_pipe[0] = 0; 426 - break; 427 - case 2: 428 - swizzle_pipe[0] = 0; 429 - swizzle_pipe[1] = 1; 430 - break; 431 - case 3: 432 - if (force_no_swizzle) { 433 - swizzle_pipe[0] = 0; 434 - swizzle_pipe[1] = 1; 435 - swizzle_pipe[2] = 2; 436 - } else { 437 - swizzle_pipe[0] = 0; 438 - swizzle_pipe[1] = 2; 439 - swizzle_pipe[2] = 1; 440 - } 441 - break; 442 - case 4: 443 - if (force_no_swizzle) { 444 - swizzle_pipe[0] = 0; 445 - swizzle_pipe[1] = 1; 446 - swizzle_pipe[2] = 2; 447 - swizzle_pipe[3] = 3; 448 - } else { 449 - swizzle_pipe[0] = 0; 450 - swizzle_pipe[1] = 2; 451 - swizzle_pipe[2] = 3; 452 - swizzle_pipe[3] = 1; 453 - } 454 - break; 455 - case 5: 456 - if (force_no_swizzle) { 457 - swizzle_pipe[0] = 0; 458 - swizzle_pipe[1] = 1; 459 - swizzle_pipe[2] = 2; 460 - swizzle_pipe[3] = 3; 461 - swizzle_pipe[4] = 4; 462 - } else { 463 - swizzle_pipe[0] = 0; 464 - swizzle_pipe[1] = 2; 465 - swizzle_pipe[2] = 4; 466 - swizzle_pipe[3] = 1; 467 - swizzle_pipe[4] = 3; 468 - } 469 - break; 470 - case 6: 471 - if (force_no_swizzle) { 472 - swizzle_pipe[0] = 0; 473 - swizzle_pipe[1] = 1; 474 - swizzle_pipe[2] = 2; 475 - swizzle_pipe[3] = 3; 476 - swizzle_pipe[4] = 4; 477 - swizzle_pipe[5] = 5; 478 - } else { 479 - swizzle_pipe[0] = 0; 480 - swizzle_pipe[1] = 2; 481 - swizzle_pipe[2] = 4; 482 - swizzle_pipe[3] = 5; 483 - swizzle_pipe[4] = 3; 484 - swizzle_pipe[5] = 1; 485 - } 486 - break; 487 - case 7: 488 - if (force_no_swizzle) { 489 - swizzle_pipe[0] = 0; 490 - swizzle_pipe[1] = 1; 491 - swizzle_pipe[2] = 2; 492 - swizzle_pipe[3] = 3; 493 - swizzle_pipe[4] = 4; 494 - swizzle_pipe[5] = 5; 495 - swizzle_pipe[6] = 6; 496 - } else { 497 - swizzle_pipe[0] = 0; 498 - swizzle_pipe[1] = 2; 499 - swizzle_pipe[2] = 4; 500 - swizzle_pipe[3] = 6; 501 - swizzle_pipe[4] = 3; 502 - swizzle_pipe[5] = 1; 503 - swizzle_pipe[6] = 5; 504 - } 505 - break; 506 - case 8: 507 - if (force_no_swizzle) { 508 - swizzle_pipe[0] = 0; 509 - swizzle_pipe[1] = 1; 510 - swizzle_pipe[2] = 2; 511 - swizzle_pipe[3] = 3; 512 - swizzle_pipe[4] = 4; 513 - swizzle_pipe[5] = 5; 514 - swizzle_pipe[6] = 6; 515 - swizzle_pipe[7] = 7; 516 - } else { 517 - swizzle_pipe[0] = 0; 518 - swizzle_pipe[1] = 2; 519 - swizzle_pipe[2] = 4; 520 - swizzle_pipe[3] = 6; 521 - swizzle_pipe[4] = 3; 522 - swizzle_pipe[5] = 1; 523 - swizzle_pipe[6] = 7; 524 - swizzle_pipe[7] = 5; 525 - } 526 - break; 527 - } 528 - 529 - cur_backend = 0; 530 - for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 531 - while (((1 << cur_backend) & enabled_backends_mask) == 0) 532 - cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 533 - 534 - backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 535 - 536 - cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 537 - } 538 - 539 - return backend_map; 540 - } 541 - 542 366 static void rv770_gpu_init(struct radeon_device *rdev) 543 367 { 544 368 int i, j, num_qd_pipes; ··· 380 552 u32 sq_thread_resource_mgmt; 381 553 u32 hdp_host_path_cntl; 382 554 u32 sq_dyn_gpr_size_simd_ab_0; 383 - u32 backend_map; 384 555 u32 gb_tiling_config = 0; 385 556 u32 cc_rb_backend_disable = 0; 386 557 u32 cc_gc_shader_pipe_config = 0; 387 558 u32 mc_arb_ramcfg; 388 - u32 db_debug4; 559 + u32 db_debug4, tmp; 560 + u32 inactive_pipes, shader_pipe_config; 561 + u32 disabled_rb_mask; 562 + unsigned active_number; 389 563 390 564 /* setup chip specs */ 565 + rdev->config.rv770.tiling_group_size = 256; 391 566 switch (rdev->family) { 392 567 case CHIP_RV770: 393 568 rdev->config.rv770.max_pipes = 4; ··· 501 670 /* setup tiling, simd, pipe config */ 502 671 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 503 672 673 + shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); 674 + inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; 675 + for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) { 676 + if (!(inactive_pipes & tmp)) { 677 + active_number++; 678 + } 679 + tmp <<= 1; 680 + } 681 + if (active_number == 1) { 682 + WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); 683 + } else { 684 + WREG32(SPI_CONFIG_CNTL, 0); 685 + } 686 + 687 + cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 688 + tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16); 689 + if (tmp < rdev->config.rv770.max_backends) { 690 + rdev->config.rv770.max_backends = tmp; 691 + } 692 + 693 + cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 694 + tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK); 695 + if (tmp < rdev->config.rv770.max_pipes) { 696 + rdev->config.rv770.max_pipes = tmp; 697 + } 698 + tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); 699 + if (tmp < rdev->config.rv770.max_simds) { 700 + rdev->config.rv770.max_simds = tmp; 701 + } 702 + 504 703 switch (rdev->config.rv770.max_tile_pipes) { 505 704 case 1: 506 705 default: 507 - gb_tiling_config |= PIPE_TILING(0); 706 + gb_tiling_config = PIPE_TILING(0); 508 707 break; 509 708 case 2: 510 - gb_tiling_config |= PIPE_TILING(1); 709 + gb_tiling_config = PIPE_TILING(1); 511 710 break; 512 711 case 4: 513 - gb_tiling_config |= PIPE_TILING(2); 712 + gb_tiling_config = PIPE_TILING(2); 514 713 break; 515 714 case 8: 516 - gb_tiling_config |= PIPE_TILING(3); 715 + gb_tiling_config = PIPE_TILING(3); 517 716 break; 518 717 } 519 718 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; 520 719 720 + disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; 721 + tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 722 + tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, 723 + R7XX_MAX_BACKENDS, disabled_rb_mask); 724 + gb_tiling_config |= tmp << 16; 725 + rdev->config.rv770.backend_map = tmp; 726 + 521 727 if (rdev->family == CHIP_RV770) 522 728 gb_tiling_config |= BANK_TILING(1); 523 - else 524 - gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 729 + else { 730 + if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 731 + gb_tiling_config |= BANK_TILING(1); 732 + else 733 + gb_tiling_config |= BANK_TILING(0); 734 + } 525 735 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); 526 736 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 527 - if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) 528 - rdev->config.rv770.tiling_group_size = 512; 529 - else 530 - rdev->config.rv770.tiling_group_size = 256; 531 737 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { 532 738 gb_tiling_config |= ROW_TILING(3); 533 739 gb_tiling_config |= SAMPLE_SPLIT(3); ··· 576 708 } 577 709 578 710 gb_tiling_config |= BANK_SWAPS(1); 579 - 580 - cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 581 - cc_rb_backend_disable |= 582 - BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); 583 - 584 - cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 585 - cc_gc_shader_pipe_config |= 586 - INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); 587 - cc_gc_shader_pipe_config |= 588 - INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); 589 - 590 - if (rdev->family == CHIP_RV740) 591 - backend_map = 0x28; 592 - else 593 - backend_map = r700_get_tile_pipe_to_backend_map(rdev, 594 - rdev->config.rv770.max_tile_pipes, 595 - (R7XX_MAX_BACKENDS - 596 - r600_count_pipe_bits((cc_rb_backend_disable & 597 - R7XX_MAX_BACKENDS_MASK) >> 16)), 598 - (cc_rb_backend_disable >> 16)); 599 - 600 711 rdev->config.rv770.tile_config = gb_tiling_config; 601 - rdev->config.rv770.backend_map = backend_map; 602 - gb_tiling_config |= BACKEND_MAP(backend_map); 603 712 604 713 WREG32(GB_TILING_CONFIG, gb_tiling_config); 605 714 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 606 715 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 607 - 608 - WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 609 - WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 610 - WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 611 - WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 612 716 613 717 WREG32(CGTS_SYS_TCC_DISABLE, 0); 614 718 WREG32(CGTS_TCC_DISABLE, 0); 615 719 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 616 720 WREG32(CGTS_USER_TCC_DISABLE, 0); 617 721 618 - num_qd_pipes = 619 - R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 722 + 723 + num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 620 724 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); 621 725 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); 622 726 ··· 648 808 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 649 809 650 810 WREG32(VGT_NUM_INSTANCES, 1); 651 - 652 - WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 653 811 654 812 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 655 813
+4
drivers/gpu/drm/radeon/rv770d.h
··· 106 106 #define BACKEND_MAP(x) ((x) << 16) 107 107 108 108 #define GB_TILING_CONFIG 0x98F0 109 + #define PIPE_TILING__SHIFT 1 110 + #define PIPE_TILING__MASK 0x0000000e 109 111 110 112 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 111 113 #define INACTIVE_QD_PIPES(x) ((x) << 8) 112 114 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 115 + #define INACTIVE_QD_PIPES_SHIFT 8 113 116 #define INACTIVE_SIMDS(x) ((x) << 16) 114 117 #define INACTIVE_SIMDS_MASK 0x00FF0000 115 118 ··· 177 174 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 178 175 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 179 176 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 177 + #define MC_VM_MD_L1_TLB3_CNTL 0x2698 180 178 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 181 179 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 182 180 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
+1
drivers/gpu/drm/ttm/ttm_bo.c
··· 1834 1834 spin_unlock(&glob->lru_lock); 1835 1835 (void) ttm_bo_cleanup_refs(bo, false, false, false); 1836 1836 kref_put(&bo->list_kref, ttm_bo_release_list); 1837 + spin_lock(&glob->lru_lock); 1837 1838 continue; 1838 1839 } 1839 1840
+1 -1
drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c
··· 66 66 cmd += sizeof(remap_cmd) / sizeof(uint32); 67 67 68 68 for (i = 0; i < num_pages; ++i) { 69 - if (VMW_PPN_SIZE > 4) 69 + if (VMW_PPN_SIZE <= 4) 70 70 *cmd = page_to_pfn(*pages++); 71 71 else 72 72 *((uint64_t *)cmd) = page_to_pfn(*pages++);