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drm/amd/display: limited pll vco w/a v2

[Why/How]
The w/a will cause reboot black screen issue.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Jingwen Zhu <Jingwen.Zhu@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Jingwen Zhu and committed by
Alex Deucher
3df95751 fa5f99ee

+4 -1
+1
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
··· 316 316 bool disable_sldo_opt; 317 317 bool enable_non_transparent_setconfig; 318 318 bool lower_hbr3_phy_ssc; 319 + bool override_hbr3_pll_vco; 319 320 }; 320 321 321 322 /**
+2 -1
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
··· 843 843 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 844 844 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 845 845 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 846 - uint32_t reserved : 6; /**< reserved */ 846 + uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ 847 + uint32_t reserved : 5; /**< reserved */ 847 848 } bits; /**< boot bits */ 848 849 uint32_t all; /**< 32-bit access to bits */ 849 850 };
+1
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
··· 377 377 boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; 378 378 boot_options.bits.power_optimization = params->power_optimization; 379 379 boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; 380 + boot_options.bits.override_hbr3_pll_vco = params->override_hbr3_pll_vco; 380 381 381 382 boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0; 382 383