Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
regulator: mt6358: Add supply names for MT6358 regulators
The DT bindings for MT6358 regulator now defines the supply names for the
PMIC.
Add support for them by adding .supply_name field settings for each
regulator.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230928085537.3246669-8-wenst@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Chen-Yu Tsai
and committed by
Mark Brown
3dfa8a70
9f3bec54
+51
-55
+51
-55
drivers/regulator/mt6358-regulator.c
+51
-55
drivers/regulator/mt6358-regulator.c
···
33
33
34
34
#define to_regulator_info(x) container_of((x), struct mt6358_regulator_info, desc)
35
35
36
-
#define MT6358_BUCK(match, vreg, min, max, step, \
37
-
vosel_mask, _da_vsel_reg, _da_vsel_mask, \
38
-
_modeset_reg, _modeset_shift) \
36
+
#define MT6358_BUCK(match, vreg, supply, min, max, step, \
37
+
vosel_mask, _da_vsel_reg, _da_vsel_mask, \
38
+
_modeset_reg, _modeset_shift) \
39
39
[MT6358_ID_##vreg] = { \
40
40
.desc = { \
41
41
.name = #vreg, \
42
+
.supply_name = supply, \
42
43
.of_match = of_match_ptr(match), \
43
44
.ops = &mt6358_volt_range_ops, \
44
45
.type = REGULATOR_VOLTAGE, \
···
62
61
.modeset_mask = BIT(_modeset_shift), \
63
62
}
64
63
65
-
#define MT6358_LDO(match, vreg, volt_ranges, enreg, enbit, vosel, vosel_mask) \
64
+
#define MT6358_LDO(match, vreg, supply, volt_ranges, enreg, enbit, vosel, vosel_mask) \
66
65
[MT6358_ID_##vreg] = { \
67
66
.desc = { \
68
67
.name = #vreg, \
68
+
.supply_name = supply, \
69
69
.of_match = of_match_ptr(match), \
70
70
.ops = &mt6358_volt_table_ops, \
71
71
.type = REGULATOR_VOLTAGE, \
···
87
85
.qi = BIT(15), \
88
86
}
89
87
90
-
#define MT6358_LDO1(match, vreg, min, max, step, \
91
-
_da_vsel_reg, _da_vsel_mask, \
92
-
vosel, vosel_mask) \
88
+
#define MT6358_LDO1(match, vreg, supply, min, max, step, \
89
+
_da_vsel_reg, _da_vsel_mask, vosel, vosel_mask) \
93
90
[MT6358_ID_##vreg] = { \
94
91
.desc = { \
95
92
.name = #vreg, \
93
+
.supply_name = supply, \
96
94
.of_match = of_match_ptr(match), \
97
95
.ops = &mt6358_volt_range_ops, \
98
96
.type = REGULATOR_VOLTAGE, \
···
112
110
.qi = BIT(0), \
113
111
}
114
112
115
-
#define MT6358_REG_FIXED(match, vreg, \
116
-
enreg, enbit, volt) \
113
+
#define MT6358_REG_FIXED(match, vreg, supply, enreg, enbit, volt) \
117
114
[MT6358_ID_##vreg] = { \
118
115
.desc = { \
119
116
.name = #vreg, \
117
+
.supply_name = supply, \
120
118
.of_match = of_match_ptr(match), \
121
119
.ops = &mt6358_volt_fixed_ops, \
122
120
.type = REGULATOR_VOLTAGE, \
···
453
451
454
452
/* The array is indexed by id(MT6358_ID_XXX) */
455
453
static const struct mt6358_regulator_info mt6358_regulators[] = {
456
-
MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
454
+
MT6358_BUCK("buck_vdram1", VDRAM1, "vsys-vdram1", 500000, 2087500, 12500,
457
455
0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, MT6358_VDRAM1_ANA_CON0, 8),
458
-
MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
456
+
MT6358_BUCK("buck_vcore", VCORE, "vsys-vcore", 500000, 1293750, 6250,
459
457
0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 1),
460
-
MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
458
+
MT6358_BUCK("buck_vpa", VPA, "vsys-vpa", 500000, 3650000, 50000,
461
459
0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, MT6358_VPA_ANA_CON0, 3),
462
-
MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
460
+
MT6358_BUCK("buck_vproc11", VPROC11, "vsys-vproc11", 500000, 1293750, 6250,
463
461
0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 1),
464
-
MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
462
+
MT6358_BUCK("buck_vproc12", VPROC12, "vsys-vproc12", 500000, 1293750, 6250,
465
463
0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 2),
466
-
MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
464
+
MT6358_BUCK("buck_vgpu", VGPU, "vsys-vgpu", 500000, 1293750, 6250,
467
465
0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 2),
468
-
MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
466
+
MT6358_BUCK("buck_vs2", VS2, "vsys-vs2", 500000, 2087500, 12500,
469
467
0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, MT6358_VS2_ANA_CON0, 8),
470
-
MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
468
+
MT6358_BUCK("buck_vmodem", VMODEM, "vsys-vmodem", 500000, 1293750, 6250,
471
469
0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8),
472
-
MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
470
+
MT6358_BUCK("buck_vs1", VS1, "vsys-vs1", 1000000, 2587500, 12500,
473
471
0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8),
474
-
MT6358_REG_FIXED("ldo_vrf12", VRF12,
475
-
MT6358_LDO_VRF12_CON0, 0, 1200000),
476
-
MT6358_REG_FIXED("ldo_vio18", VIO18,
477
-
MT6358_LDO_VIO18_CON0, 0, 1800000),
478
-
MT6358_REG_FIXED("ldo_vcamio", VCAMIO,
479
-
MT6358_LDO_VCAMIO_CON0, 0, 1800000),
480
-
MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
481
-
MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
482
-
MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
483
-
MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
484
-
MT6358_REG_FIXED("ldo_vaux18", VAUX18,
485
-
MT6358_LDO_VAUX18_CON0, 0, 1800000),
486
-
MT6358_REG_FIXED("ldo_vbif28", VBIF28,
487
-
MT6358_LDO_VBIF28_CON0, 0, 2800000),
488
-
MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
489
-
MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
490
-
MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
491
-
MT6358_REG_FIXED("ldo_vaud28", VAUD28,
492
-
MT6358_LDO_VAUD28_CON0, 0, 2800000),
493
-
MT6358_LDO("ldo_vdram2", VDRAM2, vdram2,
472
+
MT6358_REG_FIXED("ldo_vrf12", VRF12, "vs2-ldo2", MT6358_LDO_VRF12_CON0, 0, 1200000),
473
+
MT6358_REG_FIXED("ldo_vio18", VIO18, "vs1-ldo1", MT6358_LDO_VIO18_CON0, 0, 1800000),
474
+
MT6358_REG_FIXED("ldo_vcamio", VCAMIO, "vs1-ldo1", MT6358_LDO_VCAMIO_CON0, 0, 1800000),
475
+
MT6358_REG_FIXED("ldo_vcn18", VCN18, "vs1-ldo1", MT6358_LDO_VCN18_CON0, 0, 1800000),
476
+
MT6358_REG_FIXED("ldo_vfe28", VFE28, "vsys-ldo1", MT6358_LDO_VFE28_CON0, 0, 2800000),
477
+
MT6358_REG_FIXED("ldo_vcn28", VCN28, "vsys-ldo1", MT6358_LDO_VCN28_CON0, 0, 2800000),
478
+
MT6358_REG_FIXED("ldo_vxo22", VXO22, "vsys-ldo1", MT6358_LDO_VXO22_CON0, 0, 2200000),
479
+
MT6358_REG_FIXED("ldo_vaux18", VAUX18, "vsys-ldo1", MT6358_LDO_VAUX18_CON0, 0, 1800000),
480
+
MT6358_REG_FIXED("ldo_vbif28", VBIF28, "vsys-ldo1", MT6358_LDO_VBIF28_CON0, 0, 2800000),
481
+
MT6358_REG_FIXED("ldo_vio28", VIO28, "vsys-ldo2", MT6358_LDO_VIO28_CON0, 0, 2800000),
482
+
MT6358_REG_FIXED("ldo_va12", VA12, "vs2-ldo2", MT6358_LDO_VA12_CON0, 0, 1200000),
483
+
MT6358_REG_FIXED("ldo_vrf18", VRF18, "vs1-ldo1", MT6358_LDO_VRF18_CON0, 0, 1800000),
484
+
MT6358_REG_FIXED("ldo_vaud28", VAUD28, "vsys-ldo1", MT6358_LDO_VAUD28_CON0, 0, 2800000),
485
+
MT6358_LDO("ldo_vdram2", VDRAM2, "vs2-ldo1", vdram2,
494
486
MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf),
495
-
MT6358_LDO("ldo_vsim1", VSIM1, vsim,
487
+
MT6358_LDO("ldo_vsim1", VSIM1, "vsys-ldo1", vsim,
496
488
MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
497
-
MT6358_LDO("ldo_vibr", VIBR, vibr,
489
+
MT6358_LDO("ldo_vibr", VIBR, "vsys-ldo3", vibr,
498
490
MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
499
-
MT6358_LDO("ldo_vusb", VUSB, vusb,
491
+
MT6358_LDO("ldo_vusb", VUSB, "vsys-ldo1", vusb,
500
492
MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
501
-
MT6358_LDO("ldo_vcamd", VCAMD, vcamd,
493
+
MT6358_LDO("ldo_vcamd", VCAMD, "vs2-ldo4", vcamd,
502
494
MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00),
503
-
MT6358_LDO("ldo_vefuse", VEFUSE, vefuse,
495
+
MT6358_LDO("ldo_vefuse", VEFUSE, "vs1-ldo1", vefuse,
504
496
MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
505
-
MT6358_LDO("ldo_vmch", VMCH, vmch_vemc,
497
+
MT6358_LDO("ldo_vmch", VMCH, "vsys-ldo2", vmch_vemc,
506
498
MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
507
-
MT6358_LDO("ldo_vcama1", VCAMA1, vcama,
499
+
MT6358_LDO("ldo_vcama1", VCAMA1, "vsys-ldo3", vcama,
508
500
MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00),
509
-
MT6358_LDO("ldo_vemc", VEMC, vmch_vemc,
501
+
MT6358_LDO("ldo_vemc", VEMC, "vsys-ldo2", vmch_vemc,
510
502
MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
511
-
MT6358_LDO("ldo_vcn33", VCN33, vcn33,
503
+
MT6358_LDO("ldo_vcn33", VCN33, "vsys-ldo3", vcn33,
512
504
MT6358_LDO_VCN33_CON0_0, 0, MT6358_VCN33_ANA_CON0, 0x300),
513
-
MT6358_LDO("ldo_vcama2", VCAMA2, vcama,
505
+
MT6358_LDO("ldo_vcama2", VCAMA2, "vsys-ldo3", vcama,
514
506
MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00),
515
-
MT6358_LDO("ldo_vmc", VMC, vmc,
507
+
MT6358_LDO("ldo_vmc", VMC, "vsys-ldo2", vmc,
516
508
MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
517
-
MT6358_LDO("ldo_vldo28", VLDO28, vldo28,
509
+
MT6358_LDO("ldo_vldo28", VLDO28, "vsys-ldo2", vldo28,
518
510
MT6358_LDO_VLDO28_CON0_0, 0,
519
511
MT6358_VLDO28_ANA_CON0, 0x300),
520
-
MT6358_LDO("ldo_vsim2", VSIM2, vsim,
512
+
MT6358_LDO("ldo_vsim2", VSIM2, "vsys-ldo2", vsim,
521
513
MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
522
-
MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
514
+
MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, "vs2-ldo3", 500000, 1293750, 6250,
523
515
MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f),
524
-
MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
516
+
MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, "vs2-ldo3", 500000, 1293750, 6250,
525
517
MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f),
526
-
MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
518
+
MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, "vs2-ldo3", 500000, 1293750, 6250,
527
519
MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f),
528
-
MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
520
+
MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, "vs2-ldo3", 500000, 1293750, 6250,
529
521
MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f),
530
522
};
531
523