Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: only set XCC 0 related reg for rlc autoload
For RLC autoload, only set XCC id 0 related register to trigger
rlc autoload, no need to trigger muti-times for muti-xcc.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Likun Gao
and committed by
Alex Deucher
3e227861
08ba5ba0
+28
-44
+28
-44
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+28
-44
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
···
1043
1043
uint32_t rlc_g_offset, rlc_g_size;
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uint64_t gpu_addr;
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uint32_t data;
1046
-
int i, num_xcc = NUM_XCC(adev->gfx.xcc_mask);
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/* RLC autoload sequence 2: copy ucode */
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gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(adev);
···
1054
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rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size;
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gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start;
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1057
-
for (i = 0; i < num_xcc; i++) {
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-
WREG32_SOC15(GC, GET_INST(GC, i),
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-
regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1060
-
WREG32_SOC15(GC, GET_INST(GC, i),
1061
-
regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1058
+
WREG32_SOC15(GC, GET_INST(GC, 0),
1059
+
regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1060
+
WREG32_SOC15(GC, GET_INST(GC, 0),
1061
+
regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
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1063
-
WREG32_SOC15(GC, GET_INST(GC, i),
1064
-
regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1063
+
WREG32_SOC15(GC, GET_INST(GC, 0),
1064
+
regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1065
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1066
-
if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
1067
-
/* RLC autoload sequence 3: load IMU fw */
1068
-
if (adev->gfx.imu.funcs->load_microcode)
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-
adev->gfx.imu.funcs->load_microcode(adev);
1070
-
/* RLC autoload sequence 4 init IMU fw */
1071
-
if (adev->gfx.imu.funcs->setup_imu)
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-
adev->gfx.imu.funcs->setup_imu(adev);
1073
-
if (adev->gfx.imu.funcs->start_imu)
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-
adev->gfx.imu.funcs->start_imu(adev);
1066
+
if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
1067
+
/* RLC autoload sequence 3: load IMU fw */
1068
+
if (adev->gfx.imu.funcs->load_microcode)
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+
adev->gfx.imu.funcs->load_microcode(adev);
1070
+
/* RLC autoload sequence 4 init IMU fw */
1071
+
if (adev->gfx.imu.funcs->setup_imu)
1072
+
adev->gfx.imu.funcs->setup_imu(adev);
1073
+
if (adev->gfx.imu.funcs->start_imu)
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+
adev->gfx.imu.funcs->start_imu(adev);
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1076
-
/* RLC autoload sequence 5 disable gpa mode */
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gfx_v12_1_xcc_disable_gpa_mode(adev, i);
1078
-
} else {
1079
-
/* unhalt rlc to start autoload without imu */
1080
-
data = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE);
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data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);
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data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1083
-
WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE, data);
1084
-
WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
1085
-
}
1076
+
/* RLC autoload sequence 5 disable gpa mode */
1077
+
gfx_v12_1_xcc_disable_gpa_mode(adev, 0);
1078
+
} else {
1079
+
/* unhalt rlc to start autoload without imu */
1080
+
data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPM_THREAD_ENABLE);
1081
+
data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);
1082
+
data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1083
+
WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPM_THREAD_ENABLE, data);
1084
+
WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
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}
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return 0;
···
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mutex_unlock(&adev->srbm_mutex);
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}
1782
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1783
-
static int gfx_v12_1_xcc_wait_for_rlc_autoload_complete(struct amdgpu_device *adev,
1784
-
int xcc_id)
1786
+
static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
1785
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{
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uint32_t cp_status;
1787
1789
uint32_t bootload_status;
1788
-
int i;
1790
+
int i, xcc_id;
1789
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1790
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for (i = 0; i < adev->usec_timeout; i++) {
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cp_status = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_STAT);
···
1807
1811
}
1808
1812
1809
1813
if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1810
-
gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id);
1811
-
}
1812
-
1813
-
return 0;
1814
-
}
1815
-
1816
-
static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
1817
-
{
1818
-
int xcc_id, r;
1819
-
1820
-
for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {
1821
-
r = gfx_v12_1_xcc_wait_for_rlc_autoload_complete(adev, xcc_id);
1822
-
if (r)
1823
-
return r;
1814
+
for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++)
1815
+
gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id);
1824
1816
}
1825
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return 0;