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ASoC: fsl_sai: MCLK bind with TX/RX enable bit

On i.MX8MP, the sai MCLK is bound with TX/RX enable bit,
which means the TX/RE enable bit need to be enabled then
MCLK can be output on PAD.

Some codec (for example: WM8962) needs the MCLK output
earlier, otherwise there will be issue for codec
configuration.

Add new soc data "mclk_with_tere" for this platform and
enable the MCLK output in startup stage.

As "mclk_with_tere" only applied to i.MX8MP, currently
The soc data is shared with i.MX8MN, so need to add
an i.MX8MN own soc data with "mclk_with_tere" disabled.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com
Link: https://lore.kernel.org/r/1683273322-2525-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org

authored by

Shengjiu Wang and committed by
Mark Brown 3e4a8261 101b2383

+23 -3
+21 -3
sound/soc/fsl/fsl_sai.c
··· 1400 1400 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1401 1401 } 1402 1402 1403 - if (of_property_read_bool(np, "fsl,sai-mclk-direction-output") && 1403 + sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); 1404 + 1405 + if (sai->mclk_direction_output && 1404 1406 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1405 1407 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1406 1408 if (IS_ERR(gpr)) { ··· 1445 1443 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1446 1444 1447 1445 /* Select MCLK direction */ 1448 - if (of_property_read_bool(np, "fsl,sai-mclk-direction-output") && 1446 + if (sai->mclk_direction_output && 1449 1447 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1450 1448 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1451 1449 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); ··· 1564 1562 .max_register = FSL_SAI_MCTL, 1565 1563 }; 1566 1564 1565 + static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = { 1566 + .use_imx_pcm = true, 1567 + .use_edma = false, 1568 + .fifo_depth = 128, 1569 + .reg_offset = 8, 1570 + .mclk0_is_mclk1 = false, 1571 + .pins = 8, 1572 + .flags = 0, 1573 + .max_register = FSL_SAI_MDIV, 1574 + }; 1575 + 1567 1576 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1568 1577 .use_imx_pcm = true, 1569 1578 .use_edma = false, ··· 1584 1571 .pins = 8, 1585 1572 .flags = 0, 1586 1573 .max_register = FSL_SAI_MDIV, 1574 + .mclk_with_tere = true, 1587 1575 }; 1588 1576 1589 1577 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { ··· 1620 1606 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1621 1607 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1622 1608 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1623 - { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mp_data }, 1609 + { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data }, 1624 1610 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1625 1611 { /* sentinel */ } 1626 1612 }; ··· 1684 1670 ret = regcache_sync(sai->regmap); 1685 1671 if (ret) 1686 1672 goto disable_rx_clk; 1673 + 1674 + if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 1675 + regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), 1676 + FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 1687 1677 1688 1678 return 0; 1689 1679
+2
sound/soc/fsl/fsl_sai.h
··· 230 230 bool use_imx_pcm; 231 231 bool use_edma; 232 232 bool mclk0_is_mclk1; 233 + bool mclk_with_tere; 233 234 unsigned int fifo_depth; 234 235 unsigned int pins; 235 236 unsigned int reg_offset; ··· 288 287 bool synchronous[2]; 289 288 struct fsl_sai_dl_cfg *dl_cfg; 290 289 unsigned int dl_cfg_cnt; 290 + bool mclk_direction_output; 291 291 292 292 unsigned int mclk_id[2]; 293 293 unsigned int mclk_streams;