tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel

* 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel:
drm/i915: don't enable self-refresh on Ironlake
drm/i915: Double check that the wait_request is not pending before warning
Revert "drm/i915: Warn if we run out of FIFO space for a mode"
Revert "drm/i915: Allow LVDS on pipe A on gen4+"
Revert "drm/i915: Enable RC6 on Ironlake."

Linus Torvalds 3e6dce76 fbc14870

+31 -24
+15 -7
drivers/gpu/drm/i915/i915_irq.c
··· 1350 1350 i915_seqno_passed(i915_get_gem_seqno(dev, 1351 1351 &dev_priv->render_ring), 1352 1352 i915_get_tail_request(dev)->seqno)) { 1353 + bool missed_wakeup = false; 1354 + 1353 1355 dev_priv->hangcheck_count = 0; 1354 1356 1355 1357 /* Issue a wake-up to catch stuck h/w. */ 1356 - if (dev_priv->render_ring.waiting_gem_seqno | 1357 - dev_priv->bsd_ring.waiting_gem_seqno) { 1358 - DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n"); 1359 - if (dev_priv->render_ring.waiting_gem_seqno) 1360 - DRM_WAKEUP(&dev_priv->render_ring.irq_queue); 1361 - if (dev_priv->bsd_ring.waiting_gem_seqno) 1362 - DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); 1358 + if (dev_priv->render_ring.waiting_gem_seqno && 1359 + waitqueue_active(&dev_priv->render_ring.irq_queue)) { 1360 + DRM_WAKEUP(&dev_priv->render_ring.irq_queue); 1361 + missed_wakeup = true; 1363 1362 } 1363 + 1364 + if (dev_priv->bsd_ring.waiting_gem_seqno && 1365 + waitqueue_active(&dev_priv->bsd_ring.irq_queue)) { 1366 + DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); 1367 + missed_wakeup = true; 1368 + } 1369 + 1370 + if (missed_wakeup) 1371 + DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n"); 1364 1372 return; 1365 1373 } 1366 1374
+8
drivers/gpu/drm/i915/i915_reg.h
··· 2206 2206 #define WM1_LP_SR_EN (1<<31) 2207 2207 #define WM1_LP_LATENCY_SHIFT 24 2208 2208 #define WM1_LP_LATENCY_MASK (0x7f<<24) 2209 + #define WM1_LP_FBC_LP1_MASK (0xf<<20) 2210 + #define WM1_LP_FBC_LP1_SHIFT 20 2209 2211 #define WM1_LP_SR_MASK (0x1ff<<8) 2210 2212 #define WM1_LP_SR_SHIFT 8 2211 2213 #define WM1_LP_CURSOR_MASK (0x3f) 2214 + #define WM2_LP_ILK 0x4510c 2215 + #define WM2_LP_EN (1<<31) 2216 + #define WM3_LP_ILK 0x45110 2217 + #define WM3_LP_EN (1<<31) 2218 + #define WM1S_LP_ILK 0x45120 2219 + #define WM1S_LP_EN (1<<31) 2212 2220 2213 2221 /* Memory latency timer register */ 2214 2222 #define MLTR_ILK 0x11222
+8 -15
drivers/gpu/drm/i915/intel_display.c
··· 2767 2767 /* Don't promote wm_size to unsigned... */ 2768 2768 if (wm_size > (long)wm->max_wm) 2769 2769 wm_size = wm->max_wm; 2770 - if (wm_size <= 0) { 2770 + if (wm_size <= 0) 2771 2771 wm_size = wm->default_wm; 2772 - DRM_ERROR("Insufficient FIFO for plane, expect flickering:" 2773 - " entries required = %ld, available = %lu.\n", 2774 - entries_required + wm->guard_size, 2775 - wm->fifo_size); 2776 - } 2777 - 2778 2772 return wm_size; 2779 2773 } 2780 2774 ··· 3382 3388 reg_value = I915_READ(WM1_LP_ILK); 3383 3389 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK | 3384 3390 WM1_LP_CURSOR_MASK); 3385 - reg_value |= WM1_LP_SR_EN | 3386 - (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | 3391 + reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | 3387 3392 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm; 3388 3393 3389 3394 I915_WRITE(WM1_LP_ILK, reg_value); ··· 5668 5675 I915_WRITE(DISP_ARB_CTL, 5669 5676 (I915_READ(DISP_ARB_CTL) | 5670 5677 DISP_FBC_WM_DIS)); 5678 + I915_WRITE(WM3_LP_ILK, 0); 5679 + I915_WRITE(WM2_LP_ILK, 0); 5680 + I915_WRITE(WM1_LP_ILK, 0); 5671 5681 } 5672 5682 /* 5673 5683 * Based on the document from hardware guys the following bits ··· 5692 5696 ILK_DPFC_DIS2 | 5693 5697 ILK_CLK_FBC); 5694 5698 } 5695 - if (IS_GEN6(dev)) 5696 - return; 5699 + return; 5697 5700 } else if (IS_G4X(dev)) { 5698 5701 uint32_t dspclk_gate; 5699 5702 I915_WRITE(RENCLK_GATE_D1, 0); ··· 5753 5758 OUT_RING(MI_FLUSH); 5754 5759 ADVANCE_LP_RING(); 5755 5760 } 5756 - } else { 5761 + } else 5757 5762 DRM_DEBUG_KMS("Failed to allocate render context." 5758 - "Disable RC6\n"); 5759 - return; 5760 - } 5763 + "Disable RC6\n"); 5761 5764 } 5762 5765 5763 5766 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
-2
drivers/gpu/drm/i915/intel_lvds.c
··· 875 875 876 876 intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); 877 877 intel_encoder->crtc_mask = (1 << 1); 878 - if (IS_I965G(dev)) 879 - intel_encoder->crtc_mask |= (1 << 0); 880 878 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); 881 879 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 882 880 connector->display_info.subpixel_order = SubPixelHorizontalRGB;