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arm64: dts: qcom: ipq8074: fix Gen3 PCIe node

IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s

v2 is the final and production version that is actually supported by the
kernel, however it looks like PCIe related nodes were added for the v1 SoC.

Finish the PCIe fixup by using the correct compatible, adding missing ATU
register space, declaring max-link-speed, use correct ranges, add missing
clocks and resets.

Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113164449.906002-8-robimarko@gmail.com

authored by

Robert Marko and committed by
Bjorn Andersson 3e83a9c4 b6059031

+17 -13
+17 -13
arch/arm64/boot/dts/qcom/ipq8074.dtsi
··· 819 819 }; 820 820 821 821 pcie0: pci@20000000 { 822 - compatible = "qcom,pcie-ipq8074"; 822 + compatible = "qcom,pcie-ipq8074-gen3"; 823 823 reg = <0x20000000 0xf1d>, 824 824 <0x20000f20 0xa8>, 825 - <0x00080000 0x2000>, 825 + <0x20001000 0x1000>, 826 + <0x00080000 0x4000>, 826 827 <0x20100000 0x1000>; 827 - reg-names = "dbi", "elbi", "parf", "config"; 828 + reg-names = "dbi", "elbi", "atu", "parf", "config"; 828 829 device_type = "pci"; 829 830 linux,pci-domain = <0>; 830 831 bus-range = <0x00 0xff>; 831 832 num-lanes = <1>; 833 + max-link-speed = <3>; 832 834 #address-cells = <3>; 833 835 #size-cells = <2>; 834 836 ··· 838 836 phy-names = "pciephy"; 839 837 840 838 ranges = <0x81000000 0 0x20200000 0x20200000 841 - 0 0x100000 /* downstream I/O */ 842 - 0x82000000 0 0x20300000 0x20300000 843 - 0 0xd00000>; /* non-prefetchable memory */ 839 + 0 0x10000>, /* downstream I/O */ 840 + <0x82000000 0 0x20220000 0x20220000 841 + 0 0xfde0000>; /* non-prefetchable memory */ 844 842 845 843 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 846 844 interrupt-names = "msi"; ··· 858 856 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 859 857 <&gcc GCC_PCIE0_AXI_M_CLK>, 860 858 <&gcc GCC_PCIE0_AXI_S_CLK>, 861 - <&gcc GCC_PCIE0_AHB_CLK>, 862 - <&gcc GCC_PCIE0_AUX_CLK>; 863 - 859 + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 860 + <&gcc GCC_PCIE0_RCHNG_CLK>; 864 861 clock-names = "iface", 865 862 "axi_m", 866 863 "axi_s", 867 - "ahb", 868 - "aux"; 864 + "axi_bridge", 865 + "rchng"; 866 + 869 867 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 870 868 <&gcc GCC_PCIE0_SLEEP_ARES>, 871 869 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 872 870 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 873 871 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 874 872 <&gcc GCC_PCIE0_AHB_ARES>, 875 - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 873 + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 874 + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 876 875 reset-names = "pipe", 877 876 "sleep", 878 877 "sticky", 879 878 "axi_m", 880 879 "axi_s", 881 880 "ahb", 882 - "axi_m_sticky"; 881 + "axi_m_sticky", 882 + "axi_s_sticky"; 883 883 status = "disabled"; 884 884 }; 885 885 };