tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa

Pull Xtensa updates from Max Filippov:

- clean up PCI support code

- add defconfig and DTS for the 'virt' board

- abstract 'entry' and 'retw' uses in xtensa assembly in preparation
for XEA3/NX pipeline support

- random small cleanups

* tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa:
xtensa: virt: add defconfig and DTS
xtensa: abstract 'entry' and 'retw' in assembly code
xtensa: One function call less in bootmem_init()
xtensa: remove arch/xtensa/include/asm/types.h
xtensa: use generic pcibios_set_master and pcibios_enable_device
xtensa: drop dead PCI support code
xtensa/PCI: Remove unused variable

Linus Torvalds 3e859477 1ec4013b

+339 -269
+72
arch/xtensa/boot/dts/virt.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /dts-v1/; 3 + 4 + / { 5 + compatible = "cdns,xtensa-iss"; 6 + #address-cells = <1>; 7 + #size-cells = <1>; 8 + interrupt-parent = <&pic>; 9 + 10 + chosen { 11 + bootargs = "console=ttyS0,115200n8 debug"; 12 + }; 13 + 14 + memory@0 { 15 + device_type = "memory"; 16 + reg = <0x00000000 0x80000000>; 17 + }; 18 + 19 + cpus { 20 + #address-cells = <1>; 21 + #size-cells = <0>; 22 + cpu@0 { 23 + compatible = "cdns,xtensa-cpu"; 24 + reg = <0>; 25 + clocks = <&osc>; 26 + }; 27 + }; 28 + 29 + clocks { 30 + osc: osc { 31 + #clock-cells = <0>; 32 + compatible = "fixed-clock"; 33 + clock-frequency = <40000000>; 34 + }; 35 + }; 36 + 37 + pic: pic { 38 + compatible = "cdns,xtensa-pic"; 39 + /* one cell: internal irq number, 40 + * two cells: second cell == 0: internal irq number 41 + * second cell == 1: external irq number 42 + */ 43 + #address-cells = <0>; 44 + #interrupt-cells = <2>; 45 + interrupt-controller; 46 + }; 47 + 48 + pci { 49 + compatible = "pci-host-ecam-generic"; 50 + device_type = "pci"; 51 + #address-cells = <3>; 52 + #size-cells = <2>; 53 + #interrupt-cells = <0x1>; 54 + 55 + bus-range = <0x0 0x3f>; 56 + reg = <0xc0000000 0x04000000>; 57 + 58 + // BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2) 59 + ranges = <0x01000000 0x0 0xc4000000 0xc4000000 0x0 0x04000000>, 60 + <0x02000000 0x0 0xc8000000 0xc8000000 0x0 0x18000000>; 61 + 62 + // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(2) 63 + interrupt-map = < 64 + 0x0000 0x0 0x0 0x1 &pic 0x0 0x1 65 + 0x0800 0x0 0x0 0x1 &pic 0x1 0x1 66 + 0x1000 0x0 0x0 0x1 &pic 0x2 0x1 67 + 0x1800 0x0 0x0 0x1 &pic 0x3 0x1 68 + >; 69 + 70 + interrupt-map-mask = <0x1800 0x0 0x0 0x7>; 71 + }; 72 + };
+113
arch/xtensa/configs/virt_defconfig
··· 1 + CONFIG_SYSVIPC=y 2 + CONFIG_POSIX_MQUEUE=y 3 + CONFIG_NO_HZ_IDLE=y 4 + CONFIG_HIGH_RES_TIMERS=y 5 + CONFIG_PREEMPT=y 6 + CONFIG_IRQ_TIME_ACCOUNTING=y 7 + CONFIG_BSD_PROCESS_ACCT=y 8 + CONFIG_MEMCG=y 9 + CONFIG_CGROUP_FREEZER=y 10 + CONFIG_CGROUP_DEVICE=y 11 + CONFIG_CGROUP_CPUACCT=y 12 + CONFIG_CGROUP_DEBUG=y 13 + CONFIG_NAMESPACES=y 14 + CONFIG_SCHED_AUTOGROUP=y 15 + CONFIG_RELAY=y 16 + CONFIG_BLK_DEV_INITRD=y 17 + CONFIG_EXPERT=y 18 + CONFIG_SYSCTL_SYSCALL=y 19 + CONFIG_KALLSYMS_ALL=y 20 + CONFIG_PERF_EVENTS=y 21 + CONFIG_XTENSA_VARIANT_DC233C=y 22 + CONFIG_XTENSA_UNALIGNED_USER=y 23 + CONFIG_VECTORS_OFFSET=0x00002000 24 + CONFIG_XTENSA_KSEG_512M=y 25 + CONFIG_HIGHMEM=y 26 + CONFIG_CMDLINE_BOOL=y 27 + CONFIG_CMDLINE="console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x80000000@0" 28 + CONFIG_USE_OF=y 29 + CONFIG_BUILTIN_DTB_SOURCE="virt" 30 + # CONFIG_PARSE_BOOTPARAM is not set 31 + CONFIG_JUMP_LABEL=y 32 + CONFIG_MODULES=y 33 + CONFIG_MODULE_UNLOAD=y 34 + # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 35 + # CONFIG_COMPACTION is not set 36 + CONFIG_NET=y 37 + CONFIG_PACKET=y 38 + CONFIG_UNIX=y 39 + CONFIG_INET=y 40 + CONFIG_IP_MULTICAST=y 41 + CONFIG_IP_PNP=y 42 + CONFIG_IP_PNP_DHCP=y 43 + CONFIG_IP_PNP_BOOTP=y 44 + CONFIG_IP_PNP_RARP=y 45 + # CONFIG_IPV6 is not set 46 + CONFIG_NETFILTER=y 47 + # CONFIG_WIRELESS is not set 48 + CONFIG_PCI=y 49 + CONFIG_PCI_HOST_GENERIC=y 50 + CONFIG_UEVENT_HELPER=y 51 + CONFIG_DEVTMPFS=y 52 + CONFIG_DEVTMPFS_MOUNT=y 53 + # CONFIG_STANDALONE is not set 54 + CONFIG_BLK_DEV_LOOP=y 55 + CONFIG_BLK_DEV_RAM=y 56 + CONFIG_VIRTIO_BLK=y 57 + CONFIG_SCSI=y 58 + CONFIG_BLK_DEV_SD=y 59 + CONFIG_NETDEVICES=y 60 + CONFIG_VIRTIO_NET=y 61 + # CONFIG_ETHERNET is not set 62 + # CONFIG_WLAN is not set 63 + CONFIG_INPUT_MOUSEDEV=y 64 + CONFIG_INPUT_EVDEV=y 65 + # CONFIG_INPUT_KEYBOARD is not set 66 + # CONFIG_LEGACY_PTYS is not set 67 + CONFIG_HW_RANDOM=y 68 + CONFIG_HW_RANDOM_VIRTIO=y 69 + # CONFIG_HWMON is not set 70 + CONFIG_DRM=y 71 + CONFIG_DRM_VGEM=y 72 + CONFIG_DRM_VIRTIO_GPU=y 73 + CONFIG_FB_MODE_HELPERS=y 74 + # CONFIG_VGA_CONSOLE is not set 75 + CONFIG_FRAMEBUFFER_CONSOLE=y 76 + CONFIG_LOGO=y 77 + # CONFIG_USB_SUPPORT is not set 78 + CONFIG_VIRTIO_PCI=y 79 + CONFIG_VIRTIO_INPUT=y 80 + # CONFIG_IOMMU_SUPPORT is not set 81 + CONFIG_EXT3_FS=y 82 + CONFIG_FANOTIFY=y 83 + CONFIG_VFAT_FS=y 84 + CONFIG_PROC_KCORE=y 85 + CONFIG_TMPFS=y 86 + CONFIG_TMPFS_POSIX_ACL=y 87 + CONFIG_NFS_FS=y 88 + CONFIG_NFS_V4=y 89 + CONFIG_NFS_SWAP=y 90 + CONFIG_ROOT_NFS=y 91 + CONFIG_SUNRPC_DEBUG=y 92 + CONFIG_NLS_CODEPAGE_437=y 93 + CONFIG_NLS_ISO8859_1=y 94 + CONFIG_CRYPTO_ECHAINIV=y 95 + CONFIG_CRYPTO_DEFLATE=y 96 + CONFIG_CRYPTO_LZO=y 97 + CONFIG_CRYPTO_ANSI_CPRNG=y 98 + CONFIG_CRYPTO_DEV_VIRTIO=y 99 + CONFIG_FONTS=y 100 + CONFIG_PRINTK_TIME=y 101 + CONFIG_DYNAMIC_DEBUG=y 102 + CONFIG_DEBUG_INFO=y 103 + CONFIG_MAGIC_SYSRQ=y 104 + # CONFIG_SCHED_DEBUG is not set 105 + CONFIG_SCHEDSTATS=y 106 + CONFIG_DEBUG_RT_MUTEXES=y 107 + CONFIG_DEBUG_SPINLOCK=y 108 + CONFIG_DEBUG_MUTEXES=y 109 + CONFIG_DEBUG_ATOMIC_SLEEP=y 110 + CONFIG_STACKTRACE=y 111 + CONFIG_RCU_TRACE=y 112 + # CONFIG_FTRACE is not set 113 + # CONFIG_S32C1I_SELFTEST is not set
+46
arch/xtensa/include/asm/asmmacro.h
··· 191 191 #endif 192 192 .endm 193 193 194 + #define XTENSA_STACK_ALIGNMENT 16 195 + 196 + #if defined(__XTENSA_WINDOWED_ABI__) 197 + #define XTENSA_FRAME_SIZE_RESERVE 16 198 + #define XTENSA_SPILL_STACK_RESERVE 32 199 + 200 + #define abi_entry(frame_size) \ 201 + entry sp, (XTENSA_FRAME_SIZE_RESERVE + \ 202 + (((frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \ 203 + -XTENSA_STACK_ALIGNMENT)) 204 + #define abi_entry_default abi_entry(0) 205 + 206 + #define abi_ret(frame_size) retw 207 + #define abi_ret_default retw 208 + 209 + #elif defined(__XTENSA_CALL0_ABI__) 210 + 211 + #define XTENSA_SPILL_STACK_RESERVE 0 212 + 213 + #define abi_entry(frame_size) __abi_entry (frame_size) 214 + 215 + .macro __abi_entry frame_size 216 + .ifgt \frame_size 217 + addi sp, sp, -(((\frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \ 218 + -XTENSA_STACK_ALIGNMENT) 219 + .endif 220 + .endm 221 + 222 + #define abi_entry_default 223 + 224 + #define abi_ret(frame_size) __abi_ret (frame_size) 225 + 226 + .macro __abi_ret frame_size 227 + .ifgt \frame_size 228 + addi sp, sp, (((\frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \ 229 + -XTENSA_STACK_ALIGNMENT) 230 + .endif 231 + ret 232 + .endm 233 + 234 + #define abi_ret_default ret 235 + 236 + #else 237 + #error Unsupported Xtensa ABI 238 + #endif 239 + 194 240 #endif /* _XTENSA_ASMMACRO_H */
-10
arch/xtensa/include/asm/platform.h
··· 55 55 extern void platform_heartbeat (void); 56 56 57 57 /* 58 - * platform_pcibios_init is called to allow the platform to setup the pci bus. 59 - */ 60 - extern void platform_pcibios_init (void); 61 - 62 - /* 63 - * platform_pcibios_fixup allows to modify the PCI configuration. 64 - */ 65 - extern int platform_pcibios_fixup (void); 66 - 67 - /* 68 58 * platform_calibrate_ccount calibrates cpu clock freq (CONFIG_XTENSA_CALIBRATE) 69 59 */ 70 60 extern void platform_calibrate_ccount (void);
-23
arch/xtensa/include/asm/types.h
··· 1 - /* 2 - * include/asm-xtensa/types.h 3 - * 4 - * This file is subject to the terms and conditions of the GNU General Public 5 - * License. See the file "COPYING" in the main directory of this archive 6 - * for more details. 7 - * 8 - * Copyright (C) 2001 - 2005 Tensilica Inc. 9 - */ 10 - #ifndef _XTENSA_TYPES_H 11 - #define _XTENSA_TYPES_H 12 - 13 - #include <uapi/asm/types.h> 14 - 15 - #ifndef __ASSEMBLY__ 16 - /* 17 - * These aren't exported outside the kernel to avoid name space clashes 18 - */ 19 - 20 - #define BITS_PER_LONG 32 21 - 22 - #endif 23 - #endif /* _XTENSA_TYPES_H */
+5 -2
arch/xtensa/kernel/coprocessor.S
··· 121 121 122 122 ENTRY(coprocessor_flush) 123 123 124 - entry a1, 32 124 + /* reserve 4 bytes on stack to save a0 */ 125 + abi_entry(4) 126 + 125 127 s32i a0, a1, 0 126 128 movi a0, .Lsave_cp_regs_jump_table 127 129 addx8 a3, a3, a0 ··· 133 131 beqz a3, 1f 134 132 callx0 a3 135 133 1: l32i a0, a1, 0 136 - retw 134 + 135 + abi_ret(4) 137 136 138 137 ENDPROC(coprocessor_flush) 139 138
+6 -5
arch/xtensa/kernel/entry.S
··· 1842 1842 1843 1843 ENTRY(system_call) 1844 1844 1845 - entry a1, 32 1845 + /* reserve 4 bytes on stack for function parameter */ 1846 + abi_entry(4) 1846 1847 1847 1848 /* regs->syscall = regs->areg[2] */ 1848 1849 ··· 1893 1892 1894 1893 s32i a6, a2, PT_AREG2 1895 1894 bnez a3, 1f 1896 - retw 1895 + abi_ret(4) 1897 1896 1898 1897 1: 1899 1898 l32i a4, a1, 4 ··· 1902 1901 mov a6, a2 1903 1902 call4 do_syscall_trace_leave 1904 1903 s32i a3, a2, PT_SYSCALL 1905 - retw 1904 + abi_ret(4) 1906 1905 1907 1906 ENDPROC(system_call) 1908 1907 ··· 1953 1952 1954 1953 ENTRY(_switch_to) 1955 1954 1956 - entry a1, 48 1955 + abi_entry(XTENSA_SPILL_STACK_RESERVE) 1957 1956 1958 1957 mov a11, a3 # and 'next' (a3) 1959 1958 ··· 2014 2013 wsr a14, ps 2015 2014 rsync 2016 2015 2017 - retw 2016 + abi_ret(XTENSA_SPILL_STACK_RESERVE) 2018 2017 2019 2018 ENDPROC(_switch_to) 2020 2019
+6 -5
arch/xtensa/kernel/mcount.S
··· 11 11 */ 12 12 13 13 #include <linux/linkage.h> 14 + #include <asm/asmmacro.h> 14 15 #include <asm/ftrace.h> 15 16 16 17 /* ··· 22 21 23 22 ENTRY(_mcount) 24 23 25 - entry a1, 16 24 + abi_entry_default 26 25 27 26 movi a4, ftrace_trace_function 28 27 l32i a4, a4, 0 29 28 movi a3, ftrace_stub 30 29 bne a3, a4, 1f 31 - retw 30 + abi_ret_default 32 31 33 32 1: xor a7, a2, a1 34 33 movi a3, 0x3fffffff ··· 41 40 addi a6, a6, -MCOUNT_INSN_SIZE 42 41 callx4 a4 43 42 44 - retw 43 + abi_ret_default 45 44 46 45 ENDPROC(_mcount) 47 46 48 47 ENTRY(ftrace_stub) 49 - entry a1, 16 50 - retw 48 + abi_entry_default 49 + abi_ret_default 51 50 ENDPROC(ftrace_stub)
-124
arch/xtensa/kernel/pci.c
··· 24 24 #include <asm/pci-bridge.h> 25 25 #include <asm/platform.h> 26 26 27 - /* PCI Controller */ 28 - 29 - 30 - /* 31 - * pcibios_alloc_controller 32 - * pcibios_enable_device 33 - * pcibios_fixups 34 - * pcibios_align_resource 35 - * pcibios_fixup_bus 36 - * pci_bus_add_device 37 - */ 38 - 39 - static struct pci_controller *pci_ctrl_head; 40 - static struct pci_controller **pci_ctrl_tail = &pci_ctrl_head; 41 - 42 - static int pci_bus_count; 43 - 44 27 /* 45 28 * We need to avoid collisions with `mirrored' VGA ports 46 29 * and other strange ISA hardware, so we always want the ··· 58 75 return start; 59 76 } 60 77 61 - static void __init pci_controller_apertures(struct pci_controller *pci_ctrl, 62 - struct list_head *resources) 63 - { 64 - struct resource *res; 65 - unsigned long io_offset; 66 - int i; 67 - 68 - io_offset = (unsigned long)pci_ctrl->io_space.base; 69 - res = &pci_ctrl->io_resource; 70 - if (!res->flags) { 71 - if (io_offset) 72 - pr_err("I/O resource not set for host bridge %d\n", 73 - pci_ctrl->index); 74 - res->start = 0; 75 - res->end = IO_SPACE_LIMIT; 76 - res->flags = IORESOURCE_IO; 77 - } 78 - res->start += io_offset; 79 - res->end += io_offset; 80 - pci_add_resource_offset(resources, res, io_offset); 81 - 82 - for (i = 0; i < 3; i++) { 83 - res = &pci_ctrl->mem_resources[i]; 84 - if (!res->flags) { 85 - if (i > 0) 86 - continue; 87 - pr_err("Memory resource not set for host bridge %d\n", 88 - pci_ctrl->index); 89 - res->start = 0; 90 - res->end = ~0U; 91 - res->flags = IORESOURCE_MEM; 92 - } 93 - pci_add_resource(resources, res); 94 - } 95 - } 96 - 97 - static int __init pcibios_init(void) 98 - { 99 - struct pci_controller *pci_ctrl; 100 - struct list_head resources; 101 - struct pci_bus *bus; 102 - int next_busno = 0, ret; 103 - 104 - pr_info("PCI: Probing PCI hardware\n"); 105 - 106 - /* Scan all of the recorded PCI controllers. */ 107 - for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { 108 - pci_ctrl->last_busno = 0xff; 109 - INIT_LIST_HEAD(&resources); 110 - pci_controller_apertures(pci_ctrl, &resources); 111 - bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno, 112 - pci_ctrl->ops, pci_ctrl, &resources); 113 - if (!bus) 114 - continue; 115 - 116 - pci_ctrl->bus = bus; 117 - pci_ctrl->last_busno = bus->busn_res.end; 118 - if (next_busno <= pci_ctrl->last_busno) 119 - next_busno = pci_ctrl->last_busno+1; 120 - } 121 - pci_bus_count = next_busno; 122 - ret = platform_pcibios_fixup(); 123 - if (ret) 124 - return ret; 125 - 126 - for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { 127 - if (pci_ctrl->bus) 128 - pci_bus_add_devices(pci_ctrl->bus); 129 - } 130 - 131 - return 0; 132 - } 133 - 134 - subsys_initcall(pcibios_init); 135 - 136 78 void pcibios_fixup_bus(struct pci_bus *bus) 137 79 { 138 80 if (bus->parent) { 139 81 /* This is a subordinate bridge */ 140 82 pci_read_bridge_bases(bus); 141 83 } 142 - } 143 - 144 - void pcibios_set_master(struct pci_dev *dev) 145 - { 146 - /* No special bus mastering setup handling */ 147 - } 148 - 149 - int pcibios_enable_device(struct pci_dev *dev, int mask) 150 - { 151 - u16 cmd, old_cmd; 152 - int idx; 153 - struct resource *r; 154 - 155 - pci_read_config_word(dev, PCI_COMMAND, &cmd); 156 - old_cmd = cmd; 157 - for (idx=0; idx<6; idx++) { 158 - r = &dev->resource[idx]; 159 - if (!r->start && r->end) { 160 - pci_err(dev, "can't enable device: resource collisions\n"); 161 - return -EINVAL; 162 - } 163 - if (r->flags & IORESOURCE_IO) 164 - cmd |= PCI_COMMAND_IO; 165 - if (r->flags & IORESOURCE_MEM) 166 - cmd |= PCI_COMMAND_MEMORY; 167 - } 168 - if (cmd != old_cmd) { 169 - pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); 170 - pci_write_config_word(dev, PCI_COMMAND, cmd); 171 - } 172 - 173 - return 0; 174 84 } 175 85 176 86 /*
-2
arch/xtensa/kernel/platform.c
··· 34 34 _F(void, power_off, (void), { while(1); }); 35 35 _F(void, idle, (void), { __asm__ __volatile__ ("waiti 0" ::: "memory"); }); 36 36 _F(void, heartbeat, (void), { }); 37 - _F(int, pcibios_fixup, (void), { return 0; }); 38 - _F(void, pcibios_init, (void), { }); 39 37 40 38 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT 41 39 _F(void, calibrate_ccount, (void),
-4
arch/xtensa/kernel/setup.c
··· 405 405 conswitchp = &dummy_con; 406 406 # endif 407 407 #endif 408 - 409 - #ifdef CONFIG_PCI 410 - platform_pcibios_init(); 411 - #endif 412 408 } 413 409 414 410 static DEFINE_PER_CPU(struct cpu, cpu_data);
+6 -6
arch/xtensa/lib/checksum.S
··· 43 43 * Experiments with Ethernet and SLIP connections show that buf 44 44 * is aligned on either a 2-byte or 4-byte boundary. 45 45 */ 46 - entry sp, 32 46 + abi_entry_default 47 47 extui a5, a2, 0, 2 48 48 bnez a5, 8f /* branch if 2-byte aligned */ 49 49 /* Fall-through on common case, 4-byte alignment */ ··· 107 107 ONES_ADD(a4, a6) 108 108 7: 109 109 mov a2, a4 110 - retw 110 + abi_ret_default 111 111 112 112 /* uncommon case, buf is 2-byte aligned */ 113 113 8: ··· 195 195 196 196 ENTRY(csum_partial_copy_generic) 197 197 198 - entry sp, 32 198 + abi_entry_default 199 199 mov a12, a3 200 200 mov a11, a4 201 201 or a10, a2, a3 ··· 316 316 ONES_ADD(a5, a9) 317 317 8: 318 318 mov a2, a5 319 - retw 319 + abi_ret_default 320 320 321 321 5: 322 322 /* Control branch to here when either src or dst is odd. We ··· 383 383 blt a12, a11, .Leloop 384 384 #endif 385 385 2: 386 - retw 386 + abi_ret_default 387 387 388 388 11: 389 389 movi a2, -EFAULT 390 390 s32i a2, a7, 0 /* dst_err_ptr */ 391 391 movi a2, 0 392 - retw 392 + abi_ret_default 393 393 394 394 .previous
+19 -19
arch/xtensa/lib/memcopy.S
··· 79 79 bne a3, a7, .Lnextbyte # continue loop if $a3:src != $a7:src_end 80 80 #endif /* !XCHAL_HAVE_LOOPS */ 81 81 .Lbytecopydone: 82 - retw 82 + abi_ret_default 83 83 84 84 /* 85 85 * Destination is unaligned ··· 112 112 ENTRY(__memcpy) 113 113 WEAK(memcpy) 114 114 115 - entry sp, 16 # minimal stack frame 115 + abi_entry_default 116 116 # a2/ dst, a3/ src, a4/ len 117 117 mov a5, a2 # copy dst so that a2 is return value 118 118 .Lcommon: ··· 161 161 bbsi.l a4, 2, .L3 162 162 bbsi.l a4, 1, .L4 163 163 bbsi.l a4, 0, .L5 164 - retw 164 + abi_ret_default 165 165 .L3: 166 166 # copy 4 bytes 167 167 l32i a6, a3, 0 ··· 170 170 addi a5, a5, 4 171 171 bbsi.l a4, 1, .L4 172 172 bbsi.l a4, 0, .L5 173 - retw 173 + abi_ret_default 174 174 .L4: 175 175 # copy 2 bytes 176 176 l16ui a6, a3, 0 ··· 178 178 s16i a6, a5, 0 179 179 addi a5, a5, 2 180 180 bbsi.l a4, 0, .L5 181 - retw 181 + abi_ret_default 182 182 .L5: 183 183 # copy 1 byte 184 184 l8ui a6, a3, 0 185 185 s8i a6, a5, 0 186 - retw 186 + abi_ret_default 187 187 188 188 /* 189 189 * Destination is aligned, Source is unaligned ··· 255 255 #endif 256 256 bbsi.l a4, 1, .L14 257 257 bbsi.l a4, 0, .L15 258 - .Ldone: retw 258 + .Ldone: abi_ret_default 259 259 .L14: 260 260 # copy 2 bytes 261 261 l8ui a6, a3, 0 ··· 265 265 s8i a7, a5, 1 266 266 addi a5, a5, 2 267 267 bbsi.l a4, 0, .L15 268 - retw 268 + abi_ret_default 269 269 .L15: 270 270 # copy 1 byte 271 271 l8ui a6, a3, 0 272 272 s8i a6, a5, 0 273 - retw 273 + abi_ret_default 274 274 275 275 ENDPROC(__memcpy) 276 276 ··· 280 280 281 281 ENTRY(bcopy) 282 282 283 - entry sp, 16 # minimal stack frame 283 + abi_entry_default 284 284 # a2=src, a3=dst, a4=len 285 285 mov a5, a3 286 286 mov a3, a2 ··· 346 346 # $a3:src != $a7:src_start 347 347 #endif /* !XCHAL_HAVE_LOOPS */ 348 348 .Lbackbytecopydone: 349 - retw 349 + abi_ret_default 350 350 351 351 /* 352 352 * Destination is unaligned ··· 380 380 ENTRY(__memmove) 381 381 WEAK(memmove) 382 382 383 - entry sp, 16 # minimal stack frame 383 + abi_entry_default 384 384 # a2/ dst, a3/ src, a4/ len 385 385 mov a5, a2 # copy dst so that a2 is return value 386 386 .Lmovecommon: ··· 435 435 bbsi.l a4, 2, .Lback3 436 436 bbsi.l a4, 1, .Lback4 437 437 bbsi.l a4, 0, .Lback5 438 - retw 438 + abi_ret_default 439 439 .Lback3: 440 440 # copy 4 bytes 441 441 addi a3, a3, -4 ··· 444 444 s32i a6, a5, 0 445 445 bbsi.l a4, 1, .Lback4 446 446 bbsi.l a4, 0, .Lback5 447 - retw 447 + abi_ret_default 448 448 .Lback4: 449 449 # copy 2 bytes 450 450 addi a3, a3, -2 ··· 452 452 addi a5, a5, -2 453 453 s16i a6, a5, 0 454 454 bbsi.l a4, 0, .Lback5 455 - retw 455 + abi_ret_default 456 456 .Lback5: 457 457 # copy 1 byte 458 458 addi a3, a3, -1 459 459 l8ui a6, a3, 0 460 460 addi a5, a5, -1 461 461 s8i a6, a5, 0 462 - retw 462 + abi_ret_default 463 463 464 464 /* 465 465 * Destination is aligned, Source is unaligned ··· 531 531 bbsi.l a4, 1, .Lback14 532 532 bbsi.l a4, 0, .Lback15 533 533 .Lbackdone: 534 - retw 534 + abi_ret_default 535 535 .Lback14: 536 536 # copy 2 bytes 537 537 addi a3, a3, -2 ··· 541 541 s8i a6, a5, 0 542 542 s8i a7, a5, 1 543 543 bbsi.l a4, 0, .Lback15 544 - retw 544 + abi_ret_default 545 545 .Lback15: 546 546 # copy 1 byte 547 547 addi a3, a3, -1 548 548 addi a5, a5, -1 549 549 l8ui a6, a3, 0 550 550 s8i a6, a5, 0 551 - retw 551 + abi_ret_default 552 552 553 553 ENDPROC(__memmove)
+5 -5
arch/xtensa/lib/memset.S
··· 34 34 ENTRY(__memset) 35 35 WEAK(memset) 36 36 37 - entry sp, 16 # minimal stack frame 37 + abi_entry_default 38 38 # a2/ dst, a3/ c, a4/ length 39 39 extui a3, a3, 0, 8 # mask to just 8 bits 40 40 slli a7, a3, 8 # duplicate character in all bytes of word ··· 48 48 srli a7, a4, 4 # number of loop iterations with 16B 49 49 # per iteration 50 50 bnez a4, .Laligned 51 - retw 51 + abi_ret_default 52 52 53 53 /* 54 54 * Destination is word-aligned. ··· 95 95 EX(10f) s8i a3, a5, 0 96 96 .L5: 97 97 .Lret1: 98 - retw 98 + abi_ret_default 99 99 100 100 /* 101 101 * Destination is unaligned ··· 139 139 blt a5, a6, .Lbyteloop 140 140 #endif /* !XCHAL_HAVE_LOOPS */ 141 141 .Lbytesetdone: 142 - retw 142 + abi_ret_default 143 143 144 144 ENDPROC(__memset) 145 145 ··· 150 150 151 151 10: 152 152 movi a2, 0 153 - retw 153 + abi_ret_default
+8 -8
arch/xtensa/lib/strncpy_user.S
··· 50 50 .text 51 51 ENTRY(__strncpy_user) 52 52 53 - entry sp, 16 # minimal stack frame 53 + abi_entry_default 54 54 # a2/ dst, a3/ src, a4/ len 55 55 mov a11, a2 # leave dst in return value register 56 56 beqz a4, .Lret # if len is zero ··· 93 93 bnez a4, .Lsrcaligned # if len is nonzero 94 94 .Lret: 95 95 sub a2, a11, a2 # compute strlen 96 - retw 96 + abi_ret_default 97 97 98 98 /* 99 99 * dst is word-aligned, src is word-aligned ··· 148 148 .Lz3: # byte 3 is zero 149 149 addi a11, a11, 3 # advance dst pointer 150 150 sub a2, a11, a2 # compute strlen 151 - retw 151 + abi_ret_default 152 152 .Lz0: # byte 0 is zero 153 153 #ifdef __XTENSA_EB__ 154 154 movi a9, 0 155 155 #endif /* __XTENSA_EB__ */ 156 156 EX(10f) s8i a9, a11, 0 157 157 sub a2, a11, a2 # compute strlen 158 - retw 158 + abi_ret_default 159 159 .Lz1: # byte 1 is zero 160 160 #ifdef __XTENSA_EB__ 161 161 extui a9, a9, 16, 16 ··· 163 163 EX(10f) s16i a9, a11, 0 164 164 addi a11, a11, 1 # advance dst pointer 165 165 sub a2, a11, a2 # compute strlen 166 - retw 166 + abi_ret_default 167 167 .Lz2: # byte 2 is zero 168 168 #ifdef __XTENSA_EB__ 169 169 extui a9, a9, 16, 16 ··· 173 173 EX(10f) s8i a9, a11, 2 174 174 addi a11, a11, 2 # advance dst pointer 175 175 sub a2, a11, a2 # compute strlen 176 - retw 176 + abi_ret_default 177 177 178 178 .align 4 # 1 mod 4 alignment for LOOPNEZ 179 179 .byte 0 # (0 mod 4 alignment for LBEG) ··· 199 199 200 200 .Lunalignedend: 201 201 sub a2, a11, a2 # compute strlen 202 - retw 202 + abi_ret_default 203 203 204 204 ENDPROC(__strncpy_user) 205 205 ··· 214 214 10: 215 215 11: 216 216 movi a2, -EFAULT 217 - retw 217 + abi_ret_default
+7 -7
arch/xtensa/lib/strnlen_user.S
··· 45 45 .text 46 46 ENTRY(__strnlen_user) 47 47 48 - entry sp, 16 # minimal stack frame 48 + abi_entry_default 49 49 # a2/ s, a3/ len 50 50 addi a4, a2, -4 # because we overincrement at the end; 51 51 # we compensate with load offsets of 4 ··· 96 96 addi a4, a4, 1 # advance string pointer 97 97 .L101: 98 98 sub a2, a4, a2 # compute length 99 - retw 99 + abi_ret_default 100 100 101 101 # NOTE that in several places below, we point to the byte just after 102 102 # the zero byte in order to include the NULL terminator in the count. ··· 106 106 .Lz0: # byte 0 is zero 107 107 addi a4, a4, 1 # point just beyond zero byte 108 108 sub a2, a4, a2 # subtract to get length 109 - retw 109 + abi_ret_default 110 110 .Lz1: # byte 1 is zero 111 111 addi a4, a4, 1+1 # point just beyond zero byte 112 112 sub a2, a4, a2 # subtract to get length 113 - retw 113 + abi_ret_default 114 114 .Lz2: # byte 2 is zero 115 115 addi a4, a4, 2+1 # point just beyond zero byte 116 116 sub a2, a4, a2 # subtract to get length 117 - retw 117 + abi_ret_default 118 118 119 119 .L1mod2: # address is odd 120 120 EX(10f) l8ui a9, a4, 4 # get byte 0 ··· 130 130 # byte 3 is zero 131 131 addi a4, a4, 3+1 # point just beyond zero byte 132 132 sub a2, a4, a2 # subtract to get length 133 - retw 133 + abi_ret_default 134 134 135 135 ENDPROC(__strnlen_user) 136 136 ··· 138 138 .align 4 139 139 10: 140 140 movi a2, 0 141 - retw 141 + abi_ret_default
+6 -6
arch/xtensa/lib/usercopy.S
··· 60 60 .text 61 61 ENTRY(__xtensa_copy_user) 62 62 63 - entry sp, 16 # minimal stack frame 63 + abi_entry_default 64 64 # a2/ dst, a3/ src, a4/ len 65 65 mov a5, a2 # copy dst so that a2 is return value 66 66 mov a11, a4 # preserve original len for error case ··· 75 75 __ssa8 a3 # set shift amount from byte offset 76 76 bnez a4, .Lsrcunaligned 77 77 movi a2, 0 # return success for len==0 78 - retw 78 + abi_ret_default 79 79 80 80 /* 81 81 * Destination is unaligned ··· 127 127 #endif /* !XCHAL_HAVE_LOOPS */ 128 128 .Lbytecopydone: 129 129 movi a2, 0 # return success for len bytes copied 130 - retw 130 + abi_ret_default 131 131 132 132 /* 133 133 * Destination and source are word-aligned. ··· 187 187 EX(10f) s8i a6, a5, 0 188 188 .L5: 189 189 movi a2, 0 # return success for len bytes copied 190 - retw 190 + abi_ret_default 191 191 192 192 /* 193 193 * Destination is aligned, Source is unaligned ··· 264 264 EX(10f) s8i a6, a5, 0 265 265 .L15: 266 266 movi a2, 0 # return success for len bytes copied 267 - retw 267 + abi_ret_default 268 268 269 269 ENDPROC(__xtensa_copy_user) 270 270 ··· 281 281 10: 282 282 sub a2, a5, a2 /* a2 <-- bytes copied */ 283 283 sub a2, a11, a2 /* a2 <-- bytes not copied */ 284 - retw 284 + abi_ret_default
+1 -4
arch/xtensa/mm/init.c
··· 45 45 * If PHYS_OFFSET is zero reserve page at address 0: 46 46 * successfull allocations should never return NULL. 47 47 */ 48 - if (PHYS_OFFSET) 49 - memblock_reserve(0, PHYS_OFFSET); 50 - else 51 - memblock_reserve(0, 1); 48 + memblock_reserve(0, PHYS_OFFSET ? PHYS_OFFSET : 1); 52 49 53 50 early_init_fdt_scan_reserved_mem(); 54 51
+39 -39
arch/xtensa/mm/misc.S
··· 30 30 31 31 ENTRY(clear_page) 32 32 33 - entry a1, 16 33 + abi_entry_default 34 34 35 35 movi a3, 0 36 36 __loopi a2, a7, PAGE_SIZE, 32 ··· 44 44 s32i a3, a2, 28 45 45 __endla a2, a7, 32 46 46 47 - retw 47 + abi_ret_default 48 48 49 49 ENDPROC(clear_page) 50 50 ··· 57 57 58 58 ENTRY(copy_page) 59 59 60 - entry a1, 16 60 + abi_entry_default 61 61 62 62 __loopi a2, a4, PAGE_SIZE, 32 63 63 ··· 86 86 87 87 __endl a2, a4 88 88 89 - retw 89 + abi_ret_default 90 90 91 91 ENDPROC(copy_page) 92 92 ··· 116 116 117 117 ENTRY(clear_page_alias) 118 118 119 - entry a1, 32 119 + abi_entry_default 120 120 121 121 /* Skip setting up a temporary DTLB if not aliased low page. */ 122 122 ··· 144 144 __endla a2, a7, 32 145 145 146 146 bnez a6, 1f 147 - retw 147 + abi_ret_default 148 148 149 149 /* We need to invalidate the temporary idtlb entry, if any. */ 150 150 151 151 1: idtlb a4 152 152 dsync 153 153 154 - retw 154 + abi_ret_default 155 155 156 156 ENDPROC(clear_page_alias) 157 157 ··· 164 164 165 165 ENTRY(copy_page_alias) 166 166 167 - entry a1, 32 167 + abi_entry_default 168 168 169 169 /* Skip setting up a temporary DTLB for destination if not aliased. */ 170 170 ··· 221 221 222 222 bnez a6, 1f 223 223 bnez a7, 2f 224 - retw 224 + abi_ret_default 225 225 226 226 1: addi a2, a2, -PAGE_SIZE 227 227 idtlb a2 228 228 dsync 229 229 bnez a7, 2f 230 - retw 230 + abi_ret_default 231 231 232 232 2: addi a3, a3, -PAGE_SIZE+1 233 233 idtlb a3 234 234 dsync 235 235 236 - retw 236 + abi_ret_default 237 237 238 238 ENDPROC(copy_page_alias) 239 239 ··· 248 248 249 249 ENTRY(__flush_invalidate_dcache_page_alias) 250 250 251 - entry sp, 16 251 + abi_entry_default 252 252 253 253 movi a7, 0 # required for exception handler 254 254 addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) ··· 261 261 idtlb a4 262 262 dsync 263 263 264 - retw 264 + abi_ret_default 265 265 266 266 ENDPROC(__flush_invalidate_dcache_page_alias) 267 267 ··· 272 272 273 273 ENTRY(__invalidate_dcache_page_alias) 274 274 275 - entry sp, 16 275 + abi_entry_default 276 276 277 277 movi a7, 0 # required for exception handler 278 278 addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) ··· 285 285 idtlb a4 286 286 dsync 287 287 288 - retw 288 + abi_ret_default 289 289 290 290 ENDPROC(__invalidate_dcache_page_alias) 291 291 #endif ··· 296 296 297 297 ENTRY(__invalidate_icache_page_alias) 298 298 299 - entry sp, 16 299 + abi_entry_default 300 300 301 301 addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE) 302 302 mov a4, a2 ··· 307 307 308 308 iitlb a4 309 309 isync 310 - retw 310 + abi_ret_default 311 311 312 312 ENDPROC(__invalidate_icache_page_alias) 313 313 ··· 325 325 326 326 ENTRY(__invalidate_icache_page) 327 327 328 - entry sp, 16 328 + abi_entry_default 329 329 330 330 ___invalidate_icache_page a2 a3 331 331 isync 332 332 333 - retw 333 + abi_ret_default 334 334 335 335 ENDPROC(__invalidate_icache_page) 336 336 ··· 340 340 341 341 ENTRY(__invalidate_dcache_page) 342 342 343 - entry sp, 16 343 + abi_entry_default 344 344 345 345 ___invalidate_dcache_page a2 a3 346 346 dsync 347 347 348 - retw 348 + abi_ret_default 349 349 350 350 ENDPROC(__invalidate_dcache_page) 351 351 ··· 355 355 356 356 ENTRY(__flush_invalidate_dcache_page) 357 357 358 - entry sp, 16 358 + abi_entry_default 359 359 360 360 ___flush_invalidate_dcache_page a2 a3 361 361 362 362 dsync 363 - retw 363 + abi_ret_default 364 364 365 365 ENDPROC(__flush_invalidate_dcache_page) 366 366 ··· 370 370 371 371 ENTRY(__flush_dcache_page) 372 372 373 - entry sp, 16 373 + abi_entry_default 374 374 375 375 ___flush_dcache_page a2 a3 376 376 377 377 dsync 378 - retw 378 + abi_ret_default 379 379 380 380 ENDPROC(__flush_dcache_page) 381 381 ··· 385 385 386 386 ENTRY(__invalidate_icache_range) 387 387 388 - entry sp, 16 388 + abi_entry_default 389 389 390 390 ___invalidate_icache_range a2 a3 a4 391 391 isync 392 392 393 - retw 393 + abi_ret_default 394 394 395 395 ENDPROC(__invalidate_icache_range) 396 396 ··· 400 400 401 401 ENTRY(__flush_invalidate_dcache_range) 402 402 403 - entry sp, 16 403 + abi_entry_default 404 404 405 405 ___flush_invalidate_dcache_range a2 a3 a4 406 406 dsync 407 407 408 - retw 408 + abi_ret_default 409 409 410 410 ENDPROC(__flush_invalidate_dcache_range) 411 411 ··· 415 415 416 416 ENTRY(__flush_dcache_range) 417 417 418 - entry sp, 16 418 + abi_entry_default 419 419 420 420 ___flush_dcache_range a2 a3 a4 421 421 dsync 422 422 423 - retw 423 + abi_ret_default 424 424 425 425 ENDPROC(__flush_dcache_range) 426 426 ··· 430 430 431 431 ENTRY(__invalidate_dcache_range) 432 432 433 - entry sp, 16 433 + abi_entry_default 434 434 435 435 ___invalidate_dcache_range a2 a3 a4 436 436 437 - retw 437 + abi_ret_default 438 438 439 439 ENDPROC(__invalidate_dcache_range) 440 440 ··· 444 444 445 445 ENTRY(__invalidate_icache_all) 446 446 447 - entry sp, 16 447 + abi_entry_default 448 448 449 449 ___invalidate_icache_all a2 a3 450 450 isync 451 451 452 - retw 452 + abi_ret_default 453 453 454 454 ENDPROC(__invalidate_icache_all) 455 455 ··· 459 459 460 460 ENTRY(__flush_invalidate_dcache_all) 461 461 462 - entry sp, 16 462 + abi_entry_default 463 463 464 464 ___flush_invalidate_dcache_all a2 a3 465 465 dsync 466 466 467 - retw 467 + abi_ret_default 468 468 469 469 ENDPROC(__flush_invalidate_dcache_all) 470 470 ··· 474 474 475 475 ENTRY(__invalidate_dcache_all) 476 476 477 - entry sp, 16 477 + abi_entry_default 478 478 479 479 ___invalidate_dcache_all a2 a3 480 480 dsync 481 481 482 - retw 482 + abi_ret_default 483 483 484 484 ENDPROC(__invalidate_dcache_all)