Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
sh: Add in PCI bus for DMA API debugging.
sh: Pre-allocate a reasonable number of DMA debug entries.
sh: sh7786: modify usb setup timeout judgment bug.
MAINTAINERS: Update sh architecture file patterns.
sh: ap325: use edge control for ov772x camera
sh: Plug in support for ARCH=sh64 using sh SRCARCH.
sh: urquell: Fix up address mapping in board comments.
sh: Add support for DMA API debugging.
sh: Provide cpumask_of_pcibus() to fix NUMA build.
sh: urquell: Add board comment
sh: wire up sys_preadv/sys_pwritev() syscalls.
sh: sh7785lcr: fix PCI address map for 32-bit mode
sh: intc: Added resume from hibernation support to the intc
+179
-35
+2
MAINTAINERS
+2
MAINTAINERS
+6
-1
Makefile
+6
-1
Makefile
···
169
169
-e s/arm.*/arm/ -e s/sa110/arm/ \
170
170
-e s/s390x/s390/ -e s/parisc64/parisc/ \
171
171
-e s/ppc.*/powerpc/ -e s/mips.*/mips/ \
172
-
-e s/sh.*/sh/ )
172
+
-e s/sh[234].*/sh/ )
173
173
174
174
# Cross compiling and selecting different set of gcc/bin-utils
175
175
# ---------------------------------------------------------------------------
···
208
208
# Additional ARCH settings for sparc
209
209
ifeq ($(ARCH),sparc64)
210
210
SRCARCH := sparc
211
+
endif
212
+
213
+
# Additional ARCH settings for sh
214
+
ifeq ($(ARCH),sh64)
215
+
SRCARCH := sh
211
216
endif
212
217
213
218
# Where to locate arch specific headers
+16
-2
arch/sh/Kconfig
+16
-2
arch/sh/Kconfig
···
14
14
select HAVE_GENERIC_DMA_COHERENT
15
15
select HAVE_IOREMAP_PROT if MMU
16
16
select HAVE_ARCH_TRACEHOOK
17
+
select HAVE_DMA_API_DEBUG
17
18
help
18
19
The SuperH is a RISC processor targeted for use in embedded systems
19
20
and consumer electronics; it was also used in the Sega Dreamcast
···
22
21
<http://www.linux-sh.org/>.
23
22
24
23
config SUPERH32
25
-
def_bool !SUPERH64
24
+
def_bool ARCH = "sh"
26
25
select HAVE_KPROBES
27
26
select HAVE_KRETPROBES
28
27
select HAVE_FUNCTION_TRACER
···
32
31
select ARCH_HIBERNATION_POSSIBLE if MMU
33
32
34
33
config SUPERH64
35
-
def_bool y if CPU_SH5
34
+
def_bool ARCH = "sh64"
36
35
37
36
config ARCH_DEFCONFIG
38
37
string
···
187
186
config ARCH_SHMOBILE
188
187
bool
189
188
select ARCH_SUSPEND_POSSIBLE
189
+
190
+
if SUPERH32
190
191
191
192
choice
192
193
prompt "Processor sub-type selection"
···
411
408
select SYS_SUPPORTS_NUMA
412
409
select SYS_SUPPORTS_CMT
413
410
411
+
endchoice
412
+
413
+
endif
414
+
415
+
if SUPERH64
416
+
417
+
choice
418
+
prompt "Processor sub-type selection"
419
+
414
420
# SH-5 Processor Support
415
421
416
422
config CPU_SUBTYPE_SH5_101
···
431
419
select CPU_SH5
432
420
433
421
endchoice
422
+
423
+
endif
434
424
435
425
source "arch/sh/mm/Kconfig"
436
426
+1
arch/sh/boards/board-ap325rxa.c
+1
arch/sh/boards/board-ap325rxa.c
+30
arch/sh/boards/board-urquell.c
+30
arch/sh/boards/board-urquell.c
···
2
2
* Renesas Technology Corp. SH7786 Urquell Support.
3
3
*
4
4
* Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
5
+
*
6
+
* Based on board-sh7785lcr.c
5
7
* Copyright (C) 2008 Yoshihiro Shimoda
6
8
*
7
9
* This file is subject to the terms and conditions of the GNU General Public
···
23
21
#include <asm/heartbeat.h>
24
22
#include <asm/sizes.h>
25
23
24
+
/*
25
+
* bit 1234 5678
26
+
*----------------------------
27
+
* SW1 0101 0010 -> Pck 33MHz version
28
+
* (1101 0010) Pck 66MHz version
29
+
* SW2 0x1x xxxx -> little endian
30
+
* 29bit mode
31
+
* SW47 0001 1000 -> CS0 : on-board flash
32
+
* CS1 : SRAM, registers, LAN, PCMCIA
33
+
* 38400 bps for SCIF1
34
+
*
35
+
* Address
36
+
* 0x00000000 - 0x04000000 (CS0) Nor Flash
37
+
* 0x04000000 - 0x04200000 (CS1) SRAM
38
+
* 0x05000000 - 0x05800000 (CS1) on board register
39
+
* 0x05800000 - 0x06000000 (CS1) LAN91C111
40
+
* 0x06000000 - 0x06400000 (CS1) PCMCIA
41
+
* 0x08000000 - 0x10000000 (CS2-CS3) DDR3
42
+
* 0x10000000 - 0x14000000 (CS4) PCIe
43
+
* 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
44
+
* 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
45
+
* 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash
46
+
* 0x1C000000 - (CS7) SH7786 Control register
47
+
*/
48
+
49
+
/* HeartBeat */
26
50
static struct resource heartbeat_resources[] = {
27
51
[0] = {
28
52
.start = BOARDREG(SLEDR),
···
71
43
.resource = heartbeat_resources,
72
44
};
73
45
46
+
/* LAN91C111 */
74
47
static struct smc91x_platdata smc91x_info = {
75
48
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
76
49
};
···
98
69
},
99
70
};
100
71
72
+
/* Nor Flash */
101
73
static struct mtd_partition nor_flash_partitions[] = {
102
74
{
103
75
.name = "loader",
+5
arch/sh/drivers/pci/ops-sh7785lcr.c
+5
arch/sh/drivers/pci/ops-sh7785lcr.c
···
48
48
49
49
static struct sh4_pci_address_map sh7785_pci_map = {
50
50
.window0 = {
51
+
#if defined(CONFIG_32BIT)
52
+
.base = SH7780_32BIT_DDR_BASE_ADDR,
53
+
.size = 0x40000000,
54
+
#else
51
55
.base = SH7780_CS0_BASE_ADDR,
52
56
.size = 0x20000000,
57
+
#endif
53
58
},
54
59
55
60
.flags = SH4_PCIC_NO_RESET,
+2
arch/sh/drivers/pci/pci-sh7780.h
+2
arch/sh/drivers/pci/pci-sh7780.h
···
104
104
#define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
105
105
#define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)
106
106
107
+
#define SH7780_32BIT_DDR_BASE_ADDR 0x40000000
108
+
107
109
struct sh4_pci_address_map;
108
110
109
111
/* arch/sh/drivers/pci/pci-sh7780.c */
+3
arch/sh/drivers/pci/pci.c
+3
arch/sh/drivers/pci/pci.c
···
19
19
#include <linux/kernel.h>
20
20
#include <linux/pci.h>
21
21
#include <linux/init.h>
22
+
#include <linux/dma-debug.h>
22
23
#include <asm/io.h>
23
24
24
25
static int __init pcibios_init(void)
···
43
42
}
44
43
45
44
pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
45
+
46
+
dma_debug_add_bus(&pci_bus_type);
46
47
47
48
return 0;
48
49
}
+31
-5
arch/sh/include/asm/dma-mapping.h
+31
-5
arch/sh/include/asm/dma-mapping.h
···
3
3
4
4
#include <linux/mm.h>
5
5
#include <linux/scatterlist.h>
6
+
#include <linux/dma-debug.h>
6
7
#include <asm/cacheflush.h>
7
8
#include <asm/io.h>
8
9
#include <asm-generic/dma-coherent.h>
···
39
38
void *ptr, size_t size,
40
39
enum dma_data_direction dir)
41
40
{
41
+
dma_addr_t addr = virt_to_phys(ptr);
42
+
42
43
#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
43
44
if (dev->bus == &pci_bus_type)
44
-
return virt_to_phys(ptr);
45
+
return addr;
45
46
#endif
46
47
dma_cache_sync(dev, ptr, size, dir);
47
48
48
-
return virt_to_phys(ptr);
49
+
debug_dma_map_page(dev, virt_to_page(ptr),
50
+
(unsigned long)ptr & ~PAGE_MASK, size,
51
+
dir, addr, true);
52
+
53
+
return addr;
49
54
}
50
55
51
-
#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
56
+
static inline void dma_unmap_single(struct device *dev, dma_addr_t addr,
57
+
size_t size, enum dma_data_direction dir)
58
+
{
59
+
debug_dma_unmap_page(dev, addr, size, dir, true);
60
+
}
52
61
53
62
static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
54
63
int nents, enum dma_data_direction dir)
···
70
59
dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
71
60
#endif
72
61
sg[i].dma_address = sg_phys(&sg[i]);
62
+
sg[i].dma_length = sg[i].length;
73
63
}
64
+
65
+
debug_dma_map_sg(dev, sg, nents, i, dir);
74
66
75
67
return nents;
76
68
}
77
69
78
-
#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
70
+
static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
71
+
int nents, enum dma_data_direction dir)
72
+
{
73
+
debug_dma_unmap_sg(dev, sg, nents, dir);
74
+
}
79
75
80
76
static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
81
77
unsigned long offset, size_t size,
···
129
111
dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
130
112
#endif
131
113
sg[i].dma_address = sg_phys(&sg[i]);
114
+
sg[i].dma_length = sg[i].length;
132
115
}
133
116
}
134
117
···
138
119
enum dma_data_direction dir)
139
120
{
140
121
dma_sync_single(dev, dma_handle, size, dir);
122
+
debug_dma_sync_single_for_cpu(dev, dma_handle, size, dir);
141
123
}
142
124
143
125
static inline void dma_sync_single_for_device(struct device *dev,
···
147
127
enum dma_data_direction dir)
148
128
{
149
129
dma_sync_single(dev, dma_handle, size, dir);
130
+
debug_dma_sync_single_for_device(dev, dma_handle, size, dir);
150
131
}
151
132
152
133
static inline void dma_sync_single_range_for_cpu(struct device *dev,
···
157
136
enum dma_data_direction direction)
158
137
{
159
138
dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
139
+
debug_dma_sync_single_range_for_cpu(dev, dma_handle,
140
+
offset, size, direction);
160
141
}
161
142
162
143
static inline void dma_sync_single_range_for_device(struct device *dev,
···
168
145
enum dma_data_direction direction)
169
146
{
170
147
dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
148
+
debug_dma_sync_single_range_for_device(dev, dma_handle,
149
+
offset, size, direction);
171
150
}
172
151
173
152
···
178
153
enum dma_data_direction dir)
179
154
{
180
155
dma_sync_sg(dev, sg, nelems, dir);
156
+
debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir);
181
157
}
182
158
183
159
static inline void dma_sync_sg_for_device(struct device *dev,
···
186
160
enum dma_data_direction dir)
187
161
{
188
162
dma_sync_sg(dev, sg, nelems, dir);
163
+
debug_dma_sync_sg_for_device(dev, sg, nelems, dir);
189
164
}
190
-
191
165
192
166
static inline int dma_get_cache_alignment(void)
193
167
{
+6
-5
arch/sh/include/asm/scatterlist.h
+6
-5
arch/sh/include/asm/scatterlist.h
···
5
5
6
6
struct scatterlist {
7
7
#ifdef CONFIG_DEBUG_SG
8
-
unsigned long sg_magic;
8
+
unsigned long sg_magic;
9
9
#endif
10
-
unsigned long page_link;
11
-
unsigned int offset;/* for highmem, page offset */
12
-
dma_addr_t dma_address;
13
-
unsigned int length;
10
+
unsigned long page_link;
11
+
unsigned int offset; /* for highmem, page offset */
12
+
unsigned int length;
13
+
dma_addr_t dma_address;
14
+
unsigned int dma_length;
14
15
};
15
16
16
17
#define ISA_DMA_THRESHOLD PHYS_ADDR_MASK
+5
-2
arch/sh/include/asm/topology.h
+5
-2
arch/sh/include/asm/topology.h
···
37
37
#define pcibus_to_node(bus) ((void)(bus), -1)
38
38
#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
39
39
CPU_MASK_ALL : \
40
-
node_to_cpumask(pcibus_to_node(bus)) \
41
-
)
40
+
node_to_cpumask(pcibus_to_node(bus)))
41
+
#define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? \
42
+
CPU_MASK_ALL_PTR : \
43
+
cpumask_of_node(pcibus_to_node(bus)))
44
+
42
45
#endif
43
46
44
47
#include <asm-generic/topology.h>
+3
-1
arch/sh/include/asm/unistd_32.h
+3
-1
arch/sh/include/asm/unistd_32.h
+3
-1
arch/sh/include/asm/unistd_64.h
+3
-1
arch/sh/include/asm/unistd_64.h
···
381
381
#define __NR_dup3 358
382
382
#define __NR_pipe2 359
383
383
#define __NR_inotify_init1 360
384
+
#define __NR_preadv 361
385
+
#define __NR_pwritev 362
384
386
385
387
#ifdef __KERNEL__
386
388
387
-
#define NR_syscalls 361
389
+
#define NR_syscalls 363
388
390
389
391
#define __ARCH_WANT_IPC_PARSE_VERSION
390
392
#define __ARCH_WANT_OLD_READDIR
+7
-7
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+7
-7
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
···
143
143
* Set the PHY and PLL enable bit
144
144
*/
145
145
__raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
146
-
while (i-- &&
147
-
((__raw_readl(USBST) & ACT_PLL_STATUS) != ACT_PLL_STATUS))
146
+
while (i--) {
147
+
if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
148
+
/* Set the PHY RST bit */
149
+
__raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
150
+
printk(KERN_INFO "sh7786 usb setup done\n");
151
+
break;
152
+
}
148
153
cpu_relax();
149
-
150
-
if (i) {
151
-
/* Set the PHY RST bit */
152
-
__raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
153
-
printk(KERN_INFO "sh7786 usb setup done\n");
154
154
}
155
155
}
156
156
+2
arch/sh/kernel/syscalls_32.S
+2
arch/sh/kernel/syscalls_32.S
+2
arch/sh/kernel/syscalls_64.S
+2
arch/sh/kernel/syscalls_64.S
+24
-7
arch/sh/mm/consistent.c
+24
-7
arch/sh/mm/consistent.c
···
10
10
* for more details.
11
11
*/
12
12
#include <linux/mm.h>
13
+
#include <linux/init.h>
13
14
#include <linux/platform_device.h>
14
15
#include <linux/dma-mapping.h>
16
+
#include <linux/dma-debug.h>
17
+
#include <linux/io.h>
15
18
#include <asm/cacheflush.h>
16
19
#include <asm/addrspace.h>
17
-
#include <asm/io.h>
20
+
21
+
#define PREALLOC_DMA_DEBUG_ENTRIES 4096
22
+
23
+
static int __init dma_init(void)
24
+
{
25
+
dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
26
+
return 0;
27
+
}
28
+
fs_initcall(dma_init);
18
29
19
30
void *dma_alloc_coherent(struct device *dev, size_t size,
20
31
dma_addr_t *dma_handle, gfp_t gfp)
···
56
45
split_page(pfn_to_page(virt_to_phys(ret) >> PAGE_SHIFT), order);
57
46
58
47
*dma_handle = virt_to_phys(ret);
48
+
49
+
debug_dma_alloc_coherent(dev, size, *dma_handle, ret_nocache);
50
+
59
51
return ret_nocache;
60
52
}
61
53
EXPORT_SYMBOL(dma_alloc_coherent);
···
70
56
unsigned long pfn = dma_handle >> PAGE_SHIFT;
71
57
int k;
72
58
73
-
if (!dma_release_from_coherent(dev, order, vaddr)) {
74
-
WARN_ON(irqs_disabled()); /* for portability */
75
-
for (k = 0; k < (1 << order); k++)
76
-
__free_pages(pfn_to_page(pfn + k), 0);
77
-
iounmap(vaddr);
78
-
}
59
+
WARN_ON(irqs_disabled()); /* for portability */
60
+
61
+
if (dma_release_from_coherent(dev, order, vaddr))
62
+
return;
63
+
64
+
debug_dma_free_coherent(dev, size, vaddr, dma_handle);
65
+
for (k = 0; k < (1 << order); k++)
66
+
__free_pages(pfn_to_page(pfn + k), 0);
67
+
iounmap(vaddr);
79
68
}
80
69
EXPORT_SYMBOL(dma_free_coherent);
81
70
+31
-4
drivers/sh/intc.c
+31
-4
drivers/sh/intc.c
···
44
44
struct intc_desc_int {
45
45
struct list_head list;
46
46
struct sys_device sysdev;
47
+
pm_message_t state;
47
48
unsigned long *reg;
48
49
#ifdef CONFIG_SMP
49
50
unsigned long *smp;
···
787
786
/* get intc controller associated with this sysdev */
788
787
d = container_of(dev, struct intc_desc_int, sysdev);
789
788
790
-
/* enable wakeup irqs belonging to this intc controller */
791
-
for_each_irq_desc(irq, desc) {
792
-
if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
793
-
intc_enable(irq);
789
+
switch (state.event) {
790
+
case PM_EVENT_ON:
791
+
if (d->state.event != PM_EVENT_FREEZE)
792
+
break;
793
+
for_each_irq_desc(irq, desc) {
794
+
if (desc->chip != &d->chip)
795
+
continue;
796
+
if (desc->status & IRQ_DISABLED)
797
+
intc_disable(irq);
798
+
else
799
+
intc_enable(irq);
800
+
}
801
+
break;
802
+
case PM_EVENT_FREEZE:
803
+
/* nothing has to be done */
804
+
break;
805
+
case PM_EVENT_SUSPEND:
806
+
/* enable wakeup irqs belonging to this intc controller */
807
+
for_each_irq_desc(irq, desc) {
808
+
if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
809
+
intc_enable(irq);
810
+
}
811
+
break;
794
812
}
813
+
d->state = state;
795
814
796
815
return 0;
816
+
}
817
+
818
+
static int intc_resume(struct sys_device *dev)
819
+
{
820
+
return intc_suspend(dev, PMSG_ON);
797
821
}
798
822
799
823
static struct sysdev_class intc_sysdev_class = {
800
824
.name = "intc",
801
825
.suspend = intc_suspend,
826
+
.resume = intc_resume,
802
827
};
803
828
804
829
/* register this intc as sysdev to allow suspend/resume */