Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

+3 -3

drivers/gpu/drm/nouveau/core/subdev/therm/temp.c

··· 192 192 nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_shutdown, 193 193 NOUVEAU_THERM_THRS_SHUTDOWN); 194 194 195 + spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags); 196 + 195 197 /* schedule the next poll in one second */ 196 198 if (therm->temp_get(therm) >= 0 && list_empty(&alarm->head)) 197 - ptimer->alarm(ptimer, 1000 * 1000 * 1000, alarm); 198 - 199 - spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags); 199 + ptimer->alarm(ptimer, 1000000000ULL, alarm); 200 200 } 201 201 202 202 void

+3

drivers/gpu/drm/qxl/qxl_irq.c

··· 33 33 34 34 pending = xchg(&qdev->ram_header->int_pending, 0); 35 35 36 + if (!pending) 37 + return IRQ_NONE; 38 + 36 39 atomic_inc(&qdev->irq_received); 37 40 38 41 if (pending & QXL_INTERRUPT_DISPLAY) {

+4 -4

drivers/gpu/drm/radeon/atombios_crtc.c

··· 1414 1414 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1415 1415 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1416 1416 1417 - /* set pageflip to happen anywhere in vblank interval */ 1418 - WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1417 + /* set pageflip to happen only at start of vblank interval (front porch) */ 1418 + WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); 1419 1419 1420 1420 if (!atomic && fb && fb != crtc->primary->fb) { 1421 1421 radeon_fb = to_radeon_framebuffer(fb); ··· 1614 1614 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1615 1615 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1616 1616 1617 - /* set pageflip to happen anywhere in vblank interval */ 1618 - WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1617 + /* set pageflip to happen only at start of vblank interval (front porch) */ 1618 + WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); 1619 1619 1620 1620 if (!atomic && fb && fb != crtc->primary->fb) { 1621 1621 radeon_fb = to_radeon_framebuffer(fb);

+7 -3

drivers/gpu/drm/radeon/atombios_encoders.c

··· 183 183 struct backlight_properties props; 184 184 struct radeon_backlight_privdata *pdata; 185 185 struct radeon_encoder_atom_dig *dig; 186 - u8 backlight_level; 187 186 char bl_name[16]; 188 187 189 188 /* Mac laptops with multiple GPUs use the gmux driver for backlight ··· 221 222 222 223 pdata->encoder = radeon_encoder; 223 224 224 - backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 225 - 226 225 dig = radeon_encoder->enc_priv; 227 226 dig->bl_dev = bd; 228 227 229 228 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 229 + /* Set a reasonable default here if the level is 0 otherwise 230 + * fbdev will attempt to turn the backlight on after console 231 + * unblanking and it will try and restore 0 which turns the backlight 232 + * off again. 233 + */ 234 + if (bd->props.brightness == 0) 235 + bd->props.brightness = RADEON_MAX_BL_LEVEL; 230 236 bd->props.power = FB_BLANK_UNBLANK; 231 237 backlight_update_status(bd); 232 238

+3 -2

drivers/gpu/drm/radeon/evergreen.c

··· 2642 2642 for (i = 0; i < rdev->num_crtc; i++) { 2643 2643 if (save->crtc_enabled[i]) { 2644 2644 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); 2645 - if ((tmp & 0x3) != 0) { 2646 - tmp &= ~0x3; 2645 + if ((tmp & 0x7) != 3) { 2646 + tmp &= ~0x7; 2647 + tmp |= 0x3; 2647 2648 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 2648 2649 } 2649 2650 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);

-1

drivers/gpu/drm/radeon/evergreen_reg.h

··· 239 239 # define EVERGREEN_CRTC_V_BLANK (1 << 0) 240 240 #define EVERGREEN_CRTC_STATUS_POSITION 0x6e90 241 241 #define EVERGREEN_CRTC_STATUS_HV_COUNT 0x6ea0 242 - #define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8 243 242 #define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 244 243 #define EVERGREEN_MASTER_UPDATE_LOCK 0x6ef4 245 244 #define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8

+1 -2

drivers/gpu/drm/radeon/radeon.h

··· 684 684 struct work_struct unpin_work; 685 685 struct radeon_device *rdev; 686 686 int crtc_id; 687 - struct drm_framebuffer *fb; 687 + uint64_t base; 688 688 struct drm_pending_vblank_event *event; 689 689 struct radeon_bo *old_rbo; 690 - struct radeon_bo *new_rbo; 691 690 struct radeon_fence *fence; 692 691 }; 693 692

+105 -101

drivers/gpu/drm/radeon/radeon_display.c

··· 366 366 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 367 367 368 368 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 369 - radeon_fence_unref(&work->fence); 370 369 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 371 370 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 372 371 } ··· 385 386 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 386 387 387 388 struct drm_crtc *crtc = &radeon_crtc->base; 388 - struct drm_framebuffer *fb = work->fb; 389 - 390 - uint32_t tiling_flags, pitch_pixels; 391 - uint64_t base; 392 - 393 389 unsigned long flags; 394 390 int r; 395 391 396 392 down_read(&rdev->exclusive_lock); 397 - while (work->fence) { 393 + if (work->fence) { 398 394 r = radeon_fence_wait(work->fence, false); 399 395 if (r == -EDEADLK) { 400 396 up_read(&rdev->exclusive_lock); 401 397 r = radeon_gpu_reset(rdev); 402 398 down_read(&rdev->exclusive_lock); 403 399 } 400 + if (r) 401 + DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 404 402 405 - if (r) { 406 - DRM_ERROR("failed to wait on page flip fence (%d)!\n", 407 - r); 408 - goto cleanup; 409 - } else 410 - radeon_fence_unref(&work->fence); 403 + /* We continue with the page flip even if we failed to wait on 404 + * the fence, otherwise the DRM core and userspace will be 405 + * confused about which BO the CRTC is scanning out 406 + */ 407 + 408 + radeon_fence_unref(&work->fence); 411 409 } 412 410 413 - /* pin the new buffer */ 414 - DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", 415 - work->old_rbo, work->new_rbo); 411 + /* We borrow the event spin lock for protecting flip_status */ 412 + spin_lock_irqsave(&crtc->dev->event_lock, flags); 416 413 417 - r = radeon_bo_reserve(work->new_rbo, false); 414 + /* set the proper interrupt */ 415 + radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 416 + 417 + /* do the flip (mmio) */ 418 + radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base); 419 + 420 + radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 421 + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 422 + up_read(&rdev->exclusive_lock); 423 + } 424 + 425 + static int radeon_crtc_page_flip(struct drm_crtc *crtc, 426 + struct drm_framebuffer *fb, 427 + struct drm_pending_vblank_event *event, 428 + uint32_t page_flip_flags) 429 + { 430 + struct drm_device *dev = crtc->dev; 431 + struct radeon_device *rdev = dev->dev_private; 432 + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 433 + struct radeon_framebuffer *old_radeon_fb; 434 + struct radeon_framebuffer *new_radeon_fb; 435 + struct drm_gem_object *obj; 436 + struct radeon_flip_work *work; 437 + struct radeon_bo *new_rbo; 438 + uint32_t tiling_flags, pitch_pixels; 439 + uint64_t base; 440 + unsigned long flags; 441 + int r; 442 + 443 + work = kzalloc(sizeof *work, GFP_KERNEL); 444 + if (work == NULL) 445 + return -ENOMEM; 446 + 447 + INIT_WORK(&work->flip_work, radeon_flip_work_func); 448 + INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 449 + 450 + work->rdev = rdev; 451 + work->crtc_id = radeon_crtc->crtc_id; 452 + work->event = event; 453 + 454 + /* schedule unpin of the old buffer */ 455 + old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 456 + obj = old_radeon_fb->obj; 457 + 458 + /* take a reference to the old object */ 459 + drm_gem_object_reference(obj); 460 + work->old_rbo = gem_to_radeon_bo(obj); 461 + 462 + new_radeon_fb = to_radeon_framebuffer(fb); 463 + obj = new_radeon_fb->obj; 464 + new_rbo = gem_to_radeon_bo(obj); 465 + 466 + spin_lock(&new_rbo->tbo.bdev->fence_lock); 467 + if (new_rbo->tbo.sync_obj) 468 + work->fence = radeon_fence_ref(new_rbo->tbo.sync_obj); 469 + spin_unlock(&new_rbo->tbo.bdev->fence_lock); 470 + 471 + /* pin the new buffer */ 472 + DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 473 + work->old_rbo, new_rbo); 474 + 475 + r = radeon_bo_reserve(new_rbo, false); 418 476 if (unlikely(r != 0)) { 419 477 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 420 478 goto cleanup; 421 479 } 422 480 /* Only 27 bit offset for legacy CRTC */ 423 - r = radeon_bo_pin_restricted(work->new_rbo, RADEON_GEM_DOMAIN_VRAM, 481 + r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 424 482 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 425 483 if (unlikely(r != 0)) { 426 - radeon_bo_unreserve(work->new_rbo); 484 + radeon_bo_unreserve(new_rbo); 427 485 r = -EINVAL; 428 486 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 429 487 goto cleanup; 430 488 } 431 - radeon_bo_get_tiling_flags(work->new_rbo, &tiling_flags, NULL); 432 - radeon_bo_unreserve(work->new_rbo); 489 + radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 490 + radeon_bo_unreserve(new_rbo); 433 491 434 492 if (!ASIC_IS_AVIVO(rdev)) { 435 493 /* crtc offset is from display base addr not FB location */ ··· 523 467 } 524 468 base &= ~7; 525 469 } 470 + work->base = base; 526 471 527 472 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); 528 473 if (r) { ··· 534 477 /* We borrow the event spin lock for protecting flip_work */ 535 478 spin_lock_irqsave(&crtc->dev->event_lock, flags); 536 479 537 - /* set the proper interrupt */ 538 - radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 539 - 540 - /* do the flip (mmio) */ 541 - radeon_page_flip(rdev, radeon_crtc->crtc_id, base); 542 - 543 - radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 544 - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 545 - up_read(&rdev->exclusive_lock); 546 - 547 - return; 548 - 549 - pflip_cleanup: 550 - if (unlikely(radeon_bo_reserve(work->new_rbo, false) != 0)) { 551 - DRM_ERROR("failed to reserve new rbo in error path\n"); 552 - goto cleanup; 553 - } 554 - if (unlikely(radeon_bo_unpin(work->new_rbo) != 0)) { 555 - DRM_ERROR("failed to unpin new rbo in error path\n"); 556 - } 557 - radeon_bo_unreserve(work->new_rbo); 558 - 559 - cleanup: 560 - drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 561 - radeon_fence_unref(&work->fence); 562 - kfree(work); 563 - up_read(&rdev->exclusive_lock); 564 - } 565 - 566 - static int radeon_crtc_page_flip(struct drm_crtc *crtc, 567 - struct drm_framebuffer *fb, 568 - struct drm_pending_vblank_event *event, 569 - uint32_t page_flip_flags) 570 - { 571 - struct drm_device *dev = crtc->dev; 572 - struct radeon_device *rdev = dev->dev_private; 573 - struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 574 - struct radeon_framebuffer *old_radeon_fb; 575 - struct radeon_framebuffer *new_radeon_fb; 576 - struct drm_gem_object *obj; 577 - struct radeon_flip_work *work; 578 - unsigned long flags; 579 - 580 - work = kzalloc(sizeof *work, GFP_KERNEL); 581 - if (work == NULL) 582 - return -ENOMEM; 583 - 584 - INIT_WORK(&work->flip_work, radeon_flip_work_func); 585 - INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 586 - 587 - work->rdev = rdev; 588 - work->crtc_id = radeon_crtc->crtc_id; 589 - work->fb = fb; 590 - work->event = event; 591 - 592 - /* schedule unpin of the old buffer */ 593 - old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 594 - obj = old_radeon_fb->obj; 595 - 596 - /* take a reference to the old object */ 597 - drm_gem_object_reference(obj); 598 - work->old_rbo = gem_to_radeon_bo(obj); 599 - 600 - new_radeon_fb = to_radeon_framebuffer(fb); 601 - obj = new_radeon_fb->obj; 602 - work->new_rbo = gem_to_radeon_bo(obj); 603 - 604 - spin_lock(&work->new_rbo->tbo.bdev->fence_lock); 605 - if (work->new_rbo->tbo.sync_obj) 606 - work->fence = radeon_fence_ref(work->new_rbo->tbo.sync_obj); 607 - spin_unlock(&work->new_rbo->tbo.bdev->fence_lock); 608 - 609 - /* We borrow the event spin lock for protecting flip_work */ 610 - spin_lock_irqsave(&crtc->dev->event_lock, flags); 611 - 612 480 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 613 481 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 614 482 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 615 - drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 616 - radeon_fence_unref(&work->fence); 617 - kfree(work); 618 - return -EBUSY; 483 + r = -EBUSY; 484 + goto vblank_cleanup; 619 485 } 620 486 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 621 487 radeon_crtc->flip_work = work; ··· 549 569 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 550 570 551 571 queue_work(radeon_crtc->flip_queue, &work->flip_work); 552 - 553 572 return 0; 573 + 574 + vblank_cleanup: 575 + drm_vblank_put(crtc->dev, radeon_crtc->crtc_id); 576 + 577 + pflip_cleanup: 578 + if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 579 + DRM_ERROR("failed to reserve new rbo in error path\n"); 580 + goto cleanup; 581 + } 582 + if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 583 + DRM_ERROR("failed to unpin new rbo in error path\n"); 584 + } 585 + radeon_bo_unreserve(new_rbo); 586 + 587 + cleanup: 588 + drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 589 + radeon_fence_unref(&work->fence); 590 + kfree(work); 591 + 592 + return r; 554 593 } 555 594 556 595 static int ··· 829 830 struct radeon_device *rdev = dev->dev_private; 830 831 int ret = 0; 831 832 833 + /* don't leak the edid if we already fetched it in detect() */ 834 + if (radeon_connector->edid) 835 + goto got_edid; 836 + 832 837 /* on hw with routers, select right port */ 833 838 if (radeon_connector->router.ddc_valid) 834 839 radeon_router_select_ddc_port(radeon_connector); ··· 871 868 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 872 869 } 873 870 if (radeon_connector->edid) { 871 + got_edid: 874 872 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); 875 873 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); 876 874 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);

+3 -2

drivers/gpu/drm/radeon/rv515.c

··· 406 406 for (i = 0; i < rdev->num_crtc; i++) { 407 407 if (save->crtc_enabled[i]) { 408 408 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); 409 - if ((tmp & 0x3) != 0) { 410 - tmp &= ~0x3; 409 + if ((tmp & 0x7) != 3) { 410 + tmp &= ~0x7; 411 + tmp |= 0x3; 411 412 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 412 413 } 413 414 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);

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