tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (21 commits)
Blackfin Serial Driver: abstract away DLAB differences into header
Blackfin Serial Driver: macro away the IER differences between processors
[Blackfin] arch: remove useless IRQ_SW_INT defines
[Blackfin] arch: protect linux/usb/musb.h include until the driver gets mainlined
[Blackfin] arch: protect linux/usb/isp1362.h include until the driver gets mainlined
[Blackfin] arch: add EBIU supporting for BF54x EZKIT SMSC LAN911x/LAN921x families embedded ethernet driver
[Blackfin] arch: Set spi flash partition on bf527 as like bf548.
[Blackfin] arch: fix bug - Remove module will not free L1 memory used
[Blackfin] arch: fix wrong header name in comment
[Blackfin] arch: Fix BUG - spi flash on bf527 ezkit would fail at mount
[Blackfin] arch: add twi_lcd and twi_keypad i2c board info to bf527-ezkit
[Blackfin] arch: Add physmap partition for BF527-EZkit
[Blackfin] arch: fix gdb testing regression
[Blackfin] arch: disable single stepping when delivering a signal
[Blackfin] arch: Delete unused (copied from m68k) entries in asm-offsets.c.
[Blackfin] arch: In the double fault handler, set up the PT_RETI slot
[Blackfin] arch: Support for CPU_FREQ and NOHZ
[Blackfin] arch: Functional power management support: Add CPU and platform voltage scaling support
[Blackfin] arch: fix bug - breaking the atomic sections code.
[Blackfin] arch: Equalize include files: Add VR_CTL masks
...

Linus Torvalds 3ed43c74 26c5e98e

+817 -229
+10 -8
arch/blackfin/Kconfig
··· 832 832 config BANK_1 833 833 hex "Bank 1" 834 834 default 0x7BB0 835 + default 0x5558 if BF54x 835 836 836 837 config BANK_2 837 838 hex "Bank 2" ··· 964 963 965 964 endmenu 966 965 967 - if (BF537 || BF533 || BF54x) 968 - 969 966 menu "CPU Frequency scaling" 970 967 971 968 source "drivers/cpufreq/Kconfig" 972 969 973 - config CPU_FREQ 974 - bool 970 + config CPU_VOLTAGE 971 + bool "CPU Voltage scaling" 972 + depends on EXPERIMENTAL 973 + depends on CPU_FREQ 975 974 default n 976 975 help 977 - If you want to enable this option, you should select the 978 - DPMC driver from Character Devices. 979 - endmenu 976 + Say Y here if you want CPU voltage scaling according to the CPU frequency. 977 + This option violates the PLL BYPASS recommendation in the Blackfin Processor 978 + manuals. There is a theoretical risk that during VDDINT transitions 979 + the PLL may unlock. 980 980 981 - endif 981 + endmenu 982 982 983 983 source "net/Kconfig" 984 984
-3
arch/blackfin/kernel/asm-offsets.c
··· 56 56 /* offsets into the thread struct */ 57 57 DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp)); 58 58 DEFINE(THREAD_USP, offsetof(struct thread_struct, usp)); 59 - DEFINE(THREAD_SR, offsetof(struct thread_struct, seqstat)); 60 - DEFINE(PT_SR, offsetof(struct thread_struct, seqstat)); 61 - DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0)); 62 59 DEFINE(THREAD_PC, offsetof(struct thread_struct, pc)); 63 60 DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE); 64 61
+1 -1
arch/blackfin/kernel/fixed_code.S
··· 1 1 /* 2 2 * This file contains sequences of code that will be copied to a 3 - * fixed location, defined in <asm/atomic_seq.h>. The interrupt 3 + * fixed location, defined in <asm/fixed_code.h>. The interrupt 4 4 * handlers ensure that these sequences appear to be atomic when 5 5 * executed from userspace. 6 6 * These are aligned to 16 bytes, so that we have some space to replace
+22 -15
arch/blackfin/kernel/module.c
··· 160 160 module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs, 161 161 char *secstrings, struct module *mod) 162 162 { 163 + /* 164 + * XXX: sechdrs are vmalloced in kernel/module.c 165 + * and would be vfreed just after module is loaded, 166 + * so we hack to keep the only information we needed 167 + * in mod->arch to correctly free L1 I/D sram later. 168 + * NOTE: this breaks the semantic of mod->arch structure. 169 + */ 163 170 Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; 164 171 void *dest = NULL; 165 172 ··· 174 167 if ((strcmp(".l1.text", secstrings + s->sh_name) == 0) || 175 168 ((strcmp(".text", secstrings + s->sh_name) == 0) && 176 169 (hdr->e_flags & FLG_CODE_IN_L1) && (s->sh_size > 0))) { 177 - mod->arch.text_l1 = s; 178 170 dest = l1_inst_sram_alloc(s->sh_size); 171 + mod->arch.text_l1 = dest; 179 172 if (dest == NULL) { 180 173 printk(KERN_ERR 181 174 "module %s: L1 instruction memory allocation failed\n", ··· 189 182 if ((strcmp(".l1.data", secstrings + s->sh_name) == 0) || 190 183 ((strcmp(".data", secstrings + s->sh_name) == 0) && 191 184 (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) { 192 - mod->arch.data_a_l1 = s; 193 185 dest = l1_data_sram_alloc(s->sh_size); 186 + mod->arch.data_a_l1 = dest; 194 187 if (dest == NULL) { 195 188 printk(KERN_ERR 196 189 "module %s: L1 data memory allocation failed\n", ··· 204 197 if (strcmp(".l1.bss", secstrings + s->sh_name) == 0 || 205 198 ((strcmp(".bss", secstrings + s->sh_name) == 0) && 206 199 (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) { 207 - mod->arch.bss_a_l1 = s; 208 200 dest = l1_data_sram_alloc(s->sh_size); 201 + mod->arch.bss_a_l1 = dest; 209 202 if (dest == NULL) { 210 203 printk(KERN_ERR 211 204 "module %s: L1 data memory allocation failed\n", ··· 217 210 s->sh_addr = (unsigned long)dest; 218 211 } 219 212 if (strcmp(".l1.data.B", secstrings + s->sh_name) == 0) { 220 - mod->arch.data_b_l1 = s; 221 213 dest = l1_data_B_sram_alloc(s->sh_size); 214 + mod->arch.data_b_l1 = dest; 222 215 if (dest == NULL) { 223 216 printk(KERN_ERR 224 217 "module %s: L1 data memory allocation failed\n", ··· 230 223 s->sh_addr = (unsigned long)dest; 231 224 } 232 225 if (strcmp(".l1.bss.B", secstrings + s->sh_name) == 0) { 233 - mod->arch.bss_b_l1 = s; 234 226 dest = l1_data_B_sram_alloc(s->sh_size); 227 + mod->arch.bss_b_l1 = dest; 235 228 if (dest == NULL) { 236 229 printk(KERN_ERR 237 230 "module %s: L1 data memory allocation failed\n", ··· 423 416 424 417 void module_arch_cleanup(struct module *mod) 425 418 { 426 - if ((mod->arch.text_l1) && (mod->arch.text_l1->sh_addr)) 427 - l1_inst_sram_free((void *)mod->arch.text_l1->sh_addr); 428 - if ((mod->arch.data_a_l1) && (mod->arch.data_a_l1->sh_addr)) 429 - l1_data_sram_free((void *)mod->arch.data_a_l1->sh_addr); 430 - if ((mod->arch.bss_a_l1) && (mod->arch.bss_a_l1->sh_addr)) 431 - l1_data_sram_free((void *)mod->arch.bss_a_l1->sh_addr); 432 - if ((mod->arch.data_b_l1) && (mod->arch.data_b_l1->sh_addr)) 433 - l1_data_B_sram_free((void *)mod->arch.data_b_l1->sh_addr); 434 - if ((mod->arch.bss_b_l1) && (mod->arch.bss_b_l1->sh_addr)) 435 - l1_data_B_sram_free((void *)mod->arch.bss_b_l1->sh_addr); 419 + if (mod->arch.text_l1) 420 + l1_inst_sram_free((void *)mod->arch.text_l1); 421 + if (mod->arch.data_a_l1) 422 + l1_data_sram_free((void *)mod->arch.data_a_l1); 423 + if (mod->arch.bss_a_l1) 424 + l1_data_sram_free((void *)mod->arch.bss_a_l1); 425 + if (mod->arch.data_b_l1) 426 + l1_data_B_sram_free((void *)mod->arch.data_b_l1); 427 + if (mod->arch.bss_b_l1) 428 + l1_data_B_sram_free((void *)mod->arch.bss_b_l1); 436 429 }
+1 -1
arch/blackfin/kernel/process.c
··· 245 245 246 246 void finish_atomic_sections (struct pt_regs *regs) 247 247 { 248 - int __user *up0 = (int __user *)&regs->p0; 248 + int __user *up0 = (int __user *)regs->p0; 249 249 250 250 if (regs->pc < ATOMIC_SEQS_START || regs->pc >= ATOMIC_SEQS_END) 251 251 return;
+2 -2
arch/blackfin/kernel/ptrace.c
··· 185 185 { 186 186 unsigned long tmp; 187 187 /* make sure the single step bit is not set. */ 188 - tmp = get_reg(child, PT_SR) & ~(TRACE_BITS << 16); 189 - put_reg(child, PT_SR, tmp); 188 + tmp = get_reg(child, PT_SYSCFG) & ~TRACE_BITS; 189 + put_reg(child, PT_SYSCFG, tmp); 190 190 } 191 191 192 192 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
+13
arch/blackfin/kernel/signal.c
··· 42 42 43 43 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) 44 44 45 + /* Location of the trace bit in SYSCFG. */ 46 + #define TRACE_BITS 0x0001 47 + 45 48 struct fdpic_func_descriptor { 46 49 unsigned long text; 47 50 unsigned long GOT; ··· 227 224 regs->r0 = frame->sig; 228 225 regs->r1 = (unsigned long)(&frame->info); 229 226 regs->r2 = (unsigned long)(&frame->uc); 227 + 228 + /* 229 + * Clear the trace flag when entering the signal handler, but 230 + * notify any tracer that was single-stepping it. The tracer 231 + * may want to single-step inside the handler too. 232 + */ 233 + if (regs->syscfg & TRACE_BITS) { 234 + regs->syscfg &= ~TRACE_BITS; 235 + ptrace_notify(SIGTRAP); 236 + } 230 237 231 238 return 0; 232 239
+7 -3
arch/blackfin/kernel/time-ts.c
··· 60 60 61 61 static cycle_t read_cycles(void) 62 62 { 63 - return get_cycles(); 63 + return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod); 64 64 } 65 65 66 66 unsigned long long sched_clock(void) ··· 117 117 break; 118 118 } 119 119 case CLOCK_EVT_MODE_ONESHOT: 120 - bfin_write_TSCALE(0); 120 + bfin_write_TSCALE(TIME_SCALE - 1); 121 121 bfin_write_TCOUNT(0); 122 122 bfin_write_TCNTL(TMPWR | TMREN); 123 123 CSYNC(); ··· 183 183 184 184 static int __init bfin_clockevent_init(void) 185 185 { 186 + unsigned long timer_clk; 187 + 188 + timer_clk = get_cclk() / TIME_SCALE; 189 + 186 190 setup_irq(IRQ_CORETMR, &bfin_timer_irq); 187 191 bfin_timer_init(); 188 192 189 - clockevent_bfin.mult = div_sc(get_cclk(), NSEC_PER_SEC, clockevent_bfin.shift); 193 + clockevent_bfin.mult = div_sc(timer_clk, NSEC_PER_SEC, clockevent_bfin.shift); 190 194 clockevent_bfin.max_delta_ns = clockevent_delta2ns(-1, &clockevent_bfin); 191 195 clockevent_bfin.min_delta_ns = clockevent_delta2ns(100, &clockevent_bfin); 192 196 clockevents_register_device(&clockevent_bfin);
+98 -6
arch/blackfin/mach-bf527/boards/ezkit.c
··· 32 32 #include <linux/platform_device.h> 33 33 #include <linux/mtd/mtd.h> 34 34 #include <linux/mtd/partitions.h> 35 + #include <linux/mtd/physmap.h> 35 36 #include <linux/spi/spi.h> 36 37 #include <linux/spi/flash.h> 37 38 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 38 39 #include <linux/usb/isp1362.h> 39 40 #endif 40 41 #include <linux/ata_platform.h> 42 + #include <linux/i2c.h> 41 43 #include <linux/irq.h> 42 44 #include <linux/interrupt.h> 43 45 #include <linux/usb/sl811.h> ··· 52 50 #include <asm/reboot.h> 53 51 #include <asm/nand.h> 54 52 #include <asm/portmux.h> 53 + #include <asm/dpmc.h> 55 54 #include <linux/spi/ad7877.h> 56 55 57 56 /* ··· 171 168 .id = -1, 172 169 .num_resources = ARRAY_SIZE(bf52x_t350mcqb_resources), 173 170 .resource = bf52x_t350mcqb_resources, 171 + }; 172 + #endif 173 + 174 + #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 175 + static struct mtd_partition ezkit_partitions[] = { 176 + { 177 + .name = "Bootloader", 178 + .size = 0x40000, 179 + .offset = 0, 180 + }, { 181 + .name = "Kernel", 182 + .size = 0x1C0000, 183 + .offset = MTDPART_OFS_APPEND, 184 + }, { 185 + .name = "RootFS", 186 + .size = MTDPART_SIZ_FULL, 187 + .offset = MTDPART_OFS_APPEND, 188 + } 189 + }; 190 + 191 + static struct physmap_flash_data ezkit_flash_data = { 192 + .width = 2, 193 + .parts = ezkit_partitions, 194 + .nr_parts = ARRAY_SIZE(ezkit_partitions), 195 + }; 196 + 197 + static struct resource ezkit_flash_resource = { 198 + .start = 0x20000000, 199 + .end = 0x203fffff, 200 + .flags = IORESOURCE_MEM, 201 + }; 202 + 203 + static struct platform_device ezkit_flash_device = { 204 + .name = "physmap-flash", 205 + .id = 0, 206 + .dev = { 207 + .platform_data = &ezkit_flash_data, 208 + }, 209 + .num_resources = 1, 210 + .resource = &ezkit_flash_resource, 174 211 }; 175 212 #endif 176 213 ··· 463 420 .offset = 0, 464 421 .mask_flags = MTD_CAP_ROM 465 422 }, { 466 - .name = "kernel", 467 - .size = 0xe0000, 468 - .offset = MTDPART_OFS_APPEND, 469 - }, { 470 - .name = "file system", 423 + .name = "linux kernel", 471 424 .size = MTDPART_SIZ_FULL, 472 425 .offset = MTDPART_OFS_APPEND, 473 426 } ··· 473 434 .name = "m25p80", 474 435 .parts = bfin_spi_flash_partitions, 475 436 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), 476 - .type = "m25p64", 437 + .type = "m25p16", 477 438 }; 478 439 479 440 /* SPI flash chip (m25p64) */ ··· 794 755 }; 795 756 #endif 796 757 758 + #ifdef CONFIG_I2C_BOARDINFO 759 + static struct i2c_board_info __initdata bfin_i2c_board_info[] = { 760 + #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) 761 + { 762 + I2C_BOARD_INFO("pcf8574_lcd", 0x22), 763 + .type = "pcf8574_lcd", 764 + }, 765 + #endif 766 + #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) 767 + { 768 + I2C_BOARD_INFO("pcf8574_keypad", 0x27), 769 + .type = "pcf8574_keypad", 770 + .irq = IRQ_PF8, 771 + }, 772 + #endif 773 + }; 774 + #endif 775 + 797 776 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 798 777 static struct platform_device bfin_sport0_uart_device = { 799 778 .name = "bfin-sport-uart", ··· 896 839 .resource = &bfin_gpios_resources, 897 840 }; 898 841 842 + static const unsigned int cclk_vlev_datasheet[] = 843 + { 844 + VRPAIR(VLEV_100, 400000000), 845 + VRPAIR(VLEV_105, 426000000), 846 + VRPAIR(VLEV_110, 500000000), 847 + VRPAIR(VLEV_115, 533000000), 848 + VRPAIR(VLEV_120, 600000000), 849 + }; 850 + 851 + static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 852 + .tuple_tab = cclk_vlev_datasheet, 853 + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 854 + .vr_settling_time = 25 /* us */, 855 + }; 856 + 857 + static struct platform_device bfin_dpmc = { 858 + .name = "bfin dpmc", 859 + .dev = { 860 + .platform_data = &bfin_dmpc_vreg_data, 861 + }, 862 + }; 863 + 899 864 static struct platform_device *stamp_devices[] __initdata = { 865 + 866 + &bfin_dpmc, 867 + 900 868 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 901 869 &bf5xx_nand_device, 902 870 #endif ··· 1003 921 &bfin_device_gpiokeys, 1004 922 #endif 1005 923 924 + #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 925 + &ezkit_flash_device, 926 + #endif 927 + 1006 928 &bfin_gpios_device, 1007 929 }; 1008 930 1009 931 static int __init stamp_init(void) 1010 932 { 1011 933 printk(KERN_INFO "%s(): registering device resources\n", __func__); 934 + 935 + #ifdef CONFIG_I2C_BOARDINFO 936 + i2c_register_board_info(0, bfin_i2c_board_info, 937 + ARRAY_SIZE(bfin_i2c_board_info)); 938 + #endif 939 + 1012 940 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); 1013 941 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 1014 942 spi_register_board_info(bfin_spi_board_info,
+33
arch/blackfin/mach-bf533/boards/cm_bf533.c
··· 33 33 #include <linux/mtd/partitions.h> 34 34 #include <linux/spi/spi.h> 35 35 #include <linux/spi/flash.h> 36 + #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 36 37 #include <linux/usb/isp1362.h> 38 + #endif 37 39 #include <linux/ata_platform.h> 38 40 #include <linux/irq.h> 39 41 #include <asm/dma.h> 40 42 #include <asm/bfin5xx_spi.h> 41 43 #include <asm/portmux.h> 44 + #include <asm/dpmc.h> 42 45 43 46 /* 44 47 * Name the Board for the /proc/cpuinfo ··· 344 341 }; 345 342 #endif 346 343 344 + static const unsigned int cclk_vlev_datasheet[] = 345 + { 346 + VRPAIR(VLEV_085, 250000000), 347 + VRPAIR(VLEV_090, 376000000), 348 + VRPAIR(VLEV_095, 426000000), 349 + VRPAIR(VLEV_100, 426000000), 350 + VRPAIR(VLEV_105, 476000000), 351 + VRPAIR(VLEV_110, 476000000), 352 + VRPAIR(VLEV_115, 476000000), 353 + VRPAIR(VLEV_120, 600000000), 354 + VRPAIR(VLEV_125, 600000000), 355 + VRPAIR(VLEV_130, 600000000), 356 + }; 357 + 358 + static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 359 + .tuple_tab = cclk_vlev_datasheet, 360 + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 361 + .vr_settling_time = 25 /* us */, 362 + }; 363 + 364 + static struct platform_device bfin_dpmc = { 365 + .name = "bfin dpmc", 366 + .dev = { 367 + .platform_data = &bfin_dmpc_vreg_data, 368 + }, 369 + }; 370 + 347 371 static struct platform_device *cm_bf533_devices[] __initdata = { 372 + 373 + &bfin_dpmc, 374 + 348 375 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 349 376 &bfin_uart_device, 350 377 #endif
+31
arch/blackfin/mach-bf533/boards/ezkit.c
··· 42 42 #include <asm/dma.h> 43 43 #include <asm/bfin5xx_spi.h> 44 44 #include <asm/portmux.h> 45 + #include <asm/dpmc.h> 45 46 46 47 /* 47 48 * Name the Board for the /proc/cpuinfo ··· 351 350 }; 352 351 #endif 353 352 353 + static const unsigned int cclk_vlev_datasheet[] = 354 + { 355 + VRPAIR(VLEV_085, 250000000), 356 + VRPAIR(VLEV_090, 376000000), 357 + VRPAIR(VLEV_095, 426000000), 358 + VRPAIR(VLEV_100, 426000000), 359 + VRPAIR(VLEV_105, 476000000), 360 + VRPAIR(VLEV_110, 476000000), 361 + VRPAIR(VLEV_115, 476000000), 362 + VRPAIR(VLEV_120, 600000000), 363 + VRPAIR(VLEV_125, 600000000), 364 + VRPAIR(VLEV_130, 600000000), 365 + }; 366 + 367 + static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 368 + .tuple_tab = cclk_vlev_datasheet, 369 + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 370 + .vr_settling_time = 25 /* us */, 371 + }; 372 + 373 + static struct platform_device bfin_dpmc = { 374 + .name = "bfin dpmc", 375 + .dev = { 376 + .platform_data = &bfin_dmpc_vreg_data, 377 + }, 378 + }; 379 + 354 380 static struct platform_device *ezkit_devices[] __initdata = { 381 + 382 + &bfin_dpmc, 383 + 355 384 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 356 385 &smc91x_device, 357 386 #endif
+31
arch/blackfin/mach-bf533/boards/stamp.c
··· 45 45 #include <asm/bfin5xx_spi.h> 46 46 #include <asm/reboot.h> 47 47 #include <asm/portmux.h> 48 + #include <asm/dpmc.h> 48 49 49 50 /* 50 51 * Name the Board for the /proc/cpuinfo ··· 517 516 }; 518 517 #endif 519 518 519 + static const unsigned int cclk_vlev_datasheet[] = 520 + { 521 + VRPAIR(VLEV_085, 250000000), 522 + VRPAIR(VLEV_090, 376000000), 523 + VRPAIR(VLEV_095, 426000000), 524 + VRPAIR(VLEV_100, 426000000), 525 + VRPAIR(VLEV_105, 476000000), 526 + VRPAIR(VLEV_110, 476000000), 527 + VRPAIR(VLEV_115, 476000000), 528 + VRPAIR(VLEV_120, 600000000), 529 + VRPAIR(VLEV_125, 600000000), 530 + VRPAIR(VLEV_130, 600000000), 531 + }; 532 + 533 + static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 534 + .tuple_tab = cclk_vlev_datasheet, 535 + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 536 + .vr_settling_time = 25 /* us */, 537 + }; 538 + 539 + static struct platform_device bfin_dpmc = { 540 + .name = "bfin dpmc", 541 + .dev = { 542 + .platform_data = &bfin_dmpc_vreg_data, 543 + }, 544 + }; 545 + 520 546 static struct platform_device *stamp_devices[] __initdata = { 547 + 548 + &bfin_dpmc, 549 + 521 550 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 522 551 &rtc_device, 523 552 #endif
+33
arch/blackfin/mach-bf537/boards/cm_bf537.c
··· 35 35 #include <linux/mtd/partitions.h> 36 36 #include <linux/spi/spi.h> 37 37 #include <linux/spi/flash.h> 38 + #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 38 39 #include <linux/usb/isp1362.h> 40 + #endif 39 41 #include <linux/ata_platform.h> 40 42 #include <linux/irq.h> 41 43 #include <asm/dma.h> 42 44 #include <asm/bfin5xx_spi.h> 43 45 #include <asm/portmux.h> 46 + #include <asm/dpmc.h> 44 47 45 48 /* 46 49 * Name the Board for the /proc/cpuinfo ··· 431 428 }; 432 429 #endif 433 430 431 + static const unsigned int cclk_vlev_datasheet[] = 432 + { 433 + VRPAIR(VLEV_085, 250000000), 434 + VRPAIR(VLEV_090, 376000000), 435 + VRPAIR(VLEV_095, 426000000), 436 + VRPAIR(VLEV_100, 426000000), 437 + VRPAIR(VLEV_105, 476000000), 438 + VRPAIR(VLEV_110, 476000000), 439 + VRPAIR(VLEV_115, 476000000), 440 + VRPAIR(VLEV_120, 500000000), 441 + VRPAIR(VLEV_125, 533000000), 442 + VRPAIR(VLEV_130, 600000000), 443 + }; 444 + 445 + static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 446 + .tuple_tab = cclk_vlev_datasheet, 447 + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 448 + .vr_settling_time = 25 /* us */, 449 + }; 450 + 451 + static struct platform_device bfin_dpmc = { 452 + .name = "bfin dpmc", 453 + .dev = { 454 + .platform_data = &bfin_dmpc_vreg_data, 455 + }, 456 + }; 457 + 434 458 static struct platform_device *cm_bf537_devices[] __initdata = { 459 + 460 + &bfin_dpmc, 461 + 435 462 #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) 436 463 &hitachi_fb_device, 437 464 #endif
+31
arch/blackfin/mach-bf537/boards/stamp.c
··· 47 47 #include <asm/bfin5xx_spi.h> 48 48 #include <asm/reboot.h> 49 49 #include <asm/portmux.h> 50 + #include <asm/dpmc.h> 50 51 #include <linux/spi/ad7877.h> 51 52 52 53 /* ··· 818 817 }; 819 818 #endif 820 819 820 + static const unsigned int cclk_vlev_datasheet[] = 821 + { 822 + VRPAIR(VLEV_085, 250000000), 823 + VRPAIR(VLEV_090, 376000000), 824 + VRPAIR(VLEV_095, 426000000), 825 + VRPAIR(VLEV_100, 426000000), 826 + VRPAIR(VLEV_105, 476000000), 827 + VRPAIR(VLEV_110, 476000000), 828 + VRPAIR(VLEV_115, 476000000), 829 + VRPAIR(VLEV_120, 500000000), 830 + VRPAIR(VLEV_125, 533000000), 831 + VRPAIR(VLEV_130, 600000000), 832 + }; 833 + 834 + static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 835 + .tuple_tab = cclk_vlev_datasheet, 836 + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 837 + .vr_settling_time = 25 /* us */, 838 + }; 839 + 840 + static struct platform_device bfin_dpmc = { 841 + .name = "bfin dpmc", 842 + .dev = { 843 + .platform_data = &bfin_dmpc_vreg_data, 844 + }, 845 + }; 846 + 821 847 static struct platform_device *stamp_devices[] __initdata = { 848 + 849 + &bfin_dpmc, 850 + 822 851 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) 823 852 &bfin_pcmcia_cf_device, 824 853 #endif
+34
arch/blackfin/mach-bf548/boards/cm_bf548.c
··· 36 36 #include <linux/spi/flash.h> 37 37 #include <linux/irq.h> 38 38 #include <linux/interrupt.h> 39 + #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) 39 40 #include <linux/usb/musb.h> 41 + #endif 40 42 #include <asm/bfin5xx_spi.h> 41 43 #include <asm/cplb.h> 42 44 #include <asm/dma.h> ··· 46 44 #include <asm/nand.h> 47 45 #include <asm/portmux.h> 48 46 #include <asm/mach/bf54x_keys.h> 47 + #include <asm/dpmc.h> 49 48 #include <linux/input.h> 50 49 #include <linux/spi/ad7877.h> 51 50 ··· 593 590 }; 594 591 #endif 595 592 593 + static const unsigned int cclk_vlev_datasheet[] = 594 + { 595 + /* 596 + * Internal VLEV BF54XSBBC1533 597 + ****temporarily using these values until data sheet is updated 598 + */ 599 + VRPAIR(VLEV_085, 150000000), 600 + VRPAIR(VLEV_090, 250000000), 601 + VRPAIR(VLEV_110, 276000000), 602 + VRPAIR(VLEV_115, 301000000), 603 + VRPAIR(VLEV_120, 525000000), 604 + VRPAIR(VLEV_125, 550000000), 605 + VRPAIR(VLEV_130, 600000000), 606 + }; 607 + 608 + static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 609 + .tuple_tab = cclk_vlev_datasheet, 610 + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 611 + .vr_settling_time = 25 /* us */, 612 + }; 613 + 614 + static struct platform_device bfin_dpmc = { 615 + .name = "bfin dpmc", 616 + .dev = { 617 + .platform_data = &bfin_dmpc_vreg_data, 618 + }, 619 + }; 620 + 596 621 static struct platform_device *cm_bf548_devices[] __initdata = { 622 + 623 + &bfin_dpmc, 624 + 597 625 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 598 626 &rtc_device, 599 627 #endif
+32
arch/blackfin/mach-bf548/boards/ezkit.c
··· 46 46 #include <asm/dma.h> 47 47 #include <asm/gpio.h> 48 48 #include <asm/nand.h> 49 + #include <asm/dpmc.h> 49 50 #include <asm/portmux.h> 50 51 #include <asm/mach/bf54x_keys.h> 51 52 #include <linux/input.h> ··· 690 689 .resource = &bfin_gpios_resources, 691 690 }; 692 691 692 + static const unsigned int cclk_vlev_datasheet[] = 693 + { 694 + /* 695 + * Internal VLEV BF54XSBBC1533 696 + ****temporarily using these values until data sheet is updated 697 + */ 698 + VRPAIR(VLEV_085, 150000000), 699 + VRPAIR(VLEV_090, 250000000), 700 + VRPAIR(VLEV_110, 276000000), 701 + VRPAIR(VLEV_115, 301000000), 702 + VRPAIR(VLEV_120, 525000000), 703 + VRPAIR(VLEV_125, 550000000), 704 + VRPAIR(VLEV_130, 600000000), 705 + }; 706 + 707 + static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 708 + .tuple_tab = cclk_vlev_datasheet, 709 + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 710 + .vr_settling_time = 25 /* us */, 711 + }; 712 + 713 + static struct platform_device bfin_dpmc = { 714 + .name = "bfin dpmc", 715 + .dev = { 716 + .platform_data = &bfin_dmpc_vreg_data, 717 + }, 718 + }; 719 + 693 720 static struct platform_device *ezkit_devices[] __initdata = { 721 + 722 + &bfin_dpmc, 723 + 694 724 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 695 725 &rtc_device, 696 726 #endif
+32
arch/blackfin/mach-bf561/boards/cm_bf561.c
··· 33 33 #include <linux/mtd/partitions.h> 34 34 #include <linux/spi/spi.h> 35 35 #include <linux/spi/flash.h> 36 + #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 36 37 #include <linux/usb/isp1362.h> 38 + #endif 37 39 #include <linux/ata_platform.h> 38 40 #include <linux/irq.h> 39 41 #include <asm/dma.h> 40 42 #include <asm/bfin5xx_spi.h> 41 43 #include <asm/portmux.h> 44 + #include <asm/dpmc.h> 42 45 43 46 /* 44 47 * Name the Board for the /proc/cpuinfo ··· 342 339 }; 343 340 #endif 344 341 342 + static const unsigned int cclk_vlev_datasheet[] = 343 + { 344 + VRPAIR(VLEV_085, 250000000), 345 + VRPAIR(VLEV_090, 300000000), 346 + VRPAIR(VLEV_095, 313000000), 347 + VRPAIR(VLEV_100, 350000000), 348 + VRPAIR(VLEV_105, 400000000), 349 + VRPAIR(VLEV_110, 444000000), 350 + VRPAIR(VLEV_115, 450000000), 351 + VRPAIR(VLEV_120, 475000000), 352 + VRPAIR(VLEV_125, 500000000), 353 + VRPAIR(VLEV_130, 600000000), 354 + }; 355 + 356 + static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 357 + .tuple_tab = cclk_vlev_datasheet, 358 + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 359 + .vr_settling_time = 25 /* us */, 360 + }; 361 + 362 + static struct platform_device bfin_dpmc = { 363 + .name = "bfin dpmc", 364 + .dev = { 365 + .platform_data = &bfin_dmpc_vreg_data, 366 + }, 367 + }; 368 + 345 369 static struct platform_device *cm_bf561_devices[] __initdata = { 370 + 371 + &bfin_dpmc, 346 372 347 373 #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) 348 374 &hitachi_fb_device,
+31
arch/blackfin/mach-bf561/boards/ezkit.c
··· 39 39 #include <asm/dma.h> 40 40 #include <asm/bfin5xx_spi.h> 41 41 #include <asm/portmux.h> 42 + #include <asm/dpmc.h> 42 43 43 44 /* 44 45 * Name the Board for the /proc/cpuinfo ··· 444 443 }; 445 444 #endif 446 445 446 + static const unsigned int cclk_vlev_datasheet[] = 447 + { 448 + VRPAIR(VLEV_085, 250000000), 449 + VRPAIR(VLEV_090, 300000000), 450 + VRPAIR(VLEV_095, 313000000), 451 + VRPAIR(VLEV_100, 350000000), 452 + VRPAIR(VLEV_105, 400000000), 453 + VRPAIR(VLEV_110, 444000000), 454 + VRPAIR(VLEV_115, 450000000), 455 + VRPAIR(VLEV_120, 475000000), 456 + VRPAIR(VLEV_125, 500000000), 457 + VRPAIR(VLEV_130, 600000000), 458 + }; 459 + 460 + static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 461 + .tuple_tab = cclk_vlev_datasheet, 462 + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 463 + .vr_settling_time = 25 /* us */, 464 + }; 465 + 466 + static struct platform_device bfin_dpmc = { 467 + .name = "bfin dpmc", 468 + .dev = { 469 + .platform_data = &bfin_dmpc_vreg_data, 470 + }, 471 + }; 472 + 447 473 static struct platform_device *ezkit_devices[] __initdata = { 474 + 475 + &bfin_dpmc, 476 + 448 477 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 449 478 &smc91x_device, 450 479 #endif
+3 -2
arch/blackfin/mach-common/Makefile
··· 6 6 cache.o cacheinit.o entry.o \ 7 7 interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o 8 8 9 - obj-$(CONFIG_PM) += pm.o dpmc.o 10 - obj-$(CONFIG_CPU_FREQ) += cpufreq.o 9 + obj-$(CONFIG_PM) += pm.o dpmc_modes.o 10 + obj-$(CONFIG_CPU_FREQ) += cpufreq.o 11 + obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
+16 -10
arch/blackfin/mach-common/cpufreq.c
··· 62 62 unsigned int tscale; /* change the divider on the core timer interrupt */ 63 63 } dpm_state_table[3]; 64 64 65 + /* 66 + normalized to maximum frequncy offset for CYCLES, 67 + used in time-ts cycles clock source, but could be used 68 + somewhere also. 69 + */ 70 + unsigned long long __bfin_cycles_off; 71 + unsigned int __bfin_cycles_mod; 72 + 65 73 /**************************************************************************/ 66 74 67 75 static unsigned int bfin_getfreq(unsigned int cpu) ··· 88 80 unsigned int index, plldiv, tscale; 89 81 unsigned long flags, cclk_hz; 90 82 struct cpufreq_freqs freqs; 83 + cycles_t cycles; 91 84 92 85 if (cpufreq_frequency_table_target(policy, bfin_freq_table, 93 86 target_freq, relation, &index)) ··· 110 101 bfin_write_PLL_DIV(plldiv); 111 102 /* we have to adjust the core timer, because it is using cclk */ 112 103 bfin_write_TSCALE(tscale); 104 + cycles = get_cycles(); 113 105 SSYNC(); 106 + cycles += 10; /* ~10 cycles we loose after get_cycles() */ 107 + __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index); 108 + __bfin_cycles_mod = index; 114 109 local_irq_restore(flags); 110 + /* TODO: just test case for cycles clock source, remove later */ 111 + pr_debug("cpufreq: done\n"); 115 112 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 116 113 117 114 return 0; ··· 134 119 unsigned long cclk, sclk, csel, min_cclk; 135 120 int index; 136 121 137 - #ifdef CONFIG_CYCLES_CLOCKSOURCE 138 - /* 139 - * Clocksource CYCLES is still CONTINUOUS but not longer MONOTONIC in case we enable 140 - * CPU frequency scaling, since CYCLES runs off Core Clock. 141 - */ 142 - printk(KERN_WARNING "CPU frequency scaling not supported: Clocksource not suitable\n" 143 - return -ENODEV; 144 - #endif 145 - 146 122 if (policy->cpu != 0) 147 123 return -EINVAL; 148 124 149 125 cclk = get_cclk(); 150 126 sclk = get_sclk(); 151 127 152 - #if ANOMALY_05000273 128 + #if ANOMALY_05000273 || (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) 153 129 min_cclk = sclk * 2; 154 130 #else 155 131 min_cclk = sclk;
+2 -25
arch/blackfin/mach-common/dpmc.S arch/blackfin/mach-common/dpmc_modes.S
··· 1 1 /* 2 - * File: arch/blackfin/mach-common/dpmc.S 3 - * Based on: 4 - * Author: LG Soft India 2 + * Copyright 2004-2008 Analog Devices Inc. 5 3 * 6 - * Created: ? 7 - * Description: Watchdog Timer APIs 8 - * 9 - * Modified: 10 - * Copyright 2004-2006 Analog Devices Inc. 11 - * 12 - * Bugs: Enter bugs at http://blackfin.uclinux.org/ 13 - * 14 - * This program is free software; you can redistribute it and/or modify 15 - * it under the terms of the GNU General Public License as published by 16 - * the Free Software Foundation; either version 2 of the License, or 17 - * (at your option) any later version. 18 - * 19 - * This program is distributed in the hope that it will be useful, 20 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 - * GNU General Public License for more details. 23 - * 24 - * You should have received a copy of the GNU General Public License 25 - * along with this program; if not, see the file COPYING, or write 26 - * to the Free Software Foundation, Inc., 27 - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 4 + * Licensed under the GPL-2 or later. 28 5 */ 29 6 30 7 #include <linux/linkage.h>
+137
arch/blackfin/mach-common/dpmc.c
··· 1 + /* 2 + * Copyright 2008 Analog Devices Inc. 3 + * 4 + * Licensed under the GPL-2 or later. 5 + */ 6 + 7 + #include <linux/cdev.h> 8 + #include <linux/device.h> 9 + #include <linux/errno.h> 10 + #include <linux/fs.h> 11 + #include <linux/kernel.h> 12 + #include <linux/module.h> 13 + #include <linux/platform_device.h> 14 + #include <linux/types.h> 15 + #include <linux/cpufreq.h> 16 + 17 + #include <asm/delay.h> 18 + #include <asm/dpmc.h> 19 + 20 + #define DRIVER_NAME "bfin dpmc" 21 + 22 + #define dprintk(msg...) \ 23 + cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, DRIVER_NAME, msg) 24 + 25 + struct bfin_dpmc_platform_data *pdata; 26 + 27 + /** 28 + * bfin_set_vlev - Update VLEV field in VR_CTL Reg. 29 + * Avoid BYPASS sequence 30 + */ 31 + static void bfin_set_vlev(unsigned int vlev) 32 + { 33 + unsigned pll_lcnt; 34 + 35 + pll_lcnt = bfin_read_PLL_LOCKCNT(); 36 + 37 + bfin_write_PLL_LOCKCNT(1); 38 + bfin_write_VR_CTL((bfin_read_VR_CTL() & ~VLEV) | vlev); 39 + bfin_write_PLL_LOCKCNT(pll_lcnt); 40 + } 41 + 42 + /** 43 + * bfin_get_vlev - Get CPU specific VLEV from platform device data 44 + */ 45 + static unsigned int bfin_get_vlev(unsigned int freq) 46 + { 47 + int i; 48 + 49 + if (!pdata) 50 + goto err_out; 51 + 52 + freq >>= 16; 53 + 54 + for (i = 0; i < pdata->tabsize; i++) 55 + if (freq <= (pdata->tuple_tab[i] & 0xFFFF)) 56 + return pdata->tuple_tab[i] >> 16; 57 + 58 + err_out: 59 + printk(KERN_WARNING "DPMC: No suitable CCLK VDDINT voltage pair found\n"); 60 + return VLEV_120; 61 + } 62 + 63 + #ifdef CONFIG_CPU_FREQ 64 + static int 65 + vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data) 66 + { 67 + struct cpufreq_freqs *freq = data; 68 + 69 + if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) { 70 + bfin_set_vlev(bfin_get_vlev(freq->new)); 71 + udelay(pdata->vr_settling_time); /* Wait until Volatge settled */ 72 + 73 + } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) 74 + bfin_set_vlev(bfin_get_vlev(freq->new)); 75 + 76 + return 0; 77 + } 78 + 79 + static struct notifier_block vreg_cpufreq_notifier_block = { 80 + .notifier_call = vreg_cpufreq_notifier 81 + }; 82 + #endif /* CONFIG_CPU_FREQ */ 83 + 84 + /** 85 + * bfin_dpmc_probe - 86 + * 87 + */ 88 + static int __devinit bfin_dpmc_probe(struct platform_device *pdev) 89 + { 90 + if (pdev->dev.platform_data) 91 + pdata = pdev->dev.platform_data; 92 + else 93 + return -EINVAL; 94 + 95 + return cpufreq_register_notifier(&vreg_cpufreq_notifier_block, 96 + CPUFREQ_TRANSITION_NOTIFIER); 97 + } 98 + 99 + /** 100 + * bfin_dpmc_remove - 101 + */ 102 + static int __devexit bfin_dpmc_remove(struct platform_device *pdev) 103 + { 104 + pdata = NULL; 105 + return cpufreq_unregister_notifier(&vreg_cpufreq_notifier_block, 106 + CPUFREQ_TRANSITION_NOTIFIER); 107 + } 108 + 109 + struct platform_driver bfin_dpmc_device_driver = { 110 + .probe = bfin_dpmc_probe, 111 + .remove = __devexit_p(bfin_dpmc_remove), 112 + .driver = { 113 + .name = DRIVER_NAME, 114 + } 115 + }; 116 + 117 + /** 118 + * bfin_dpmc_init - Init driver 119 + */ 120 + static int __init bfin_dpmc_init(void) 121 + { 122 + return platform_driver_register(&bfin_dpmc_device_driver); 123 + } 124 + module_init(bfin_dpmc_init); 125 + 126 + /** 127 + * bfin_dpmc_exit - break down driver 128 + */ 129 + static void __exit bfin_dpmc_exit(void) 130 + { 131 + platform_driver_unregister(&bfin_dpmc_device_driver); 132 + } 133 + module_exit(bfin_dpmc_exit); 134 + 135 + MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); 136 + MODULE_DESCRIPTION("cpu power management driver for Blackfin"); 137 + MODULE_LICENSE("GPL");
+82 -31
arch/blackfin/mach-common/entry.S
··· 151 151 ENDPROC(_ex_soft_bp) 152 152 153 153 ENTRY(_ex_single_step) 154 + /* If we just returned from an interrupt, the single step event is 155 + for the RTI instruction. */ 154 156 r7 = retx; 155 157 r6 = reti; 156 158 cc = r7 == r6; 157 - if cc jump _bfin_return_from_exception 159 + if cc jump _bfin_return_from_exception; 160 + 161 + /* If we were in user mode, do the single step normally. */ 162 + p5.l = lo(IPEND); 163 + p5.h = hi(IPEND); 164 + r6 = [p5]; 165 + r7 = 0xffe0 (z); 166 + r7 = r7 & r6; 167 + cc = r7 == 0; 168 + if !cc jump 1f; 169 + 170 + /* Single stepping only a single instruction, so clear the trace 171 + * bit here. */ 172 + r7 = syscfg; 173 + bitclr (r7, 0); 174 + syscfg = R7; 175 + jump _ex_trap_c; 176 + 177 + 1: 178 + /* 179 + * We were in an interrupt handler. By convention, all of them save 180 + * SYSCFG with their first instruction, so by checking whether our 181 + * RETX points at the entry point, we can determine whether to allow 182 + * a single step, or whether to clear SYSCFG. 183 + * 184 + * First, find out the interrupt level and the event vector for it. 185 + */ 186 + p5.l = lo(EVT0); 187 + p5.h = hi(EVT0); 188 + p5 += -4; 189 + 2: 190 + r7 = rot r7 by -1; 191 + p5 += 4; 192 + if !cc jump 2b; 193 + 194 + /* What we actually do is test for the _second_ instruction in the 195 + * IRQ handler. That way, if there are insns following the restore 196 + * of SYSCFG after leaving the handler, we will not turn off SYSCFG 197 + * for them. */ 198 + 199 + r7 = [p5]; 200 + r7 += 2; 201 + r6 = RETX; 202 + cc = R7 == R6; 203 + if !cc jump _bfin_return_from_exception; 204 + 158 205 r7 = syscfg; 159 206 bitclr (r7, 0); 160 207 syscfg = R7; 161 208 162 - p5.l = lo(IPEND); 163 - p5.h = hi(IPEND); 164 - r6 = [p5]; 165 - cc = bittst(r6, 5); 166 - if !cc jump _ex_trap_c; 167 - p4.l = lo(EVT5); 168 - p4.h = hi(EVT5); 169 - r6.h = _exception_to_level5; 170 - r6.l = _exception_to_level5; 171 - r7 = [p4]; 172 - cc = r6 == r7; 173 - if !cc jump _ex_trap_c; 209 + /* Fall through to _bfin_return_from_exception. */ 174 210 ENDPROC(_ex_single_step) 175 211 176 212 ENTRY(_bfin_return_from_exception) ··· 270 234 p5.l = _saved_icplb_fault_addr; 271 235 [p5] = r7; 272 236 273 - p4.l = __retx; 274 - p4.h = __retx; 237 + p4.l = _excpt_saved_stuff; 238 + p4.h = _excpt_saved_stuff; 239 + 275 240 r6 = retx; 276 241 [p4] = r6; 277 - p4.l = lo(SAFE_USER_INSTRUCTION); 278 - p4.h = hi(SAFE_USER_INSTRUCTION); 279 - retx = p4; 242 + 243 + r6 = SYSCFG; 244 + [p4 + 4] = r6; 245 + BITCLR(r6, 0); 246 + SYSCFG = r6; 280 247 281 248 /* Disable all interrupts, but make sure level 5 is enabled so 282 249 * we can switch to that level. Save the old mask. */ 283 250 cli r6; 284 - p4.l = _excpt_saved_imask; 285 - p4.h = _excpt_saved_imask; 286 - [p4] = r6; 251 + [p4 + 8] = r6; 252 + 253 + p4.l = lo(SAFE_USER_INSTRUCTION); 254 + p4.h = hi(SAFE_USER_INSTRUCTION); 255 + retx = p4; 256 + 287 257 r6 = 0x3f; 288 258 sti r6; 289 259 ··· 337 295 */ 338 296 SAVE_ALL_SYS 339 297 298 + /* The dumping functions expect the return address in the RETI 299 + * slot. */ 300 + r6 = retx; 301 + [sp + PT_PC] = r6; 302 + 340 303 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ 341 304 SP += -12; 342 305 call _double_fault_c; ··· 354 307 ENTRY(_exception_to_level5) 355 308 SAVE_ALL_SYS 356 309 357 - p4.l = __retx; 358 - p4.h = __retx; 310 + p4.l = _excpt_saved_stuff; 311 + p4.h = _excpt_saved_stuff; 359 312 r6 = [p4]; 360 313 [sp + PT_PC] = r6; 361 314 315 + r6 = [p4 + 4]; 316 + [sp + PT_SYSCFG] = r6; 317 + 362 318 /* Restore interrupt mask. We haven't pushed RETI, so this 363 319 * doesn't enable interrupts until we return from this handler. */ 364 - p4.l = _excpt_saved_imask; 365 - p4.h = _excpt_saved_imask; 366 - r6 = [p4]; 320 + r6 = [p4 + 8]; 367 321 sti r6; 368 322 369 323 /* Restore the hardware error vector. */ ··· 1392 1344 .rept NR_syscalls-(.-_sys_call_table)/4 1393 1345 .long _sys_ni_syscall 1394 1346 .endr 1395 - _excpt_saved_imask: 1347 + 1348 + /* 1349 + * Used to save the real RETX, IMASK and SYSCFG when temporarily 1350 + * storing safe values across the transition from exception to IRQ5. 1351 + */ 1352 + _excpt_saved_stuff: 1353 + .long 0; 1354 + .long 0; 1396 1355 .long 0; 1397 1356 1398 1357 _exception_stack: ··· 1413 1358 _last_cplb_fault_retx: 1414 1359 .long 0; 1415 1360 #endif 1416 - /* Used to save the real RETX when temporarily storing a safe 1417 - * return address. */ 1418 - __retx: 1419 - .long 0;
+11 -87
drivers/serial/bfin_5xx.c
··· 65 65 { 66 66 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; 67 67 struct circ_buf *xmit = &uart->port.info->xmit; 68 - #if !defined(CONFIG_BF54x) && !defined(CONFIG_SERIAL_BFIN_DMA) 69 - unsigned short ier; 70 - #endif 71 68 72 69 while (!(UART_GET_LSR(uart) & TEMT)) 73 70 cpu_relax(); ··· 79 82 #ifdef CONFIG_BF54x 80 83 /* Clear TFI bit */ 81 84 UART_PUT_LSR(uart, TFI); 82 - UART_CLEAR_IER(uart, ETBEI); 83 - #else 84 - ier = UART_GET_IER(uart); 85 - ier &= ~ETBEI; 86 - UART_PUT_IER(uart, ier); 87 85 #endif 86 + UART_CLEAR_IER(uart, ETBEI); 88 87 #endif 89 88 } 90 89 ··· 95 102 if (uart->tx_done) 96 103 bfin_serial_dma_tx_chars(uart); 97 104 #else 98 - #ifdef CONFIG_BF54x 99 105 UART_SET_IER(uart, ETBEI); 100 - #else 101 - unsigned short ier; 102 - ier = UART_GET_IER(uart); 103 - ier |= ETBEI; 104 - UART_PUT_IER(uart, ier); 105 - #endif 106 106 bfin_serial_tx_chars(uart); 107 107 #endif 108 108 } ··· 106 120 static void bfin_serial_stop_rx(struct uart_port *port) 107 121 { 108 122 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; 109 - #ifdef CONFIG_KGDB_UART 110 - if (uart->port.line != CONFIG_KGDB_UART_PORT) { 123 + #ifdef CONFIG_KGDB_UART 124 + if (uart->port.line != CONFIG_KGDB_UART_PORT) 111 125 #endif 112 - #ifdef CONFIG_BF54x 113 126 UART_CLEAR_IER(uart, ERBFI); 114 - #else 115 - unsigned short ier; 116 - 117 - ier = UART_GET_IER(uart); 118 - ier &= ~ERBFI; 119 - UART_PUT_IER(uart, ier); 120 - #endif 121 - #ifdef CONFIG_KGDB_UART 122 - } 123 - #endif 124 127 } 125 128 126 129 /* ··· 136 161 SSYNC(); 137 162 } 138 163 139 - #ifndef CONFIG_BF54x 140 - UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); 141 - SSYNC(); 142 - #endif 164 + UART_CLEAR_DLAB(uart); 143 165 UART_PUT_CHAR(uart, (unsigned char)chr); 144 166 SSYNC(); 145 167 } ··· 155 183 while(!(UART_GET_LSR(uart) & DR)) { 156 184 SSYNC(); 157 185 } 158 - #ifndef CONFIG_BF54x 159 - UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); 160 - SSYNC(); 161 - #endif 186 + UART_CLEAR_DLAB(uart); 162 187 chr = UART_GET_CHAR(uart); 163 188 SSYNC(); 164 189 ··· 177 208 struct tty_struct *tty = uart->port.info->tty; 178 209 unsigned int status, ch, flg; 179 210 static struct timeval anomaly_start = { .tv_sec = 0 }; 180 - #ifdef CONFIG_KGDB_UART 181 - struct pt_regs *regs = get_irq_regs(); 182 - #endif 183 211 184 212 status = UART_GET_LSR(uart); 185 213 UART_CLEAR_LSR(uart); ··· 186 220 187 221 #ifdef CONFIG_KGDB_UART 188 222 if (uart->port.line == CONFIG_KGDB_UART_PORT) { 223 + struct pt_regs *regs = get_irq_regs(); 189 224 if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */ 190 225 kgdb_breakkey_pressed(regs); 191 226 return; ··· 358 391 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) 359 392 { 360 393 struct circ_buf *xmit = &uart->port.info->xmit; 361 - unsigned short ier; 362 394 363 395 uart->tx_done = 0; 364 396 ··· 395 429 set_dma_x_modify(uart->tx_dma_channel, 1); 396 430 enable_dma(uart->tx_dma_channel); 397 431 398 - #ifdef CONFIG_BF54x 399 432 UART_SET_IER(uart, ETBEI); 400 - #else 401 - ier = UART_GET_IER(uart); 402 - ier |= ETBEI; 403 - UART_PUT_IER(uart, ier); 404 - #endif 405 433 } 406 434 407 435 static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) ··· 473 513 { 474 514 struct bfin_serial_port *uart = dev_id; 475 515 struct circ_buf *xmit = &uart->port.info->xmit; 476 - unsigned short ier; 477 516 478 517 spin_lock(&uart->port.lock); 479 518 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { 480 519 disable_dma(uart->tx_dma_channel); 481 520 clear_dma_irqstat(uart->tx_dma_channel); 482 - #ifdef CONFIG_BF54x 483 521 UART_CLEAR_IER(uart, ETBEI); 484 - #else 485 - ier = UART_GET_IER(uart); 486 - ier &= ~ETBEI; 487 - UART_PUT_IER(uart, ier); 488 - #endif 489 522 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); 490 523 uart->port.icount.tx += uart->tx_count; 491 524 ··· 654 701 # endif 655 702 } 656 703 657 - 658 704 if (request_irq 659 705 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, 660 706 "BFIN_UART_TX", uart)) { ··· 662 710 return -EBUSY; 663 711 } 664 712 #endif 665 - #ifdef CONFIG_BF54x 666 713 UART_SET_IER(uart, ERBFI); 667 - #else 668 - UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); 669 - #endif 670 714 return 0; 671 715 } 672 716 ··· 758 810 UART_PUT_IER(uart, 0); 759 811 #endif 760 812 761 - #ifndef CONFIG_BF54x 762 813 /* Set DLAB in LCR to Access DLL and DLH */ 763 - val = UART_GET_LCR(uart); 764 - val |= DLAB; 765 - UART_PUT_LCR(uart, val); 766 - SSYNC(); 767 - #endif 814 + UART_SET_DLAB(uart); 768 815 769 816 UART_PUT_DLL(uart, quot & 0xFF); 770 - SSYNC(); 771 817 UART_PUT_DLH(uart, (quot >> 8) & 0xFF); 772 818 SSYNC(); 773 819 774 - #ifndef CONFIG_BF54x 775 820 /* Clear DLAB in LCR to Access THR RBR IER */ 776 - val = UART_GET_LCR(uart); 777 - val &= ~DLAB; 778 - UART_PUT_LCR(uart, val); 779 - SSYNC(); 780 - #endif 821 + UART_CLEAR_DLAB(uart); 781 822 782 823 UART_PUT_LCR(uart, lcr); 783 824 ··· 929 992 status = UART_GET_IER(uart) & (ERBFI | ETBEI); 930 993 if (status == (ERBFI | ETBEI)) { 931 994 /* ok, the port was enabled */ 932 - unsigned short lcr, val; 933 - unsigned short dlh, dll; 995 + u16 lcr, dlh, dll; 934 996 935 997 lcr = UART_GET_LCR(uart); 936 998 ··· 946 1010 case 2: *bits = 7; break; 947 1011 case 3: *bits = 8; break; 948 1012 } 949 - #ifndef CONFIG_BF54x 950 1013 /* Set DLAB in LCR to Access DLL and DLH */ 951 - val = UART_GET_LCR(uart); 952 - val |= DLAB; 953 - UART_PUT_LCR(uart, val); 954 - #endif 1014 + UART_SET_DLAB(uart); 955 1015 956 1016 dll = UART_GET_DLL(uart); 957 1017 dlh = UART_GET_DLH(uart); 958 1018 959 - #ifndef CONFIG_BF54x 960 1019 /* Clear DLAB in LCR to Access THR RBR IER */ 961 - val = UART_GET_LCR(uart); 962 - val &= ~DLAB; 963 - UART_PUT_LCR(uart, val); 964 - #endif 1020 + UART_CLEAR_DLAB(uart); 965 1021 966 1022 *baud = get_sclk() / (16*(dll | dlh << 8)); 967 1023 } ··· 1218 1290 request_irq(uart->port.irq, bfin_serial_rx_int, 1219 1291 IRQF_DISABLED, "BFIN_UART_RX", uart); 1220 1292 pr_info("Request irq for kgdb uart port\n"); 1221 - #ifdef CONFIG_BF54x 1222 1293 UART_SET_IER(uart, ERBFI); 1223 - #else 1224 - UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); 1225 - #endif 1226 1294 SSYNC(); 1227 1295 t.c_cflag = CS8|B57600; 1228 1296 t.c_iflag = 0;
+9 -1
include/asm-blackfin/dpmc.h
··· 1 1 /* 2 2 * include/asm-blackfin/dpmc.h - Miscellaneous IOCTL commands for Dynamic Power 3 3 * Management Controller Driver. 4 - * Copyright (C) 2004 Analog Device Inc. 4 + * Copyright (C) 2004-2008 Analog Device Inc. 5 5 * 6 6 */ 7 7 #ifndef _BLACKFIN_DPMC_H_ ··· 64 64 65 65 extern unsigned long get_cclk(void); 66 66 extern unsigned long get_sclk(void); 67 + 68 + struct bfin_dpmc_platform_data { 69 + const unsigned int *tuple_tab; 70 + unsigned short tabsize; 71 + unsigned short vr_settling_time; /* in us */ 72 + }; 73 + 74 + #define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) 67 75 68 76 #endif /* __KERNEL__ */ 69 77
+5
include/asm-blackfin/entry.h
··· 17 17 #define PF_DTRACE_OFF 1 18 18 #define PF_DTRACE_BIT 5 19 19 20 + /* 21 + * NOTE! The single-stepping code assumes that all interrupt handlers 22 + * start by saving SYSCFG on the stack with their first instruction. 23 + */ 24 + 20 25 /* This one is used for exceptions, emulation, and NMI. It doesn't push 21 26 RETI and doesn't do cli. */ 22 27 #define SAVE_ALL_SYS save_context_no_interrupts
+5
include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
··· 44 44 #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) 45 45 #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) 46 46 #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) 47 + #define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) 48 + #define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) 47 49 #define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) 48 50 #define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) 49 51 #define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) 52 + 53 + #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 54 + #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 50 55 51 56 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 52 57 # define CONFIG_SERIAL_BFIN_CTSRTS
+5
include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
··· 44 44 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 45 45 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 46 46 #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) 47 + #define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) 48 + #define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) 47 49 #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 48 50 #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 49 51 #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 52 + 53 + #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 54 + #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 50 55 51 56 #ifdef CONFIG_BFIN_UART0_CTSRTS 52 57 # define CONFIG_SERIAL_BFIN_CTSRTS
+2
include/asm-blackfin/mach-bf533/defBF532.h
··· 468 468 #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 469 469 #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 470 470 #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 471 + #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ 472 + #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 471 473 472 474 #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 473 475 #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
+6 -8
include/asm-blackfin/mach-bf533/irq.h
··· 66 66 DMA8/9 Interrupt IVG13 28 67 67 DMA10/11 Interrupt IVG13 29 68 68 Watchdog Timer IVG13 30 69 - Software Interrupt 1 IVG14 31 70 - Software Interrupt 2 -- 69 + 70 + Softirq IVG14 31 71 + System Call -- 71 72 (lowest priority) IVG15 32 * 72 73 */ 73 - #define SYS_IRQS 32 74 - #define NR_PERI_INTS 24 74 + #define SYS_IRQS 31 75 + #define NR_PERI_INTS 24 75 76 76 77 /* The ABSTRACT IRQ definitions */ 77 78 /** the first seven of the following are fixed, the rest you change if you need to **/ ··· 97 96 #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ 98 97 #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ 99 98 #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ 100 - #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ 99 + #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ 101 100 #define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */ 102 101 #define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */ 103 102 #define IRQ_TMR0 23 /*Timer 0 */ ··· 108 107 #define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ 109 108 #define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */ 110 109 #define IRQ_WATCH 30 /*Watch Dog Timer */ 111 - 112 - #define IRQ_SW_INT1 31 /*Software Int 1 */ 113 - #define IRQ_SW_INT2 32 /*Software Int 2 (reserved for SYSCALL) */ 114 110 115 111 #define IRQ_PF0 33 116 112 #define IRQ_PF1 34
+5
include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
··· 44 44 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 45 45 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 46 46 #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) 47 + #define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) 48 + #define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) 47 49 #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 48 50 #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 49 51 #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 52 + 53 + #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 54 + #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 50 55 51 56 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 52 57 # define CONFIG_SERIAL_BFIN_CTSRTS
+16 -19
include/asm-blackfin/mach-bf537/irq.h
··· 34 34 35 35 /* 36 36 * Interrupt source definitions 37 - Event Source Core Event Name 38 - Core Emulation ** 39 - Events (highest priority) EMU 0 40 - Reset RST 1 41 - NMI NMI 2 42 - Exception EVX 3 43 - Reserved -- 4 44 - Hardware Error IVHW 5 45 - Core Timer IVTMR 6 * 46 - 47 - ..... 48 - 49 - Software Interrupt 1 IVG14 31 50 - Software Interrupt 2 -- 51 - (lowest priority) IVG15 32 * 37 + * Event Source Core Event Name 38 + * Core Emulation ** 39 + * Events (highest priority) EMU 0 40 + * Reset RST 1 41 + * NMI NMI 2 42 + * Exception EVX 3 43 + * Reserved -- 4 44 + * Hardware Error IVHW 5 45 + * Core Timer IVTMR 6 46 + * ..... 47 + * 48 + * Softirq IVG14 49 + * System Call -- 50 + * (lowest priority) IVG15 52 51 */ 53 52 54 - #define SYS_IRQS 41 53 + #define SYS_IRQS 39 55 54 #define NR_PERI_INTS 32 56 55 57 56 /* The ABSTRACT IRQ definitions */ ··· 94 95 #define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ 95 96 #define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ 96 97 #define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */ 97 - #define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ 98 + #define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ 98 99 #define IRQ_WATCH 38 /*Watch Dog Timer */ 99 - #define IRQ_SW_INT1 40 /*Software Int 1 */ 100 - #define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */ 101 100 102 101 #define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ 103 102 #define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
+3
include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
··· 54 54 #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 55 55 #define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) 56 56 57 + #define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */ 58 + #define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */ 59 + 57 60 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 58 61 # define CONFIG_SERIAL_BFIN_CTSRTS 59 62
+20
include/asm-blackfin/mach-bf548/defBF54x_base.h
··· 2329 2329 #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ 2330 2330 #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ 2331 2331 2332 + #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ 2333 + #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ 2334 + #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ 2335 + 2336 + #define GAIN_5 0x0000 /* GAIN = 5*/ 2337 + #define GAIN_10 0x0004 /* GAIN = 1*/ 2338 + #define GAIN_20 0x0008 /* GAIN = 2*/ 2339 + #define GAIN_50 0x000C /* GAIN = 5*/ 2340 + 2341 + #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 2342 + #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 2343 + #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 2344 + #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 2345 + #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ 2346 + #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 2347 + #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 2348 + #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 2349 + #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ 2350 + #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 2351 + 2332 2352 /* Bit masks for NFC_CTL */ 2333 2353 2334 2354 #define WR_DLY 0xf /* Write Strobe Delay */
+5
include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
··· 44 44 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 45 45 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 46 46 #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) 47 + #define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) 48 + #define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) 47 49 #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 48 50 #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 49 51 #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 52 + 53 + #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 54 + #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 50 55 51 56 #ifdef CONFIG_BFIN_UART0_CTSRTS 52 57 # define CONFIG_SERIAL_BFIN_CTSRTS
+28
include/asm-blackfin/mach-bf561/defBF561.h
··· 868 868 #define CHIPID_FAMILY 0x0FFFF000 869 869 #define CHIPID_MANUFACTURE 0x00000FFE 870 870 871 + /* VR_CTL Masks */ 872 + #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ 873 + #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ 874 + #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ 875 + #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ 876 + #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ 877 + 878 + #define GAIN 0x000C /* Voltage Level Gain */ 879 + #define GAIN_5 0x0000 /* GAIN = 5*/ 880 + #define GAIN_10 0x0004 /* GAIN = 1*/ 881 + #define GAIN_20 0x0008 /* GAIN = 2*/ 882 + #define GAIN_50 0x000C /* GAIN = 5*/ 883 + 884 + #define VLEV 0x00F0 /* Internal Voltage Level */ 885 + #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 886 + #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 887 + #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 888 + #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 889 + #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ 890 + #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 891 + #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 892 + #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 893 + #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ 894 + #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 895 + 896 + #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 897 + #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ 898 + 871 899 /* PLL_DIV Masks */ 872 900 #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ 873 901
+6 -7
include/asm-blackfin/mach-bf561/irq.h
··· 118 118 Supplemental interrupt 0 IVG7 69 119 119 supplemental interrupt 1 IVG7 70 120 120 121 - Software Interrupt 1 IVG14 71 122 - Software Interrupt 2 IVG15 72 * 123 - (lowest priority) 121 + Softirq IVG14 122 + System Call -- 123 + (lowest priority) IVG15 124 + 124 125 **********************************************************************/ 125 126 126 - #define SYS_IRQS 72 127 + #define SYS_IRQS 71 127 128 #define NR_PERI_INTS 64 128 129 129 130 /* ··· 238 237 #define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ 239 238 #define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ 240 239 #define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ 241 - #define IRQ_SW_INT1 71 /* Software Interrupt 1 */ 242 - #define IRQ_SW_INT2 72 /* Software Interrupt 2 */ 243 - /* reserved for SYSCALL */ 240 + 244 241 #define IRQ_PF0 73 245 242 #define IRQ_PF1 74 246 243 #define IRQ_PF2 75
+5
include/asm-blackfin/mach-common/context.S
··· 28 28 */ 29 29 30 30 /* 31 + * NOTE! The single-stepping code assumes that all interrupt handlers 32 + * start by saving SYSCFG on the stack with their first instruction. 33 + */ 34 + 35 + /* 31 36 * Code to save processor context. 32 37 * We even save the register which are preserved by a function call 33 38 * - r4, r5, r6, r7, p3, p4, p5
+4
include/asm-blackfin/time.h
··· 24 24 25 25 #ifndef CONFIG_CPU_FREQ 26 26 #define TIME_SCALE 1 27 + #define __bfin_cycles_off (0) 28 + #define __bfin_cycles_mod (0) 27 29 #else 28 30 /* 29 31 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . ··· 33 31 * adjust the Core Timer Presale Register. This way we don't lose time. 34 32 */ 35 33 #define TIME_SCALE 4 34 + extern unsigned long long __bfin_cycles_off; 35 + extern unsigned int __bfin_cycles_mod; 36 36 #endif 37 37 38 38 #endif